1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI-IDE bus nexus driver 30 */ 31 32 #include <sys/types.h> 33 #include <sys/cmn_err.h> 34 #include <sys/conf.h> 35 #include <sys/errno.h> 36 #include <sys/debug.h> 37 #include <sys/ddidmareq.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/dma_engine.h> 40 #include <sys/modctl.h> 41 #include <sys/ddi.h> 42 #include <sys/sunddi.h> 43 #include <sys/mach_intr.h> 44 #include <sys/kmem.h> 45 #include <sys/pci.h> 46 #include <sys/promif.h> 47 #include <sys/pci_intr_lib.h> 48 49 int pciide_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 50 51 #define PCIIDE_NATIVE_MODE(dip) \ 52 (!ddi_prop_exists(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, \ 53 "compatibility-mode")) 54 55 #define PCIIDE_PRE26(dip) \ 56 ddi_prop_exists(DDI_DEV_T_ANY, (dip), 0, "ignore-hardware-nodes") 57 58 #define PCI_IDE_IF_BM_CAP_MASK 0x80 59 60 #define PCIIDE_PDSIZE (sizeof (struct ddi_parent_private_data) + \ 61 sizeof (struct intrspec)) 62 63 #ifdef DEBUG 64 static int pci_ide_debug = 0; 65 #define PDBG(fmt) \ 66 if (pci_ide_debug) { \ 67 prom_printf fmt; \ 68 } 69 #else 70 #define PDBG(fmt) 71 #endif 72 73 #ifndef TRUE 74 #define TRUE 1 75 #endif 76 #ifndef FALSE 77 #define FALSE 0 78 #endif 79 80 /* 81 * bus_ops functions 82 */ 83 84 static int pciide_bus_map(dev_info_t *dip, dev_info_t *rdip, 85 ddi_map_req_t *mp, off_t offset, off_t len, 86 caddr_t *vaddrp); 87 88 static int pciide_ddi_ctlops(dev_info_t *dip, dev_info_t *rdip, 89 ddi_ctl_enum_t ctlop, void *arg, 90 void *result); 91 92 static int pciide_get_pri(dev_info_t *dip, dev_info_t *rdip, 93 ddi_intr_handle_impl_t *hdlp, int *pri); 94 95 static int pciide_intr_ops(dev_info_t *dip, dev_info_t *rdip, 96 ddi_intr_op_t intr_op, 97 ddi_intr_handle_impl_t *hdlp, void *result); 98 99 static struct intrspec *pciide_get_ispec(dev_info_t *dip, dev_info_t *rdip, 100 int inum); 101 102 /* 103 * Local Functions 104 */ 105 static int pciide_initchild(dev_info_t *mydip, dev_info_t *cdip); 106 107 static void pciide_compat_setup(dev_info_t *mydip, dev_info_t *cdip, 108 int dev); 109 static int pciide_pre26_rnumber_map(dev_info_t *mydip, int rnumber); 110 static int pciide_map_rnumber(int canonical_rnumber, int pri_native, 111 int sec_native); 112 113 114 /* 115 * Config information 116 */ 117 118 struct bus_ops pciide_bus_ops = { 119 BUSO_REV, 120 pciide_bus_map, 121 0, 122 0, 123 0, 124 i_ddi_map_fault, 125 ddi_dma_map, 126 ddi_dma_allochdl, 127 ddi_dma_freehdl, 128 ddi_dma_bindhdl, 129 ddi_dma_unbindhdl, 130 ddi_dma_flush, 131 ddi_dma_win, 132 ddi_dma_mctl, 133 pciide_ddi_ctlops, 134 ddi_bus_prop_op, 135 0, /* (*bus_get_eventcookie)(); */ 136 0, /* (*bus_add_eventcall)(); */ 137 0, /* (*bus_remove_eventcall)(); */ 138 0, /* (*bus_post_event)(); */ 139 0, 140 0, 141 0, 142 0, 143 0, 144 0, 145 0, 146 0, 147 pciide_intr_ops 148 }; 149 150 struct dev_ops pciide_ops = { 151 DEVO_REV, /* devo_rev, */ 152 0, /* refcnt */ 153 ddi_no_info, /* info */ 154 nulldev, /* identify */ 155 nulldev, /* probe */ 156 pciide_attach, /* attach */ 157 nodev, /* detach */ 158 nodev, /* reset */ 159 (struct cb_ops *)0, /* driver operations */ 160 &pciide_bus_ops /* bus operations */ 161 162 }; 163 164 /* 165 * Module linkage information for the kernel. 166 */ 167 168 static struct modldrv modldrv = { 169 &mod_driverops, /* Type of module. This is PCI-IDE bus driver */ 170 "pciide nexus driver for 'PCI-IDE' %I%", 171 &pciide_ops, /* driver ops */ 172 }; 173 174 static struct modlinkage modlinkage = { 175 MODREV_1, 176 &modldrv, 177 NULL 178 }; 179 180 181 int 182 _init(void) 183 { 184 return (mod_install(&modlinkage)); 185 } 186 187 int 188 _fini(void) 189 { 190 return (mod_remove(&modlinkage)); 191 } 192 193 int 194 _info(struct modinfo *modinfop) 195 { 196 return (mod_info(&modlinkage, modinfop)); 197 } 198 199 int 200 pciide_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 201 { 202 uint16_t cmdreg; 203 ddi_acc_handle_t conf_hdl = NULL; 204 int rc; 205 206 207 if (cmd == DDI_ATTACH) { 208 209 /* 210 * Make sure bus-mastering is enabled, even if 211 * BIOS didn't. 212 */ 213 rc = pci_config_setup(dip, &conf_hdl); 214 215 /* 216 * In case of error, return SUCCESS. This is because 217 * bus-mastering could be already enabled by BIOS. 218 */ 219 if (rc != DDI_SUCCESS) 220 return (DDI_SUCCESS); 221 222 cmdreg = pci_config_get16(conf_hdl, PCI_CONF_COMM); 223 if ((cmdreg & PCI_COMM_ME) == 0) { 224 pci_config_put16(conf_hdl, PCI_CONF_COMM, 225 cmdreg | PCI_COMM_ME); 226 } 227 pci_config_teardown(&conf_hdl); 228 229 return (DDI_SUCCESS); 230 } else { 231 return (DDI_FAILURE); 232 } 233 } 234 235 236 /*ARGSUSED*/ 237 static int 238 pciide_ddi_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 239 void *arg, void *result) 240 { 241 dev_info_t *cdip; 242 int controller; 243 void *pdptr; 244 int rnumber; 245 off_t tmp; 246 int rc; 247 248 PDBG(("pciide_bus_ctl\n")); 249 250 switch (ctlop) { 251 case DDI_CTLOPS_INITCHILD: 252 cdip = (dev_info_t *)arg; 253 return (pciide_initchild(dip, cdip)); 254 255 case DDI_CTLOPS_UNINITCHILD: 256 cdip = (dev_info_t *)arg; 257 pdptr = ddi_get_parent_data(cdip); 258 ddi_set_parent_data(cdip, NULL); 259 ddi_set_name_addr(cdip, NULL); 260 kmem_free(pdptr, PCIIDE_PDSIZE); 261 return (DDI_SUCCESS); 262 263 case DDI_CTLOPS_NREGS: 264 *(int *)result = 3; 265 return (DDI_SUCCESS); 266 267 case DDI_CTLOPS_REGSIZE: 268 /* 269 * Adjust the rnumbers based on which controller instance 270 * is requested; adjust for the 2 tuples per controller. 271 */ 272 if (strcmp("0", ddi_get_name_addr(rdip)) == 0) 273 controller = 0; 274 else 275 controller = 1; 276 277 278 switch (rnumber = *(int *)arg) { 279 case 0: 280 case 1: 281 rnumber += (2 * controller); 282 break; 283 case 2: 284 rnumber = 4; 285 break; 286 default: 287 PDBG(("pciide_ctlops invalid rnumber\n")); 288 return (DDI_FAILURE); 289 } 290 291 292 if (PCIIDE_PRE26(dip)) { 293 int old_rnumber; 294 int new_rnumber; 295 296 old_rnumber = rnumber; 297 new_rnumber 298 = pciide_pre26_rnumber_map(dip, old_rnumber); 299 PDBG(("pciide rnumber old %d new %d\n", 300 old_rnumber, new_rnumber)); 301 rnumber = new_rnumber; 302 } 303 304 /* 305 * Add 1 to skip over the PCI config space tuple 306 */ 307 rnumber++; 308 309 /* 310 * If it's not tuple #2 pass the adjusted request to my parent 311 */ 312 if (*(int *)arg != 2) { 313 return (ddi_ctlops(dip, dip, ctlop, &rnumber, result)); 314 } 315 316 /* 317 * Handle my child's reg-tuple #2 here by splitting my 16 byte 318 * reg-tuple #4 into two 8 byte ranges based on the 319 * the child's controller #. 320 */ 321 322 tmp = 8; 323 rc = ddi_ctlops(dip, dip, ctlop, &rnumber, &tmp); 324 325 /* 326 * Allow for the possibility of less than 16 bytes by 327 * by checking what's actually returned for my reg-tuple #4. 328 */ 329 if (controller == 1) { 330 if (tmp < 8) 331 tmp = 0; 332 else 333 tmp -= 8; 334 } 335 if (tmp > 8) 336 tmp = 8; 337 *(off_t *)result = tmp; 338 339 return (rc); 340 341 default: 342 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 343 } 344 } 345 346 /* 347 * IEEE 1275 Working Group Proposal #414 says that the Primary 348 * controller is "ata@0" and the Secondary controller "ata@1". 349 * 350 * By the time we get here, boot Bootconf (2.6+) has created devinfo 351 * nodes with the appropriate "reg", "assigned-addresses" and "interrupts" 352 * properites on the pci-ide node and both ide child nodes. 353 * 354 * In compatibility mode the "reg" and "assigned-addresses" properties 355 * of the pci-ide node are set up like this: 356 * 357 * 1. PCI-IDE Nexus 358 * 359 * interrupts=0 360 * (addr-hi addr-mid addr-low size-hi size-low) 361 * reg= assigned-addresses=00000000.00000000.00000000.00000000.00000000 362 * 81000000.00000000.000001f0.00000000.00000008 363 * 81000000.00000000.000003f4.00000000.00000004 364 * 81000000.00000000,00000170.00000000.00000008 365 * 81000000.00000000,00000374.00000000.00000004 366 * 01000020.00000000,-[BAR4]-.00000000.00000010 367 * 368 * In native PCI mode the "reg" and "assigned-addresses" properties 369 * would be set up like this: 370 * 371 * 2. PCI-IDE Nexus 372 * 373 * interrupts=0 374 * reg= assigned-addresses=00000000.00000000.00000000.00000000.00000000 375 * 01000010.00000000.-[BAR0]-.00000000.00000008 376 * 01000014,00000000.-[BAR1]-.00000000.00000004 377 * 01000018.00000000.-[BAR2]-.00000000.00000008 378 * 0100001c.00000000.-[BAR3]-.00000000.00000004 379 * 01000020.00000000.-[BAR4]-.00000000.00000010 380 * 381 * 382 * In both modes the child nodes simply have the following: 383 * 384 * 2. primary controller (compatibility mode) 385 * 386 * interrupts=14 387 * reg=00000000 388 * 389 * 3. secondary controller 390 * 391 * interrupts=15 392 * reg=00000001 393 * 394 * The pciide_bus_map() function is responsible for turning requests 395 * to map primary or secondary controller rnumbers into mapping requests 396 * of the appropriate regspec on the pci-ide node. 397 * 398 */ 399 400 static int 401 pciide_initchild(dev_info_t *mydip, dev_info_t *cdip) 402 { 403 struct ddi_parent_private_data *pdptr; 404 struct intrspec *ispecp; 405 int vec; 406 int *rp; 407 uint_t proplen; 408 char name[80]; 409 int dev; 410 411 PDBG(("pciide_initchild\n")); 412 413 /* 414 * Set the address portion of the node name based on 415 * the controller number (0 or 1) from the 'reg' property. 416 */ 417 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 418 "reg", &rp, (uint_t *)&proplen) != DDI_PROP_SUCCESS) { 419 PDBG(("pciide_intchild prop error\n")); 420 return (DDI_NOT_WELL_FORMED); 421 } 422 423 /* 424 * copy the controller number and 425 * free the memory allocated by ddi_prop_lookup_int_array 426 */ 427 dev = *rp; 428 ddi_prop_free(rp); 429 430 /* 431 * I only support two controllers per device, determine 432 * which this one is and set its unit address. 433 */ 434 if (dev > 1) { 435 PDBG(("pciide_initchild bad dev\n")); 436 return (DDI_NOT_WELL_FORMED); 437 } 438 (void) sprintf(name, "%d", dev); 439 ddi_set_name_addr(cdip, name); 440 441 /* 442 * determine if this instance is running in native or compat mode 443 */ 444 pciide_compat_setup(mydip, cdip, dev); 445 446 /* interrupts property is required */ 447 if (PCIIDE_NATIVE_MODE(cdip)) { 448 vec = 1; 449 } else { 450 /* 451 * In compatibility mode, dev 0 should always be 452 * IRQ 14 and dev 1 is IRQ 15. If for some reason 453 * this needs to be changed, do it via the interrupts 454 * property in the ata.conf file. 455 */ 456 vec = ddi_prop_get_int(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 457 "interrupts", -1); 458 if (vec == -1) { 459 /* setup compatibility mode interrupts */ 460 if (dev == 0) { 461 vec = 14; 462 } else if (dev == 1) { 463 vec = 15; 464 } else { 465 PDBG(("pciide_initchild bad intr\n")); 466 return (DDI_NOT_WELL_FORMED); 467 } 468 } 469 } 470 471 pdptr = kmem_zalloc(PCIIDE_PDSIZE, KM_SLEEP); 472 ispecp = (struct intrspec *)(pdptr + 1); 473 pdptr->par_nintr = 1; 474 pdptr->par_intr = ispecp; 475 ispecp->intrspec_vec = vec; 476 ddi_set_parent_data(cdip, pdptr); 477 478 PDBG(("pciide_initchild okay\n")); 479 return (DDI_SUCCESS); 480 } 481 482 static int 483 pciide_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 484 off_t offset, off_t len, caddr_t *vaddrp) 485 { 486 dev_info_t *pdip; 487 int rnumber = mp->map_obj.rnumber; 488 int controller; 489 int rc; 490 491 PDBG(("pciide_bus_map\n")); 492 493 if (strcmp("0", ddi_get_name_addr(rdip)) == 0) 494 controller = 0; 495 else 496 controller = 1; 497 498 /* 499 * Adjust the rnumbers based on which controller instance 500 * is being mapped; adjust for the 2 tuples per controller. 501 */ 502 503 switch (rnumber) { 504 case 0: 505 case 1: 506 mp->map_obj.rnumber += (controller * 2); 507 break; 508 case 2: 509 /* 510 * split the 16 I/O ports into two 8 port ranges 511 */ 512 mp->map_obj.rnumber = 4; 513 if (offset + len > 8) { 514 PDBG(("pciide_bus_map offset\n")); 515 return (DDI_FAILURE); 516 } 517 if (len == 0) 518 len = 8 - offset; 519 offset += 8 * controller; 520 break; 521 default: 522 PDBG(("pciide_bus_map default\n")); 523 return (DDI_FAILURE); 524 } 525 526 if (PCIIDE_PRE26(dip)) { 527 int old_rnumber; 528 int new_rnumber; 529 530 old_rnumber = mp->map_obj.rnumber; 531 new_rnumber = pciide_pre26_rnumber_map(dip, old_rnumber); 532 PDBG(("pciide rnumber old %d new %d\n", 533 old_rnumber, new_rnumber)); 534 mp->map_obj.rnumber = new_rnumber; 535 } 536 537 /* 538 * Add 1 to skip over the PCI config space tuple 539 */ 540 mp->map_obj.rnumber++; 541 542 543 /* 544 * pass the adjusted request to my parent 545 */ 546 pdip = ddi_get_parent(dip); 547 rc = ((*(DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)) 548 (pdip, dip, mp, offset, len, vaddrp)); 549 550 PDBG(("pciide_bus_map %s\n", rc == DDI_SUCCESS ? "okay" : "!ok")); 551 552 return (rc); 553 } 554 555 556 static struct intrspec * 557 pciide_get_ispec(dev_info_t *dip, dev_info_t *rdip, int inumber) 558 { 559 struct ddi_parent_private_data *ppdptr; 560 561 PDBG(("pciide_get_ispec\n")); 562 563 /* 564 * Native mode PCI-IDE controllers share the parent's 565 * PCI interrupt line. 566 * 567 * Compatibility mode PCI-IDE controllers have their 568 * own intrspec which specifies ISA IRQ 14 or 15. 569 * 570 */ 571 if (PCIIDE_NATIVE_MODE(rdip)) { 572 ddi_intrspec_t is; 573 574 is = pci_intx_get_ispec(dip, dip, inumber); 575 PDBG(("pciide_get_ispec okay\n")); 576 return ((struct intrspec *)is); 577 } 578 579 /* Else compatibility mode, use the ISA IRQ */ 580 if ((ppdptr = ddi_get_parent_data(rdip)) == NULL) { 581 PDBG(("pciide_get_ispec null\n")); 582 return (NULL); 583 } 584 585 /* validate the interrupt number */ 586 if (inumber >= ppdptr->par_nintr) { 587 PDBG(("pciide_get_inum\n")); 588 return (NULL); 589 } 590 591 PDBG(("pciide_get_ispec ok\n")); 592 593 return ((struct intrspec *)&ppdptr->par_intr[inumber]); 594 } 595 596 static int 597 pciide_get_pri(dev_info_t *dip, dev_info_t *rdip, 598 ddi_intr_handle_impl_t *hdlp, int *pri) 599 { 600 struct intrspec *ispecp; 601 int *intpriorities; 602 uint_t num_intpriorities; 603 604 PDBG(("pciide_get_pri\n")); 605 606 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == NULL) { 607 PDBG(("pciide_get_pri null\n")); 608 return (DDI_FAILURE); 609 } 610 611 if (PCIIDE_NATIVE_MODE(rdip)) { 612 *pri = ispecp->intrspec_pri; 613 PDBG(("pciide_get_pri ok\n")); 614 return (DDI_SUCCESS); 615 } 616 617 /* check if the intrspec has been initialized */ 618 if (ispecp->intrspec_pri != 0) { 619 *pri = ispecp->intrspec_pri; 620 PDBG(("pciide_get_pri ok2\n")); 621 return (DDI_SUCCESS); 622 } 623 624 /* Use a default of level 5 */ 625 ispecp->intrspec_pri = 5; 626 627 /* 628 * If there's an interrupt-priorities property, use it to 629 * over-ride the default interrupt priority. 630 */ 631 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, rdip, DDI_PROP_DONTPASS, 632 "interrupt-priorities", &intpriorities, &num_intpriorities) == 633 DDI_PROP_SUCCESS) { 634 if (hdlp->ih_inum < num_intpriorities) 635 ispecp->intrspec_pri = intpriorities[hdlp->ih_inum]; 636 ddi_prop_free(intpriorities); 637 } 638 *pri = ispecp->intrspec_pri; 639 640 PDBG(("pciide_get_pri ok3\n")); 641 642 return (DDI_SUCCESS); 643 } 644 645 static int 646 pciide_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 647 ddi_intr_handle_impl_t *hdlp, void *result) 648 { 649 struct intrspec *ispecp; 650 int rc; 651 int pri = 0; 652 653 PDBG(("pciide_intr_ops: dip %p rdip %p op %x hdlp %p\n", 654 (void *)dip, (void *)rdip, intr_op, (void *)hdlp)); 655 656 switch (intr_op) { 657 case DDI_INTROP_SUPPORTED_TYPES: 658 *(int *)result = DDI_INTR_TYPE_FIXED; 659 break; 660 case DDI_INTROP_GETCAP: 661 *(int *)result = DDI_INTR_FLAG_LEVEL; 662 break; 663 case DDI_INTROP_NINTRS: 664 case DDI_INTROP_NAVAIL: 665 *(int *)result = (!PCIIDE_NATIVE_MODE(rdip)) ? 666 i_ddi_get_intx_nintrs(rdip) : 1; 667 break; 668 case DDI_INTROP_ALLOC: 669 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 670 NULL) 671 return (DDI_FAILURE); 672 *(int *)result = hdlp->ih_scratch1; 673 break; 674 case DDI_INTROP_FREE: 675 break; 676 case DDI_INTROP_GETPRI: 677 if (pciide_get_pri(dip, rdip, hdlp, &pri) != DDI_SUCCESS) { 678 *(int *)result = 0; 679 return (DDI_FAILURE); 680 } 681 *(int *)result = pri; 682 break; 683 case DDI_INTROP_ADDISR: 684 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 685 NULL) 686 return (DDI_FAILURE); 687 ((ihdl_plat_t *)hdlp->ih_private)->ip_ispecp = ispecp; 688 ispecp->intrspec_func = hdlp->ih_cb_func; 689 break; 690 case DDI_INTROP_REMISR: 691 if ((ispecp = pciide_get_ispec(dip, rdip, hdlp->ih_inum)) == 692 NULL) 693 return (DDI_FAILURE); 694 ispecp->intrspec_func = (uint_t (*)()) 0; 695 break; 696 case DDI_INTROP_ENABLE: 697 /* FALLTHRU */ 698 case DDI_INTROP_DISABLE: 699 if (PCIIDE_NATIVE_MODE(rdip)) { 700 rdip = dip; 701 dip = ddi_get_parent(dip); 702 } else { /* get ptr to the root node */ 703 dip = ddi_root_node(); 704 } 705 706 rc = (*(DEVI(dip)->devi_ops->devo_bus_ops->bus_intr_op))(dip, 707 rdip, intr_op, hdlp, result); 708 709 #ifdef DEBUG 710 if (intr_op == DDI_INTROP_ENABLE) { 711 PDBG(("pciide_enable rc=%d", rc)); 712 } else 713 PDBG(("pciide_disable rc=%d", rc)); 714 #endif /* DEBUG */ 715 return (rc); 716 default: 717 return (DDI_FAILURE); 718 } 719 720 return (DDI_SUCCESS); 721 } 722 723 /* 724 * This is one of the places where controller specific setup needs to be 725 * considered. 726 * At this point the controller was already pre-qualified as a known and 727 * supported pciide controller. 728 * Some controllers do not provide PCI_MASS_IDE sub-class code and IDE 729 * programming interface code but rather PCI_MASS_OTHER sub-class code 730 * without any additional data. 731 * For those controllers IDE programming interface cannot be extracted 732 * from PCI class - we assume that they are pci-native type and we fix 733 * the programming interface used by other functions. 734 * The programming interface byte is set to indicate pci-native mode 735 * for both controllers and the Bus Master DMA capabilitiy of the controller. 736 */ 737 static void 738 pciide_compat_setup(dev_info_t *mydip, dev_info_t *cdip, int dev) 739 { 740 int class_code; 741 int rc = DDI_PROP_SUCCESS; 742 743 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, mydip, 744 DDI_PROP_DONTPASS, "class-code", 0); 745 746 if (((class_code & 0x00FF00) >> 8) == PCI_MASS_IDE) { 747 /* 748 * Controller provides PCI_MASS_IDE sub-class code first 749 * (implied IDE programming interface) 750 */ 751 if ((dev == 0 && !(class_code & PCI_IDE_IF_NATIVE_PRI)) || 752 (dev == 1 && !(class_code & PCI_IDE_IF_NATIVE_SEC))) { 753 rc = ddi_prop_update_int(DDI_DEV_T_NONE, cdip, 754 "compatibility-mode", 1); 755 if (rc != DDI_PROP_SUCCESS) 756 cmn_err(CE_WARN, 757 "pciide prop error %d compat-mode", rc); 758 } 759 } else { 760 /* 761 * Pci-ide controllers not providing PCI_MASS_IDE sub-class are 762 * assumed to be of pci-native type and bus master DMA capable. 763 * Programming interface part of the class-code property is 764 * fixed here. 765 */ 766 class_code &= 0x00ffff00; 767 class_code |= PCI_IDE_IF_BM_CAP_MASK | 768 PCI_IDE_IF_NATIVE_PRI | PCI_IDE_IF_NATIVE_SEC; 769 rc = ddi_prop_update_int(DDI_DEV_T_NONE, mydip, 770 "class-code", class_code); 771 if (rc != DDI_PROP_SUCCESS) 772 cmn_err(CE_WARN, 773 "pciide prop error %d class-code", rc); 774 } 775 } 776 777 778 static int 779 pciide_pre26_rnumber_map(dev_info_t *mydip, int rnumber) 780 { 781 int pri_native; 782 int sec_native; 783 int class_code; 784 785 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, mydip, DDI_PROP_DONTPASS, 786 "class-code", 0); 787 788 pri_native = (class_code & PCI_IDE_IF_NATIVE_PRI) ? TRUE : FALSE; 789 sec_native = (class_code & PCI_IDE_IF_NATIVE_SEC) ? TRUE : FALSE; 790 791 return (pciide_map_rnumber(rnumber, pri_native, sec_native)); 792 793 } 794 795 /* 796 * The canonical order of the reg property tuples for the 797 * Base Address Registers is supposed to be: 798 * 799 * primary controller (BAR 0) 800 * primary controller (BAR 1) 801 * secondary controller (BAR 2) 802 * secondary controller (BAR 3) 803 * bus mastering regs (BAR 4) 804 * 805 * For 2.6, bootconf has been fixed to always generate the 806 * reg property (and assigned-addresses property) tuples 807 * in the above order. 808 * 809 * But in releases prior to 2.6 the order varies depending 810 * on whether compatibility or native mode is being used for 811 * each controller. There ends up being four possible 812 * orders: 813 * 814 * BM, P0, P1, S0, S1 primary compatible, secondary compatible 815 * S0, S1, BM, P0, P1 primary compatible, secondary native 816 * P0, P1, BM, S0, S1 primary native, secondary compatible 817 * P0, P1, S0, S1, BM primary native, secondary native 818 * 819 * where: Px is the primary tuples, Sx the secondary tuples, and 820 * B the Bus Master tuple. 821 * 822 * Here's the results for each of the four states: 823 * 824 * 0, 1, 2, 3, 4 825 * 826 * CC 1, 2, 3, 4, 0 827 * CN 3, 4, 0, 1, 2 828 * NC 0, 1, 3, 4, 2 829 * NN 0, 1, 2, 3, 4 830 * 831 * C = compatible(!native) == 0 832 * N = native == 1 833 * 834 * Here's the transformation matrix: 835 */ 836 837 static int pciide_transform[2][2][5] = { 838 /* P S */ 839 /* [C][C] */ +1, +1, +1, +1, -4, 840 /* [C][N] */ +3, +3, -2, -2, -2, 841 /* [N][C] */ +0, +0, +1, +1, -2, 842 /* [N][N] */ +0, +0, +0, +0, +0 843 }; 844 845 846 static int 847 pciide_map_rnumber(int rnumber, int pri_native, int sec_native) 848 { 849 /* transform flags into indexes */ 850 pri_native = pri_native ? 1 : 0; 851 sec_native = sec_native ? 1 : 0; 852 853 rnumber += pciide_transform[pri_native][sec_native][rnumber]; 854 return (rnumber); 855 } 856