1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_hio.h> 28 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 int nxge_param_set_mac(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_ether_usr(p_nxge_t, 90 queue_t *, mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ip_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_fflp_hash_init(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 100 mblk_t *, char *, caddr_t); 101 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 106 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 107 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 108 p_mblk_t, caddr_t); 109 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 118 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 119 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 120 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 121 char *, caddr_t); 122 static int nxge_param_set_npi_debug_flag(p_nxge_t, 123 queue_t *, mblk_t *, char *, caddr_t); 124 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 125 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 126 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 127 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 128 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static void nxge_param_sync(p_nxge_t); 133 134 /* 135 * Global array of Neptune changable parameters. 136 * This array is initialized to correspond to the default 137 * Neptune 4 port configuration. This array would be copied 138 * into each port's parameter structure and modifed per 139 * fcode and nxge.conf configuration. Later, the parameters are 140 * exported to ndd to display and run-time configuration (at least 141 * some of them). 142 * 143 * Parameters with DONT_SHOW are not shown by ndd. 144 * 145 */ 146 147 static nxge_param_t nxge_param_arr[] = { 148 /* 149 * min max value old hw-name conf-name 150 */ 151 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152 0, 999, 1000, 0, "instance", "instance"}, 153 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "main-instance", "main_instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158 0, 3, 0, 0, "function-number", "function_number"}, 159 160 /* Partition Id */ 161 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162 0, 8, 0, 0, "partition-id", "partition_id"}, 163 164 /* Read Write Permission Mode */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167 168 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 169 0, 32, 0, 0, "version", "fw_version"}, 170 171 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "port-mode", "port_mode"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 RXDMA_RCR_PTHRES_DEFAULT, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 #if defined(__i386) 574 cfg_value = 575 (uint32_t *)(int32_t)param_arr[i].value; 576 #else 577 cfg_value = (uint32_t *)param_arr[i].value; 578 #endif 579 for (j = 0; j < prop_len; j++) { 580 cfg_value[j] = int_prop_val[j]; 581 } 582 prop_count = prop_len; 583 param_arr[i].type |= 584 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 585 ddi_prop_free(int_prop_val); 586 } 587 continue; 588 } 589 590 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591 param_arr[i].fcode_name, 592 (int **)&int_prop_val, 593 &prop_len) == DDI_PROP_SUCCESS) { 594 if ((*int_prop_val >= param_arr[i].minimum) && 595 (*int_prop_val <= param_arr[i].maximum)) 596 param_arr[i].value = *int_prop_val; 597 #ifdef NXGE_DEBUG_ERROR 598 else { 599 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600 "nxge%d: 'prom' file parameter error\n", 601 nxgep->instance)); 602 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603 "Parameter keyword '%s'" 604 " is outside valid range\n", 605 param_arr[i].name)); 606 } 607 #endif 608 ddi_prop_free(int_prop_val); 609 } 610 611 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612 param_arr[i].name, 613 (int **)&int_prop_val, 614 &prop_len) == DDI_PROP_SUCCESS) { 615 if ((*int_prop_val >= param_arr[i].minimum) && 616 (*int_prop_val <= param_arr[i].maximum)) 617 param_arr[i].value = *int_prop_val; 618 #ifdef NXGE_DEBUG_ERROR 619 else { 620 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621 "nxge%d: 'conf' file parameter error\n", 622 nxgep->instance)); 623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624 "Parameter keyword '%s'" 625 "is outside valid range\n", 626 param_arr[i].name)); 627 } 628 #endif 629 ddi_prop_free(int_prop_val); 630 } 631 } 632 } 633 634 static int 635 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 636 { 637 int status = B_TRUE; 638 int channel; 639 uint8_t grp; 640 char *prop_name; 641 char *end; 642 uint32_t name_chars; 643 644 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645 "nxge_private_param_register %s", param_arr->name)); 646 647 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 648 return (B_TRUE); 649 650 prop_name = param_arr->name; 651 if (param_arr->type & NXGE_PARAM_RXDMA) { 652 if (strncmp("rxdma_intr", prop_name, 10) == 0) 653 return (B_TRUE); 654 name_chars = strlen("default_grp"); 655 if (strncmp("default_grp", prop_name, name_chars) == 0) { 656 prop_name += name_chars; 657 grp = mi_strtol(prop_name, &end, 10); 658 /* now check if this rdcgrp is in config */ 659 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 660 } 661 name_chars = strlen(prop_name); 662 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 663 return (B_TRUE); 664 } 665 return (B_FALSE); 666 } 667 668 if (param_arr->type & NXGE_PARAM_TXDMA) { 669 name_chars = strlen("txdma"); 670 if (strncmp("txdma", prop_name, name_chars) == 0) { 671 prop_name += name_chars; 672 channel = mi_strtol(prop_name, &end, 10); 673 /* now check if this rdc is in config */ 674 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 675 " nxge_private_param_register: %d", 676 channel)); 677 return (nxge_check_txdma_port_member(nxgep, channel)); 678 } 679 return (B_FALSE); 680 } 681 682 status = B_FALSE; 683 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 684 685 return (status); 686 } 687 688 void 689 nxge_setup_param(p_nxge_t nxgep) 690 { 691 p_nxge_param_t param_arr; 692 int i; 693 pfi_t set_pfi; 694 695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696 697 /* 698 * Make sure the param_instance is set to a valid device instance. 699 */ 700 if (nxge_param_arr[param_instance].value == 1000) 701 nxge_param_arr[param_instance].value = nxgep->instance; 702 703 param_arr = nxgep->param_arr; 704 param_arr[param_instance].value = nxgep->instance; 705 param_arr[param_function_number].value = nxgep->function_num; 706 707 for (i = 0; i < nxgep->param_count; i++) { 708 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709 (nxge_private_param_register(nxgep, 710 ¶m_arr[i]) == B_FALSE)) { 711 param_arr[i].setf = NULL; 712 param_arr[i].getf = NULL; 713 } 714 715 if (param_arr[i].type & NXGE_PARAM_CMPLX) 716 param_arr[i].setf = NULL; 717 718 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 719 param_arr[i].setf = NULL; 720 param_arr[i].getf = NULL; 721 } 722 723 set_pfi = (pfi_t)param_arr[i].setf; 724 725 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 726 set_pfi = NULL; 727 } 728 729 } 730 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 731 } 732 733 void 734 nxge_init_param(p_nxge_t nxgep) 735 { 736 p_nxge_param_t param_arr; 737 int i, alloc_size; 738 uint64_t alloc_count; 739 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 740 /* 741 * Make sure the param_instance is set to a valid device instance. 742 */ 743 if (nxge_param_arr[param_instance].value == 1000) 744 nxge_param_arr[param_instance].value = nxgep->instance; 745 746 param_arr = nxgep->param_arr; 747 if (param_arr == NULL) { 748 param_arr = (p_nxge_param_t) 749 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 750 } 751 752 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 753 param_arr[i] = nxge_param_arr[i]; 754 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 755 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 756 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 757 alloc_size = alloc_count * sizeof (uint64_t); 758 param_arr[i].value = 759 #if defined(__i386) 760 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 761 KM_SLEEP); 762 #else 763 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 764 #endif 765 param_arr[i].old_value = 766 #if defined(__i386) 767 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 768 KM_SLEEP); 769 #else 770 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 771 #endif 772 param_arr[i].type |= 773 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 774 } 775 } 776 777 nxgep->param_arr = param_arr; 778 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 779 780 nxge_param_sync(nxgep); 781 782 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 783 nxgep->param_count)); 784 } 785 786 void 787 nxge_destroy_param(p_nxge_t nxgep) 788 { 789 int i; 790 uint64_t free_size, free_count; 791 792 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 793 794 if (nxgep->param_arr == NULL) 795 return; 796 /* 797 * Make sure the param_instance is set to a valid device instance. 798 */ 799 if (nxge_param_arr[param_instance].value == nxgep->instance) { 800 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 801 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 802 (i != nxgep->instance)) 803 break; 804 } 805 nxge_param_arr[param_instance].value = i; 806 } 807 808 for (i = 0; i < nxgep->param_count; i++) 809 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 810 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 811 free_count = ((nxgep->param_arr[i].type & 812 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 813 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 814 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 815 free_size = sizeof (uint64_t) * free_count; 816 #if defined(__i386) 817 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 818 free_size); 819 #else 820 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 821 #endif 822 #if defined(__i386) 823 KMEM_FREE((void *)(uint32_t) 824 nxgep->param_arr[i].old_value, free_size); 825 #else 826 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 827 free_size); 828 #endif 829 } 830 831 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 832 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 833 } 834 835 /* 836 * Extracts the value from the 'nxge' parameter array and prints the 837 * parameter value. cp points to the required parameter. 838 */ 839 840 /* ARGSUSED */ 841 int 842 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 843 { 844 p_nxge_param_t pa = (p_nxge_param_t)cp; 845 846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 847 "==> nxge_param_get_generic name %s ", pa->name)); 848 849 if (pa->value > 0xffffffff) 850 (void) mi_mpprintf(mp, "%x%x", 851 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 852 else 853 (void) mi_mpprintf(mp, "%x", (int)pa->value); 854 855 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 856 return (0); 857 } 858 859 /* ARGSUSED */ 860 static int 861 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 862 { 863 p_nxge_param_t pa = (p_nxge_param_t)cp; 864 865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 866 867 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 868 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 869 return (0); 870 } 871 872 /* ARGSUSED */ 873 static int 874 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 875 { 876 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 877 878 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 879 nxgep->instance, nxgep->vpd_info.ver); 880 881 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 882 return (0); 883 } 884 885 /* ARGSUSED */ 886 static int 887 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 888 { 889 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 890 891 switch (nxgep->mac.portmode) { 892 case PORT_1G_COPPER: 893 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 894 nxgep->instance, 895 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 896 break; 897 case PORT_1G_FIBER: 898 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 899 nxgep->instance, 900 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 901 break; 902 case PORT_10G_COPPER: 903 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 904 "%s\n", nxgep->instance, 905 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 906 break; 907 case PORT_10G_FIBER: 908 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 909 nxgep->instance, 910 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 911 break; 912 case PORT_10G_SERDES: 913 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 914 "%s\n", nxgep->instance, 915 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 916 break; 917 case PORT_1G_SERDES: 918 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 919 nxgep->instance, 920 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 921 break; 922 case PORT_1G_RGMII_FIBER: 923 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 924 "Fiber %s\n", nxgep->instance, 925 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 926 break; 927 case PORT_HSP_MODE: 928 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 929 "PHY, Currently NOT present\n", nxgep->instance); 930 break; 931 case PORT_10G_TN1010: 932 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 933 " 10G Copper with TN1010 %s\n", nxgep->instance, 934 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 935 break; 936 case PORT_1G_TN1010: 937 (void) mi_mpprintf(mp, "Port mode for nxge%d:" 938 " 1G Copper with TN1010 %s\n", nxgep->instance, 939 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 940 break; 941 default: 942 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 943 nxgep->instance, 944 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 945 break; 946 } 947 948 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 949 nxgep->instance, 950 nxgep->soft_lso_enable ? "enable" : "disable"); 951 952 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 953 return (0); 954 } 955 956 /* ARGSUSED */ 957 int 958 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 959 { 960 961 uint_t print_len, buf_len; 962 p_mblk_t np; 963 964 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 965 int tdc; 966 967 nxge_grp_set_t *set; 968 969 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 970 971 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 972 nxgep->function_num); 973 974 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 975 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 976 return (0); 977 } 978 979 buf_len = buff_alloc_size; 980 mp->b_cont = np; 981 print_len = 0; 982 983 ((mblk_t *)np)->b_wptr += print_len; 984 buf_len -= print_len; 985 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 986 "TDC\t HW TDC\t\n"); 987 ((mblk_t *)np)->b_wptr += print_len; 988 buf_len -= print_len; 989 990 set = &nxgep->tx_set; 991 for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 992 if ((1 << tdc) & set->owned.map) { 993 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 994 buf_len, "%d\n", tdc); 995 ((mblk_t *)np)->b_wptr += print_len; 996 buf_len -= print_len; 997 } 998 } 999 1000 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 1001 return (0); 1002 } 1003 1004 /* ARGSUSED */ 1005 int 1006 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1007 { 1008 uint_t print_len, buf_len; 1009 p_mblk_t np; 1010 int rdc; 1011 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1012 p_nxge_hw_pt_cfg_t p_cfgp; 1013 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1014 p_rx_rcr_rings_t rx_rcr_rings; 1015 p_rx_rcr_ring_t *rcr_rings; 1016 p_rx_rbr_rings_t rx_rbr_rings; 1017 p_rx_rbr_ring_t *rbr_rings; 1018 nxge_grp_set_t *set; 1019 1020 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1021 1022 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1023 nxgep->function_num); 1024 1025 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1026 /* The following may work even if we cannot get a large buf. */ 1027 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1028 return (0); 1029 } 1030 1031 buf_len = buff_alloc_size; 1032 mp->b_cont = np; 1033 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1034 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1035 1036 rx_rcr_rings = nxgep->rx_rcr_rings; 1037 rcr_rings = rx_rcr_rings->rcr_rings; 1038 rx_rbr_rings = nxgep->rx_rbr_rings; 1039 rbr_rings = rx_rbr_rings->rbr_rings; 1040 1041 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1042 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1043 1044 ((mblk_t *)np)->b_wptr += print_len; 1045 buf_len -= print_len; 1046 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1047 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1048 "chunks\t RCR ptr\n"); 1049 1050 ((mblk_t *)np)->b_wptr += print_len; 1051 buf_len -= print_len; 1052 1053 set = &nxgep->rx_set; 1054 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1055 if ((1 << rdc) & set->owned.map) { 1056 print_len = snprintf((char *) 1057 ((mblk_t *)np)->b_wptr, buf_len, 1058 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1059 rdc, 1060 p_dma_cfgp->rcr_timeout[rdc], 1061 p_dma_cfgp->rcr_threshold[rdc], 1062 (void *)rbr_rings[rdc], 1063 rbr_rings[rdc]->num_blocks, (void *)rcr_rings[rdc]); 1064 ((mblk_t *)np)->b_wptr += print_len; 1065 buf_len -= print_len; 1066 } 1067 } 1068 1069 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1070 return (0); 1071 } 1072 1073 /* ARGSUSED */ 1074 int 1075 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1076 p_mblk_t mp, caddr_t cp) 1077 { 1078 uint_t print_len, buf_len; 1079 p_mblk_t np; 1080 int offset, rdc, i, rdc_grp; 1081 p_nxge_rdc_grp_t rdc_grp_p; 1082 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1083 p_nxge_hw_pt_cfg_t p_cfgp; 1084 1085 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1086 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1087 "==> nxge_param_get_rxdma_rdcgrp_info")); 1088 1089 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1090 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1091 1092 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1093 nxgep->function_num); 1094 1095 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1096 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1097 /* The following may work even if we cannot get a large buf. */ 1098 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1099 return (0); 1100 } 1101 1102 buf_len = buff_alloc_size; 1103 mp->b_cont = np; 1104 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1105 "Total RDC Groups\t %d \n" 1106 "default RDC group\t %d\n", 1107 p_cfgp->max_rdc_grpids, 1108 p_cfgp->def_mac_rxdma_grpid); 1109 1110 ((mblk_t *)np)->b_wptr += print_len; 1111 buf_len -= print_len; 1112 1113 for (i = 0; i < NXGE_MAX_RDCS; i++) { 1114 if (p_cfgp->grpids[i]) { 1115 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1116 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1117 buf_len, 1118 "\nRDC Group Info for Group [%d] %d\n" 1119 "RDC Count %d\tstart RDC %d\n" 1120 "RDC Group Population Information" 1121 " (offsets 0 - 15)\n", 1122 i, rdc_grp, rdc_grp_p->max_rdcs, 1123 rdc_grp_p->start_rdc); 1124 1125 ((mblk_t *)np)->b_wptr += print_len; 1126 buf_len -= print_len; 1127 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1128 buf_len, "\n"); 1129 ((mblk_t *)np)->b_wptr += print_len; 1130 buf_len -= print_len; 1131 1132 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1133 print_len = snprintf( 1134 (char *)((mblk_t *)np)->b_wptr, 1135 buf_len, "[%d]=%d ", rdc, 1136 rdc_grp_p->start_rdc + rdc); 1137 ((mblk_t *)np)->b_wptr += print_len; 1138 buf_len -= print_len; 1139 } 1140 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1141 buf_len, "\n"); 1142 ((mblk_t *)np)->b_wptr += print_len; 1143 buf_len -= print_len; 1144 1145 for (offset = 0; offset < 16; offset++) { 1146 print_len = snprintf( 1147 (char *)((mblk_t *)np)->b_wptr, 1148 buf_len, " %c", 1149 rdc_grp_p->map & (1 << offset) ? 1150 '1' : '0'); 1151 ((mblk_t *)np)->b_wptr += print_len; 1152 buf_len -= print_len; 1153 } 1154 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1155 buf_len, "\n"); 1156 ((mblk_t *)np)->b_wptr += print_len; 1157 buf_len -= print_len; 1158 } 1159 } 1160 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1161 "<== nxge_param_get_rxdma_rdcgrp_info")); 1162 return (0); 1163 } 1164 1165 int 1166 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1167 { 1168 p_mblk_t tmp; 1169 1170 tmp = mp; 1171 while (tmp->b_cont) 1172 tmp = tmp->b_cont; 1173 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1174 tmp->b_cont = allocb(1024, BPRI_HI); 1175 tmp = tmp->b_cont; 1176 if (!tmp) 1177 return (ENOMEM); 1178 } 1179 1180 *nmp = tmp; 1181 return (0); 1182 } 1183 1184 1185 /* ARGSUSED */ 1186 int 1187 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1188 char *value, caddr_t cp) 1189 { 1190 char *end; 1191 uint32_t new_value; 1192 p_nxge_param_t pa = (p_nxge_param_t)cp; 1193 1194 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1195 new_value = (uint32_t)mi_strtol(value, &end, 10); 1196 if (end == value || new_value < pa->minimum || 1197 new_value > pa->maximum) { 1198 return (EINVAL); 1199 } 1200 pa->value = new_value; 1201 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1202 return (0); 1203 } 1204 1205 1206 /* ARGSUSED */ 1207 int 1208 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1209 char *value, caddr_t cp) 1210 { 1211 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1212 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1213 return (0); 1214 } 1215 1216 1217 /* ARGSUSED */ 1218 int 1219 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1220 char *value, caddr_t cp) 1221 { 1222 char *end; 1223 uint32_t new_value; 1224 int status = 0; 1225 p_nxge_param_t pa = (p_nxge_param_t)cp; 1226 1227 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1228 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1229 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1230 return (EINVAL); 1231 } 1232 1233 if (pa->value != new_value) { 1234 pa->old_value = pa->value; 1235 pa->value = new_value; 1236 } 1237 1238 if (!nxge_param_link_update(nxgep)) { 1239 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1240 " false ret from nxge_param_link_update")); 1241 status = EINVAL; 1242 } 1243 1244 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1245 return (status); 1246 } 1247 1248 /* ARGSUSED */ 1249 int 1250 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1251 char *value, caddr_t cp) 1252 { 1253 char *end; 1254 uint32_t cfg_value; 1255 p_nxge_param_t pa = (p_nxge_param_t)cp; 1256 1257 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1258 1259 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1260 1261 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1262 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1263 return (EINVAL); 1264 } 1265 1266 if ((pa->value != cfg_value)) { 1267 pa->old_value = pa->value; 1268 pa->value = cfg_value; 1269 nxgep->intr_threshold = pa->value; 1270 } 1271 1272 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1273 return (0); 1274 } 1275 1276 /* ARGSUSED */ 1277 int 1278 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1279 char *value, caddr_t cp) 1280 { 1281 char *end; 1282 uint32_t cfg_value; 1283 p_nxge_param_t pa = (p_nxge_param_t)cp; 1284 1285 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1286 1287 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1288 1289 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1290 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1291 return (EINVAL); 1292 } 1293 1294 if ((pa->value != cfg_value)) { 1295 pa->old_value = pa->value; 1296 pa->value = cfg_value; 1297 nxgep->intr_timeout = pa->value; 1298 } 1299 1300 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1301 return (0); 1302 } 1303 1304 /* ARGSUSED */ 1305 static int 1306 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1307 mblk_t *mp, char *value, caddr_t cp) 1308 { 1309 char *end; 1310 uint32_t status = 0, cfg_value; 1311 p_nxge_param_t pa = (p_nxge_param_t)cp; 1312 uint32_t cfg_it = B_FALSE; 1313 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1314 p_nxge_hw_pt_cfg_t p_cfgp; 1315 uint32_t *val_ptr, *old_val_ptr; 1316 nxge_param_map_t *mac_map; 1317 p_nxge_class_pt_cfg_t p_class_cfgp; 1318 nxge_mv_cfg_t *mac_host_info; 1319 1320 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1321 1322 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1323 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1324 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1325 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1326 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1327 1328 /* 1329 * now do decoding 1330 */ 1331 mac_map = (nxge_param_map_t *)&cfg_value; 1332 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1333 cfg_value, mac_map->param_id, mac_map->map_to)); 1334 1335 if ((mac_map->param_id < p_cfgp->max_macs) && 1336 p_cfgp->grpids[mac_map->map_to]) { 1337 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1338 " nxge_param_set_mac_rdcgrp mapping" 1339 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1340 #if defined(__i386) 1341 val_ptr = (uint32_t *)(uint32_t)pa->value; 1342 #else 1343 val_ptr = (uint32_t *)pa->value; 1344 #endif 1345 #if defined(__i386) 1346 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1347 #else 1348 old_val_ptr = (uint32_t *)pa->old_value; 1349 #endif 1350 if (val_ptr[mac_map->param_id] != cfg_value) { 1351 old_val_ptr[mac_map->param_id] = 1352 val_ptr[mac_map->param_id]; 1353 val_ptr[mac_map->param_id] = cfg_value; 1354 mac_host_info[mac_map->param_id].mpr_npr = 1355 mac_map->pref; 1356 mac_host_info[mac_map->param_id].flag = 1; 1357 mac_host_info[mac_map->param_id].rdctbl = 1358 mac_map->map_to; 1359 cfg_it = B_TRUE; 1360 } 1361 } else { 1362 return (EINVAL); 1363 } 1364 1365 if (cfg_it == B_TRUE) { 1366 status = nxge_logical_mac_assign_rdc_table(nxgep, 1367 (uint8_t)mac_map->param_id); 1368 if (status != NXGE_OK) 1369 return (EINVAL); 1370 } 1371 1372 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1373 return (0); 1374 } 1375 1376 /* ARGSUSED */ 1377 static int 1378 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1379 mblk_t *mp, char *value, caddr_t cp) 1380 { 1381 char *end; 1382 uint32_t status = 0, cfg_value; 1383 p_nxge_param_t pa = (p_nxge_param_t)cp; 1384 uint32_t cfg_it = B_FALSE; 1385 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1386 p_nxge_hw_pt_cfg_t p_cfgp; 1387 uint32_t *val_ptr, *old_val_ptr; 1388 nxge_param_map_t *vmap, *old_map; 1389 p_nxge_class_pt_cfg_t p_class_cfgp; 1390 uint64_t cfgd_vlans; 1391 int i, inc = 0, cfg_position; 1392 nxge_mv_cfg_t *vlan_tbl; 1393 1394 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1395 1396 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1397 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1398 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1399 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1400 1401 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1402 1403 /* now do decoding */ 1404 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1405 NXGE_PARAM_ARRAY_CNT_SHIFT); 1406 1407 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1408 /* 1409 * for now, we process only upto max 1410 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1411 * In the future, we may want to expand 1412 * the storage array and continue 1413 */ 1414 return (EINVAL); 1415 } 1416 1417 vmap = (nxge_param_map_t *)&cfg_value; 1418 if ((vmap->param_id) && 1419 (vmap->param_id < NXGE_MAX_VLANS) && 1420 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1421 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1422 "nxge_param_set_vlan_rdcgrp mapping" 1423 " id %d grp %d", 1424 vmap->param_id, vmap->map_to)); 1425 #if defined(__i386) 1426 val_ptr = (uint32_t *)(uint32_t)pa->value; 1427 #else 1428 val_ptr = (uint32_t *)pa->value; 1429 #endif 1430 #if defined(__i386) 1431 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1432 #else 1433 old_val_ptr = (uint32_t *)pa->old_value; 1434 #endif 1435 1436 /* search to see if this vlan id is already configured */ 1437 for (i = 0; i < cfgd_vlans; i++) { 1438 old_map = (nxge_param_map_t *)&val_ptr[i]; 1439 if ((old_map->param_id == 0) || 1440 (vmap->param_id == old_map->param_id) || 1441 (vlan_tbl[vmap->param_id].flag)) { 1442 cfg_position = i; 1443 break; 1444 } 1445 } 1446 1447 if (cfgd_vlans == 0) { 1448 cfg_position = 0; 1449 inc++; 1450 } 1451 1452 if (i == cfgd_vlans) { 1453 cfg_position = i; 1454 inc++; 1455 } 1456 1457 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1458 "set_vlan_rdcgrp mapping" 1459 " i %d cfgd_vlans %llx position %d ", 1460 i, cfgd_vlans, cfg_position)); 1461 if (val_ptr[cfg_position] != cfg_value) { 1462 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1463 val_ptr[cfg_position] = cfg_value; 1464 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1465 vlan_tbl[vmap->param_id].flag = 1; 1466 vlan_tbl[vmap->param_id].rdctbl = 1467 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1468 cfg_it = B_TRUE; 1469 if (inc) { 1470 cfgd_vlans++; 1471 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1472 pa->type |= (cfgd_vlans << 1473 NXGE_PARAM_ARRAY_CNT_SHIFT); 1474 1475 } 1476 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1477 "after: param_set_vlan_rdcgrp " 1478 " cfg_vlans %llx position %d \n", 1479 cfgd_vlans, cfg_position)); 1480 } 1481 } else { 1482 return (EINVAL); 1483 } 1484 1485 if (cfg_it == B_TRUE) { 1486 status = nxge_fflp_config_vlan_table(nxgep, 1487 (uint16_t)vmap->param_id); 1488 if (status != NXGE_OK) 1489 return (EINVAL); 1490 } 1491 1492 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1493 return (0); 1494 } 1495 1496 /* ARGSUSED */ 1497 static int 1498 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1499 mblk_t *mp, caddr_t cp) 1500 { 1501 1502 uint_t print_len, buf_len; 1503 p_mblk_t np; 1504 int i; 1505 uint32_t *val_ptr; 1506 nxge_param_map_t *vmap; 1507 p_nxge_param_t pa = (p_nxge_param_t)cp; 1508 p_nxge_class_pt_cfg_t p_class_cfgp; 1509 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1510 p_nxge_hw_pt_cfg_t p_cfgp; 1511 uint64_t cfgd_vlans = 0; 1512 nxge_mv_cfg_t *vlan_tbl; 1513 int buff_alloc_size = 1514 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1515 1516 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1517 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1518 nxgep->function_num); 1519 1520 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1521 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1522 return (0); 1523 } 1524 1525 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1526 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1527 1528 buf_len = buff_alloc_size; 1529 mp->b_cont = np; 1530 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1531 NXGE_PARAM_ARRAY_CNT_SHIFT; 1532 1533 i = (int)cfgd_vlans; 1534 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1535 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1536 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1537 "Configured VLANs %d\n" 1538 "VLAN ID\t RDC GRP (Actual/Port)\t" 1539 " Prefernce\n", i); 1540 ((mblk_t *)np)->b_wptr += print_len; 1541 buf_len -= print_len; 1542 #if defined(__i386) 1543 val_ptr = (uint32_t *)(uint32_t)pa->value; 1544 #else 1545 val_ptr = (uint32_t *)pa->value; 1546 #endif 1547 1548 for (i = 0; i < cfgd_vlans; i++) { 1549 vmap = (nxge_param_map_t *)&val_ptr[i]; 1550 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1551 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1552 buf_len, 1553 " %d\t\t %d/%d\t\t %d\n", 1554 vmap->param_id, 1555 vlan_tbl[vmap->param_id].rdctbl, 1556 vlan_tbl[vmap->param_id].rdctbl - 1557 p_cfgp->def_mac_rxdma_grpid, 1558 vlan_tbl[vmap->param_id].mpr_npr); 1559 ((mblk_t *)np)->b_wptr += print_len; 1560 buf_len -= print_len; 1561 } 1562 } 1563 1564 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1565 return (0); 1566 } 1567 1568 /* ARGSUSED */ 1569 static int 1570 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1571 mblk_t *mp, caddr_t cp) 1572 { 1573 uint_t print_len, buf_len; 1574 p_mblk_t np; 1575 int i; 1576 p_nxge_class_pt_cfg_t p_class_cfgp; 1577 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1578 p_nxge_hw_pt_cfg_t p_cfgp; 1579 nxge_mv_cfg_t *mac_host_info; 1580 1581 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1582 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1583 (void) mi_mpprintf(mp, 1584 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1585 nxgep->function_num); 1586 1587 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1588 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1589 return (0); 1590 } 1591 1592 buf_len = buff_alloc_size; 1593 mp->b_cont = np; 1594 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1595 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1596 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1597 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1598 print_len = snprintf((char *)np->b_wptr, buf_len, 1599 "MAC ID\t RDC GRP (Actual/Port)\t" 1600 " Prefernce\n"); 1601 ((mblk_t *)np)->b_wptr += print_len; 1602 buf_len -= print_len; 1603 for (i = 0; i < p_cfgp->max_macs; i++) { 1604 if (mac_host_info[i].flag) { 1605 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1606 buf_len, 1607 " %d\t %d/%d\t\t %d\n", 1608 i, mac_host_info[i].rdctbl, 1609 mac_host_info[i].rdctbl - 1610 p_cfgp->def_mac_rxdma_grpid, 1611 mac_host_info[i].mpr_npr); 1612 ((mblk_t *)np)->b_wptr += print_len; 1613 buf_len -= print_len; 1614 } 1615 } 1616 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1617 "Done Info Dumping \n"); 1618 ((mblk_t *)np)->b_wptr += print_len; 1619 buf_len -= print_len; 1620 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1621 return (0); 1622 } 1623 1624 /* ARGSUSED */ 1625 static int 1626 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1627 mblk_t *mp, char *value, caddr_t cp) 1628 { 1629 uint32_t status = 0, cfg_value; 1630 p_nxge_param_t pa = (p_nxge_param_t)cp; 1631 uint32_t cfg_it = B_FALSE; 1632 char *end; 1633 1634 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1635 1636 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1637 if (pa->value != cfg_value) { 1638 pa->old_value = pa->value; 1639 pa->value = cfg_value; 1640 cfg_it = B_TRUE; 1641 } 1642 1643 if (cfg_it == B_TRUE) { 1644 if (pa->value) 1645 status = nxge_fflp_config_tcam_enable(nxgep); 1646 else 1647 status = nxge_fflp_config_tcam_disable(nxgep); 1648 if (status != NXGE_OK) 1649 return (EINVAL); 1650 } 1651 1652 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1653 return (0); 1654 } 1655 1656 /* ARGSUSED */ 1657 static int 1658 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1659 mblk_t *mp, char *value, caddr_t cp) 1660 { 1661 uint32_t status = 0, cfg_value; 1662 p_nxge_param_t pa = (p_nxge_param_t)cp; 1663 uint32_t cfg_it = B_FALSE; 1664 char *end; 1665 1666 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1667 1668 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1669 if (pa->value != cfg_value) { 1670 pa->old_value = pa->value; 1671 pa->value = cfg_value; 1672 cfg_it = B_TRUE; 1673 } 1674 1675 if (cfg_it == B_TRUE) { 1676 if (pa->value) 1677 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1678 else 1679 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1680 if (status != NXGE_OK) 1681 return (EINVAL); 1682 } 1683 1684 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1685 return (0); 1686 } 1687 1688 /* ARGSUSED */ 1689 static int 1690 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1691 mblk_t *mp, char *value, caddr_t cp) 1692 { 1693 char *end; 1694 uint32_t status = 0, cfg_value; 1695 p_nxge_param_t pa = (p_nxge_param_t)cp; 1696 uint32_t cfg_it = B_FALSE; 1697 1698 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1699 1700 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1701 if (pa->value != cfg_value) { 1702 pa->old_value = pa->value; 1703 pa->value = cfg_value; 1704 cfg_it = B_TRUE; 1705 } 1706 1707 if (cfg_it == B_TRUE) { 1708 if (pa->value) 1709 status = nxge_fflp_config_tcam_enable(nxgep); 1710 else 1711 status = nxge_fflp_config_tcam_disable(nxgep); 1712 if (status != NXGE_OK) 1713 return (EINVAL); 1714 } 1715 1716 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1717 return (0); 1718 } 1719 1720 /* ARGSUSED */ 1721 static int 1722 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1723 mblk_t *mp, char *value, caddr_t cp) 1724 { 1725 char *end; 1726 uint8_t ether_class; 1727 uint32_t status = 0, cfg_value; 1728 p_nxge_param_t pa = (p_nxge_param_t)cp; 1729 uint8_t cfg_it = B_FALSE; 1730 1731 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1732 1733 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1734 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1735 return (EINVAL); 1736 } 1737 1738 if (pa->value != cfg_value) { 1739 pa->old_value = pa->value; 1740 pa->value = cfg_value; 1741 cfg_it = B_TRUE; 1742 } 1743 1744 /* do the actual hw setup */ 1745 if (cfg_it == B_TRUE) { 1746 ether_class = mi_strtol(pa->name, &end, 10); 1747 #ifdef lint 1748 ether_class = ether_class; 1749 #endif 1750 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1751 } 1752 1753 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1754 return (status); 1755 } 1756 1757 /* ARGSUSED */ 1758 static int 1759 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1760 mblk_t *mp, char *value, caddr_t cp) 1761 { 1762 char *end; 1763 tcam_class_t class; 1764 uint32_t status, cfg_value; 1765 p_nxge_param_t pa = (p_nxge_param_t)cp; 1766 uint32_t cfg_it = B_FALSE; 1767 1768 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1769 1770 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1771 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1772 return (EINVAL); 1773 } 1774 1775 if (pa->value != cfg_value) { 1776 pa->old_value = pa->value; 1777 pa->value = cfg_value; 1778 cfg_it = B_TRUE; 1779 } 1780 1781 /* do the actual hw setup with cfg_value. */ 1782 if (cfg_it == B_TRUE) { 1783 class = mi_strtol(pa->name, &end, 10); 1784 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1785 } 1786 1787 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1788 return (status); 1789 } 1790 1791 /* ARGSUSED */ 1792 static int 1793 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1794 { 1795 int i; 1796 int class_instance = param_class_opt_ip_usr4; 1797 p_nxge_param_t param_arr; 1798 1799 param_arr = nxgep->param_arr; 1800 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1801 if (strcmp(param_arr[class_instance].name, name) == 0) 1802 return (i); 1803 class_instance++; 1804 } 1805 return (-1); 1806 } 1807 1808 /* ARGSUSED */ 1809 int 1810 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1811 mblk_t *mp, char *value, caddr_t cp) 1812 { 1813 char *end; 1814 uint32_t status, cfg_value; 1815 p_nxge_param_t pa = (p_nxge_param_t)cp; 1816 tcam_class_t class; 1817 uint32_t cfg_it = B_FALSE; 1818 1819 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1820 1821 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1822 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1823 return (EINVAL); 1824 } 1825 1826 if (pa->value != cfg_value) { 1827 pa->old_value = pa->value; 1828 pa->value = cfg_value; 1829 cfg_it = B_TRUE; 1830 } 1831 1832 if (cfg_it == B_TRUE) { 1833 /* do the actual hw setup */ 1834 class = nxge_class_name_2value(nxgep, pa->name); 1835 if (class == -1) 1836 return (EINVAL); 1837 1838 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1839 if (status != NXGE_OK) 1840 return (EINVAL); 1841 } 1842 1843 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1844 return (0); 1845 } 1846 1847 /* ARGSUSED */ 1848 static int 1849 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1850 mblk_t *mp, caddr_t cp) 1851 { 1852 uint32_t status, cfg_value; 1853 p_nxge_param_t pa = (p_nxge_param_t)cp; 1854 tcam_class_t class; 1855 1856 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1857 1858 /* do the actual hw setup */ 1859 class = nxge_class_name_2value(nxgep, pa->name); 1860 if (class == -1) 1861 return (EINVAL); 1862 1863 cfg_value = 0; 1864 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1865 if (status != NXGE_OK) 1866 return (EINVAL); 1867 1868 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1869 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1870 1871 pa->value = cfg_value; 1872 (void) mi_mpprintf(mp, "%x", cfg_value); 1873 1874 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1875 return (0); 1876 } 1877 1878 /* ARGSUSED */ 1879 static int 1880 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1881 mblk_t *mp, char *value, caddr_t cp) 1882 { 1883 char *end; 1884 uint32_t status, cfg_value; 1885 p_nxge_param_t pa = (p_nxge_param_t)cp; 1886 tcam_class_t class; 1887 uint32_t cfg_it = B_FALSE; 1888 1889 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1890 1891 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1892 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1893 return (EINVAL); 1894 } 1895 1896 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1897 "nxge_param_fflp_hash_init value %x", cfg_value)); 1898 1899 if (pa->value != cfg_value) { 1900 pa->old_value = pa->value; 1901 pa->value = cfg_value; 1902 cfg_it = B_TRUE; 1903 } 1904 1905 if (cfg_it == B_TRUE) { 1906 char *h_name; 1907 1908 /* do the actual hw setup */ 1909 h_name = pa->name; 1910 h_name++; 1911 class = mi_strtol(h_name, &end, 10); 1912 switch (class) { 1913 case 1: 1914 status = nxge_fflp_set_hash1(nxgep, 1915 (uint32_t)pa->value); 1916 break; 1917 case 2: 1918 status = nxge_fflp_set_hash2(nxgep, 1919 (uint16_t)pa->value); 1920 break; 1921 1922 default: 1923 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1924 " nxge_param_fflp_hash_init" 1925 " %s Wrong hash var %d", 1926 pa->name, class)); 1927 return (EINVAL); 1928 } 1929 if (status != NXGE_OK) 1930 return (EINVAL); 1931 } 1932 1933 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1934 return (0); 1935 } 1936 1937 /* ARGSUSED */ 1938 static int 1939 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1940 mblk_t *mp, char *value, caddr_t cp) 1941 { 1942 char *end; 1943 uint32_t status = 0, cfg_value; 1944 p_nxge_param_t pa = (p_nxge_param_t)cp; 1945 uint32_t cfg_it = B_FALSE; 1946 int rdc_grp; 1947 uint8_t real_rdc; 1948 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1949 p_nxge_hw_pt_cfg_t p_cfgp; 1950 p_nxge_rdc_grp_t rdc_grp_p; 1951 1952 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1953 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1954 1955 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1956 1957 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1958 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1959 return (EINVAL); 1960 } 1961 1962 if (cfg_value >= p_cfgp->max_rdcs) { 1963 return (EINVAL); 1964 } 1965 1966 if (pa->value != cfg_value) { 1967 pa->old_value = pa->value; 1968 pa->value = cfg_value; 1969 cfg_it = B_TRUE; 1970 } 1971 1972 if (cfg_it == B_TRUE) { 1973 char *grp_name; 1974 grp_name = pa->name; 1975 grp_name += strlen("default-grp"); 1976 rdc_grp = mi_strtol(grp_name, &end, 10); 1977 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1978 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1979 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1980 cfg_value) == B_FALSE) { 1981 pa->value = pa->old_value; 1982 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1983 " nxge_param_set_grp_rdc" 1984 " %d read %d actual %d outof range", 1985 rdc_grp, cfg_value, real_rdc)); 1986 return (EINVAL); 1987 } 1988 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1989 real_rdc); 1990 if (status != NXGE_OK) 1991 return (EINVAL); 1992 } 1993 1994 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1995 return (0); 1996 } 1997 1998 /* ARGSUSED */ 1999 static int 2000 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2001 mblk_t *mp, char *value, caddr_t cp) 2002 { 2003 char *end; 2004 uint32_t status = B_TRUE, cfg_value; 2005 p_nxge_param_t pa = (p_nxge_param_t)cp; 2006 uint32_t cfg_it = B_FALSE; 2007 2008 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2009 p_nxge_hw_pt_cfg_t p_cfgp; 2010 2011 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2012 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2013 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2014 2015 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2016 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2017 return (EINVAL); 2018 } 2019 2020 if (pa->value != cfg_value) { 2021 if (cfg_value >= p_cfgp->max_rdcs) 2022 return (EINVAL); 2023 pa->old_value = pa->value; 2024 pa->value = cfg_value; 2025 cfg_it = B_TRUE; 2026 } 2027 2028 if (cfg_it == B_TRUE) { 2029 int rdc; 2030 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2031 return (EINVAL); 2032 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2033 nxgep->function_num, rdc); 2034 if (status != NXGE_OK) 2035 return (EINVAL); 2036 } 2037 2038 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2039 return (0); 2040 } 2041 2042 /* ARGSUSED */ 2043 static int 2044 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2045 mblk_t *mp, char *value, caddr_t cp) 2046 { 2047 char *end; 2048 uint32_t status = 0; 2049 uint64_t cfg_value = 0; 2050 p_nxge_param_t pa = (p_nxge_param_t)cp; 2051 uint32_t cfg_it = B_FALSE; 2052 2053 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2054 cfg_value = mi_strtol(value, &end, BASE_HEX); 2055 2056 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2057 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2058 " nxge_param_set_nxge_debug_flag" 2059 " outof range %llx", cfg_value)); 2060 return (EINVAL); 2061 } 2062 if (pa->value != cfg_value) { 2063 pa->old_value = pa->value; 2064 pa->value = cfg_value; 2065 cfg_it = B_TRUE; 2066 } 2067 2068 if (cfg_it == B_TRUE) { 2069 nxgep->nxge_debug_level = pa->value; 2070 } 2071 2072 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2073 return (status); 2074 } 2075 2076 /* ARGSUSED */ 2077 static int 2078 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2079 { 2080 int status = 0; 2081 p_nxge_param_t pa = (p_nxge_param_t)cp; 2082 2083 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2084 2085 if (pa->value > 0xffffffff) 2086 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2087 (int)(pa->value & 0xffffffff)); 2088 else 2089 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2090 2091 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2092 return (status); 2093 } 2094 2095 /* ARGSUSED */ 2096 static int 2097 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2098 mblk_t *mp, char *value, caddr_t cp) 2099 { 2100 char *end; 2101 uint32_t status = 0; 2102 uint64_t cfg_value = 0; 2103 p_nxge_param_t pa; 2104 uint32_t cfg_it = B_FALSE; 2105 2106 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2107 cfg_value = mi_strtol(value, &end, BASE_HEX); 2108 pa = (p_nxge_param_t)cp; 2109 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2110 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2111 " outof range %llx", cfg_value)); 2112 return (EINVAL); 2113 } 2114 if (pa->value != cfg_value) { 2115 pa->old_value = pa->value; 2116 pa->value = cfg_value; 2117 cfg_it = B_TRUE; 2118 } 2119 2120 if (cfg_it == B_TRUE) { 2121 npi_debug_level = pa->value; 2122 } 2123 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2124 return (status); 2125 } 2126 2127 /* ARGSUSED */ 2128 static int 2129 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2130 { 2131 nxge_grp_set_t *set = &nxgep->rx_set; 2132 int rdc; 2133 2134 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2135 2136 if (!isLDOMguest(nxgep)) 2137 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2138 2139 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2140 if ((1 << rdc) & set->owned.map) { 2141 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2142 } 2143 } 2144 2145 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2146 return (0); 2147 } 2148 2149 /* ARGSUSED */ 2150 static int 2151 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2152 { 2153 nxge_grp_set_t *set = &nxgep->tx_set; 2154 int tdc; 2155 2156 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2157 2158 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2159 if ((1 << tdc) & set->owned.map) { 2160 (void) nxge_txdma_regs_dump(nxgep, tdc); 2161 } 2162 } 2163 2164 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2165 return (0); 2166 } 2167 2168 /* ARGSUSED */ 2169 static int 2170 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2171 { 2172 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2173 2174 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2175 2176 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2177 return (0); 2178 } 2179 2180 /* ARGSUSED */ 2181 static int 2182 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2183 { 2184 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2185 2186 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2187 nxgep->function_num); 2188 2189 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2190 return (0); 2191 } 2192 2193 /* ARGSUSED */ 2194 static int 2195 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2196 { 2197 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2198 2199 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2200 nxgep->function_num); 2201 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2202 return (0); 2203 } 2204 2205 /* ARGSUSED */ 2206 static int 2207 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2208 { 2209 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2210 2211 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2212 2213 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2214 return (0); 2215 } 2216 2217 /* ARGSUSED */ 2218 static int 2219 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2220 { 2221 uint8_t table; 2222 2223 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2224 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2225 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2226 table); 2227 } 2228 2229 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2230 return (0); 2231 } 2232 2233 typedef struct block_info { 2234 char *name; 2235 uint32_t offset; 2236 } block_info_t; 2237 2238 block_info_t reg_block[] = { 2239 {"PIO", PIO}, 2240 {"FZC_PIO", FZC_PIO}, 2241 {"FZC_XMAC", FZC_MAC}, 2242 {"FZC_IPP", FZC_IPP}, 2243 {"FFLP", FFLP}, 2244 {"FZC_FFLP", FZC_FFLP}, 2245 {"PIO_VADDR", PIO_VADDR}, 2246 {"ZCP", ZCP}, 2247 {"FZC_ZCP", FZC_ZCP}, 2248 {"DMC", DMC}, 2249 {"FZC_DMC", FZC_DMC}, 2250 {"TXC", TXC}, 2251 {"FZC_TXC", FZC_TXC}, 2252 {"PIO_LDSV", PIO_LDSV}, 2253 {"PIO_LDGIM", PIO_LDGIM}, 2254 {"PIO_IMASK0", PIO_IMASK0}, 2255 {"PIO_IMASK1", PIO_IMASK1}, 2256 {"FZC_PROM", FZC_PROM}, 2257 {"END", ALL_FF_32}, 2258 }; 2259 2260 /* ARGSUSED */ 2261 static int 2262 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2263 { 2264 uint_t print_len, buf_len; 2265 p_mblk_t np; 2266 int rdc, tdc, block; 2267 uint64_t base; 2268 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2269 p_nxge_hw_pt_cfg_t p_cfgp; 2270 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2271 p_tx_ring_t *tx_rings; 2272 p_rx_rcr_rings_t rx_rcr_rings; 2273 p_rx_rcr_ring_t *rcr_rings; 2274 p_rx_rbr_rings_t rx_rbr_rings; 2275 p_rx_rbr_ring_t *rbr_rings; 2276 2277 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2278 "==> nxge_param_dump_ptrs")); 2279 2280 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2281 nxgep->function_num); 2282 2283 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2284 /* The following may work even if we cannot get a large buf. */ 2285 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2286 return (0); 2287 } 2288 2289 buf_len = buff_alloc_size; 2290 mp->b_cont = np; 2291 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2292 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2293 2294 rx_rcr_rings = nxgep->rx_rcr_rings; 2295 rcr_rings = rx_rcr_rings->rcr_rings; 2296 rx_rbr_rings = nxgep->rx_rbr_rings; 2297 rbr_rings = rx_rbr_rings->rbr_rings; 2298 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2299 "nxgep (nxge_t) $%p\n" 2300 "dev_regs (dev_regs_t) $%p\n", 2301 (void *)nxgep, (void *)nxgep->dev_regs); 2302 2303 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2304 2305 /* do register pointers */ 2306 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2307 "reg base (npi_reg_ptr_t) $%p\t " 2308 "pci reg (npi_reg_ptr_t) $%p\n", 2309 (void *)nxgep->dev_regs->nxge_regp, 2310 (void *)nxgep->dev_regs->nxge_pciregp); 2311 2312 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2313 2314 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2315 "\nBlock \t Offset \n"); 2316 2317 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2318 block = 0; 2319 #if defined(__i386) 2320 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2321 #else 2322 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2323 #endif 2324 while (reg_block[block].offset != ALL_FF_32) { 2325 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2326 "%9s\t 0x%llx\n", 2327 reg_block[block].name, 2328 (unsigned long long)(reg_block[block].offset + base)); 2329 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2330 block++; 2331 } 2332 2333 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2334 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2335 "rbrp (rx_rbr_ring_t)\n"); 2336 2337 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2338 2339 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2340 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2341 " %d\t $%p\t\t $%p\n", 2342 rdc, (void *)rcr_rings[rdc], 2343 (void *)rbr_rings[rdc]); 2344 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2345 } 2346 2347 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2348 "\nTDC\t tdcp (tx_ring_t)\n"); 2349 2350 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2351 tx_rings = nxgep->tx_rings->rings; 2352 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2353 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2354 " %d\t $%p\n", tdc, (void *)tx_rings[tdc]); 2355 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2356 } 2357 2358 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2359 2360 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2361 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2362 return (0); 2363 } 2364 2365 2366 /* ARGSUSED */ 2367 int 2368 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2369 { 2370 ND *nd; 2371 NDE *nde; 2372 char *rwtag; 2373 boolean_t get_ok, set_ok; 2374 size_t param_len; 2375 int status = 0; 2376 2377 nd = (ND *)param; 2378 if (!nd) 2379 return (ENOENT); 2380 2381 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2382 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2383 (nde->nde_get_pfi != NULL); 2384 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2385 (nde->nde_set_pfi != NULL); 2386 if (get_ok) { 2387 if (set_ok) 2388 rwtag = "read and write"; 2389 else 2390 rwtag = "read only"; 2391 } else if (set_ok) 2392 rwtag = "write only"; 2393 else { 2394 continue; 2395 } 2396 param_len = strlen(rwtag); 2397 param_len += strlen(nde->nde_name); 2398 param_len += 4; 2399 2400 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2401 } 2402 return (status); 2403 } 2404 2405 /* ARGSUSED */ 2406 int 2407 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2408 { 2409 return (EACCES); 2410 } 2411 2412 /* ARGSUSED */ 2413 int 2414 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2415 caddr_t data) 2416 { 2417 return (EACCES); 2418 } 2419 2420 boolean_t 2421 nxge_param_link_update(p_nxge_t nxgep) 2422 { 2423 p_nxge_param_t param_arr; 2424 nxge_param_index_t i; 2425 boolean_t update_xcvr; 2426 boolean_t update_dev; 2427 int instance; 2428 boolean_t status = B_TRUE; 2429 2430 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2431 2432 param_arr = nxgep->param_arr; 2433 instance = nxgep->instance; 2434 update_xcvr = B_FALSE; 2435 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2436 update_xcvr |= param_arr[i].value; 2437 } 2438 2439 if (update_xcvr) { 2440 update_xcvr = B_FALSE; 2441 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2442 update_xcvr |= 2443 (param_arr[i].value != param_arr[i].old_value); 2444 param_arr[i].old_value = param_arr[i].value; 2445 } 2446 if (update_xcvr) { 2447 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2448 "==> nxge_param_link_update: update xcvr")); 2449 RW_ENTER_WRITER(&nxgep->filter_lock); 2450 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2451 (void) nxge_link_init(nxgep); 2452 (void) nxge_mac_init(nxgep); 2453 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2454 RW_EXIT(&nxgep->filter_lock); 2455 } 2456 } else { 2457 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2458 " no link capabilities.", instance); 2459 cmn_err(CE_WARN, " Restoring previous setting."); 2460 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2461 param_arr[i].value = param_arr[i].old_value; 2462 } 2463 2464 update_dev = B_FALSE; 2465 2466 if (update_dev) { 2467 RW_ENTER_WRITER(&nxgep->filter_lock); 2468 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2469 "==> nxge_param_link_update: update dev")); 2470 (void) nxge_rx_mac_disable(nxgep); 2471 (void) nxge_tx_mac_disable(nxgep); 2472 (void) nxge_tx_mac_enable(nxgep); 2473 (void) nxge_rx_mac_enable(nxgep); 2474 RW_EXIT(&nxgep->filter_lock); 2475 } 2476 2477 nxge_param_hw_update_exit: 2478 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2479 "<== nxge_param_link_update status = 0x%08x", status)); 2480 return (status); 2481 } 2482 2483 /* 2484 * synchronize the adv* and en* parameters. 2485 * 2486 * See comments in <sys/dld.h> for details of the *_en_* 2487 * parameters. The usage of ndd for setting adv parameters will 2488 * synchronize all the en parameters with the nxge parameters, 2489 * implicitly disabling any settings made via dladm. 2490 */ 2491 static void 2492 nxge_param_sync(p_nxge_t nxgep) 2493 { 2494 p_nxge_param_t param_arr; 2495 param_arr = nxgep->param_arr; 2496 2497 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2498 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2499 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2500 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2501 } 2502 2503 /* ARGSUSED */ 2504 int 2505 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2506 { 2507 uint32_t status, cfg_value; 2508 p_nxge_param_t pa = (p_nxge_param_t)cp; 2509 tcam_class_t class; 2510 2511 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2512 2513 /* do the actual hw setup */ 2514 class = nxge_class_name_2value(nxgep, pa->name); 2515 if (class == -1) 2516 return (EINVAL); 2517 2518 cfg_value = 0; 2519 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2520 if (status != NXGE_OK) 2521 return (EINVAL); 2522 2523 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2524 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2525 2526 pa->value = cfg_value; 2527 2528 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2529 return (0); 2530 } 2531