1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2007, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Copyright (c) 2006 13 * Copyright (c) 2007 14 * Damien Bergamini <damien.bergamini@free.fr> 15 * 16 * Permission to use, copy, modify, and distribute this software for any 17 * purpose with or without fee is hereby granted, provided that the above 18 * copyright notice and this permission notice appear in all copies. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 21 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 23 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 24 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 25 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 26 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 27 */ 28 29 #ifndef _IWK_VAR_H 30 #define _IWK_VAR_H 31 32 #pragma ident "%Z%%M% %I% %E% SMI" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #define IWK_DMA_SYNC(area, flag) \ 39 (void) ddi_dma_sync((area).dma_hdl, (area).offset, \ 40 (area).alength, (flag)) 41 42 typedef struct iwk_dma_area { 43 ddi_acc_handle_t acc_hdl; /* handle for memory */ 44 caddr_t mem_va; /* CPU VA of memory */ 45 uint32_t nslots; /* number of slots */ 46 uint32_t size; /* size per slot */ 47 size_t alength; /* allocated size */ 48 /* >= product of above */ 49 ddi_dma_handle_t dma_hdl; /* DMA handle */ 50 offset_t offset; /* relative to handle */ 51 ddi_dma_cookie_t cookie; /* associated cookie */ 52 uint32_t ncookies; 53 uint32_t token; /* arbitrary identifier */ 54 } iwk_dma_t; 55 56 typedef struct iwk_tx_data { 57 iwk_dma_t dma_data; 58 iwk_tx_desc_t *desc; 59 uint32_t paddr_desc; 60 iwk_cmd_t *cmd; 61 uint32_t paddr_cmd; 62 } iwk_tx_data_t; 63 64 typedef struct iwk_tx_ring { 65 iwk_dma_t dma_desc; 66 iwk_dma_t dma_cmd; 67 iwk_tx_data_t *data; 68 int qid; 69 int count; 70 int window; 71 int queued; 72 int cur; 73 } iwk_tx_ring_t; 74 75 typedef struct iwk_rx_data { 76 iwk_dma_t dma_data; 77 } iwk_rx_data_t; 78 79 typedef struct iwk_rx_ring { 80 iwk_dma_t dma_desc; 81 uint32_t *desc; 82 iwk_rx_data_t data[RX_QUEUE_SIZE]; 83 int cur; 84 } iwk_rx_ring_t; 85 86 typedef struct iwk_amrr { 87 ieee80211_node_t in; /* must be the first */ 88 int txcnt; 89 int retrycnt; 90 int success; 91 int success_threshold; 92 int recovery; 93 } iwk_amrr_t; 94 95 typedef struct iwk_softc { 96 struct ieee80211com sc_ic; 97 dev_info_t *sc_dip; 98 int (*sc_newstate)(struct ieee80211com *, 99 enum ieee80211_state, int); 100 enum ieee80211_state sc_ostate; 101 kmutex_t sc_glock; 102 kmutex_t sc_mt_lock; 103 kmutex_t sc_tx_lock; 104 kcondvar_t sc_mt_cv; 105 kcondvar_t sc_tx_cv; 106 kcondvar_t sc_cmd_cv; 107 kcondvar_t sc_fw_cv; 108 109 kthread_t *sc_mf_thread; 110 uint32_t sc_mf_thread_switch; 111 112 uint32_t sc_flags; 113 uint32_t sc_dmabuf_sz; 114 uint16_t sc_clsz; 115 uint8_t sc_rev; 116 uint8_t sc_resv; 117 uint16_t sc_assoc_id; 118 uint16_t sc_reserved0; 119 120 /* shared area */ 121 iwk_dma_t sc_dma_sh; 122 iwk_shared_t *sc_shared; 123 /* keep warm area */ 124 iwk_dma_t sc_dma_kw; 125 /* tx scheduler base address */ 126 uint32_t sc_scd_base_addr; 127 128 iwk_tx_ring_t sc_txq[IWK_NUM_QUEUES]; 129 iwk_rx_ring_t sc_rxq; 130 131 /* firmware dma */ 132 iwk_firmware_hdr_t *sc_hdr; 133 char *sc_boot; 134 iwk_dma_t sc_dma_fw_text; 135 iwk_dma_t sc_dma_fw_init_text; 136 iwk_dma_t sc_dma_fw_data; 137 iwk_dma_t sc_dma_fw_data_bak; 138 iwk_dma_t sc_dma_fw_init_data; 139 140 ddi_acc_handle_t sc_cfg_handle; 141 caddr_t sc_cfg_base; 142 ddi_acc_handle_t sc_handle; 143 caddr_t sc_base; 144 ddi_iblock_cookie_t sc_iblk; 145 146 iwk_rxon_cmd_t sc_config; 147 struct iwk_eep sc_eep_map; /* eeprom map */ 148 uint32_t sc_scd_base; 149 150 struct iwk_alive_resp sc_card_alive_run; 151 struct iwk_init_alive_resp sc_card_alive_init; 152 153 uint32_t sc_tx_timer; 154 uint8_t *sc_fw_bin; 155 156 ddi_softintr_t sc_rx_softint_id; 157 uint32_t sc_rx_softint_pending; 158 uint32_t sc_need_reschedule; 159 160 clock_t sc_clk; 161 162 /* kstats */ 163 uint32_t sc_tx_nobuf; 164 uint32_t sc_rx_nobuf; 165 uint32_t sc_tx_err; 166 uint32_t sc_rx_err; 167 uint32_t sc_tx_retries; 168 } iwk_sc_t; 169 170 #define IWK_F_ATTACHED (1 << 0) 171 #define IWK_F_CMD_DONE (1 << 1) 172 #define IWK_F_FW_INIT (1 << 2) 173 #define IWK_F_HW_ERR_RECOVER (1 << 3) 174 #define IWK_F_RATE_AUTO_CTL (1 << 4) 175 #define IWK_F_RUNNING (1 << 5) 176 #define IWK_F_SCANNING (1 << 6) 177 #define IWK_F_SUSPEND (1 << 7) 178 #define IWK_F_RADIO_OFF (1 << 8) 179 180 #define IWK_SUCCESS 0 181 #define IWK_FAIL EIO 182 #ifdef __cplusplus 183 } 184 #endif 185 186 #endif /* _IWK_VAR_H */ 187