1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 /* Driver states */ 81 #define E1000G_UNKNOWN 0x00 82 #define E1000G_INITIALIZED 0x01 83 #define E1000G_STARTED 0x02 84 #define E1000G_SUSPENDED 0x04 85 #define E1000G_ERROR 0x80 86 87 #define JUMBO_FRAG_LENGTH 4096 88 89 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 90 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 91 #define MAX_NUM_MULTICAST_ADDRESSES 256 92 93 /* 94 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 95 * + one for cross page split 96 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 97 * two for the workaround of the 82546 chip 98 */ 99 #define MAX_COOKIES 18 100 #define MAX_TX_DESC_PER_PACKET 21 101 102 /* 103 * constants used in setting flow control thresholds 104 */ 105 #define E1000_PBA_10K 0x000A 106 #define E1000_PBA_MASK 0xffff 107 #define E1000_PBA_SHIFT 10 108 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 109 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 110 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 111 112 #define MAX_NUM_TX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_DESCRIPTOR 4096 114 #define MAX_NUM_RX_FREELIST 4096 115 #define MAX_NUM_TX_FREELIST 4096 116 #define MAX_RX_LIMIT_ON_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 #define MAX_INTR_THROTTLING 65535 122 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 123 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 124 125 #define MIN_NUM_TX_DESCRIPTOR 80 126 #define MIN_NUM_RX_DESCRIPTOR 80 127 #define MIN_NUM_RX_FREELIST 64 128 #define MIN_NUM_TX_FREELIST 80 129 #define MIN_RX_LIMIT_ON_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_BCOPY_THRESHOLD 0 136 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 137 138 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 139 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_RX_FREELIST 4096 141 #define DEFAULT_NUM_TX_FREELIST 2304 142 #define DEFAULT_RX_LIMIT_ON_INTR 128 143 144 #ifdef __sparc 145 #define MAX_INTR_PER_SEC 7100 146 #define MIN_INTR_PER_SEC 3000 147 #define DEFAULT_INTR_PACKET_LOW 5 148 #define DEFAULT_INTR_PACKET_HIGH 128 149 #else 150 #define MAX_INTR_PER_SEC 15000 151 #define MIN_INTR_PER_SEC 4000 152 #define DEFAULT_INTR_PACKET_LOW 10 153 #define DEFAULT_INTR_PACKET_HIGH 48 154 #endif 155 156 #define DEFAULT_RX_INTR_DELAY 0 157 #define DEFAULT_RX_INTR_ABS_DELAY 64 158 #define DEFAULT_TX_INTR_DELAY 64 159 #define DEFAULT_TX_INTR_ABS_DELAY 64 160 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 161 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 162 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 163 164 #define DEFAULT_RX_BCOPY_THRESHOLD 128 165 #define DEFAULT_TX_BCOPY_THRESHOLD 512 166 #define DEFAULT_TX_UPDATE_THRESHOLD 256 167 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 168 169 #define DEFAULT_TX_INTR_ENABLE 1 170 #define DEFAULT_FLOW_CONTROL 3 171 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 172 /* which is normally 0x040 */ 173 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 174 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 175 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 176 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 177 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 178 179 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 180 181 /* 182 * The size of the receive/transmite buffers 183 */ 184 #define E1000_RX_BUFFER_SIZE_2K (2048) 185 #define E1000_RX_BUFFER_SIZE_4K (4096) 186 #define E1000_RX_BUFFER_SIZE_8K (8192) 187 #define E1000_RX_BUFFER_SIZE_16K (16384) 188 189 #define E1000_TX_BUFFER_SIZE_2K (2048) 190 #define E1000_TX_BUFFER_SIZE_4K (4096) 191 #define E1000_TX_BUFFER_SIZE_8K (8192) 192 #define E1000_TX_BUFFER_SIZE_16K (16384) 193 194 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 195 196 #define E1000G_RX_SW_FREE 0x0 197 #define E1000G_RX_SW_SENDUP 0x1 198 #define E1000G_RX_SW_STOP 0x2 199 #define E1000G_RX_SW_DETACH 0x3 200 201 /* 202 * definitions for smartspeed workaround 203 */ 204 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 205 /* or 30 seconds */ 206 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 207 /* or 6 seconds */ 208 209 /* 210 * Definitions for module_info. 211 */ 212 #define WSNAME "e1000g" /* module name */ 213 214 /* 215 * Defined for IP header alignment. We also need to preserve space for 216 * VLAN tag (4 bytes) 217 */ 218 #define E1000G_IPALIGNROOM 6 219 #define E1000G_IPALIGNPRESERVEROOM 64 220 221 /* 222 * bit flags for 'attach_progress' which is a member variable in struct e1000g 223 */ 224 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 225 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 226 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 227 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 228 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 229 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 230 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 231 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 232 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 233 /* 0200 used to be PROGRESS_NDD. Now unused */ 234 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 235 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 236 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 237 238 /* 239 * Speed and Duplex Settings 240 */ 241 #define GDIAG_10_HALF 1 242 #define GDIAG_10_FULL 2 243 #define GDIAG_100_HALF 3 244 #define GDIAG_100_FULL 4 245 #define GDIAG_1000_FULL 6 246 #define GDIAG_ANY 7 247 248 /* 249 * Coexist Workaround RP: 07/04/03 250 * 82544 Workaround : Co-existence 251 */ 252 #define MAX_TX_BUF_SIZE (8 * 1024) 253 254 /* 255 * Defines for Jumbo Frame 256 */ 257 #define FRAME_SIZE_UPTO_2K 2048 258 #define FRAME_SIZE_UPTO_4K 4096 259 #define FRAME_SIZE_UPTO_8K 8192 260 #define FRAME_SIZE_UPTO_16K 16384 261 #define FRAME_SIZE_UPTO_9K 9234 262 263 #define MAXIMUM_MTU 9000 264 #define DEFAULT_MTU ETHERMTU 265 266 #define DEFAULT_FRAME_SIZE \ 267 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 268 #define MAXIMUM_FRAME_SIZE \ 269 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 270 271 #define E1000_LSO_MAXLEN 65535 272 273 /* Defines for Tx stall check */ 274 #define E1000G_STALL_WATCHDOG_COUNT 8 275 276 #define MAX_TX_LINK_DOWN_TIMEOUT 8 277 278 /* Defines for DVMA */ 279 #ifdef __sparc 280 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 281 #endif 282 283 /* 284 * Loopback definitions 285 */ 286 #define E1000G_LB_NONE 0 287 #define E1000G_LB_EXTERNAL_1000 1 288 #define E1000G_LB_EXTERNAL_100 2 289 #define E1000G_LB_EXTERNAL_10 3 290 #define E1000G_LB_INTERNAL_PHY 4 291 292 /* 293 * Private dip list definitions 294 */ 295 #define E1000G_PRIV_DEVI_ATTACH 0x0 296 #define E1000G_PRIV_DEVI_DETACH 0x1 297 298 /* 299 * Tx descriptor LENGTH field mask 300 */ 301 #define E1000G_TBD_LENGTH_MASK 0x000fffff 302 303 /* 304 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 305 */ 306 #define QUEUE_INIT_LIST(_LH) \ 307 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 308 309 /* 310 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 311 */ 312 #define IS_QUEUE_EMPTY(_LH) \ 313 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 314 315 /* 316 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 317 * not remove the head from the queue. 318 */ 319 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 320 321 /* 322 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 323 */ 324 #define QUEUE_REMOVE_HEAD(_LH) \ 325 { \ 326 PSINGLE_LIST_LINK ListElem; \ 327 if (ListElem = (_LH)->Flink) \ 328 { \ 329 if (!((_LH)->Flink = ListElem->Flink)) \ 330 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 331 } \ 332 } 333 334 /* 335 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 336 * and return it (this differs from QUEUE_REMOVE_HEAD only in 337 * the 1st line). 338 */ 339 #define QUEUE_POP_HEAD(_LH) \ 340 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 341 { \ 342 PSINGLE_LIST_LINK ListElem; \ 343 ListElem = (_LH)->Flink; \ 344 if (ListElem) \ 345 { \ 346 (_LH)->Flink = ListElem->Flink; \ 347 if (!(_LH)->Flink) \ 348 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 349 } \ 350 } 351 352 /* 353 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 354 * remove the tail from the queue. 355 */ 356 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 357 358 /* 359 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 360 */ 361 #define QUEUE_PUSH_TAIL(_LH, _E) \ 362 if ((_LH)->Blink) \ 363 { \ 364 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 365 (PSINGLE_LIST_LINK)(_E); \ 366 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 367 } else { \ 368 (_LH)->Flink = \ 369 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 370 } \ 371 (_E)->Flink = (PSINGLE_LIST_LINK)0; 372 373 /* 374 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 375 */ 376 #define QUEUE_PUSH_HEAD(_LH, _E) \ 377 if (!((_E)->Flink = (_LH)->Flink)) \ 378 { \ 379 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 380 } \ 381 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 382 383 /* 384 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 385 * current element. 386 */ 387 #define QUEUE_GET_NEXT(_LH, _E) \ 388 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 389 (0) : ((_E)->Flink)) 390 391 /* 392 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 393 */ 394 #define QUEUE_APPEND(_LH1, _LH2) \ 395 if ((_LH2)->Flink) { \ 396 if ((_LH1)->Flink) { \ 397 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 398 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 399 } else { \ 400 (_LH1)->Flink = \ 401 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 402 } \ 403 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 404 } 405 406 407 #define QUEUE_SWITCH(_LH1, _LH2) \ 408 if ((_LH2)->Flink) { \ 409 (_LH1)->Flink = (_LH2)->Flink; \ 410 (_LH1)->Blink = (_LH2)->Blink; \ 411 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 412 } 413 414 /* 415 * Property lookups 416 */ 417 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 418 DDI_PROP_DONTPASS, (n)) 419 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 420 DDI_PROP_DONTPASS, (n), -1) 421 422 #ifdef E1000G_DEBUG 423 /* 424 * E1000G-specific ioctls ... 425 */ 426 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 427 + 'K') << 4) + 'G') << 4) 428 429 /* 430 * These diagnostic IOCTLS are enabled only in DEBUG drivers 431 */ 432 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 433 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 434 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 435 436 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 437 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 438 439 typedef struct { 440 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 441 uint64_t pp_acc_space; /* See #defines below */ 442 uint64_t pp_acc_offset; /* See regs definition */ 443 uint64_t pp_acc_data; /* output for peek */ 444 /* input for poke */ 445 } e1000g_peekpoke_t; 446 #endif /* E1000G_DEBUG */ 447 448 /* 449 * (Internal) return values from ioctl subroutines 450 */ 451 enum ioc_reply { 452 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 453 IOC_DONE, /* OK, reply sent */ 454 IOC_ACK, /* OK, just send ACK */ 455 IOC_REPLY /* OK, just send reply */ 456 }; 457 458 /* 459 * Named Data (ND) Parameter Management Structure 460 */ 461 typedef struct { 462 uint32_t ndp_info; 463 uint32_t ndp_min; 464 uint32_t ndp_max; 465 uint32_t ndp_val; 466 struct e1000g *ndp_instance; 467 char *ndp_name; 468 } nd_param_t; 469 470 /* 471 * The entry of the private dip list 472 */ 473 typedef struct _private_devi_list { 474 dev_info_t *priv_dip; 475 uint16_t flag; 476 struct _private_devi_list *next; 477 } private_devi_list_t; 478 479 /* 480 * A structure that points to the next entry in the queue. 481 */ 482 typedef struct _SINGLE_LIST_LINK { 483 struct _SINGLE_LIST_LINK *Flink; 484 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 485 486 /* 487 * A "ListHead" structure that points to the head and tail of a queue 488 */ 489 typedef struct _LIST_DESCRIBER { 490 struct _SINGLE_LIST_LINK *volatile Flink; 491 struct _SINGLE_LIST_LINK *volatile Blink; 492 } LIST_DESCRIBER, *PLIST_DESCRIBER; 493 494 /* 495 * Address-Length pair structure that stores descriptor info 496 */ 497 typedef struct _sw_desc { 498 uint64_t address; 499 uint32_t length; 500 } sw_desc_t, *p_sw_desc_t; 501 502 typedef struct _desc_array { 503 sw_desc_t descriptor[4]; 504 uint32_t elements; 505 } desc_array_t, *p_desc_array_t; 506 507 typedef enum { 508 USE_NONE, 509 USE_BCOPY, 510 USE_DVMA, 511 USE_DMA 512 } dma_type_t; 513 514 typedef struct _dma_buffer { 515 caddr_t address; 516 uint64_t dma_address; 517 ddi_acc_handle_t acc_handle; 518 ddi_dma_handle_t dma_handle; 519 size_t size; 520 size_t len; 521 } dma_buffer_t, *p_dma_buffer_t; 522 523 /* 524 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 525 * structure stores the additional information that is 526 * associated with every packet to be transmitted. It stores the 527 * message block pointer and the TBD addresses associated with 528 * the m_blk and also the link to the next tcb in the chain 529 */ 530 typedef struct _tx_sw_packet { 531 /* Link to the next tx_sw_packet in the list */ 532 SINGLE_LIST_LINK Link; 533 mblk_t *mp; 534 uint32_t num_desc; 535 uint32_t num_mblk_frag; 536 dma_type_t dma_type; 537 dma_type_t data_transfer_type; 538 ddi_dma_handle_t tx_dma_handle; 539 dma_buffer_t tx_buf[1]; 540 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 541 } tx_sw_packet_t, *p_tx_sw_packet_t; 542 543 /* 544 * This structure is similar to the rx_sw_packet structure used 545 * for Ndis. This structure stores information about the 2k 546 * aligned receive buffer into which the FX1000 DMA's frames. 547 * This structure is maintained as a linked list of many 548 * receiver buffer pointers. 549 */ 550 typedef struct _rx_sw_packet { 551 /* Link to the next rx_sw_packet_t in the list */ 552 SINGLE_LIST_LINK Link; 553 struct _rx_sw_packet *next; 554 uint16_t flag; 555 mblk_t *mp; 556 caddr_t rx_ring; 557 dma_type_t dma_type; 558 frtn_t free_rtn; 559 dma_buffer_t rx_buf[1]; 560 } rx_sw_packet_t, *p_rx_sw_packet_t; 561 562 typedef struct _mblk_list { 563 mblk_t *head; 564 mblk_t *tail; 565 } mblk_list_t, *p_mblk_list_t; 566 567 typedef struct _context_data { 568 uint32_t ether_header_size; 569 uint32_t cksum_flags; 570 uint32_t cksum_start; 571 uint32_t cksum_stuff; 572 uint16_t mss; 573 uint8_t hdr_len; 574 uint32_t pay_len; 575 boolean_t lso_flag; 576 } context_data_t; 577 578 typedef union _e1000g_ether_addr { 579 struct { 580 uint32_t high; 581 uint32_t low; 582 } reg; 583 struct { 584 uint8_t set; 585 uint8_t redundant; 586 uint8_t addr[ETHERADDRL]; 587 } mac; 588 } e1000g_ether_addr_t; 589 590 typedef struct _e1000g_stat { 591 592 kstat_named_t link_speed; /* Link Speed */ 593 kstat_named_t reset_count; /* Reset Count */ 594 595 kstat_named_t rx_error; /* Rx Error in Packet */ 596 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 597 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 598 599 kstat_named_t tx_no_desc; /* Tx No Desc */ 600 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 601 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 602 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 603 kstat_named_t tx_reschedule; /* Tx Reschedule */ 604 605 #ifdef E1000G_DEBUG 606 kstat_named_t rx_none; /* Rx No Incoming Data */ 607 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 608 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 609 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 610 611 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 612 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 613 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 614 kstat_named_t tx_recycle; /* Tx Recycle */ 615 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 616 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 617 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 618 kstat_named_t tx_copy; /* Tx Send Copy */ 619 kstat_named_t tx_bind; /* Tx Send Bind */ 620 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 621 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 622 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 623 #endif 624 625 kstat_named_t Crcerrs; /* CRC Error Count */ 626 kstat_named_t Symerrs; /* Symbol Error Count */ 627 kstat_named_t Mpc; /* Missed Packet Count */ 628 kstat_named_t Scc; /* Single Collision Count */ 629 kstat_named_t Ecol; /* Excessive Collision Count */ 630 kstat_named_t Mcc; /* Multiple Collision Count */ 631 kstat_named_t Latecol; /* Late Collision Count */ 632 kstat_named_t Colc; /* Collision Count */ 633 kstat_named_t Dc; /* Defer Count */ 634 kstat_named_t Sec; /* Sequence Error Count */ 635 kstat_named_t Rlec; /* Receive Length Error Count */ 636 kstat_named_t Xonrxc; /* XON Received Count */ 637 kstat_named_t Xontxc; /* XON Xmitted Count */ 638 kstat_named_t Xoffrxc; /* XOFF Received Count */ 639 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 640 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 641 #ifdef E1000G_DEBUG 642 kstat_named_t Prc64; /* Packets Received - 64b */ 643 kstat_named_t Prc127; /* Packets Received - 65-127b */ 644 kstat_named_t Prc255; /* Packets Received - 127-255b */ 645 kstat_named_t Prc511; /* Packets Received - 256-511b */ 646 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 647 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 648 #endif 649 kstat_named_t Gprc; /* Good Packets Received Count */ 650 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 651 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 652 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 653 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 654 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 655 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 656 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 657 kstat_named_t Rnbc; /* Receive No Buffers Count */ 658 kstat_named_t Ruc; /* Receive Undersize Count */ 659 kstat_named_t Rfc; /* Receive Frag Count */ 660 kstat_named_t Roc; /* Receive Oversize Count */ 661 kstat_named_t Rjc; /* Receive Jabber Count */ 662 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 663 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 664 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 665 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 666 kstat_named_t Tpr; /* Total Packets Received */ 667 kstat_named_t Tpt; /* Total Packets Xmitted */ 668 #ifdef E1000G_DEBUG 669 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 670 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 671 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 672 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 673 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 674 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 675 #endif 676 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 677 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 678 kstat_named_t Algnerrc; /* Alignment Error count */ 679 kstat_named_t Tuc; /* Transmit Underrun count */ 680 kstat_named_t Rxerrc; /* Rx Error Count */ 681 kstat_named_t Tncrs; /* Transmit with no CRS */ 682 kstat_named_t Cexterr; /* Carrier Extension Error count */ 683 kstat_named_t Rutec; /* Receive DMA too Early count */ 684 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 685 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 686 } e1000g_stat_t, *p_e1000g_stat_t; 687 688 typedef struct _e1000g_tx_ring { 689 kmutex_t tx_lock; 690 kmutex_t freelist_lock; 691 kmutex_t usedlist_lock; 692 /* 693 * Descriptor queue definitions 694 */ 695 ddi_dma_handle_t tbd_dma_handle; 696 ddi_acc_handle_t tbd_acc_handle; 697 struct e1000_tx_desc *tbd_area; 698 uint64_t tbd_dma_addr; 699 struct e1000_tx_desc *tbd_first; 700 struct e1000_tx_desc *tbd_last; 701 struct e1000_tx_desc *tbd_oldest; 702 struct e1000_tx_desc *tbd_next; 703 uint32_t tbd_avail; 704 /* 705 * Software packet structures definitions 706 */ 707 p_tx_sw_packet_t packet_area; 708 LIST_DESCRIBER used_list; 709 LIST_DESCRIBER free_list; 710 /* 711 * TCP/UDP Context Data Information 712 */ 713 context_data_t pre_context; 714 /* 715 * Timer definitions for 82547 716 */ 717 timeout_id_t timer_id_82547; 718 boolean_t timer_enable_82547; 719 /* 720 * reschedule when tx resource is available 721 */ 722 boolean_t resched_needed; 723 clock_t resched_timestamp; 724 uint32_t stall_watchdog; 725 uint32_t recycle_fail; 726 mblk_list_t mblks; 727 /* 728 * Statistics 729 */ 730 uint32_t stat_no_swpkt; 731 uint32_t stat_no_desc; 732 uint32_t stat_send_fail; 733 uint32_t stat_reschedule; 734 uint32_t stat_timer_reschedule; 735 uint32_t stat_over_size; 736 #ifdef E1000G_DEBUG 737 uint32_t stat_under_size; 738 uint32_t stat_exceed_frags; 739 uint32_t stat_empty_frags; 740 uint32_t stat_recycle; 741 uint32_t stat_recycle_intr; 742 uint32_t stat_recycle_retry; 743 uint32_t stat_recycle_none; 744 uint32_t stat_copy; 745 uint32_t stat_bind; 746 uint32_t stat_multi_copy; 747 uint32_t stat_multi_cookie; 748 uint32_t stat_lack_desc; 749 uint32_t stat_lso_header_fail; 750 #endif 751 /* 752 * Pointer to the adapter 753 */ 754 struct e1000g *adapter; 755 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 756 757 typedef struct _e1000g_rx_ring { 758 kmutex_t rx_lock; 759 kmutex_t freelist_lock; 760 kmutex_t recycle_lock; 761 /* 762 * Descriptor queue definitions 763 */ 764 ddi_dma_handle_t rbd_dma_handle; 765 ddi_acc_handle_t rbd_acc_handle; 766 struct e1000_rx_desc *rbd_area; 767 uint64_t rbd_dma_addr; 768 struct e1000_rx_desc *rbd_first; 769 struct e1000_rx_desc *rbd_last; 770 struct e1000_rx_desc *rbd_next; 771 /* 772 * Software packet structures definitions 773 */ 774 p_rx_sw_packet_t packet_area; 775 LIST_DESCRIBER recv_list; 776 LIST_DESCRIBER free_list; 777 LIST_DESCRIBER recycle_list; 778 779 p_rx_sw_packet_t pending_list; 780 uint32_t pending_count; 781 uint32_t avail_freepkt; 782 uint32_t recycle_freepkt; 783 uint32_t rx_mblk_len; 784 mblk_t *rx_mblk; 785 mblk_t *rx_mblk_tail; 786 mac_ring_handle_t mrh; 787 mac_ring_handle_t mrh_init; 788 uint64_t ring_gen_num; 789 mblk_t *poll_list_head; 790 mblk_t *poll_list_tail; 791 uint_t poll_list_sz; 792 boolean_t poll_flag; 793 794 /* 795 * Statistics 796 */ 797 uint32_t stat_error; 798 uint32_t stat_esballoc_fail; 799 uint32_t stat_allocb_fail; 800 uint32_t stat_exceed_pkt; 801 #ifdef E1000G_DEBUG 802 uint32_t stat_none; 803 uint32_t stat_multi_desc; 804 uint32_t stat_no_freepkt; 805 #endif 806 /* 807 * Pointer to the adapter 808 */ 809 struct e1000g *adapter; 810 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 811 812 typedef struct e1000g { 813 int instance; 814 dev_info_t *dip; 815 dev_info_t *priv_dip; 816 mac_handle_t mh; 817 mac_resource_handle_t mrh; 818 struct e1000_hw shared; 819 struct e1000g_osdep osdep; 820 821 uint32_t e1000g_state; 822 boolean_t e1000g_promisc; 823 boolean_t strip_crc; 824 boolean_t rx_buffer_setup; 825 boolean_t esb2_workaround; 826 link_state_t link_state; 827 uint32_t link_speed; 828 uint32_t link_duplex; 829 uint32_t master_latency_timer; 830 uint32_t smartspeed; /* smartspeed w/a counter */ 831 uint32_t init_count; 832 uint32_t reset_count; 833 uint32_t attach_progress; /* attach tracking */ 834 uint32_t loopback_mode; 835 836 uint32_t tx_desc_num; 837 uint32_t tx_freelist_num; 838 uint32_t rx_desc_num; 839 uint32_t rx_freelist_num; 840 uint32_t tx_buffer_size; 841 uint32_t rx_buffer_size; 842 843 uint32_t tx_link_down_timeout; 844 uint32_t tx_bcopy_thresh; 845 uint32_t rx_limit_onintr; 846 uint32_t rx_bcopy_thresh; 847 uint32_t rx_buf_align; 848 uint32_t desc_align; 849 850 boolean_t intr_adaptive; 851 boolean_t tx_intr_enable; 852 uint32_t tx_intr_delay; 853 uint32_t tx_intr_abs_delay; 854 uint32_t rx_intr_delay; 855 uint32_t rx_intr_abs_delay; 856 uint32_t intr_throttling_rate; 857 858 uint32_t default_mtu; 859 uint32_t max_frame_size; 860 uint32_t min_frame_size; 861 862 boolean_t watchdog_timer_enabled; 863 boolean_t watchdog_timer_started; 864 timeout_id_t watchdog_tid; 865 boolean_t link_complete; 866 timeout_id_t link_tid; 867 868 e1000g_rx_ring_t rx_ring[1]; 869 e1000g_tx_ring_t tx_ring[1]; 870 mac_group_handle_t rx_group; 871 872 /* 873 * Rx and Tx packet count for interrupt adaptive setting 874 */ 875 uint32_t rx_pkt_cnt; 876 uint32_t tx_pkt_cnt; 877 878 /* 879 * The watchdog_lock must be held when updateing the 880 * timeout fields in struct e1000g, that is, 881 * watchdog_tid, watchdog_timer_started. 882 */ 883 kmutex_t watchdog_lock; 884 /* 885 * The link_lock protects the link fields in struct e1000g, 886 * such as link_state, link_speed, link_duplex, link_complete, and 887 * link_tid. 888 */ 889 kmutex_t link_lock; 890 /* 891 * The chip_lock assures that the Rx/Tx process must be 892 * stopped while other functions change the hardware 893 * configuration of e1000g card, such as e1000g_reset(), 894 * e1000g_reset_hw() etc are executed. 895 */ 896 krwlock_t chip_lock; 897 898 boolean_t unicst_init; 899 uint32_t unicst_avail; 900 uint32_t unicst_total; 901 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 902 903 uint32_t mcast_count; 904 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 905 906 ulong_t sys_page_sz; 907 #ifdef __sparc 908 uint_t dvma_page_num; 909 #endif 910 911 boolean_t msi_enable; 912 boolean_t tx_hcksum_enable; 913 boolean_t lso_enable; 914 boolean_t lso_premature_issue; 915 boolean_t mem_workaround_82546; 916 int intr_type; 917 int intr_cnt; 918 int intr_cap; 919 size_t intr_size; 920 uint_t intr_pri; 921 ddi_intr_handle_t *htable; 922 923 int tx_softint_pri; 924 ddi_softint_handle_t tx_softint_handle; 925 926 kstat_t *e1000g_ksp; 927 928 boolean_t poll_mode; 929 930 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 931 uint16_t phy_status; /* contents of PHY_STATUS */ 932 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 933 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 934 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 935 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 936 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 937 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 938 939 /* 940 * FMA capabilities 941 */ 942 int fm_capabilities; 943 944 uint32_t param_en_1000fdx:1, 945 param_en_1000hdx:1, 946 param_en_100fdx:1, 947 param_en_100hdx:1, 948 param_en_10fdx:1, 949 param_en_10hdx:1, 950 param_autoneg_cap:1, 951 param_pause_cap:1, 952 param_asym_pause_cap:1, 953 param_1000fdx_cap:1, 954 param_1000hdx_cap:1, 955 param_100t4_cap:1, 956 param_100fdx_cap:1, 957 param_100hdx_cap:1, 958 param_10fdx_cap:1, 959 param_10hdx_cap:1, 960 param_adv_autoneg:1, 961 param_adv_pause:1, 962 param_adv_asym_pause:1, 963 param_adv_1000fdx:1, 964 param_adv_1000hdx:1, 965 param_adv_100t4:1, 966 param_adv_100fdx:1, 967 param_adv_100hdx:1, 968 param_adv_10fdx:1, 969 param_adv_10hdx:1, 970 param_lp_autoneg:1, 971 param_lp_pause:1, 972 param_lp_asym_pause:1, 973 param_lp_1000fdx:1, 974 param_lp_1000hdx:1, 975 param_lp_100t4:1; 976 977 uint32_t param_lp_100fdx:1, 978 param_lp_100hdx:1, 979 param_lp_10fdx:1, 980 param_lp_10hdx:1, 981 param_pad_to_32:28; 982 983 } e1000g_t; 984 985 986 /* 987 * Function prototypes 988 */ 989 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 990 void e1000g_release_dma_resources(struct e1000g *Adapter); 991 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 992 void e1000g_tx_setup(struct e1000g *Adapter); 993 void e1000g_rx_setup(struct e1000g *Adapter); 994 void e1000g_setup_multicast(struct e1000g *Adapter); 995 996 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 997 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 998 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 999 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1000 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1001 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t *sz); 1002 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1003 1004 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1005 int e1000g_init_stats(struct e1000g *Adapter); 1006 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1007 uint32_t frame_len, uint8_t *mac_addr); 1008 1009 void e1000g_clear_interrupt(struct e1000g *Adapter); 1010 void e1000g_mask_interrupt(struct e1000g *Adapter); 1011 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1012 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1013 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1014 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1015 void e1000_enable_pciex_master(struct e1000_hw *hw); 1016 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1017 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1018 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1019 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1020 int e1000g_reset_link(struct e1000g *Adapter); 1021 1022 /* 1023 * Global variables 1024 */ 1025 extern boolean_t e1000g_force_detach; 1026 extern uint32_t e1000g_mblks_pending; 1027 extern krwlock_t e1000g_rx_detach_lock; 1028 extern private_devi_list_t *e1000g_private_devi_list; 1029 extern int e1000g_poll_mode; 1030 1031 #ifdef __cplusplus 1032 } 1033 #endif 1034 1035 #endif /* _E1000G_SW_H */ 1036