1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000_OSDEP_H 27 #define _E1000_OSDEP_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/types.h> 36 #include <sys/conf.h> 37 #include <sys/debug.h> 38 #include <sys/stropts.h> 39 #include <sys/stream.h> 40 #include <sys/strlog.h> 41 #include <sys/kmem.h> 42 #include <sys/stat.h> 43 #include <sys/kstat.h> 44 #include <sys/modctl.h> 45 #include <sys/errno.h> 46 #include <sys/ddi.h> 47 #include <sys/sunddi.h> 48 #include <sys/pci.h> 49 50 /* 51 * === BEGIN CONTENT FORMERLY IN FXHW.H === 52 */ 53 #define DelayInMicroseconds(x) drv_usecwait(x) 54 #define DelayInMilliseconds(x) drv_usecwait(x * 1000) 55 #define usec_delay(x) drv_usecwait(x) 56 #define msec_delay(x) drv_usecwait(x * 1000) 57 58 #ifdef e1000g_DEBUG 59 #define DEBUGOUT(S) cmn_err(CE_CONT, S) 60 #define DEBUGOUT1(S, A) cmn_err(CE_CONT, S, A) 61 #define DEBUGOUT2(S, A, B) cmn_err(CE_CONT, S, A, B) 62 #define DEBUGOUT3(S, A, B, C) cmn_err(CE_CONT, S, A, B, C) 63 #define DEBUGOUT7(S, A, B, C, D, E, F, G) \ 64 cmn_err(CE_CONT, S, A, B, C, D, E, F, G) 65 #else 66 #define DEBUGOUT(S) 67 #define DEBUGOUT1(S, A) 68 #define DEBUGOUT2(S, A, B) 69 #define DEBUGOUT3(S, A, B, C) 70 #define DEBUGOUT7(S, A, B, C, D, E, F, G) 71 #endif 72 73 #define DEBUGFUNC(F) DEBUGOUT(F) 74 75 #define IN 76 #define OUT 77 #define FALSE 0 78 #define TRUE 1 79 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */ 80 #define PCI_COMMAND_REGISTER 0x04 81 82 #define E1000_WRITE_FLUSH(a) /* NOOP */ 83 84 #define E1000_WRITE_REG(a, reg, value) \ 85 {\ 86 if ((a)->mac_type >= e1000_82543) \ 87 ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 88 (uint32_t *)((a)->hw_addr + E1000_##reg), \ 89 value); \ 90 else \ 91 ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 92 (uint32_t *)((a)->hw_addr + E1000_82542_##reg), \ 93 value); \ 94 } 95 96 #define E1000_READ_REG(a, reg) (\ 97 ((a)->mac_type >= e1000_82543) ? \ 98 ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 99 (uint32_t *)((a)->hw_addr + E1000_##reg)) : \ 100 ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 101 (uint32_t *)((a)->hw_addr + E1000_82542_##reg))) 102 103 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \ 104 {\ 105 if ((a)->mac_type >= e1000_82543) \ 106 ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 107 (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2)),\ 108 value); \ 109 else \ 110 ddi_put32(((struct e1000g_osdep *)((a)->back))->E1000_handle, \ 111 (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ 112 ((offset) << 2)), value); \ 113 } 114 115 #define E1000_READ_REG_ARRAY(a, reg, offset) (\ 116 ((a)->mac_type >= e1000_82543) ? \ 117 ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 118 (uint32_t *)((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \ 119 ddi_get32(((struct e1000g_osdep *)(a)->back)->E1000_handle, \ 120 (uint32_t *)((a)->hw_addr + E1000_82542_##reg + \ 121 ((offset) << 2)))) 122 123 124 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) NULL 125 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) NULL 126 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) NULL 127 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) NULL 128 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) NULL 129 #define E1000_READ_REG_ARRAY_DWORD(a, reg, offset) NULL 130 131 132 #define ICH_FLASH_REG_SET 2 /* solaris mapping of flash memory */ 133 #define OS_DEP(hw) ((struct e1000g_osdep *)((hw)->back)) 134 135 #define E1000_READ_ICH_FLASH_REG(hw, reg) \ 136 ddi_get32((OS_DEP(hw))->ich_flash_handle, \ 137 (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg))) 138 139 #define E1000_READ_ICH_FLASH_REG16(hw, reg) \ 140 ddi_get16((OS_DEP(hw))->ich_flash_handle, \ 141 (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg))) 142 143 #define E1000_WRITE_ICH_FLASH_REG(hw, reg, value) \ 144 ddi_put32((OS_DEP(hw))->ich_flash_handle, \ 145 (uint32_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) 146 147 #define E1000_WRITE_ICH_FLASH_REG16(hw, reg, value) \ 148 ddi_put16((OS_DEP(hw))->ich_flash_handle, \ 149 (uint16_t *)((OS_DEP(hw))->ich_flash_base + (reg)), (value)) 150 151 /* 152 * The size of the receive buffers we allocate, 153 */ 154 #define E1000_SIZE_OF_RECEIVE_BUFFERS (2048) 155 156 /* 157 * Use this define refer to the size of a recieve buffer plus its 158 * align size 159 */ 160 #define E1000_SIZE_OF_UNALIGNED_RECEIVE_BUFFERS \ 161 E1000_SIZE_OF_RECEIVE_BUFFERS + RECEIVE_BUFFER_ALIGN_SIZE 162 163 /* 164 * === END CONTENT FORMERLY IN FXHW.H === 165 */ 166 167 #define msec_delay_irq msec_delay 168 169 typedef uint8_t UCHAR; /* 8-bit unsigned */ 170 typedef UCHAR UINT8; /* 8-bit unsigned */ 171 typedef uint16_t USHORT; /* 16-bit unsigned */ 172 typedef uint16_t UINT16; /* 16-bit unsigned */ 173 typedef uint32_t ULONG; /* 32-bit unsigned */ 174 typedef uint32_t UINT32; 175 typedef uint32_t UINT; /* 32-bit unsigned */ 176 typedef UCHAR BOOLEAN; 177 typedef UCHAR *PUCHAR; 178 typedef UINT *PUINT; 179 typedef ULONG *PLONG; 180 typedef ULONG NDIS_STATUS; 181 typedef USHORT *PUSHORT; 182 typedef PUSHORT PUINT16; /* 16-bit unsigned pointer */ 183 typedef ULONG E1000_32_BIT_PHYSICAL_ADDRESS, 184 *PFX_32_BIT_PHYSICAL_ADDRESS; 185 typedef uint64_t E1000_64_BIT_PHYSICAL_ADDRESS, 186 *PFX_64_BIT_PHYSICAL_ADDRESS; 187 188 struct e1000g_osdep { 189 ddi_acc_handle_t E1000_handle; 190 ddi_acc_handle_t handle; 191 /* flash access */ 192 ddi_acc_handle_t ich_flash_handle; 193 caddr_t ich_flash_base; 194 off_t ich_flash_size; 195 }; 196 197 #ifdef __sparc /* on SPARC, use only memory-mapped routines */ 198 199 #define E1000_READ_REG_IO E1000_READ_REG 200 #define E1000_WRITE_REG_IO E1000_WRITE_REG 201 202 #else /* on x86, use port io routines */ 203 204 #define E1000_READ_REG_IO(a, reg) \ 205 e1000_read_reg_io((a), E1000_##reg) 206 #define E1000_WRITE_REG_IO(a, reg, val) \ 207 e1000_write_reg_io((a), E1000_##reg, val) 208 209 #endif /* __sparc */ 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /* _E1000_OSDEP_H */ 216