1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_ICH8LAN_H_ 36 #define _E1000_ICH8LAN_H_ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #define ICH_FLASH_GFPREG 0x0000 43 #define ICH_FLASH_HSFSTS 0x0004 44 #define ICH_FLASH_HSFCTL 0x0006 45 #define ICH_FLASH_FADDR 0x0008 46 #define ICH_FLASH_FDATA0 0x0010 47 48 /* Requires up to 10 seconds when MNG might be accessing part. */ 49 #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 50 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 51 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 52 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 53 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 54 55 #define ICH_CYCLE_READ 0 56 #define ICH_CYCLE_WRITE 2 57 #define ICH_CYCLE_ERASE 3 58 59 #define FLASH_GFPREG_BASE_MASK 0x1FFF 60 #define FLASH_SECTOR_ADDR_SHIFT 12 61 62 #define ICH_FLASH_SEG_SIZE_256 256 63 #define ICH_FLASH_SEG_SIZE_4K 4096 64 #define ICH_FLASH_SEG_SIZE_8K 8192 65 #define ICH_FLASH_SEG_SIZE_64K 65536 66 67 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ 68 /* FW established a valid mode */ 69 #define E1000_ICH_FWSM_FW_VALID 0x00008000 70 #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ 71 #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 72 73 #define E1000_ICH_MNG_IAMT_MODE 0x2 74 75 #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 76 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 77 78 /* Shared Receive Address Registers */ 79 #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) 80 #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) 81 82 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 83 (ID_LED_OFF1_OFF2 << 8) | \ 84 (ID_LED_OFF1_ON2 << 4) | \ 85 (ID_LED_DEF1_DEF2)) 86 87 #define E1000_ICH_NVM_SIG_WORD 0x13 88 #define E1000_ICH_NVM_SIG_MASK 0xC000 89 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 90 #define E1000_ICH_NVM_SIG_VALUE 0x80 91 92 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 93 94 #define E1000_FEXTNVM_SW_CONFIG 1 95 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */ 96 97 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 98 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 99 100 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 101 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 102 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 103 104 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 105 106 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL 107 108 #define E1000_ICH_RAR_ENTRIES 7 109 #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ 110 #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ 111 112 #define PHY_PAGE_SHIFT 5 113 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 114 ((reg) & MAX_PHY_REG_ADDRESS)) 115 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ 116 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ 117 118 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 119 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 120 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 121 122 /* PHY Wakeup Registers and defines */ 123 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) 124 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) 125 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) 126 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) 127 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) 128 #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) 129 #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) 130 #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) 131 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) 132 #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) 133 134 #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ 135 #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ 136 #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ 137 #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ 138 #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ 139 #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ 140 #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ 141 142 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ 143 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 144 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 145 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 146 #define HV_STATS_PAGE 778 147 #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision Count */ 148 #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) 149 #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. Count */ 150 #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) 151 #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Coll. Count */ 152 #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) 153 #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision Count */ 154 #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) 155 #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision Count */ 156 #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) 157 #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ 158 #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) 159 #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Transmit with no CRS */ 160 #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) 161 162 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 163 164 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 165 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 166 167 /* SMBus Control Phy Register */ 168 #define CV_SMB_CTRL PHY_REG(769, 23) 169 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 170 171 /* SMBus Address Phy Register */ 172 #define HV_SMB_ADDR PHY_REG(768, 26) 173 #define HV_SMB_ADDR_MASK 0x007F 174 #define HV_SMB_ADDR_PEC_EN 0x0200 175 #define HV_SMB_ADDR_VALID 0x0080 176 #define HV_SMB_ADDR_FREQ_MASK 0x1100 177 #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 178 #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 179 180 /* Strapping Option Register - RO */ 181 #define E1000_STRAP 0x0000C 182 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 183 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 184 #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 185 #define E1000_STRAP_SMT_FREQ_SHIFT 12 186 187 /* OEM Bits Phy Register */ 188 #define HV_OEM_BITS PHY_REG(768, 25) 189 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 190 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 191 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 192 193 /* KMRN Mode Control */ 194 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 195 #define HV_KMRN_MDIO_SLOW 0x0400 196 197 /* KMRN FIFO Control and Status */ 198 #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) 199 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 200 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 201 202 /* PHY Power Management Control */ 203 #define HV_PM_CTRL PHY_REG(770, 17) 204 #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 205 206 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ 207 208 /* PHY Low Power Idle Control */ 209 #define I82579_LPI_CTRL PHY_REG(772, 20) 210 #define I82579_LPI_CTRL_100_ENABLE 0x2000 211 #define I82579_LPI_CTRL_1000_ENABLE 0x4000 212 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 213 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 214 215 /* Extended Management Interface (EMI) Registers */ 216 #define I82579_EMI_ADDR 0x10 217 #define I82579_EMI_DATA 0x11 218 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 219 #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ 220 #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ 221 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 222 #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ 223 #define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */ 224 #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ 225 #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ 226 #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ 227 #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE supported */ 228 #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE supported */ 229 #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ 230 #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ 231 #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ 232 #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ 233 234 #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ 235 #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ 236 237 /* Intel Rapid Start Technology Support */ 238 #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) 239 #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 240 #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) 241 #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 242 #define I217_CGFREG PHY_REG(772, 29) 243 #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 244 #define I217_MEMPWR PHY_REG(772, 26) 245 #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 246 247 /* Receive Address Initial CRC Calculation */ 248 #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) 249 250 /* Latency Tolerance Reporting */ 251 #define E1000_LTRV 0x000F8 252 #define E1000_LTRV_VALUE_MASK 0x000003FF 253 #define E1000_LTRV_SCALE_MAX 5 254 #define E1000_LTRV_SCALE_FACTOR 5 255 #define E1000_LTRV_SCALE_SHIFT 10 256 #define E1000_LTRV_SCALE_MASK 0x00001C00 257 #define E1000_LTRV_REQ_SHIFT 15 258 #define E1000_LTRV_NOSNOOP_SHIFT 16 259 #define E1000_LTRV_SEND (1 << 30) 260 261 /* Proprietary Latency Tolerance Reporting PCI Capability */ 262 #define E1000_PCI_LTR_CAP_LPT 0xA8 263 264 /* OBFF Control & Threshold Defines */ 265 #define E1000_SVCR_OFF_EN 0x00000001 266 #define E1000_SVCR_OFF_MASKINT 0x00001000 267 #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 268 #define E1000_SVCR_OFF_TIMER_SHIFT 16 269 #define E1000_SVT_OFF_HWM_MASK 0x0000001F 270 271 void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, 272 bool state); 273 void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); 274 void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); 275 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); 276 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); 277 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); 278 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); 279 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); 280 s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif /* _E1000_ICH8LAN_H_ */ 287