1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * Copyright (c) * Copyright (c) 2001 Tadpole Technology plc 27 * All rights reserved. 28 * From "@(#)pcicfg.c 1.31 99/06/18 SMI" 29 */ 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 /* 34 * Cardbus configurator 35 */ 36 37 #include <sys/ddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/ndi_impldefs.h> 40 41 #include <sys/pci.h> 42 #include <sys/ebus.h> 43 #include <sys/hotplug/hpctrl.h> 44 #include <sys/hotplug/pci/pcicfg.h> 45 46 #include <sys/pctypes.h> 47 #include <sys/pcmcia.h> 48 49 #include <sys/isa_defs.h> 50 51 #include <sys/note.h> 52 53 #include <sys/ethernet.h> 54 55 #include "cardbus.h" 56 #include "cardbus_parse.h" 57 #include "cardbus_cfg.h" 58 59 /* 60 * ************************************************************************ 61 * *** Implementation specific local data structures/definitions. *** 62 * ************************************************************************ 63 */ 64 65 #define PCICFG_MAX_DEVICE 32 66 #define PCICFG_MAX_FUNCTION 8 67 68 static uint32_t pcicfg_max_device = PCICFG_MAX_DEVICE; 69 static uint32_t pcicfg_max_function = PCICFG_MAX_FUNCTION; 70 71 #define PCICFG_NODEVICE 42 72 #define PCICFG_NOMEMORY 43 73 #define PCICFG_NOMULTI 44 74 75 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & 0xFFFFFFFF00000000)>> 32)) 76 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 77 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 78 79 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 80 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 81 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 82 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 83 84 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 85 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 86 87 #define PCICFG_MEMGRAN 0x100000 88 #define PCICFG_IOGRAN 0x1000 89 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 90 #define CBCFG_MEMGRAN 0x1000 91 #define CBCFG_IOGRAN 0x4 92 93 #define PCICFG_MEM_MULT 4 94 #define PCICFG_IO_MULT 4 95 #define PCICFG_RANGE_LEN 2 /* Number of range entries */ 96 97 /* 98 * ISA node declaration structure. 99 */ 100 struct isa_node { 101 char *name; 102 char *compatible[5]; 103 char *type; 104 char *model; 105 uint16_t reg; 106 uint16_t span; 107 }; 108 109 struct cardbus_name_entry { 110 uint32_t class_code; 111 char *name; 112 int pil; 113 }; 114 115 struct cardbus_find_ctrl { 116 uint_t bus; 117 uint_t device; 118 uint_t function; 119 dev_info_t *dip; 120 }; 121 122 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 123 (\ 124 ((ulong_t)(busnum & 0xff) << 16) |\ 125 ((ulong_t)(devnum & 0x1f) << 11) |\ 126 ((ulong_t)(funcnum & 0x7) << 8) |\ 127 ((ulong_t)(register & 0x3f))) 128 129 typedef struct cardbus_phdl cardbus_phdl_t; 130 131 struct cardbus_phdl { 132 133 dev_info_t *dip; /* Associated with the attach point */ 134 cardbus_phdl_t *next; 135 136 uint64_t memory_base; /* Memory base for this attach point */ 137 uint64_t memory_last; 138 uint64_t memory_len; 139 uint32_t memory_gran; 140 uint32_t io_base; /* I/O base for this attach point */ 141 uint32_t io_last; 142 uint32_t io_len; 143 uint32_t io_gran; 144 145 int error; 146 uint_t highest_bus; /* Highest bus seen on the probe */ 147 ndi_ra_request_t mem_req; /* allocator request for memory */ 148 ndi_ra_request_t io_req; /* allocator request for I/O */ 149 }; 150 151 typedef struct { 152 dev_info_t *dip; /* Associated with the attach point */ 153 ddi_acc_handle_t handle; /* open handle on parent PCI config space */ 154 uint32_t io_base; /* I/O base for this attach point */ 155 int io_decode_reg; 156 } isa_phdl_t; 157 158 159 /* 160 * forward declarations for routines defined in this module (called here) 161 */ 162 static cardbus_phdl_t *cardbus_find_phdl(dev_info_t *dip); 163 static cardbus_phdl_t *cardbus_create_phdl(dev_info_t *dip); 164 static int cardbus_destroy_phdl(dev_info_t *dip); 165 static int cardbus_program_ap(dev_info_t *); 166 static void cardbus_topbridge_assign(dev_info_t *, cardbus_phdl_t *); 167 static int cardbus_bridge_ranges(dev_info_t *, cardbus_phdl_t *, 168 ddi_acc_handle_t); 169 static int cardbus_bridge_assign(dev_info_t *, void *); 170 static int cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 171 ddi_acc_handle_t handle); 172 static int cardbus_add_isa_reg(dev_info_t *, void *); 173 static int cardbus_allocate_chunk(dev_info_t *, uint8_t, uint8_t); 174 static int cardbus_free_chunk(dev_info_t *); 175 static void cardbus_setup_bridge(dev_info_t *, cardbus_phdl_t *, 176 ddi_acc_handle_t); 177 static void cardbus_update_bridge(dev_info_t *, cardbus_phdl_t *, 178 ddi_acc_handle_t); 179 static void cardbus_get_mem(dev_info_t *, cardbus_phdl_t *, uint32_t, 180 uint64_t *); 181 static void cardbus_get_io(dev_info_t *, cardbus_phdl_t *, uint32_t, 182 uint32_t *); 183 static int cardbus_sum_resources(dev_info_t *, void *); 184 static int cardbus_free_bridge_resources(dev_info_t *); 185 static int cardbus_free_device_resources(dev_info_t *); 186 static int cardbus_free_resources(dev_info_t *); 187 static int cardbus_probe_bridge(cbus_t *, dev_info_t *, uint_t, 188 uint_t, uint_t); 189 static int cardbus_probe_children(cbus_t *, dev_info_t *, uint_t, uint_t, 190 uint_t, uint8_t *); 191 static int cardbus_add_config_reg(dev_info_t *, uint_t, uint_t, uint_t); 192 static int cardbus_add_isa_node(cbus_t *, dev_info_t *, struct isa_node *); 193 static int cardbus_config_setup(dev_info_t *, ddi_acc_handle_t *); 194 static void cardbus_config_teardown(ddi_acc_handle_t *); 195 static void cardbus_reparent_children(dev_info_t *, dev_info_t *); 196 static int cardbus_update_assigned_prop(dev_info_t *, pci_regspec_t *); 197 static int cardbus_update_available_prop(dev_info_t *, uint32_t, 198 uint64_t, uint64_t); 199 static int cardbus_update_ranges_prop(dev_info_t *, cardbus_range_t *); 200 static int cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, 201 uint_t reg_offset); 202 static int cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 203 ddi_acc_handle_t config_handle); 204 static int cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 205 char *name, char *compat[]); 206 static int cardbus_set_busnode_props(dev_info_t *); 207 static int cardbus_set_busnode_isaprops(dev_info_t *); 208 static int cardbus_set_childnode_props(dev_info_t *dip, 209 ddi_acc_handle_t config_handle); 210 static void cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 211 uint_t primary, uint_t secondary); 212 static void enable_pci_isa_bridge(dev_info_t *dip, 213 ddi_acc_handle_t config_handle); 214 static void enable_pci_pci_bridge(dev_info_t *dip, 215 ddi_acc_handle_t config_handle); 216 static void enable_cardbus_bridge(dev_info_t *dip, 217 ddi_acc_handle_t config_handle); 218 static void disable_pci_pci_bridge(dev_info_t *dip, 219 ddi_acc_handle_t config_handle); 220 static void disable_cardbus_bridge(dev_info_t *dip, 221 ddi_acc_handle_t config_handle); 222 static void enable_cardbus_device(dev_info_t *, ddi_acc_handle_t); 223 static void disable_cardbus_device(ddi_acc_handle_t config_handle); 224 static void cardbus_force_boolprop(dev_info_t *dip, char *pname); 225 static void cardbus_force_intprop(dev_info_t *dip, char *pname, 226 int *pval, int len); 227 static void cardbus_force_stringprop(dev_info_t *dip, char *pname, 228 char *pval); 229 static void split_addr(char *, int *, int *); 230 #ifdef DEBUG 231 static void cardbus_dump_common_config(ddi_acc_handle_t config_handle); 232 static void cardbus_dump_device_config(ddi_acc_handle_t config_handle); 233 static void cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 234 uint8_t header_type); 235 static void cardbus_dump_config(ddi_acc_handle_t config_handle); 236 static void cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, 237 int nelems); 238 #endif 239 240 static cardbus_phdl_t *cardbus_phdl_list = NULL; 241 242 static struct cardbus_name_entry cardbus_class_lookup [] = { 243 { 0x001, "display", 9 }, 244 { 0x100, "scsi", 4 }, 245 { 0x101, "ide", 4 }, 246 { 0x102, "fdc", 4 }, 247 { 0x103, "ipi", 4 }, 248 { 0x104, "raid", 4 }, 249 { 0x200, "ethernet", 6 }, 250 { 0x201, "token-ring", 6 }, 251 { 0x202, "fddi", 6 }, 252 { 0x203, "atm", 6 }, 253 { 0x300, "display", 9 }, /* VGA card */ 254 { 0x380, "display", 9 }, /* other - for the Raptor Card */ 255 { 0x400, "video", 11 }, 256 { 0x401, "sound", 11 }, 257 { 0x500, "memory", 11 }, 258 { 0x501, "flash", 11 }, 259 { 0x600, "host", 11 }, 260 { 0x601, "isa", 11 }, 261 { 0x602, "eisa", 11 }, 262 { 0x603, "mca", 11 }, 263 { 0x604, "pci", 11 }, 264 { 0x605, "pcmcia", 11 }, 265 { 0x606, "nubus", 11 }, 266 { 0x607, "cardbus", 11 }, 267 { 0x680, NULL, 8 }, 268 { 0x700, "serial", 11 }, 269 { 0x701, "parallel", 6 }, 270 { 0x800, "interrupt-controller", 3 }, 271 { 0x801, "dma-controller", 3 }, 272 { 0x802, "timer", 3 }, 273 { 0x803, "rtc", 3 }, 274 { 0x900, "keyboard", 8 }, 275 { 0x901, "pen", 8 }, 276 { 0x902, "mouse", 8 }, 277 { 0xa00, "dock", 1 }, 278 { 0xb00, "cpu", 1 }, 279 { 0xc00, "firewire", 9 }, 280 { 0xc01, "access-bus", 4 }, 281 { 0xc02, "ssa", 4 }, 282 { 0xc03, "usb", 9 }, 283 { 0xc04, "fibre-channel", 6 }, 284 { 0, 0 } 285 }; 286 287 #ifndef _DONT_USE_1275_GENERIC_NAMES 288 static char *cardbus_get_class_name(uint32_t classcode); 289 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 290 291 /* 292 * Reprogram ILINE with default value only if BIOS doesn't program it 293 */ 294 int 295 cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle) 296 { 297 uint8_t intline = 0xff; 298 299 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 300 intline = pci_config_get8(handle, PCI_CONF_ILINE); 301 if ((intline == 0) || (intline == 0xff)) { 302 intline = ddi_getprop(DDI_DEV_T_ANY, dip, 303 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 304 "interrupt-line", 0xff); 305 if (intline == (uint8_t)0xff) { 306 intline = ddi_getprop(DDI_DEV_T_ANY, 307 ddi_get_parent(dip), 308 DDI_PROP_CANSLEEP /* |DDI_PROP_DONTPASS */, 309 "interrupt-line", 0xb); 310 } 311 312 pci_config_put8(handle, PCI_CONF_ILINE, intline); 313 } 314 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 315 "interrupt-line", intline); 316 } 317 return (intline); 318 } 319 320 /* 321 * This entry point is called to configure a device (and 322 * all its children) on the given bus. It is called when 323 * a new device is added to the PCI domain. This routine 324 * will create the device tree and program the devices 325 * registers. 326 */ 327 int 328 cardbus_configure(cbus_t *cbp) 329 { 330 uint_t bus; 331 int cardbus_dev, func; 332 dev_info_t *attach_point; 333 334 cardbus_err(cbp->cb_dip, 6, "cardbus_configure ()\n"); 335 336 bus = cardbus_primary_busno(cbp->cb_dip); 337 338 if (ndi_devi_alloc(cbp->cb_dip, DEVI_PSEUDO_NEXNAME, 339 (pnode_t)DEVI_SID_NODEID, 340 &attach_point) != NDI_SUCCESS) { 341 cardbus_err(cbp->cb_dip, 1, 342 "cardbus_configure(): Failed to alloc probe node\n"); 343 return (PCICFG_FAILURE); 344 } 345 346 /* 347 * Node name marks this node as the "attachment point". 348 */ 349 if (ndi_devi_set_nodename(attach_point, 350 "hp_attachment", 0) != NDI_SUCCESS) { 351 cardbus_err(cbp->cb_dip, 1, 352 "Failed to set nodename for attachment node\n"); 353 (void) ndi_devi_free(attach_point); 354 return (PCICFG_FAILURE); 355 } 356 357 cardbus_err(ddi_get_parent(attach_point), 8, 358 "Set bus type to cardbus\n"); 359 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 360 ddi_get_parent(attach_point), PCM_DEVICETYPE, 361 "cardbus"); 362 363 split_addr(ddi_get_name_addr(cbp->cb_dip), &cardbus_dev, &func); 364 365 cardbus_err(attach_point, 8, 366 "Configuring [0x%x][0x%x][0x%x]\n", bus, cardbus_dev, func); 367 368 switch (cardbus_probe_bridge(cbp, attach_point, 369 bus, cardbus_dev, func)) { 370 case PCICFG_FAILURE: 371 cardbus_err(cbp->cb_dip, 4, 372 "configure failed: bus [0x%x] slot [0x%x] func [0x%x]\n", 373 bus, cardbus_dev, func); 374 goto cleanup; 375 case PCICFG_NODEVICE: 376 cardbus_err(cbp->cb_dip, 4, 377 "no device: bus [0x%x] slot [0x%x] func [0x%x]\n", 378 bus, cardbus_dev, func); 379 goto cleanup; 380 default: 381 cardbus_err(cbp->cb_dip, 9, 382 "configure: bus => [%d] slot => [%d] func => [%d]\n", 383 bus, cardbus_dev, func); 384 break; 385 } 386 387 if (cardbus_program_ap(cbp->cb_dip) == PCICFG_SUCCESS) { 388 (void) cardbus_reparent_children(attach_point, cbp->cb_dip); 389 (void) ndi_devi_free(attach_point); 390 cbp->cb_nex_ops->enable_intr(cbp->cb_dip); 391 return (PCICFG_SUCCESS); 392 } 393 394 cardbus_err(cbp->cb_dip, 1, "Failed to program devices\n"); 395 396 cleanup: 397 /* 398 * Clean up a partially created "probe state" tree. 399 * There are no resources allocated to the in the 400 * probe state. 401 */ 402 403 cardbus_err(cbp->cb_dip, 6, 404 "Look up device [0x%x] function [0x%x] to clean up\n", 405 cardbus_dev, func); 406 407 cardbus_err(cbp->cb_dip, 6, 408 "Cleaning up device [0x%x] function [0x%x]\n", 409 cardbus_dev, func); 410 411 /* 412 * If this was a bridge device it will have a 413 * probe handle - if not, no harm in calling this. 414 */ 415 (void) cardbus_destroy_phdl(cbp->cb_dip); 416 417 if (ddi_get_child(attach_point)) { 418 /* 419 * This will free up the node 420 */ 421 (void) ndi_devi_offline(ddi_get_child(attach_point), 422 NDI_UNCONFIG|NDI_DEVI_REMOVE); 423 } 424 (void) ndi_devi_free(attach_point); 425 426 return (PCICFG_FAILURE); 427 } 428 429 int 430 cardbus_unconfigure(cbus_t *cbp) 431 { 432 ddi_acc_handle_t config_handle; 433 dev_info_t *dip = cbp->cb_dip; 434 435 cbp->cb_nex_ops->disable_intr(dip); 436 if (pci_config_setup(dip, &config_handle) == DDI_SUCCESS) { 437 disable_cardbus_bridge(dip, config_handle); 438 (void) pci_config_teardown(&config_handle); 439 } else { 440 cardbus_err(dip, 1, 441 "cardbus_unconfigure(): Failed to setup config space\n"); 442 } 443 444 (void) cardbus_free_chunk(dip); 445 cardbus_err(dip, 6, 446 "cardbus_unconfigure: calling cardbus_free_bridge_resources\n"); 447 (void) cardbus_free_bridge_resources(dip); 448 449 return (PCICFG_SUCCESS); 450 } 451 452 int 453 cardbus_teardown_device(dev_info_t *dip) 454 { 455 /* 456 * Free up resources associated with 'dip' 457 */ 458 459 if (cardbus_free_resources(dip) != PCICFG_SUCCESS) { 460 cardbus_err(dip, 1, 461 "cardbus_teardown_device: Failed to free resources\n"); 462 return (PCICFG_FAILURE); 463 } 464 465 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 466 cardbus_err(dip, 1, 467 "cardbus_teardown_device: " 468 "Failed to offline and remove node\n"); 469 return (PCICFG_FAILURE); 470 } 471 472 return (PCICFG_SUCCESS); 473 } 474 475 /* 476 * Get the primary pci bus number. This should be the lowest number 477 * in the bus-range property of our parent. 478 */ 479 int 480 cardbus_primary_busno(dev_info_t *dip) 481 { 482 int len, rval; 483 char bus_type[16] = "(unknown)"; 484 dev_info_t *par = ddi_get_parent(dip); 485 cardbus_bus_range_t *bus_range; 486 487 ASSERT(strcmp(ddi_driver_name(dip), "pcic") == 0); 488 len = sizeof (bus_type); 489 if ((ddi_prop_op(DDI_DEV_T_ANY, par, PROP_LEN_AND_VAL_BUF, 490 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 491 "device_type", 492 (caddr_t)&bus_type, &len) == DDI_SUCCESS)) { 493 ASSERT((strcmp(bus_type, "pci") == 0) || 494 (strcmp(bus_type, "cardbus") == 0)); 495 if (ddi_getlongprop(DDI_DEV_T_ANY, par, 0, "bus-range", 496 (caddr_t)&bus_range, &len) == DDI_PROP_SUCCESS) { 497 cardbus_err(dip, 9, 498 "cardbus_primary_busno: bus range is %d to %d\n", 499 bus_range->lo, bus_range->hi); 500 rval = (int)bus_range->lo; 501 kmem_free((caddr_t)bus_range, len); 502 return (rval); 503 } 504 } 505 506 cardbus_err(dip, 2, 507 "cardbus_primary_busno: Not a pci device or no bus-range\n"); 508 return (-1); 509 } 510 511 static cardbus_phdl_t * 512 cardbus_find_phdl(dev_info_t *dip) 513 { 514 cardbus_phdl_t *entry; 515 516 mutex_enter(&cardbus_list_mutex); 517 for (entry = cardbus_phdl_list; entry != NULL; entry = entry->next) { 518 if (entry->dip == dip) { 519 mutex_exit(&cardbus_list_mutex); 520 return (entry); 521 } 522 } 523 mutex_exit(&cardbus_list_mutex); 524 525 /* 526 * Did'nt find entry - create one 527 */ 528 return (cardbus_create_phdl(dip)); 529 } 530 531 static cardbus_phdl_t * 532 cardbus_create_phdl(dev_info_t *dip) 533 { 534 cardbus_phdl_t *new; 535 536 new = (cardbus_phdl_t *)kmem_zalloc(sizeof (cardbus_phdl_t), KM_SLEEP); 537 538 new->dip = dip; 539 new->io_gran = CBCFG_IOGRAN; 540 new->memory_gran = CBCFG_MEMGRAN; 541 mutex_enter(&cardbus_list_mutex); 542 new->next = cardbus_phdl_list; 543 cardbus_phdl_list = new; 544 mutex_exit(&cardbus_list_mutex); 545 546 return (new); 547 } 548 549 static int 550 cardbus_destroy_phdl(dev_info_t *dip) 551 { 552 cardbus_phdl_t *entry; 553 cardbus_phdl_t *follow = NULL; 554 555 mutex_enter(&cardbus_list_mutex); 556 for (entry = cardbus_phdl_list; entry != NULL; follow = entry, 557 entry = entry->next) { 558 if (entry->dip == dip) { 559 if (entry == cardbus_phdl_list) { 560 cardbus_phdl_list = entry->next; 561 } else { 562 follow->next = entry->next; 563 } 564 /* 565 * If this entry has any allocated memory 566 * or IO space associated with it, that 567 * must be freed up. 568 */ 569 if (entry->memory_len > 0) { 570 (void) ndi_ra_free(dip, 571 entry->memory_base, entry->memory_len, 572 NDI_RA_TYPE_MEM, NDI_RA_PASS); 573 #ifdef _LP64 574 cardbus_err(dip, 8, 575 "cardbus_destroy_phdl: " 576 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 577 entry->memory_base, entry->memory_len); 578 #else 579 cardbus_err(dip, 8, 580 "cardbus_destroy_phdl: " 581 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 582 entry->memory_base, entry->memory_len); 583 #endif 584 } 585 if (entry->io_len > 0) { 586 (void) ndi_ra_free(dip, 587 entry->io_base, entry->io_len, 588 NDI_RA_TYPE_IO, NDI_RA_PASS); 589 cardbus_err(dip, 8, 590 "cardbus_destroy_phdl: " 591 "IO BASE = [0x%x] length [0x%x]\n", 592 entry->io_base, entry->io_len); 593 } 594 /* 595 * Destroy this entry 596 */ 597 kmem_free((caddr_t)entry, sizeof (cardbus_phdl_t)); 598 mutex_exit(&cardbus_list_mutex); 599 return (PCICFG_SUCCESS); 600 } 601 } 602 603 mutex_exit(&cardbus_list_mutex); 604 605 /* 606 * Didn't find the entry 607 */ 608 return (PCICFG_FAILURE); 609 } 610 611 static int 612 cardbus_program_ap(dev_info_t *dip) 613 { 614 cardbus_phdl_t *phdl; 615 uint8_t header_type, sec_bus; 616 ddi_acc_handle_t handle; 617 618 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 619 cardbus_err(dip, 1, 620 "cardbus_program_ap: Failed to map config space!\n"); 621 return (PCICFG_FAILURE); 622 } 623 624 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 625 sec_bus = pci_config_get8(handle, PCI_BCNF_SECBUS); 626 627 cardbus_err(dip, 6, 628 "cardbus_program_ap (header_type=0x%x)\n", header_type); 629 (void) pci_config_teardown(&handle); 630 631 /* 632 * Header type two is PCI to Cardbus bridge, see page 43 of the 633 * CL-PD6832 data sheet 634 */ 635 switch (header_type & PCI_HEADER_TYPE_M) { 636 case PCI_HEADER_CARDBUS: 637 cardbus_err(dip, 8, 638 "cardbus_program_ap calling cardbus_allocate_chunk\n"); 639 if (cardbus_allocate_chunk(dip, 640 header_type & PCI_HEADER_TYPE_M, 641 sec_bus) != PCICFG_SUCCESS) { 642 cardbus_err(dip, 1, 643 "cardbus_program_ap: " 644 "Not enough memory to hotplug\n"); 645 (void) cardbus_destroy_phdl(dip); 646 return (PCICFG_FAILURE); 647 } 648 649 cardbus_err(dip, 8, 650 "cardbus_program_ap calling cardbus_find_phdl\n"); 651 phdl = cardbus_find_phdl(dip); 652 ASSERT(phdl); 653 654 if (phdl == NULL) { 655 cardbus_err(dip, 1, "cardbus_find_phdl failed\n"); 656 return (PCICFG_FAILURE); 657 } 658 phdl->error = PCICFG_SUCCESS; 659 cardbus_err(dip, 8, 660 "cardbus_program_ap calling cardbus_topbridge_assign\n"); 661 cardbus_topbridge_assign(dip, phdl); 662 663 if (phdl->error != PCICFG_SUCCESS) { 664 cardbus_err(dip, 1, "Problem assigning bridge\n"); 665 (void) cardbus_destroy_phdl(dip); 666 return (phdl->error); 667 } 668 break; 669 670 default: 671 return (PCICFG_FAILURE); 672 } 673 674 return (PCICFG_SUCCESS); 675 } 676 677 static void 678 cardbus_topbridge_assign(dev_info_t *dip, cardbus_phdl_t *entry) 679 { 680 ddi_acc_handle_t handle; 681 uint8_t header_type; 682 683 cardbus_err(dip, 6, "cardbus_topbridge_assign\n"); 684 685 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 686 cardbus_err(dip, 1, 687 "cardbus_topbridge_bridge_assign: " 688 "Failed to map config space!\n"); 689 return; 690 } 691 692 header_type = pci_config_get8(handle, 693 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 694 695 /* cardbus bridge is the same as PCI-PCI bridge */ 696 ASSERT((header_type == PCI_HEADER_PPB) || 697 (header_type == PCI_HEADER_CARDBUS)); 698 699 (void) cardbus_bridge_ranges(dip, entry, handle); 700 701 (void) pci_config_teardown(&handle); 702 } 703 704 static int 705 cardbus_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 706 ddi_acc_handle_t handle) 707 { 708 cardbus_range_t range[PCICFG_RANGE_LEN]; 709 int bus_range[2]; 710 int count; 711 int i; 712 713 cardbus_err(dip, 8, "cardbus_bridge_ranges\n"); 714 715 bzero((caddr_t)range, sizeof (cardbus_range_t) * PCICFG_RANGE_LEN); 716 717 (void) cardbus_setup_bridge(dip, entry, handle); 718 719 range[0].child_hi = range[0].parent_hi |= (PCI_REG_REL_M | PCI_ADDR_IO); 720 range[0].child_lo = range[0].parent_lo = entry->io_last; 721 range[1].child_hi = range[1].parent_hi |= (PCI_REG_REL_M | 722 PCI_ADDR_MEM32); 723 range[1].child_lo = range[1].parent_lo = entry->memory_last; 724 725 ndi_devi_enter(dip, &count); 726 ddi_walk_devs(ddi_get_child(dip), cardbus_bridge_assign, (void *)entry); 727 ndi_devi_exit(dip, count); 728 729 (void) cardbus_update_bridge(dip, entry, handle); 730 731 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 732 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 733 734 cardbus_err(dip, 8, 735 "Set up bus-range property to %u->%u\n", 736 bus_range[0], bus_range[1]); 737 738 if ((i = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 739 "bus-range", 740 bus_range, 2)) != DDI_SUCCESS) { 741 742 if (i == DDI_PROP_NOT_FOUND) { 743 cardbus_err(dip, 8, 744 "Create bus-range property, %u->%u\n", 745 bus_range[0], bus_range[1]); 746 i = ddi_prop_create(DDI_DEV_T_NONE, dip, 747 DDI_PROP_CANSLEEP, 748 "bus-range", (caddr_t)bus_range, 749 sizeof (bus_range)); 750 } 751 752 if (i != DDI_PROP_SUCCESS) { 753 cardbus_err(dip, 1, 754 "Failed to set bus-range property, %u->%u (%d)\n", 755 bus_range[0], bus_range[1], i); 756 entry->error = PCICFG_FAILURE; 757 return (DDI_WALK_TERMINATE); 758 } 759 } 760 761 if (entry->io_len > 0) { 762 range[0].size_lo = entry->io_last - entry->io_base; 763 if (cardbus_update_ranges_prop(dip, &range[0])) { 764 cardbus_err(dip, 1, "Failed to update ranges (i/o)\n"); 765 entry->error = PCICFG_FAILURE; 766 return (DDI_WALK_TERMINATE); 767 } 768 } 769 if (entry->memory_len > 0) { 770 range[1].size_lo = entry->memory_last - entry->memory_base; 771 if (cardbus_update_ranges_prop(dip, &range[1])) { 772 cardbus_err(dip, 1, 773 "Failed to update ranges (memory)\n"); 774 entry->error = PCICFG_FAILURE; 775 return (DDI_WALK_TERMINATE); 776 } 777 } 778 779 return (DDI_WALK_PRUNECHILD); 780 } 781 static int 782 cardbus_bridge_assign(dev_info_t *dip, void *hdl) 783 { 784 ddi_acc_handle_t handle; 785 pci_regspec_t *reg; 786 int length; 787 int rcount; 788 int i; 789 int offset; 790 uint64_t mem_answer; 791 uint32_t io_answer, request; 792 uint8_t header_type, base_class; 793 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 794 795 /* 796 * Ignore the attachment point and pcs. 797 */ 798 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 799 strcmp(ddi_binding_name(dip), "pcs") == 0) { 800 cardbus_err(dip, 8, "cardbus_bridge_assign: Ignoring\n"); 801 return (DDI_WALK_CONTINUE); 802 } 803 804 805 cardbus_err(dip, 6, "cardbus_bridge_assign\n"); 806 807 if (entry == NULL) { 808 cardbus_err(dip, 1, "Failed to get entry\n"); 809 return (DDI_WALK_TERMINATE); 810 } 811 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 812 cardbus_err(dip, 1, 813 "cardbus_bridge_assign: Failed to map config space!\n"); 814 entry->error = PCICFG_FAILURE; 815 return (DDI_WALK_TERMINATE); 816 } 817 818 header_type = pci_config_get8(handle, PCI_CONF_HEADER) & 819 PCI_HEADER_TYPE_M; 820 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 821 822 /* 823 * This function is not called for the top bridge and we are 824 * not enumerating down a further cardbus interface yet! 825 */ 826 if (base_class == PCI_CLASS_BRIDGE) { 827 uint8_t sub_class; 828 829 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 830 831 switch (sub_class) { 832 case PCI_BRIDGE_PCI: 833 if (header_type == PCI_HEADER_PPB) { 834 i = cardbus_bridge_ranges(dip, entry, handle); 835 (void) cardbus_config_teardown(&handle); 836 return (i); 837 } 838 goto bad_device; 839 840 case PCI_BRIDGE_ISA: 841 i = cardbus_isa_bridge_ranges(dip, entry, handle); 842 (void) cardbus_config_teardown(&handle); 843 return (i); 844 845 case PCI_BRIDGE_CARDBUS: 846 /* 847 * Fall through, there should be at least one register 848 * set for this. 849 */ 850 break; 851 852 case PCI_BRIDGE_OTHER: 853 default: 854 break; 855 } 856 } 857 858 #ifdef sparc 859 /* 860 * If there is an interrupt pin set program 861 * interrupt line with default values. 862 */ 863 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 864 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 865 } 866 #else 867 (void) cardbus_validate_iline(dip, handle); 868 #endif 869 870 /* 871 * A single device (under a bridge). 872 * For each "reg" property with a length, allocate memory 873 * and program the base registers. 874 */ 875 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 876 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 877 &length) != DDI_PROP_SUCCESS) { 878 cardbus_err(dip, 1, "Failed to read reg property\n"); 879 entry->error = PCICFG_FAILURE; 880 (void) cardbus_config_teardown(&handle); 881 return (DDI_WALK_TERMINATE); 882 } 883 884 rcount = length / sizeof (pci_regspec_t); 885 cardbus_err(dip, 9, "rcount = %d\n", rcount); 886 887 for (i = 0; i < rcount; i++) { 888 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 889 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 890 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 891 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 892 893 (void) cardbus_get_mem(ddi_get_parent(dip), 894 entry, reg[i].pci_size_low, &mem_answer); 895 ASSERT(!PCICFG_HIADDR(mem_answer)); 896 pci_config_put32(handle, offset, 897 PCICFG_LOADDR(mem_answer)); 898 pci_config_put32(handle, offset + 4, 899 PCICFG_HIADDR(mem_answer)); 900 cardbus_err(dip, 8, 901 "REGISTER (64)LO [0x%x] ----> [0x%02x]\n", 902 pci_config_get32(handle, offset), offset); 903 cardbus_err(dip, 8, 904 "REGISTER (64)HI [0x%x] ----> [0x%02x]\n", 905 pci_config_get32(handle, offset+4), 906 offset+4); 907 reg[i].pci_phys_low = PCICFG_HIADDR(mem_answer); 908 reg[i].pci_phys_mid = PCICFG_LOADDR(mem_answer); 909 break; 910 911 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 912 /* allocate memory space from the allocator */ 913 914 (void) cardbus_get_mem(ddi_get_parent(dip), 915 entry, reg[i].pci_size_low, &mem_answer); 916 pci_config_put32(handle, offset, 0xffffffff); 917 request = pci_config_get32(handle, offset); 918 919 pci_config_put32(handle, offset, 920 (uint32_t)mem_answer); 921 reg[i].pci_phys_low = (uint32_t)mem_answer; 922 reg[i].pci_phys_mid = 0; 923 if (((PCI_BASE_TYPE_M & request) == 924 PCI_BASE_TYPE_ALL) && 925 ((PCI_BASE_SPACE_M & request) == 926 PCI_BASE_SPACE_MEM)) { 927 cardbus_err(dip, 8, 928 "REGISTER (64)LO [0x%x] ----> " 929 "[0x%02x]\n", 930 pci_config_get32(handle, offset), 931 offset); 932 pci_config_put32(handle, 933 offset + 4, 0); 934 cardbus_err(dip, 8, 935 "REGISTER (64)HI [0x%x] ----> " 936 "[0x%02x]\n", 937 pci_config_get32(handle, offset+4), 938 offset+4); 939 } else { 940 cardbus_err(dip, 8, 941 "REGISTER (32)LO [0x%x] ----> " 942 "[0x%02x]\n", 943 pci_config_get32(handle, offset), 944 offset); 945 } 946 break; 947 948 case PCI_REG_ADDR_G(PCI_ADDR_IO): 949 /* allocate I/O space from the allocator */ 950 951 (void) cardbus_get_io(ddi_get_parent(dip), 952 entry, reg[i].pci_size_low, &io_answer); 953 pci_config_put32(handle, offset, io_answer); 954 cardbus_err(dip, 8, 955 "REGISTER (I/O)LO [0x%x] ----> [0x%02x]\n", 956 pci_config_get32(handle, offset), offset); 957 reg[i].pci_phys_low = io_answer; 958 break; 959 960 default: 961 cardbus_err(dip, 1, "Unknown register type\n"); 962 kmem_free(reg, length); 963 (void) cardbus_config_teardown(&handle); 964 entry->error = PCICFG_FAILURE; 965 return (DDI_WALK_TERMINATE); 966 } /* switch */ 967 968 /* 969 * Now that memory locations are assigned, 970 * update the assigned address property. 971 */ 972 if (cardbus_update_assigned_prop(dip, 973 ®[i]) != PCICFG_SUCCESS) { 974 kmem_free(reg, length); 975 (void) cardbus_config_teardown(&handle); 976 entry->error = PCICFG_FAILURE; 977 return (DDI_WALK_TERMINATE); 978 } 979 } 980 } 981 kmem_free(reg, length); 982 enable_cardbus_device(dip, handle); 983 #ifdef CARDBUS_DEBUG 984 if (cardbus_debug >= 9) { 985 cardbus_dump_config(handle); 986 } 987 #endif 988 bad_device: 989 (void) cardbus_config_teardown(&handle); 990 return (DDI_WALK_CONTINUE); 991 } 992 993 static int 994 cardbus_isa_bridge_ranges(dev_info_t *dip, cardbus_phdl_t *entry, 995 ddi_acc_handle_t handle) 996 { 997 struct ebus_pci_rangespec range; 998 int count; 999 pci_regspec_t *reg; 1000 int length; 1001 int rcount; 1002 uint32_t io_answer = 0xffffffff; 1003 isa_phdl_t isa_phdl; 1004 int i; 1005 1006 cardbus_err(dip, 8, "cardbus_isa_bridge_ranges\n"); 1007 1008 bzero((caddr_t)&range, sizeof (range)); 1009 1010 #ifdef sparc 1011 /* 1012 * If there is an interrupt pin set program 1013 * interrupt line with default values. 1014 */ 1015 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1016 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1017 } 1018 #else 1019 (void) cardbus_validate_iline(dip, handle); 1020 #endif 1021 1022 /* 1023 * For each "reg" property with a length, allocate memory. 1024 */ 1025 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1026 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1027 &length) != DDI_PROP_SUCCESS) { 1028 cardbus_err(dip, 1, "Failed to read reg property\n"); 1029 entry->error = PCICFG_FAILURE; 1030 return (DDI_WALK_TERMINATE); 1031 } 1032 1033 rcount = length / sizeof (pci_regspec_t); 1034 1035 for (i = 0; i < rcount; i++) { 1036 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1037 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1038 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1039 /* allocate I/O space from the allocator */ 1040 1041 (void) cardbus_get_io(ddi_get_parent(dip), 1042 entry, reg[i].pci_size_low, &io_answer); 1043 cardbus_err(dip, 8, 1044 "ISA (I/O)LO ----> [0x%x]\n", io_answer); 1045 reg[i].pci_phys_low = io_answer; 1046 range.phys_hi = 0; 1047 range.phys_low = io_answer; 1048 range.par_phys_hi = reg[i].pci_phys_hi | 1049 PCI_REG_REL_M; 1050 range.par_phys_low = reg[i].pci_phys_low; 1051 range.par_phys_mid = reg[i].pci_phys_mid; 1052 range.rng_size = reg[i].pci_size_low; 1053 i = rcount; 1054 break; 1055 1056 default: 1057 cardbus_err(dip, 1, "Unknown register type\n"); 1058 kmem_free(reg, length); 1059 (void) cardbus_config_teardown(&handle); 1060 entry->error = PCICFG_FAILURE; 1061 return (DDI_WALK_TERMINATE); 1062 } /* switch */ 1063 } 1064 } 1065 kmem_free(reg, length); 1066 1067 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 1068 dip, "ranges", (int *)&range, 1069 sizeof (range)/sizeof (int)); 1070 if (io_answer != 0xffffffff) { 1071 isa_phdl.dip = dip; 1072 isa_phdl.handle = handle; 1073 isa_phdl.io_base = io_answer; 1074 isa_phdl.io_decode_reg = 0x58; /* Pos decoded IO space 0 reg */ 1075 /* i_ndi_block_device_tree_changes(&count); */ 1076 ndi_devi_enter(dip, &count); 1077 ddi_walk_devs(ddi_get_child(dip), 1078 cardbus_add_isa_reg, (void *)&isa_phdl); 1079 /* i_ndi_allow_device_tree_changes(count); */ 1080 ndi_devi_exit(dip, count); 1081 } 1082 return (DDI_WALK_PRUNECHILD); 1083 } 1084 1085 /* 1086 * This is specific to ITE8888 chip. 1087 */ 1088 static int 1089 cardbus_add_isa_reg(dev_info_t *dip, void *arg) 1090 { 1091 uint32_t io_reg = 0; 1092 int length; 1093 uint32_t reg[3], *breg; 1094 isa_phdl_t *phdl; 1095 uint8_t sz; 1096 1097 phdl = (isa_phdl_t *)arg; 1098 cardbus_err(dip, 6, 1099 "cardbus_add_isa_reg, base 0x%x\n", phdl->io_base); 1100 1101 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1102 DDI_PROP_DONTPASS, "basereg", (caddr_t)&breg, 1103 &length) != DDI_PROP_SUCCESS) { 1104 return (DDI_WALK_CONTINUE); 1105 } 1106 1107 if ((length / sizeof (reg)) < 1) { 1108 kmem_free(breg, length); 1109 return (DDI_WALK_CONTINUE); 1110 } 1111 1112 /* 1113 * Add the "reg" property. 1114 */ 1115 reg[0] = 0; 1116 reg[1] = breg[1] + phdl->io_base; 1117 reg[2] = breg[2]; 1118 1119 /* 1120 * Generate the postive IO decode register setting. 1121 */ 1122 for (sz = 0; sz < 8; sz++) 1123 if ((1<<sz) >= breg[2]) { 1124 io_reg = breg[1] 1125 | (1uL <<31) /* Enable */ 1126 | (2uL <<29) /* Medium speed */ 1127 | (1uL <<28) /* Aliase enable, */ 1128 /* Don't care A[15:10] */ 1129 | (sz<<24); /* Size code */ 1130 break; 1131 } 1132 1133 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1134 "reg", (int *)reg, 3); 1135 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "basereg"); 1136 1137 if (io_reg) { 1138 pci_config_put32(phdl->handle, phdl->io_decode_reg, io_reg); 1139 cardbus_err(dip, 6, 1140 "cardbus_add_isa_reg: I/O decode reg (0x%x) set to 0x%x\n", 1141 phdl->io_decode_reg, 1142 pci_config_get32(phdl->handle, phdl->io_decode_reg)); 1143 phdl->io_decode_reg += sizeof (io_reg); 1144 } else 1145 cardbus_err(dip, 1, 1146 "cardbus_add_isa_reg: register size (0x%x) too large\n", 1147 breg[2]); 1148 kmem_free(breg, length); 1149 return (DDI_WALK_CONTINUE); 1150 } 1151 1152 /* 1153 * In case we want to ensure that some space is allocated to the 1154 * device tree below the cardbus bridge. 1155 * This is only necessary if there is a device that needs to allocate 1156 * resource below us. This can happen if there is another cardbus/PCMCIA 1157 * bridge downstream. 1158 */ 1159 static uint32_t cardbus_min_spare_mem = 0; 1160 static uint32_t cardbus_min_spare_io = 0; 1161 1162 /* 1163 * The "dip" passed to this routine is assumed to be 1164 * the device at the attachment point. Currently it is 1165 * assumed to be a bridge. 1166 */ 1167 static int 1168 cardbus_allocate_chunk(dev_info_t *dip, uint8_t type, uint8_t sec_bus) 1169 { 1170 cardbus_phdl_t *phdl; 1171 ndi_ra_request_t *mem_request; 1172 ndi_ra_request_t *io_request; 1173 uint64_t mem_answer; 1174 uint64_t io_answer; 1175 int count; 1176 uint64_t alen; 1177 1178 /* 1179 * This should not find an existing entry - so 1180 * it will create a new one. 1181 */ 1182 phdl = cardbus_find_phdl(dip); 1183 ASSERT(phdl); 1184 1185 mem_request = &phdl->mem_req; 1186 io_request = &phdl->io_req; 1187 1188 /* 1189 * Set highest_bus here. 1190 * Otherwise if we don't find another bridge 1191 * this never gets set. 1192 */ 1193 phdl->highest_bus = sec_bus; 1194 1195 /* 1196 * From this point in the tree - walk the devices, 1197 * The function passed in will read and "sum" up 1198 * the memory and I/O requirements and put them in 1199 * structure "phdl". 1200 */ 1201 phdl->error = PCICFG_SUCCESS; 1202 ndi_devi_enter(dip, &count); 1203 ddi_walk_devs(ddi_get_child(dip), cardbus_sum_resources, (void *)phdl); 1204 ndi_devi_exit(dip, count); 1205 1206 if (phdl->error != PCICFG_SUCCESS) { 1207 cmn_err(CE_WARN, "Failure summing resources\n"); 1208 return (phdl->error); 1209 } 1210 1211 /* 1212 * Call into the memory allocator with the request. 1213 * Record the addresses returned in the phdl 1214 */ 1215 #ifdef _LP64 1216 cardbus_err(dip, 8, 1217 "AP requires [0x%lx] bytes of memory space, alligned 0x%x\n", 1218 mem_request->ra_len, phdl->memory_gran); 1219 cardbus_err(dip, 8, 1220 "AP requires [0x%lx] bytes of I/O space, alligned 0x%x\n", 1221 io_request->ra_len, phdl->io_gran); 1222 #else 1223 cardbus_err(dip, 8, 1224 "AP requires [0x%llx] bytes of memory space, alligned 0x%x\n", 1225 mem_request->ra_len, phdl->memory_gran); 1226 cardbus_err(dip, 8, 1227 "AP requires [0x%llx] bytes of I/O space, alligned 0x%x\n", 1228 io_request->ra_len, phdl->io_gran); 1229 #endif 1230 1231 ASSERT(type == PCI_HEADER_CARDBUS); 1232 1233 mem_request->ra_align_mask = phdl->memory_gran - 1; 1234 io_request->ra_align_mask = phdl->io_gran - 1; 1235 1236 mem_request->ra_len += cardbus_min_spare_mem; 1237 if (mem_request->ra_len) { 1238 mem_request->ra_len = PCICFG_ROUND_UP( 1239 mem_request->ra_len, 1240 phdl->memory_gran); 1241 #ifdef _LP64 1242 cardbus_err(dip, 8, 1243 "cardbus_allocate_chunk: ndi_ra_alloc 0x%lx bytes\n", 1244 mem_request->ra_len); 1245 #else 1246 cardbus_err(dip, 8, 1247 "cardbus_allocate_chunk: ndi_ra_alloc 0x%llx bytes\n", 1248 mem_request->ra_len); 1249 #endif 1250 1251 if (ndi_ra_alloc(dip, mem_request, &mem_answer, &alen, 1252 NDI_RA_TYPE_MEM, NDI_RA_PASS) != NDI_SUCCESS) { 1253 cmn_err(CE_WARN, "Failed to allocate memory for %s\n", 1254 ddi_driver_name(dip)); 1255 return (PCICFG_FAILURE); 1256 } 1257 1258 phdl->memory_base = phdl->memory_last = mem_answer; 1259 phdl->memory_len = alen; 1260 } 1261 1262 io_request->ra_len += cardbus_min_spare_io; 1263 if (io_request->ra_len) { 1264 1265 #if defined(__x86) || defined(__amd64) 1266 io_request->ra_boundbase = 0x1000; 1267 io_request->ra_boundlen = 0xefff; 1268 #else 1269 io_request->ra_boundbase = 0; 1270 io_request->ra_boundlen = PCICFG_4GIG_LIMIT; 1271 #endif 1272 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1273 io_request->ra_len = PCICFG_ROUND_UP(io_request->ra_len, 1274 phdl->io_gran); 1275 1276 if (ndi_ra_alloc(dip, io_request, &io_answer, 1277 &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) != NDI_SUCCESS) { 1278 cmn_err(CE_WARN, "Failed to allocate I/O space " 1279 "for %s\n", ddi_driver_name(dip)); 1280 if (mem_request->ra_len) { 1281 (void) ndi_ra_free(dip, mem_answer, 1282 alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 1283 phdl->memory_len = phdl->io_len = 0; 1284 } 1285 return (PCICFG_FAILURE); 1286 } 1287 1288 phdl->io_base = phdl->io_last = (uint32_t)io_answer; 1289 phdl->io_len = (uint32_t)alen; 1290 } 1291 1292 #ifdef _LP64 1293 cardbus_err(dip, 6, 1294 "MEMORY BASE = [0x%lx] length [0x%lx]\n", 1295 phdl->memory_base, phdl->memory_len); 1296 #else 1297 cardbus_err(dip, 6, 1298 "MEMORY BASE = [0x%llx] length [0x%llx]\n", 1299 phdl->memory_base, phdl->memory_len); 1300 #endif 1301 cardbus_err(dip, 6, 1302 "IO BASE = [0x%x] length [0x%x]\n", 1303 phdl->io_base, phdl->io_len); 1304 1305 return (PCICFG_SUCCESS); 1306 } 1307 1308 static int 1309 cardbus_free_chunk(dev_info_t *dip) 1310 { 1311 uint_t *bus; 1312 int k; 1313 1314 cardbus_err(dip, 6, "cardbus_free_chunk\n"); 1315 1316 (void) cardbus_destroy_phdl(dip); 1317 1318 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 1319 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 1320 &k) != DDI_PROP_SUCCESS) { 1321 cardbus_err(dip, 1, 1322 "cardbus_free_chunk: Failed to read bus-range property\n"); 1323 return (PCICFG_FAILURE); 1324 } 1325 1326 cardbus_err(dip, 6, 1327 "cardbus_free_chunk: Freeing bus [%d] range [%d]\n", 1328 bus[0], bus[1] - bus[0] + 1); 1329 1330 if (ndi_ra_free(dip, 1331 (uint64_t)bus[0], (uint64_t)(bus[1] - bus[0] + 1), 1332 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1333 cardbus_err(dip, 1, 1334 "cardbus_free_chunk: Failed to free bus numbers\n"); 1335 1336 kmem_free(bus, k); 1337 return (PCICFG_FAILURE); 1338 } 1339 1340 kmem_free(bus, k); 1341 return (PCICFG_SUCCESS); 1342 } 1343 1344 /* 1345 * Put bridge registers into initial state 1346 */ 1347 static void 1348 cardbus_setup_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1349 ddi_acc_handle_t handle) 1350 { 1351 uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1352 1353 #ifdef _LP64 1354 cardbus_err(NULL, 6, 1355 "cardbus_setup_bridge: " 1356 "highest bus %d, mem_last 0x%lx, io_last 0x%x\n", 1357 entry->highest_bus, entry->memory_last, entry->io_last); 1358 #else 1359 cardbus_err(NULL, 6, 1360 "cardbus_setup_bridge: " 1361 "highest bus %d, mem_last 0x%llx, io_last 0x%x\n", 1362 entry->highest_bus, entry->memory_last, entry->io_last); 1363 #endif 1364 1365 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1366 uint32_t uval; 1367 1368 /* 1369 * The highest bus seen during probing is 1370 * the max-subordinate bus 1371 */ 1372 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 1373 1374 uval = PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN); 1375 if (uval != entry->memory_last) { 1376 #ifdef _LP64 1377 cardbus_err(dip, 8, 1378 "Adding [0x%lx] before bridge (mem)\n", 1379 uval - entry->memory_last); 1380 #else 1381 cardbus_err(dip, 8, 1382 "Adding [0x%llx] before bridge (mem)\n", 1383 uval - entry->memory_last); 1384 #endif 1385 (void) cardbus_get_mem(ddi_get_parent(dip), entry, 1386 uval - entry->memory_last, NULL); 1387 } 1388 1389 /* 1390 * Program the memory base register with the 1391 * start of the memory range 1392 */ 1393 #ifdef _LP64 1394 cardbus_err(NULL, 8, 1395 "store 0x%x(0x%lx) in pci bridge memory base register\n", 1396 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1397 entry->memory_last); 1398 #else 1399 cardbus_err(NULL, 8, 1400 "store 0x%x(0x%llx) in pci bridge memory base register\n", 1401 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1402 entry->memory_last); 1403 #endif 1404 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 1405 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1406 1407 uval = PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN); 1408 if (uval != entry->io_last) { 1409 cardbus_err(dip, 8, 1410 "Adding [0x%x] before bridge (I/O)\n", 1411 uval - entry->io_last); 1412 (void) cardbus_get_io(ddi_get_parent(dip), entry, 1413 uval - entry->io_last, NULL); 1414 } 1415 cardbus_err(NULL, 8, 1416 "store 0x%02x/0x%04x(0x%x) in " 1417 "pci bridge I/O hi/low base register\n", 1418 PCICFG_HIWORD(PCICFG_LOADDR(uval)), 1419 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval))), 1420 entry->io_last); 1421 /* 1422 * Program the I/O base register with the start of the I/O range 1423 */ 1424 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 1425 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(uval)))); 1426 1427 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 1428 PCICFG_HIWORD(PCICFG_LOADDR(uval))); 1429 1430 /* 1431 * Clear status bits 1432 */ 1433 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 1434 1435 /* 1436 * Turn off prefetchable range 1437 */ 1438 pci_config_put32(handle, PCI_BCNF_PF_BASE_LOW, 0x0000ffff); 1439 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 1440 1441 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, 0x0); 1442 1443 #ifdef sparc 1444 /* 1445 * If there is an interrupt pin set program 1446 * interrupt line with default values. 1447 */ 1448 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1449 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1450 } 1451 #else 1452 (void) cardbus_validate_iline(dip, handle); 1453 #endif 1454 1455 1456 } else if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_CARDBUS) { 1457 1458 /* 1459 * The highest bus seen during probing is 1460 * the max-subordinate bus 1461 */ 1462 pci_config_put8(handle, PCI_CBUS_SUB_BUS_NO, 1463 entry->highest_bus); 1464 1465 /* 1466 * Program the memory base register with the 1467 * start of the memory range 1468 */ 1469 #ifdef _LP64 1470 cardbus_err(NULL, 8, 1471 "store 0x%x(0x%lx) in " 1472 "cardbus memory base register 0, len 0x%lx\n", 1473 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1474 entry->memory_len); 1475 #else 1476 cardbus_err(NULL, 8, 1477 "store 0x%x(0x%llx) in " 1478 "cardbus memory base register 0, len 0x%llx\n", 1479 PCICFG_LOADDR(entry->memory_last), entry->memory_last, 1480 entry->memory_len); 1481 #endif 1482 1483 pci_config_put32(handle, PCI_CBUS_MEM_BASE0, 1484 PCICFG_LOADDR(entry->memory_last)); 1485 1486 /* 1487 * Program the I/O base register with the start of the I/O range 1488 */ 1489 cardbus_err(NULL, 8, 1490 "store 0x%x in cb IO base register 0 len 0x%x\n", 1491 PCICFG_LOADDR(entry->io_last), 1492 entry->io_len); 1493 1494 pci_config_put32(handle, PCI_CBUS_IO_BASE0, 1495 PCICFG_LOADDR(entry->io_last)); 1496 1497 /* 1498 * Clear status bits 1499 */ 1500 pci_config_put16(handle, PCI_CBUS_SEC_STATUS, 0xffff); 1501 1502 #ifdef sparc 1503 /* 1504 * If there is an interrupt pin set program 1505 * interrupt line with default values. 1506 */ 1507 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1508 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1509 } 1510 #else 1511 (void) cardbus_validate_iline(dip, handle); 1512 #endif 1513 1514 1515 /* 1516 * LATER: use these registers 1517 */ 1518 pci_config_put32(handle, PCI_CBUS_MEM_BASE1, 0); 1519 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT1, 0); 1520 pci_config_put32(handle, PCI_CBUS_IO_BASE1, 0); 1521 pci_config_put32(handle, PCI_CBUS_IO_LIMIT1, 0); 1522 } else { 1523 cmn_err(CE_WARN, "header type 0x%x, probably unknown bridge\n", 1524 header_type & PCI_HEADER_TYPE_M); 1525 } 1526 1527 cardbus_err(NULL, 7, "cardbus_setup_bridge complete\n"); 1528 } 1529 1530 static void 1531 cardbus_update_bridge(dev_info_t *dip, cardbus_phdl_t *entry, 1532 ddi_acc_handle_t handle) 1533 { 1534 uint_t length; 1535 uint16_t word16 = pci_config_get16(handle, PCI_CONF_COMM); 1536 const uint8_t header_type = pci_config_get8(handle, PCI_CONF_HEADER) 1537 & PCI_HEADER_TYPE_M; 1538 uint32_t bridge_gran; 1539 uint64_t rlval; 1540 1541 if (header_type == PCI_HEADER_CARDBUS) 1542 bridge_gran = CBCFG_MEMGRAN; 1543 else 1544 bridge_gran = PCICFG_MEMGRAN; 1545 1546 /* 1547 * Program the memory limit register with the end of the memory range 1548 */ 1549 #ifdef _LP64 1550 cardbus_err(dip, 6, 1551 "cardbus_update_bridge: Mem base 0x%lx len 0x%lx " 1552 "last 0x%lx gran 0x%x gran end 0x%lx\n", 1553 entry->memory_base, entry->memory_len, 1554 entry->memory_last, entry->memory_gran, 1555 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1556 #else 1557 cardbus_err(dip, 6, 1558 "cardbus_update_bridge: Mem base 0x%llx len 0x%llx " 1559 "last 0x%llx gran 0x%x gran end 0x%lx\n", 1560 entry->memory_base, entry->memory_len, 1561 entry->memory_last, entry->memory_gran, 1562 PCICFG_ROUND_UP(entry->memory_last, entry->memory_gran)); 1563 #endif 1564 /* 1565 * Since this is a bridge, the rest of this range will 1566 * be responded to by the bridge. We have to round up 1567 * so no other device claims it. 1568 */ 1569 length = PCICFG_ROUND_UP(entry->memory_last + cardbus_min_spare_mem, 1570 bridge_gran) - entry->memory_last; 1571 1572 if (length > 0) { 1573 /* 1574 * This is to allow space that isn't actually being used by 1575 * anything to be allocated by devices such as a downstream 1576 * PCMCIA controller. 1577 */ 1578 (void) cardbus_get_mem(dip, entry, length, NULL); 1579 cardbus_err(dip, 8, 1580 "Added [0x%x] at the top of the bridge (mem)\n", length); 1581 } 1582 1583 if (entry->memory_len) { 1584 if (header_type == PCI_HEADER_CARDBUS) { 1585 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1586 CBCFG_MEMGRAN); 1587 #ifdef _LP64 1588 cardbus_err(dip, 8, 1589 "store 0x%x(0x%lx) in memory limit register 0\n", 1590 PCICFG_LOADDR(rlval), rlval); 1591 #else 1592 cardbus_err(dip, 8, 1593 "store 0x%x(0x%llx) in memory limit register 0\n", 1594 PCICFG_LOADDR(rlval), rlval); 1595 #endif 1596 pci_config_put32(handle, PCI_CBUS_MEM_LIMIT0, 1597 PCICFG_LOADDR(rlval)); 1598 } else { 1599 rlval = PCICFG_ROUND_DOWN(entry->memory_last - 1, 1600 PCICFG_MEMGRAN); 1601 #ifdef _LP64 1602 cardbus_err(dip, 8, 1603 "store 0x%x(0x%lx) in memory limit register\n", 1604 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1605 rlval); 1606 #else 1607 cardbus_err(dip, 8, 1608 "store 0x%x(0x%llx) in memory limit register\n", 1609 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1610 rlval); 1611 #endif 1612 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 1613 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1614 } 1615 word16 |= PCI_COMM_MAE; 1616 } 1617 1618 cardbus_err(dip, 6, 1619 "cardbus_update_bridge: I/O base 0x%x len 0x%x last 0x%x " 1620 "gran 0x%x gran_end 0x%lx\n", 1621 entry->io_base, entry->io_len, entry->io_last, entry->io_gran, 1622 PCICFG_ROUND_UP(entry->io_last, entry->io_gran)); 1623 1624 if (header_type == PCI_HEADER_CARDBUS) 1625 bridge_gran = CBCFG_IOGRAN; 1626 else 1627 bridge_gran = PCICFG_IOGRAN; 1628 1629 /* 1630 * Same as above for I/O space. Since this is a 1631 * bridge, the rest of this range will be responded 1632 * to by the bridge. We have to round up so no 1633 * other device claims it. 1634 */ 1635 length = PCICFG_ROUND_UP(entry->io_last + cardbus_min_spare_io, 1636 bridge_gran) - entry->io_last; 1637 if (length > 0) { 1638 (void) cardbus_get_io(dip, entry, length, NULL); 1639 cardbus_err(dip, 8, 1640 "Added [0x%x] at the top of the bridge (I/O)\n", length); 1641 } 1642 1643 /* 1644 * Program the I/O limit register with the end of the I/O range 1645 */ 1646 if (entry->io_len) { 1647 if (header_type == PCI_HEADER_CARDBUS) { 1648 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1649 CBCFG_IOGRAN); 1650 #ifdef _LP64 1651 cardbus_err(dip, 8, 1652 "store 0x%lx in IO limit register 0\n", rlval); 1653 #else 1654 cardbus_err(dip, 8, 1655 "store 0x%llx in IO limit register 0\n", rlval); 1656 #endif 1657 pci_config_put32(handle, PCI_CBUS_IO_LIMIT0, rlval); 1658 } else { 1659 rlval = PCICFG_ROUND_DOWN(entry->io_last - 1, 1660 PCICFG_IOGRAN); 1661 #ifdef _LP64 1662 cardbus_err(dip, 8, 1663 "store 0x%x/0x%x(0x%lx) in " 1664 "IO limit low/hi register\n", 1665 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1666 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1667 rlval); 1668 #else 1669 cardbus_err(dip, 8, 1670 "store 0x%x/0x%x(0x%llx) in " 1671 "IO limit low/hi register\n", 1672 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval))), 1673 PCICFG_HIWORD(PCICFG_LOADDR(rlval)), 1674 rlval); 1675 #endif 1676 1677 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 1678 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(rlval)))); 1679 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, 1680 PCICFG_HIWORD(PCICFG_LOADDR(rlval))); 1681 } 1682 word16 |= PCI_COMM_IO; 1683 } 1684 1685 pci_config_put16(handle, PCI_CONF_COMM, word16); 1686 } 1687 1688 static void 1689 cardbus_get_mem(dev_info_t *dip, cardbus_phdl_t *entry, 1690 uint32_t length, uint64_t *ans) 1691 { 1692 uint32_t hole; 1693 1694 #ifdef _LP64 1695 cardbus_err(NULL, 6, 1696 "cardbus_get_mem: memory_last 0x%lx, length 0x%x, " 1697 "memory_base 0x%lx, memory_len 0x%lx ans=0x%p\n", 1698 entry->memory_last, length, 1699 entry->memory_base, entry->memory_len, (void *) ans); 1700 #else 1701 cardbus_err(NULL, 6, 1702 "cardbus_get_mem: memory_last 0x%llx, length 0x%x, " 1703 "memory_base 0x%llx, memory_len 0x%llx ans=0x%p\n", 1704 entry->memory_last, length, 1705 entry->memory_base, entry->memory_len, (void *) ans); 1706 #endif 1707 1708 if (ans) { 1709 /* 1710 * Round up the request to the "size" boundary 1711 */ 1712 hole = PCICFG_ROUND_UP(entry->memory_last, length) 1713 - entry->memory_last; 1714 if (hole != 0) { 1715 (void) cardbus_update_available_prop(dip, 1716 PCI_ADDR_MEM32, 1717 entry->memory_last, 1718 (uint64_t)hole); 1719 entry->memory_last += hole; 1720 1721 #ifdef _LP64 1722 cardbus_err(NULL, 6, 1723 "cardbus_get_mem: " 1724 "rounded memory_last up by 0x%x to 0x%lx, ", 1725 hole, entry->memory_last); 1726 #else 1727 cardbus_err(NULL, 6, 1728 "cardbus_get_mem: " 1729 "rounded memory_last up by 0x%x to 0x%llx, ", 1730 hole, entry->memory_last); 1731 #endif 1732 } 1733 } else 1734 (void) cardbus_update_available_prop(dip, PCI_ADDR_MEM32, 1735 entry->memory_last, 1736 (uint64_t)length); 1737 1738 /* 1739 * These routines should parcel out the memory 1740 * completely. There should never be a case of 1741 * over running the bounds. 1742 */ 1743 if ((entry->memory_last + length) > 1744 (entry->memory_base + entry->memory_len)) 1745 #ifdef _LP64 1746 cardbus_err(NULL, 1, 1747 "cardbus_get_mem: assert will fail %ld <= %ld," 1748 "(0x%lx + 0x%x) <= (0x%lx + 0x%lx)\n", 1749 #else 1750 cardbus_err(NULL, 1, 1751 "cardbus_get_mem: assert will fail %lld <= %lld, " 1752 "(0x%llx + 0x%x) <= (0x%llx + 0x%llx)\n", 1753 #endif 1754 entry->memory_last + length, 1755 entry->memory_base + entry->memory_len, 1756 entry->memory_last, 1757 length, 1758 entry->memory_base, 1759 entry->memory_len); 1760 1761 ASSERT((entry->memory_last + length) <= 1762 (entry->memory_base + entry->memory_len)); 1763 /* 1764 * If ans is NULL don't return anything, 1765 * they are just asking to reserve the memory. 1766 */ 1767 if (ans != NULL) 1768 *ans = entry->memory_last; 1769 1770 /* 1771 * Increment to the next location 1772 */ 1773 entry->memory_last += length; 1774 } 1775 1776 static void 1777 cardbus_get_io(dev_info_t *dip, cardbus_phdl_t *entry, 1778 uint32_t length, uint32_t *ans) 1779 { 1780 uint32_t hole; 1781 1782 cardbus_err(NULL, 6, 1783 "cardbus_get_io: io_last 0x%x, length 0x%x, " 1784 "io_base 0x%x, io_len 0x%x ans=0x%p\n", 1785 entry->io_last, length, 1786 entry->io_base, entry->io_len, (void *) ans); 1787 1788 if (ans) { 1789 /* 1790 * Round up the request to the "size" boundary 1791 */ 1792 hole = PCICFG_ROUND_UP(entry->io_last, length) - entry->io_last; 1793 if (hole != 0) { 1794 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1795 (uint64_t)entry->io_last, 1796 (uint64_t)hole); 1797 entry->io_last += hole; 1798 1799 cardbus_err(NULL, 6, 1800 "cardbus_get_io: " 1801 "rounded io_last up by 0x%x to 0x%x, ", 1802 hole, entry->io_last); 1803 } 1804 } else 1805 (void) cardbus_update_available_prop(dip, PCI_ADDR_IO, 1806 (uint64_t)entry->io_last, 1807 (uint64_t)length); 1808 /* 1809 * These routines should parcel out the memory 1810 * completely. There should never be a case of 1811 * over running the bounds. 1812 */ 1813 ASSERT((entry->io_last + length) <= 1814 (entry->io_base + entry->io_len)); 1815 1816 /* 1817 * If ans is NULL don't return anything, 1818 * they are just asking to reserve the memory. 1819 */ 1820 if (ans != NULL) 1821 *ans = entry->io_last; 1822 1823 /* 1824 * Increment to the next location 1825 */ 1826 entry->io_last += length; 1827 } 1828 1829 static int 1830 cardbus_sum_resources(dev_info_t *dip, void *hdl) 1831 { 1832 cardbus_phdl_t *entry = (cardbus_phdl_t *)hdl; 1833 pci_regspec_t *pci_rp; 1834 int length; 1835 int rcount; 1836 int i, ret; 1837 ndi_ra_request_t *mem_request; 1838 ndi_ra_request_t *io_request; 1839 uint8_t header_type, base_class; 1840 ddi_acc_handle_t handle; 1841 1842 /* 1843 * Ignore the attachment point and pcs. 1844 */ 1845 if (strcmp(ddi_binding_name(dip), "hp_attachment") == 0 || 1846 strcmp(ddi_binding_name(dip), "pcs") == 0) { 1847 cardbus_err(dip, 8, "cardbus_sum_resources: Ignoring\n"); 1848 return (DDI_WALK_CONTINUE); 1849 } 1850 1851 mem_request = &entry->mem_req; 1852 io_request = &entry->io_req; 1853 1854 if (cardbus_config_setup(dip, &handle) != DDI_SUCCESS) { 1855 cardbus_err(dip, 1, 1856 "cardbus_sum_resources: Failed to map config space!\n"); 1857 entry->error = PCICFG_FAILURE; 1858 return (DDI_WALK_TERMINATE); 1859 } 1860 1861 ret = DDI_WALK_CONTINUE; 1862 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1863 base_class = pci_config_get8(handle, PCI_CONF_BASCLASS); 1864 1865 /* 1866 * If its a bridge - just record the highest bus seen 1867 */ 1868 if (base_class == PCI_CLASS_BRIDGE) { 1869 uint8_t sub_class; 1870 1871 sub_class = pci_config_get8(handle, PCI_CONF_SUBCLASS); 1872 1873 switch (sub_class) { 1874 case PCI_BRIDGE_PCI: 1875 if ((header_type & PCI_HEADER_TYPE_M) 1876 == PCI_HEADER_PPB) { 1877 1878 if (entry->highest_bus < pci_config_get8(handle, 1879 PCI_BCNF_SECBUS)) { 1880 entry->highest_bus = pci_config_get8( 1881 handle, PCI_BCNF_SECBUS); 1882 } 1883 1884 (void) cardbus_config_teardown(&handle); 1885 #if defined(CARDBUS_DEBUG) 1886 if (mem_request->ra_len != 1887 PCICFG_ROUND_UP(mem_request->ra_len, 1888 PCICFG_MEMGRAN)) { 1889 1890 #ifdef _LP64 1891 cardbus_err(dip, 8, 1892 "Pre-align [0x%lx] to PCI bridge " 1893 "memory gran " 1894 "[0x%lx] -> [0x%lx]\n", 1895 PCICFG_ROUND_UP(mem_request->ra_len, 1896 PCICFG_MEMGRAN) - 1897 mem_request->ra_len, 1898 mem_request->ra_len, 1899 PCICFG_ROUND_UP(mem_request->ra_len, 1900 PCICFG_MEMGRAN)); 1901 #else 1902 cardbus_err(dip, 8, 1903 "Pre-align [0x%llx] to PCI bridge " 1904 "memory gran " 1905 "[0x%llx] -> [0x%lx]\n", 1906 PCICFG_ROUND_UP(mem_request->ra_len, 1907 PCICFG_MEMGRAN) - 1908 mem_request->ra_len, 1909 mem_request->ra_len, 1910 PCICFG_ROUND_UP(mem_request->ra_len, 1911 PCICFG_MEMGRAN)); 1912 #endif 1913 } 1914 1915 if (io_request->ra_len != 1916 PCICFG_ROUND_UP(io_request->ra_len, 1917 PCICFG_IOGRAN)) { 1918 1919 #ifdef _LP64 1920 cardbus_err(dip, 8, 1921 "Pre-align [0x%lx] to PCI bridge " 1922 "I/O gran " 1923 "[0x%lx] -> [0x%lx]\n", 1924 PCICFG_ROUND_UP(io_request->ra_len, 1925 PCICFG_IOGRAN) - 1926 io_request->ra_len, 1927 io_request->ra_len, 1928 PCICFG_ROUND_UP(io_request->ra_len, 1929 PCICFG_IOGRAN)); 1930 #else 1931 cardbus_err(dip, 8, 1932 "Pre-align [0x%llx] to PCI bridge " 1933 "I/O gran " 1934 "[0x%llx] -> [0x%lx]\n", 1935 PCICFG_ROUND_UP(io_request->ra_len, 1936 PCICFG_IOGRAN) - 1937 io_request->ra_len, 1938 io_request->ra_len, 1939 PCICFG_ROUND_UP(io_request->ra_len, 1940 PCICFG_IOGRAN)); 1941 #endif 1942 } 1943 1944 #endif 1945 mem_request->ra_len = PCICFG_ROUND_UP( 1946 mem_request->ra_len, 1947 PCICFG_MEMGRAN); 1948 io_request->ra_len = PCICFG_ROUND_UP( 1949 io_request->ra_len, 1950 PCICFG_IOGRAN); 1951 if (entry->memory_gran < PCICFG_MEMGRAN) 1952 entry->memory_gran = PCICFG_MEMGRAN; 1953 if (entry->io_gran < PCICFG_IOGRAN) 1954 entry->io_gran = PCICFG_IOGRAN; 1955 ddi_walk_devs(ddi_get_child(dip), 1956 cardbus_sum_resources, 1957 (void *)entry); 1958 #if defined(CARDBUS_DEBUG) 1959 if (mem_request->ra_len != 1960 PCICFG_ROUND_UP(mem_request->ra_len + 1961 cardbus_min_spare_mem, PCICFG_MEMGRAN)) { 1962 1963 #ifdef _LP64 1964 cardbus_err(dip, 8, 1965 "Post-align [0x%lx] to PCI bridge " 1966 "memory gran " 1967 "[0x%lx] -> [0x%lx]\n", 1968 PCICFG_ROUND_UP( 1969 mem_request->ra_len + 1970 cardbus_min_spare_mem, 1971 PCICFG_MEMGRAN) - 1972 mem_request->ra_len, 1973 mem_request->ra_len, 1974 PCICFG_ROUND_UP(mem_request->ra_len 1975 + cardbus_min_spare_mem, 1976 PCICFG_MEMGRAN)); 1977 #else 1978 cardbus_err(dip, 8, 1979 "Post-align [0x%llx] to PCI bridge " 1980 "memory gran " 1981 "[0x%llx] -> [0x%lx]\n", 1982 PCICFG_ROUND_UP( 1983 mem_request->ra_len + 1984 cardbus_min_spare_mem, 1985 PCICFG_MEMGRAN) - 1986 mem_request->ra_len, 1987 mem_request->ra_len, 1988 PCICFG_ROUND_UP(mem_request->ra_len 1989 + cardbus_min_spare_mem, 1990 PCICFG_MEMGRAN)); 1991 #endif 1992 } 1993 1994 if (io_request->ra_len != 1995 PCICFG_ROUND_UP(io_request->ra_len + 1996 cardbus_min_spare_io, 1997 PCICFG_IOGRAN)) { 1998 1999 #ifdef _LP64 2000 cardbus_err(dip, 8, 2001 "Post-align [0x%lx] to PCI bridge " 2002 "I/O gran " 2003 "[0x%lx] -> [0x%lx]\n", 2004 PCICFG_ROUND_UP(io_request->ra_len + 2005 cardbus_min_spare_io, 2006 PCICFG_IOGRAN) - 2007 io_request->ra_len, 2008 io_request->ra_len, 2009 PCICFG_ROUND_UP(io_request->ra_len + 2010 cardbus_min_spare_io, 2011 PCICFG_IOGRAN)); 2012 #else 2013 cardbus_err(dip, 8, 2014 "Post-align [0x%llx] to PCI bridge " 2015 "I/O gran " 2016 "[0x%llx] -> [0x%lx]\n", 2017 PCICFG_ROUND_UP(io_request->ra_len + 2018 cardbus_min_spare_io, 2019 PCICFG_IOGRAN) - 2020 io_request->ra_len, 2021 io_request->ra_len, 2022 PCICFG_ROUND_UP(io_request->ra_len + 2023 cardbus_min_spare_io, 2024 PCICFG_IOGRAN)); 2025 #endif 2026 } 2027 #endif 2028 mem_request->ra_len = PCICFG_ROUND_UP( 2029 mem_request->ra_len + 2030 cardbus_min_spare_mem, 2031 PCICFG_MEMGRAN); 2032 io_request->ra_len = PCICFG_ROUND_UP( 2033 io_request->ra_len + 2034 cardbus_min_spare_io, 2035 PCICFG_IOGRAN); 2036 } 2037 return (DDI_WALK_PRUNECHILD); 2038 2039 case PCI_BRIDGE_CARDBUS: 2040 /* 2041 * Cardbus has I/O registers. 2042 */ 2043 break; 2044 2045 case PCI_BRIDGE_ISA: 2046 /* 2047 * All the registers requirements for ISA 2048 * are stored in the reg structure of the bridge. 2049 * Children of ISA are not of type PCI 2050 * so must not come through here because 2051 * cardbus_config_setup() will fail. 2052 */ 2053 ret = DDI_WALK_PRUNECHILD; 2054 break; 2055 2056 default: 2057 /* 2058 * Treat other bridges as leaf nodes. 2059 */ 2060 break; 2061 } 2062 } 2063 2064 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2065 DDI_PROP_DONTPASS, "reg", (caddr_t)&pci_rp, 2066 &length) != DDI_PROP_SUCCESS) { 2067 /* 2068 * If one node in (the subtree of nodes) 2069 * does'nt have a "reg" property fail the 2070 * allocation. 2071 */ 2072 entry->memory_len = 0; 2073 entry->io_len = 0; 2074 entry->error = PCICFG_FAILURE; 2075 (void) cardbus_config_teardown(&handle); 2076 return (DDI_WALK_TERMINATE); 2077 } 2078 2079 /* 2080 * For each "reg" property with a length, add that to the 2081 * total memory (or I/O) to allocate. 2082 */ 2083 rcount = length / sizeof (pci_regspec_t); 2084 2085 for (i = 0; i < rcount; i++) { 2086 2087 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2088 2089 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2090 mem_request->ra_len = 2091 pci_rp[i].pci_size_low + 2092 PCICFG_ROUND_UP(mem_request->ra_len, 2093 pci_rp[i].pci_size_low); 2094 2095 cardbus_err(dip, 8, 2096 "ADDING 32 --->0x%x for BAR@0x%x\n", 2097 pci_rp[i].pci_size_low, 2098 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2099 /* 2100 * the granualarity needs to be the larger of 2101 * the maximum amount of memory that we're going to 2102 * ask for, and the PCI-PCI bridge granularity (1M) 2103 */ 2104 if (pci_rp[i].pci_size_low > entry->memory_gran) 2105 entry->memory_gran = pci_rp[i].pci_size_low; 2106 break; 2107 2108 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2109 mem_request->ra_len = 2110 pci_rp[i].pci_size_low + 2111 PCICFG_ROUND_UP(mem_request->ra_len, 2112 pci_rp[i].pci_size_low); 2113 cardbus_err(dip, 8, 2114 "ADDING 64 --->0x%x for BAR@0x%x\n", 2115 pci_rp[i].pci_size_low, 2116 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2117 2118 if (pci_rp[i].pci_size_low > entry->memory_gran) 2119 entry->memory_gran = pci_rp[i].pci_size_low; 2120 break; 2121 2122 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2123 io_request->ra_len = 2124 pci_rp[i].pci_size_low + 2125 PCICFG_ROUND_UP(io_request->ra_len, 2126 pci_rp[i].pci_size_low); 2127 cardbus_err(dip, 8, 2128 "ADDING I/O --->0x%x for BAR@0x%x\n", 2129 pci_rp[i].pci_size_low, 2130 PCI_REG_REG_G(pci_rp[i].pci_phys_hi)); 2131 2132 if (pci_rp[i].pci_size_low > entry->io_gran) 2133 entry->io_gran = pci_rp[i].pci_size_low; 2134 break; 2135 2136 default: 2137 /* Config space register - not included */ 2138 break; 2139 } 2140 } 2141 2142 /* 2143 * free the memory allocated by ddi_getlongprop 2144 */ 2145 kmem_free(pci_rp, length); 2146 2147 /* 2148 * continue the walk to the next sibling to sum memory 2149 */ 2150 2151 (void) cardbus_config_teardown(&handle); 2152 2153 #ifdef _LP64 2154 cardbus_err(dip, 8, 2155 "Memory 0x%lx bytes, I/O 0x%lx bytes, " 2156 "Memgran 0x%x, IOgran 0x%x\n", 2157 mem_request->ra_len, io_request->ra_len, 2158 entry->memory_gran, entry->io_gran); 2159 #else 2160 cardbus_err(dip, 8, 2161 "Memory 0x%llx bytes, I/O 0x%llx bytes, " 2162 "Memgran 0x%x, IOgran 0x%x\n", 2163 mem_request->ra_len, io_request->ra_len, 2164 entry->memory_gran, entry->io_gran); 2165 #endif 2166 2167 return (ret); 2168 } 2169 2170 /* 2171 * Free resources allocated to a bridge. 2172 * Note that this routine does not call ndi_ra_free() to actually 2173 * free memory/IO/Bus. This is done as a single chunk for the entire 2174 * device tree in cardbus_free_chunk(). 2175 */ 2176 static int 2177 cardbus_free_bridge_resources(dev_info_t *dip) 2178 { 2179 cardbus_range_t *ranges; 2180 uint_t *bus; 2181 int k; 2182 int length; 2183 int i; 2184 2185 cardbus_err(dip, 6, "cardbus_free_bridge_resources\n"); 2186 2187 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2188 DDI_PROP_DONTPASS, "ranges", (caddr_t)&ranges, 2189 &length) == DDI_PROP_SUCCESS) { 2190 for (i = 0; i < length / sizeof (cardbus_range_t); i++) { 2191 if (ranges[i].size_lo != 0 || ranges[i].size_hi != 0) { 2192 switch (ranges[i].parent_hi & PCI_REG_ADDR_M) { 2193 case PCI_ADDR_IO: 2194 cardbus_err(dip, 6, 2195 "Need to Free I/O " 2196 "base/length = [0x%x]/[0x%x]\n", 2197 ranges[i].child_lo, 2198 ranges[i].size_lo); 2199 break; 2200 2201 case PCI_ADDR_MEM32: 2202 case PCI_ADDR_MEM64: 2203 cardbus_err(dip, 6, 2204 "Need to Free Memory base/length = " 2205 "[0x%x.%x]/[0x%x]\n", 2206 ranges[i].child_mid, 2207 ranges[i].child_lo, 2208 ranges[i].size_lo); 2209 break; 2210 2211 default: 2212 cardbus_err(dip, 6, 2213 "Unknown memory space\n"); 2214 break; 2215 } 2216 } 2217 } 2218 2219 kmem_free(ranges, length); 2220 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "ranges"); 2221 } else { 2222 cardbus_err(dip, 8, 2223 "cardbus_free_bridge_resources: Failed" 2224 "to read ranges property\n"); 2225 } 2226 2227 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2228 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, 2229 &k) != DDI_PROP_SUCCESS) { 2230 cardbus_err(dip, 6, "Failed to read bus-range property\n"); 2231 return (PCICFG_FAILURE); 2232 } 2233 2234 cardbus_err(dip, 6, 2235 "Need to free bus [%d] range [%d]\n", 2236 bus[0], bus[1] - bus[0] + 1); 2237 2238 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "available"); 2239 (void) ndi_prop_remove(DDI_DEV_T_NONE, dip, "bus-range"); 2240 2241 return (PCICFG_SUCCESS); 2242 } 2243 2244 static int 2245 cardbus_free_device_resources(dev_info_t *dip) 2246 { 2247 pci_regspec_t *assigned; 2248 2249 int length; 2250 int acount; 2251 int i; 2252 2253 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2254 DDI_PROP_DONTPASS, "assigned-addresses", 2255 (caddr_t)&assigned, 2256 &length) != DDI_PROP_SUCCESS) { 2257 cardbus_err(dip, 1, 2258 "Failed to read assigned-addresses property\n"); 2259 return (PCICFG_FAILURE); 2260 } 2261 2262 /* 2263 * For each "assigned-addresses" property entry with a length, 2264 * call the memory allocation routines to return the 2265 * resource. 2266 */ 2267 acount = length / sizeof (pci_regspec_t); 2268 for (i = 0; i < acount; i++) { 2269 2270 /* 2271 * Free the resource if the size of it is not zero. 2272 */ 2273 if ((assigned[i].pci_size_low != 0)|| 2274 (assigned[i].pci_size_hi != 0)) { 2275 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2276 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2277 cardbus_err(dip, 6, 2278 "Need to return 0x%x of 32 bit MEM space" 2279 " @ 0x%x from register 0x%x\n", 2280 assigned[i].pci_size_low, 2281 assigned[i].pci_phys_low, 2282 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2283 2284 break; 2285 2286 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2287 cardbus_err(dip, 6, 2288 "Need to return 0x%x of 64 bit MEM space" 2289 " @ 0x%x.%x from register 0x%x\n", 2290 assigned[i].pci_size_low, 2291 assigned[i].pci_phys_mid, 2292 assigned[i].pci_phys_low, 2293 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2294 2295 break; 2296 2297 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2298 cardbus_err(dip, 6, 2299 "Need to return 0x%x of IO space @ 0x%x" 2300 " from register 0x%x\n", 2301 assigned[i].pci_size_low, 2302 assigned[i].pci_phys_low, 2303 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2304 break; 2305 2306 default: 2307 cardbus_err(dip, 1, "Unknown register type\n"); 2308 kmem_free(assigned, length); 2309 return (PCICFG_FAILURE); 2310 } /* switch */ 2311 } 2312 } 2313 kmem_free(assigned, length); 2314 return (PCICFG_SUCCESS); 2315 } 2316 2317 static int 2318 cardbus_free_resources(dev_info_t *dip) 2319 { 2320 uint32_t classcode; 2321 2322 classcode = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2323 "class-code", -1); 2324 /* 2325 * A different algorithim is used for bridges and leaf devices. 2326 */ 2327 if (classcode != -1) { 2328 classcode = ((uint_t)classcode & 0xffff00) >> 8; 2329 if (classcode == 0x604 || classcode == 0x607) { 2330 if (cardbus_free_bridge_resources(dip) 2331 != PCICFG_SUCCESS) { 2332 cardbus_err(dip, 1, 2333 "Failed freeing up bridge resources\n"); 2334 return (PCICFG_FAILURE); 2335 } 2336 return (PCICFG_SUCCESS); 2337 } 2338 } 2339 2340 if (cardbus_free_device_resources(dip) != PCICFG_SUCCESS) { 2341 cardbus_err(dip, 1, "Failed freeing up device resources\n"); 2342 return (PCICFG_FAILURE); 2343 } 2344 return (PCICFG_SUCCESS); 2345 } 2346 2347 static int 2348 cardbus_probe_bridge(cbus_t *cbp, dev_info_t *attpt, uint_t bus, 2349 uint_t device, uint_t func) 2350 { 2351 /* Declairations */ 2352 cardbus_bus_range_t *bus_range; 2353 int i, j; 2354 uint8_t header_type; 2355 ddi_acc_handle_t config_handle; 2356 ndi_ra_request_t req; 2357 uint_t new_bus; 2358 uint64_t blen; 2359 uint64_t next_bus; 2360 int circ; 2361 2362 cardbus_err(cbp->cb_dip, 6, 2363 "cardbus_probe_bridge bus %d device %d func %d\n", 2364 bus, device, func); 2365 2366 ndi_devi_enter(cbp->cb_dip, &circ); 2367 if (pci_config_setup(cbp->cb_dip, &config_handle) != DDI_SUCCESS) { 2368 2369 cardbus_err(cbp->cb_dip, 1, 2370 "cardbus_probe_bridge(): Failed to setup config space\n"); 2371 2372 ndi_devi_exit(cbp->cb_dip, circ); 2373 return (PCICFG_FAILURE); 2374 } 2375 2376 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2377 2378 /* 2379 * As soon as we have access to config space, check device 2380 * is a bridge. 2381 */ 2382 if ((header_type & PCI_HEADER_TYPE_M) != PCI_HEADER_CARDBUS) 2383 goto failed; 2384 2385 cardbus_err(cbp->cb_dip, 8, 2386 "---Vendor ID = [0x%04x]\n", 2387 pci_config_get16(config_handle, PCI_CONF_VENID)); 2388 cardbus_err(cbp->cb_dip, 8, 2389 "---Device ID = [0x%04x]\n", 2390 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2391 2392 /* say what type of header */ 2393 cardbus_err(cbp->cb_dip, 8, 2394 "--%s bridge found root bus [0x%x] device [0x%x] func [0x%x]\n", 2395 ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) ? 2396 "PCI-PCI" : "Cardbus", 2397 bus, device, func); 2398 2399 if (ddi_getlongprop(DDI_DEV_T_ANY, cbp->cb_dip, 0, "bus-range", 2400 (caddr_t)&bus_range, &i) != DDI_PROP_SUCCESS) 2401 cardbus_err(cbp->cb_dip, 1, 2402 "No bus-range property seems to have been set up\n"); 2403 else { 2404 cardbus_err(cbp->cb_dip, 8, 2405 "allowable bus range is %u->%u\n", 2406 bus_range->lo, bus_range->hi); 2407 kmem_free((caddr_t)bus_range, i); 2408 } 2409 2410 /* 2411 * Get next bus in sequence and program device. 2412 */ 2413 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2414 req.ra_len = 1; 2415 2416 if (ndi_ra_alloc(cbp->cb_dip, &req, 2417 &next_bus, &blen, NDI_RA_TYPE_PCI_BUSNUM, 2418 NDI_RA_PASS) != NDI_SUCCESS) { 2419 cmn_err(CE_WARN, "Failed to get a bus number\n"); 2420 goto failed; 2421 } 2422 2423 new_bus = next_bus; 2424 cardbus_err(cbp->cb_dip, 8, 2425 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2426 2427 (void) cardbus_set_bus_numbers(config_handle, bus, new_bus); 2428 2429 /* Enable it all */ 2430 enable_cardbus_bridge(cbp->cb_dip, config_handle); 2431 2432 /* 2433 * Probe all children devices 2434 */ 2435 for (i = 0; i < pcicfg_max_device; i++) 2436 for (j = 0; j < pcicfg_max_function; j++) 2437 switch (cardbus_probe_children(cbp, attpt, new_bus, i, 2438 j, &header_type)) { 2439 2440 case PCICFG_FAILURE: 2441 cardbus_err(cbp->cb_dip, 1, 2442 "Failed to configure bus " 2443 "[0x%x] device [0x%x] func [0x%x]\n", 2444 new_bus, i, j); 2445 disable_cardbus_bridge(cbp->cb_dip, 2446 config_handle); 2447 goto failed; 2448 2449 case PCICFG_NODEVICE: 2450 /* 2451 * if there's no function 0 2452 * there's no point in probing other 2453 * functions 2454 */ 2455 if (j != 0) 2456 break; 2457 /* FALLTHROUGH */ 2458 case PCICFG_NOMULTI: 2459 j = pcicfg_max_function; 2460 break; 2461 2462 default: 2463 break; 2464 } 2465 2466 (void) pci_config_teardown(&config_handle); 2467 (void) i_ndi_config_node(attpt, DS_LINKED, 0); 2468 ndi_devi_exit(cbp->cb_dip, circ); 2469 2470 return (PCICFG_SUCCESS); 2471 2472 failed: 2473 (void) pci_config_teardown(&config_handle); 2474 ndi_devi_exit(cbp->cb_dip, circ); 2475 2476 return (PCICFG_FAILURE); 2477 } 2478 2479 static struct isa_node isa_nodes[] = { 2480 {"dummy", {NULL, NULL, NULL, NULL, NULL}, "serial", "", 0x4e, 0x2} 2481 }; 2482 2483 static int 2484 cardbus_probe_children(cbus_t *cbp, dev_info_t *parent, uint_t bus, 2485 uint_t device, uint_t func, uint8_t *header_type) 2486 { 2487 dev_info_t *new_child; 2488 ddi_acc_handle_t config_handle; 2489 int i, j; 2490 ndi_ra_request_t req; 2491 uint64_t next_bus; 2492 uint64_t blen; 2493 uint32_t request; 2494 uint8_t base_class; 2495 uint_t new_bus; 2496 int ret; 2497 int circ; 2498 2499 cardbus_err(parent, 6, 2500 "cardbus_probe_children bus %d device %d func %d\n", 2501 bus, device, func); 2502 2503 /* 2504 * This node will be put immediately below 2505 * "parent". Allocate a blank device node. It will either 2506 * be filled in or freed up based on further probing. 2507 */ 2508 2509 ndi_devi_enter(parent, &circ); 2510 2511 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 2512 (pnode_t)DEVI_SID_NODEID, 2513 &new_child) != NDI_SUCCESS) { 2514 cardbus_err(parent, 1, 2515 "cardbus_probe_children(): Failed to alloc child node\n"); 2516 ndi_devi_exit(parent, circ); 2517 return (PCICFG_FAILURE); 2518 } 2519 2520 if (cardbus_add_config_reg(new_child, bus, 2521 device, func) != DDI_SUCCESS) { 2522 cardbus_err(parent, 1, 2523 "cardbus_probe_children(): Failed to add candidate REG\n"); 2524 goto failedconfig; 2525 } 2526 2527 if ((ret = cardbus_config_setup(new_child, &config_handle)) 2528 != PCICFG_SUCCESS) { 2529 2530 if (ret == PCICFG_NODEVICE) { 2531 (void) ndi_devi_free(new_child); 2532 return (ret); 2533 } 2534 cardbus_err(parent, 1, 2535 "cardbus_probe_children(): Failed to setup config space\n"); 2536 2537 goto failedconfig; 2538 } 2539 2540 base_class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 2541 2542 if (func == 0) { 2543 /* 2544 * Preserve the header type from function 0. 2545 * Additional functions may not preserve the PCI_HEADER_MULTI 2546 * bit. 2547 */ 2548 *header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 2549 } else if (!(*header_type & PCI_HEADER_MULTI) || 2550 ((*header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) || 2551 (base_class == PCI_CLASS_BRIDGE)) { 2552 2553 (void) cardbus_config_teardown(&config_handle); 2554 (void) ndi_devi_free(new_child); 2555 return (PCICFG_NOMULTI); 2556 } 2557 2558 /* 2559 * As soon as we have access to config space, 2560 * turn off device. It will get turned on 2561 * later (after memory is assigned). 2562 * not if it's a cardbus device. It may be OK to leave 2563 * it on - try LATER 2564 */ 2565 disable_cardbus_device(config_handle); 2566 2567 /* 2568 * Set 1275 properties common to all devices 2569 */ 2570 if (cardbus_set_standard_props(parent, new_child, 2571 config_handle) != PCICFG_SUCCESS) { 2572 cardbus_err(parent, 1, "Failed to set standard properties\n"); 2573 goto failedchild; 2574 } 2575 2576 /* 2577 * Child node properties NOTE: Both for PCI-PCI bridge and child node 2578 */ 2579 if (cardbus_set_childnode_props(new_child, 2580 config_handle) != PCICFG_SUCCESS) { 2581 goto failedchild; 2582 } 2583 2584 cardbus_err(parent, 8, 2585 "---Vendor ID = [0x%04x]\n", 2586 pci_config_get16(config_handle, PCI_CONF_VENID)); 2587 cardbus_err(parent, 8, 2588 "---Device ID = [0x%04x]\n", 2589 pci_config_get16(config_handle, PCI_CONF_DEVID)); 2590 2591 if (base_class == PCI_CLASS_BRIDGE) { 2592 uint8_t sub_class; 2593 2594 sub_class = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 2595 2596 switch (sub_class) { 2597 case PCI_BRIDGE_PCI: 2598 if ((*header_type & PCI_HEADER_TYPE_M) 2599 == PCI_HEADER_PPB) { 2600 cardbus_bus_range_t *bus_range; 2601 int k; 2602 2603 /* say what type of header */ 2604 cardbus_err(parent, 8, 2605 "-- Found PCI-PCI bridge @ " 2606 " bus [0x%x] device [0x%x] func [0x%x]\n", 2607 bus, device, func); 2608 2609 if (ddi_getlongprop(DDI_DEV_T_ANY, 2610 new_child, 0, "bus-range", 2611 (caddr_t)&bus_range, 2612 &k) != DDI_PROP_SUCCESS) 2613 cardbus_err(new_child, 1, 2614 "No bus-range property" 2615 " seems to have been set up\n"); 2616 else { 2617 cardbus_err(new_child, 8, 2618 "allowable bus range is %u->%u\n", 2619 bus_range->lo, bus_range->hi); 2620 kmem_free((caddr_t)bus_range, k); 2621 } 2622 2623 /* 2624 * Get next bus in sequence and program device. 2625 */ 2626 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 2627 req.ra_len = 1; 2628 2629 if (ndi_ra_alloc(new_child, &req, 2630 &next_bus, &blen, 2631 NDI_RA_TYPE_PCI_BUSNUM, 2632 NDI_RA_PASS) != NDI_SUCCESS) { 2633 cmn_err(CE_WARN, 2634 "Failed to get a bus number\n"); 2635 goto failedchild; 2636 } 2637 2638 new_bus = next_bus; 2639 2640 cardbus_err(new_child, 8, 2641 "NEW bus found [%u]->[%u]\n", bus, new_bus); 2642 2643 /* Enable it all */ 2644 enable_pci_pci_bridge(new_child, config_handle); 2645 (void) cardbus_set_bus_numbers(config_handle, 2646 bus, new_bus); 2647 2648 #if defined(CARDBUS_DEBUG) 2649 if (cardbus_debug >= 9) { 2650 cardbus_dump_config(config_handle); 2651 } 2652 #endif 2653 2654 /* 2655 * Set bus properties 2656 */ 2657 if (cardbus_set_busnode_props(new_child) 2658 != PCICFG_SUCCESS) { 2659 cardbus_err(new_child, 1, 2660 "Failed to set busnode props\n"); 2661 disable_pci_pci_bridge(new_child, 2662 config_handle); 2663 goto failedchild; 2664 } 2665 2666 /* 2667 * Probe all children devices 2668 */ 2669 for (i = 0; i < pcicfg_max_device; i++) 2670 for (j = 0; j < pcicfg_max_function; 2671 j++) 2672 switch (cardbus_probe_children( 2673 cbp, 2674 new_child, 2675 new_bus, i, 2676 j, header_type)) { 2677 case PCICFG_FAILURE: 2678 cardbus_err(parent, 1, 2679 "Failed to " 2680 "configure " 2681 "bus [0x%x] " 2682 "device [0x%x] " 2683 "func [0x%x]\n", 2684 new_bus, i, j); 2685 disable_pci_pci_bridge( 2686 new_child, 2687 config_handle); 2688 goto failedchild; 2689 2690 case PCICFG_NODEVICE: 2691 /* 2692 * if there's no 2693 * function 0 2694 * there's no point in 2695 * probing other 2696 * functions 2697 */ 2698 if (j != 0) 2699 break; 2700 /* FALLTHROUGH */ 2701 case PCICFG_NOMULTI: 2702 j = pcicfg_max_function; 2703 break; 2704 2705 default: 2706 break; 2707 } 2708 } 2709 break; 2710 2711 case PCI_BRIDGE_CARDBUS: 2712 cardbus_err(parent, 8, 2713 "--Found Cardbus bridge @ " 2714 "bus [0x%x] device [0x%x] func [0x%x]\n", 2715 bus, device, func); 2716 pci_config_put32(config_handle, 2717 PCI_CONF_BASE0, 0xffffffff); 2718 2719 request = pci_config_get32(config_handle, 2720 PCI_CONF_BASE0); 2721 2722 /* 2723 * If its a zero length, don't do 2724 * any programming. 2725 */ 2726 if (request != 0) { 2727 if (request == (uint32_t)0xffffffff) { 2728 cmn_err(CE_WARN, 2729 "cardbus_probe_children: " 2730 "can't access device"); 2731 goto failedchild; 2732 } 2733 /* 2734 * Add to the "reg" property 2735 */ 2736 if (cardbus_update_reg_prop(new_child, 2737 request, 2738 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2739 goto failedchild; 2740 } 2741 cardbus_err(parent, 8, 2742 "BASE register [0x%x] asks for " 2743 "[0x%x]=[0x%x](32)\n", 2744 PCI_CONF_BASE0, request, 2745 (~(PCI_BASE_M_ADDR_M & request))+1); 2746 } 2747 break; 2748 2749 case PCI_BRIDGE_ISA: 2750 cardbus_err(parent, 8, 2751 "--Found ISA bridge @ " 2752 "bus [0x%x] device [0x%x] func [0x%x]\n", 2753 bus, device, func); 2754 enable_pci_isa_bridge(new_child, config_handle); 2755 2756 #if defined(CARDBUS_DEBUG) 2757 if (cardbus_debug >= 4) { 2758 cardbus_dump_common_config(config_handle); 2759 cardbus_err(NULL, 1, 2760 " DDMA SlvCh0 = [0x%04x] " 2761 "DDMA SlvCh1 = [0x%04x]\n", 2762 pci_config_get16(config_handle, 0x40), 2763 pci_config_get16(config_handle, 0x42)); 2764 cardbus_err(NULL, 1, 2765 " DDMA SlvCh2 = [0x%04x] " 2766 "DDMA SlvCh3 = [0x%04x]\n", 2767 pci_config_get16(config_handle, 0x44), 2768 pci_config_get16(config_handle, 0x46)); 2769 cardbus_err(NULL, 1, 2770 " DDMA SlvCh5 = [0x%04x] " 2771 "DDMA SlvCh6 = [0x%04x]\n", 2772 pci_config_get16(config_handle, 0x4a), 2773 pci_config_get16(config_handle, 0x4c)); 2774 cardbus_err(NULL, 1, 2775 " DDMA SlvCh7 = [0x%04x] " 2776 "Misc Cntrl = [0x%02x]\n", 2777 pci_config_get16(config_handle, 0x4e), 2778 pci_config_get8(config_handle, 0x57)); 2779 cardbus_err(NULL, 1, 2780 " DMA Cntl = [0x%02x] " 2781 "DMA TyF Tim = [0x%02x]\n", 2782 pci_config_get8(config_handle, 0x48), 2783 pci_config_get8(config_handle, 0x49)); 2784 cardbus_err(NULL, 1, 2785 " TimCntrl = [0x%02x] " 2786 "MTOP = [0x%02x]\n", 2787 pci_config_get8(config_handle, 0x50), 2788 pci_config_get8(config_handle, 0x51)); 2789 cardbus_err(NULL, 1, 2790 " MDMA Access = [0x%02x] " 2791 "ROMCS = [0x%02x]\n", 2792 pci_config_get8(config_handle, 0x52), 2793 pci_config_get8(config_handle, 0x53)); 2794 cardbus_err(NULL, 1, 2795 " Dscrd Tmr = [0x%02x] " 2796 "Retry Tmr = [0x%02x]\n", 2797 pci_config_get8(config_handle, 0x55), 2798 pci_config_get8(config_handle, 0x54)); 2799 cardbus_err(NULL, 1, 2800 " I/O Spc 0 = [0x%08x] " 2801 "I/O Spc 1 = [0x%08x]\n", 2802 pci_config_get32(config_handle, 0x58), 2803 pci_config_get32(config_handle, 0x5c)); 2804 cardbus_err(NULL, 1, 2805 " I/O Spc 2 = [0x%08x] " 2806 "I/O Spc 3 = [0x%08x]\n", 2807 pci_config_get32(config_handle, 0x60), 2808 pci_config_get32(config_handle, 0x64)); 2809 cardbus_err(NULL, 1, 2810 " I/O Spc 4 = [0x%08x] " 2811 "I/O Spc 5 = [0x%08x]\n", 2812 pci_config_get32(config_handle, 0x68), 2813 pci_config_get32(config_handle, 0x6c)); 2814 cardbus_err(NULL, 1, 2815 " Mem Spc 0 = [0x%08x] " 2816 "Mem Spc 1 = [0x%08x]\n", 2817 pci_config_get32(config_handle, 0x70), 2818 pci_config_get32(config_handle, 0x74)); 2819 cardbus_err(NULL, 1, 2820 " Mem Spc 2 = [0x%08x] " 2821 "Mem Spc 3 = [0x%08x]\n", 2822 pci_config_get32(config_handle, 0x78), 2823 pci_config_get32(config_handle, 0x7c)); 2824 } 2825 #endif 2826 /* 2827 * Set bus properties 2828 */ 2829 if (cardbus_set_busnode_isaprops(new_child) 2830 != PCICFG_SUCCESS) { 2831 cardbus_err(new_child, 1, 2832 "Failed to set busnode props\n"); 2833 disable_cardbus_device(config_handle); 2834 goto failedchild; 2835 } 2836 2837 /* 2838 * Add to the "reg" property. 2839 * Simply grab 1K of I/O space. 2840 */ 2841 if (cardbus_update_reg_prop(new_child, 2842 0xfffffc00 | PCI_BASE_SPACE_IO, 2843 PCI_CONF_BASE0) != PCICFG_SUCCESS) { 2844 goto failedchild; 2845 } 2846 2847 /* 2848 * Probe all potential children devices. 2849 */ 2850 for (i = 0; 2851 i < sizeof (isa_nodes) / sizeof (isa_nodes[0]); 2852 i++) 2853 switch (cardbus_add_isa_node(cbp, new_child, 2854 &isa_nodes[i])) { 2855 case PCICFG_FAILURE: 2856 cardbus_err(parent, 1, 2857 "Failed to configure isa bus\n"); 2858 disable_cardbus_device(config_handle); 2859 goto failedchild; 2860 2861 case PCICFG_NODEVICE: 2862 continue; 2863 } 2864 2865 break; 2866 2867 case PCI_BRIDGE_OTHER: 2868 default: 2869 cardbus_err(parent, 8, 2870 "--Found unknown bridge, subclass 0x%x @ " 2871 "bus [0x%x] device [0x%x] func [0x%x]\n", 2872 sub_class, bus, device, func); 2873 goto leaf_node; 2874 } 2875 } else { 2876 cardbus_err(parent, 8, 2877 "--Leaf device found " 2878 "bus [0x%x] device [0x%x] func [0x%x]\n", 2879 bus, device, func); 2880 /* 2881 * Ethernet devices. 2882 */ 2883 if (strcmp(ddi_binding_name(new_child), "ethernet") == 0) { 2884 extern int localetheraddr(struct ether_addr *, 2885 struct ether_addr *); 2886 uchar_t mac[6]; 2887 2888 cardbus_force_stringprop(new_child, 2889 "device_type", "network"); 2890 2891 if (localetheraddr(NULL, (struct ether_addr *)mac)) { 2892 (void) ddi_prop_create(DDI_DEV_T_NONE, 2893 new_child, 2894 DDI_PROP_CANSLEEP, "local-mac-address", 2895 (caddr_t)mac, 6); 2896 } 2897 } 2898 leaf_node: 2899 if (cbp->cb_dsp) { 2900 struct cb_deviceset_props *cdsp = cbp->cb_dsp; 2901 uint16_t venid = pci_config_get16(config_handle, 2902 PCI_CONF_VENID); 2903 uint16_t devid = pci_config_get16(config_handle, 2904 PCI_CONF_DEVID); 2905 ddi_prop_t *propp; 2906 2907 for (cdsp = cbp->cb_dsp; cdsp; cdsp = cdsp->next) { 2908 if (cdsp->binding_name && 2909 strcmp(ddi_binding_name(new_child), 2910 cdsp->binding_name)) 2911 continue; 2912 if (cdsp->venid && (cdsp->venid != venid)) 2913 continue; 2914 if (cdsp->devid && (cdsp->devid != devid)) 2915 continue; 2916 if (cdsp->nodename) { 2917 if (ndi_devi_set_nodename(new_child, 2918 cdsp->nodename, 2919 0) != NDI_SUCCESS) 2920 cardbus_err(new_child, 1, 2921 "Failed to set nodename\n"); 2922 } 2923 for (propp = cdsp->prop_list; propp; 2924 propp = propp->prop_next) { 2925 switch (propp->prop_flags) { 2926 case DDI_PROP_TYPE_INT: 2927 cardbus_force_intprop( 2928 new_child, 2929 propp->prop_name, 2930 (int *)propp->prop_val, 2931 propp->prop_len); 2932 break; 2933 case DDI_PROP_TYPE_STRING: 2934 cardbus_force_stringprop( 2935 new_child, 2936 propp->prop_name, 2937 (char *)propp->prop_val); 2938 break; 2939 case DDI_PROP_TYPE_ANY: 2940 cardbus_force_boolprop( 2941 new_child, 2942 propp->prop_name); 2943 break; 2944 } 2945 } 2946 } 2947 } 2948 2949 #if defined(CARDBUS_DEBUG) 2950 if (cardbus_debug >= 9) { 2951 cardbus_dump_config(config_handle); 2952 } 2953 #endif 2954 2955 i = PCI_CONF_BASE0; 2956 2957 while (i <= PCI_CONF_BASE5) { 2958 pci_config_put32(config_handle, i, 0xffffffff); 2959 2960 request = pci_config_get32(config_handle, i); 2961 2962 /* 2963 * If its a zero length, don't do 2964 * any programming. 2965 */ 2966 if (request != 0) { 2967 if (request == (uint32_t)0xffffffff) { 2968 cmn_err(CE_WARN, 2969 "cardbus_probe_children: " 2970 "can't access device"); 2971 goto failedchild; 2972 } 2973 /* 2974 * Add to the "reg" property 2975 */ 2976 if (cardbus_update_reg_prop(new_child, 2977 request, i) != PCICFG_SUCCESS) { 2978 goto failedchild; 2979 } 2980 } else { 2981 cardbus_err(parent, 8, "All memory found\n"); 2982 break; 2983 } 2984 2985 /* 2986 * Increment by eight if it is 64 bit address space 2987 * only if memory space 2988 */ 2989 if (((PCI_BASE_TYPE_M & request) 2990 == PCI_BASE_TYPE_ALL) && 2991 ((PCI_BASE_SPACE_M & request) 2992 == PCI_BASE_SPACE_MEM)) { 2993 cardbus_err(parent, 8, 2994 "BASE register [0x%x] asks for " 2995 "[0x%x]=[0x%x] (64)\n", 2996 i, request, 2997 (~(PCI_BASE_M_ADDR_M & request))+1); 2998 i += 8; 2999 } else { 3000 cardbus_err(parent, 8, 3001 "BASE register [0x%x] asks for " 3002 "[0x%x]=[0x%x](32)\n", 3003 i, request, 3004 (~(PCI_BASE_M_ADDR_M & request))+1); 3005 i += 4; 3006 } 3007 } 3008 3009 /* 3010 * Get the ROM size and create register for it 3011 */ 3012 pci_config_put32(config_handle, PCI_CONF_ROM, 0xffffffff); 3013 3014 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3015 /* 3016 * If its a zero length, don't do 3017 * any programming. 3018 */ 3019 3020 if (request != 0) { 3021 cardbus_err(parent, 9, 3022 "BASE register [0x%x] asks for " 3023 "[0x%x]=[0x%x] (ROM)\n", 3024 PCI_CONF_ROM, request, 3025 (~(PCI_BASE_ROM_ADDR_M & request))+1); 3026 /* 3027 * Add to the "reg" property 3028 */ 3029 if (cardbus_update_reg_prop(new_child, 3030 request, 3031 PCI_CONF_ROM) != PCICFG_SUCCESS) { 3032 goto failedchild; 3033 } 3034 } 3035 } 3036 3037 (void) cardbus_config_teardown(&config_handle); 3038 3039 /* 3040 * Attach the child to its parent 3041 */ 3042 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3043 ndi_devi_exit(parent, circ); 3044 3045 return (PCICFG_SUCCESS); 3046 failedchild: 3047 /* 3048 * check if it should be taken offline (if online) 3049 */ 3050 (void) cardbus_config_teardown(&config_handle); 3051 3052 failedconfig: 3053 3054 (void) ndi_devi_free(new_child); 3055 ndi_devi_exit(parent, circ); 3056 3057 return (PCICFG_FAILURE); 3058 } 3059 3060 static int 3061 cardbus_add_config_reg(dev_info_t *dip, 3062 uint_t bus, uint_t device, uint_t func) 3063 { 3064 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 3065 3066 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 3067 3068 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3069 "reg", reg, 5)); 3070 } 3071 3072 static int 3073 cardbus_add_isa_node(cbus_t *cbp, dev_info_t *parent, struct isa_node *node) 3074 { 3075 dev_info_t *new_child; 3076 int ret; 3077 uint32_t reg[3]; 3078 3079 _NOTE(ARGUNUSED(cbp)) 3080 3081 cardbus_err(parent, 6, "cardbus_add_isa_node\n"); 3082 3083 /* 3084 * This node will be put immediately below 3085 * "parent". Allocate a blank device node. 3086 */ 3087 if (ndi_devi_alloc(parent, DEVI_PSEUDO_NEXNAME, 3088 (pnode_t)DEVI_SID_NODEID, 3089 &new_child) != NDI_SUCCESS) { 3090 cardbus_err(parent, 1, 3091 "cardbus_add_isa_child(): Failed to alloc child node\n"); 3092 return (PCICFG_FAILURE); 3093 } 3094 3095 /* 3096 * Set properties common to ISA devices 3097 */ 3098 if (cardbus_set_isa_props(parent, new_child, node->name, 3099 node->compatible) != PCICFG_SUCCESS) { 3100 cardbus_err(parent, 1, "Failed to set ISA properties\n"); 3101 goto failed; 3102 } 3103 3104 cardbus_err(new_child, 8, "--Leaf ISA device\n"); 3105 3106 /* 3107 * Add the "reg" property. 3108 */ 3109 reg[0] = 0; 3110 reg[1] = node->reg; 3111 reg[2] = node->span; 3112 3113 ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 3114 "basereg", (int *)reg, 3); 3115 if (ret != DDI_SUCCESS) 3116 goto failed; 3117 3118 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3119 3120 return (PCICFG_SUCCESS); 3121 3122 failed: 3123 (void) ndi_devi_free(new_child); 3124 3125 return (PCICFG_FAILURE); 3126 } 3127 3128 static int 3129 cardbus_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 3130 { 3131 caddr_t cfgaddr; 3132 ddi_device_acc_attr_t attr; 3133 dev_info_t *anode; 3134 int status; 3135 int rlen; 3136 pci_regspec_t *reg; 3137 int ret; 3138 #ifdef sparc 3139 int16_t val; 3140 #endif 3141 3142 cardbus_err(dip, 10, 3143 "cardbus_config_setup(dip=0x%p)\n", (void *) dip); 3144 3145 /* 3146 * Get the pci register spec from the node 3147 */ 3148 status = ddi_getlongprop(DDI_DEV_T_NONE, 3149 dip, DDI_PROP_DONTPASS, "reg", 3150 (caddr_t)®, &rlen); 3151 3152 cardbus_err(dip, 10, 3153 "cardbus_config_setup, reg = 0x%p\n", (void *) reg); 3154 3155 switch (status) { 3156 case DDI_PROP_SUCCESS: 3157 break; 3158 case DDI_PROP_NO_MEMORY: 3159 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3160 return (PCICFG_FAILURE); 3161 default: 3162 cardbus_err(dip, 1, "no reg property\n"); 3163 return (PCICFG_FAILURE); 3164 } 3165 3166 anode = dip; 3167 3168 /* 3169 * Find the attachment point node 3170 */ 3171 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 3172 "hp_attachment") != 0)) { 3173 anode = ddi_get_parent(anode); 3174 } 3175 3176 if (anode == NULL) { 3177 cardbus_err(dip, 1, "Tree not in PROBE state\n"); 3178 kmem_free((caddr_t)reg, rlen); 3179 return (PCICFG_FAILURE); 3180 } 3181 3182 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, anode, 3183 "reg", (int *)reg, 5)) != 0) { 3184 cardbus_err(dip, 1, 3185 "Failed to update reg property, error code %d\n", ret); 3186 kmem_free((caddr_t)reg, rlen); 3187 return (PCICFG_FAILURE); 3188 } 3189 3190 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3191 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3192 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3193 3194 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 3195 0, /* PCI_CONF_HDR_SIZE */ 3196 0, 3197 &attr, handle) != DDI_SUCCESS) { 3198 cardbus_err(dip, 1, 3199 "Failed to setup registers for [0x%x][0x%x][0x%x]\n", 3200 PCI_REG_BUS_G(reg->pci_phys_hi), 3201 PCI_REG_DEV_G(reg->pci_phys_hi), 3202 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3203 kmem_free((caddr_t)reg, rlen); 3204 return (PCICFG_FAILURE); 3205 } 3206 3207 cardbus_err(dip, 9, 3208 "PROBING =>->->->->->-> [0x%x][0x%x][0x%x] 0x%x 0x%p\n", 3209 PCI_REG_BUS_G(reg->pci_phys_hi), 3210 PCI_REG_DEV_G(reg->pci_phys_hi), 3211 PCI_REG_FUNC_G(reg->pci_phys_hi), 3212 reg->pci_phys_hi, (void *) cfgaddr); 3213 3214 /* 3215 * must do peek16 otherwise the system crashes when probing 3216 * a non zero function on a non-multi-function card. 3217 */ 3218 #ifdef sparc 3219 if (ddi_peek16(anode, (int16_t *)cfgaddr, &val) != DDI_SUCCESS) { 3220 cardbus_err(dip, 8, 3221 "cardbus_config_setup peek failed\n"); 3222 ret = PCICFG_NODEVICE; 3223 } else if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3224 cardbus_err(dip, 8, 3225 "cardbus_config_setup PCICFG_NODEVICE\n"); 3226 ret = PCICFG_NODEVICE; 3227 #elif defined(__x86) || defined(__amd64) 3228 if (ddi_get16(*handle, (uint16_t *)cfgaddr) == 0xffff) { 3229 cardbus_err(dip, 8, 3230 "cardbus_config_setup PCICFG_NODEVICE\n"); 3231 ret = PCICFG_NODEVICE; 3232 #endif 3233 } else { 3234 cardbus_err(dip, 1, 3235 "cardbus_config_setup found device at:[0x%x][0x%x][0x%x]\n", 3236 PCI_REG_BUS_G(reg->pci_phys_hi), 3237 PCI_REG_DEV_G(reg->pci_phys_hi), 3238 PCI_REG_FUNC_G(reg->pci_phys_hi)); 3239 3240 ret = PCICFG_SUCCESS; 3241 } 3242 3243 kmem_free((caddr_t)reg, rlen); 3244 if (ret != PCICFG_SUCCESS) { 3245 cardbus_config_teardown(handle); 3246 } 3247 3248 cardbus_err(dip, 7, 3249 "cardbus_config_setup returning %d\n", ret); 3250 3251 return (ret); 3252 } 3253 3254 static void 3255 cardbus_config_teardown(ddi_acc_handle_t *handle) 3256 { 3257 (void) ddi_regs_map_free(handle); 3258 } 3259 3260 static void 3261 cardbus_reparent_children(dev_info_t *dip, dev_info_t *parent) 3262 { 3263 dev_info_t *child; 3264 int circ; 3265 3266 while (child = ddi_get_child(dip)) { 3267 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 3268 /* 3269 * Unlink node from tree before reparenting 3270 */ 3271 ndi_devi_enter(dip, &circ); 3272 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 3273 ndi_devi_exit(dip, circ); 3274 DEVI(child)->devi_parent = DEVI(parent); 3275 DEVI(child)->devi_bus_ctl = DEVI(parent); 3276 ndi_devi_enter(parent, &circ); 3277 (void) i_ndi_config_node(child, DS_LINKED, 0); 3278 ndi_devi_exit(parent, circ); 3279 } 3280 } 3281 3282 static int 3283 cardbus_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 3284 { 3285 int alen; 3286 pci_regspec_t *assigned; 3287 caddr_t newreg; 3288 uint_t status; 3289 3290 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3291 "assigned-addresses", (caddr_t)&assigned, &alen); 3292 switch (status) { 3293 case DDI_PROP_SUCCESS: 3294 cardbus_err(dip, 5, 3295 "cardbus_update_assigned_prop: found prop len %d\n", 3296 alen); 3297 /* 3298 * Allocate memory for the existing 3299 * assigned-addresses(s) plus one and then 3300 * build it. 3301 */ 3302 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 3303 3304 bcopy(assigned, newreg, alen); 3305 bcopy(newone, newreg + alen, sizeof (*newone)); 3306 break; 3307 3308 case DDI_PROP_NO_MEMORY: 3309 cardbus_err(dip, 1, 3310 "no memory for assigned-addresses property\n"); 3311 return (PCICFG_FAILURE); 3312 3313 default: 3314 cardbus_err(dip, 5, 3315 "cardbus_update_assigned_prop: creating prop\n"); 3316 alen = 0; 3317 newreg = (caddr_t)newone; 3318 break; 3319 } 3320 3321 /* 3322 * Write out the new "assigned-addresses" spec 3323 */ 3324 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3325 "assigned-addresses", (int *)newreg, 3326 (alen + sizeof (*newone))/sizeof (int)); 3327 3328 if (status == DDI_PROP_SUCCESS) 3329 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 3330 3331 if (alen) 3332 kmem_free(assigned, alen); 3333 3334 return (PCICFG_SUCCESS); 3335 } 3336 3337 static int 3338 cardbus_update_available_prop(dev_info_t *dip, uint32_t hi_type, 3339 uint64_t base, uint64_t size) 3340 { 3341 int alen, rlen; 3342 pci_regspec_t *available, *reg; 3343 pci_regspec_t addition; 3344 caddr_t newreg; 3345 uint_t status; 3346 3347 cardbus_err(dip, 6, "cardbus_update_available_prop\n"); 3348 3349 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3350 "reg", (caddr_t)®, &rlen); 3351 3352 switch (status) { 3353 case DDI_PROP_SUCCESS: 3354 break; 3355 case DDI_PROP_NO_MEMORY: 3356 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3357 return (PCICFG_FAILURE); 3358 default: 3359 cardbus_err(dip, 1, "no reg property\n"); 3360 return (PCICFG_FAILURE); 3361 } 3362 3363 status = ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 3364 "available", (caddr_t)&available, &alen); 3365 switch (status) { 3366 case DDI_PROP_SUCCESS: 3367 break; 3368 case DDI_PROP_NO_MEMORY: 3369 cardbus_err(dip, 1, "no memory for available property\n"); 3370 kmem_free((caddr_t)reg, rlen); 3371 return (PCICFG_FAILURE); 3372 default: 3373 alen = 0; 3374 } 3375 3376 /* 3377 * Allocate memory for the existing 3378 * available(s) plus one and then 3379 * build it. 3380 */ 3381 newreg = kmem_zalloc(alen + sizeof (pci_regspec_t), KM_SLEEP); 3382 3383 /* 3384 * Build the regspec, then add it to the existing one(s) 3385 */ 3386 addition.pci_phys_hi = hi_type | 3387 PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3388 PCI_REG_DEV_G(reg->pci_phys_hi), 3389 PCI_REG_FUNC_G(reg->pci_phys_hi), 0); 3390 3391 addition.pci_phys_mid = (uint32_t)((base>>32) & 0xffffffff); 3392 addition.pci_phys_low = (uint32_t)(base & 0xffffffff); 3393 addition.pci_size_hi = (uint32_t)((size>>32) & 0xffffffff); 3394 addition.pci_size_low = (uint32_t)(size & 0xffffffff); 3395 3396 #ifdef DEBUG 3397 cardbus_dump_reg(dip, &addition, 1); 3398 #endif 3399 3400 if (alen) 3401 bcopy(available, newreg, alen); 3402 bcopy(&addition, newreg + alen, sizeof (pci_regspec_t)); 3403 3404 /* 3405 * Write out the new "available" spec 3406 */ 3407 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 3408 "available", (int *)newreg, 3409 (alen + sizeof (pci_regspec_t))/sizeof (int)); 3410 3411 if (alen) 3412 kmem_free((caddr_t)available, alen); 3413 kmem_free((caddr_t)reg, rlen); 3414 kmem_free((caddr_t)newreg, alen + sizeof (pci_regspec_t)); 3415 3416 return (PCICFG_SUCCESS); 3417 } 3418 3419 static int 3420 cardbus_update_ranges_prop(dev_info_t *dip, cardbus_range_t *addition) 3421 { 3422 int rlen; 3423 cardbus_range_t *ranges; 3424 caddr_t newreg; 3425 uint_t status; 3426 #if defined(CARDBUS_DEBUG) 3427 int i, nrange; 3428 const cardbus_range_t *nr; 3429 #endif 3430 3431 cardbus_err(dip, 6, "cardbus_update_ranges_prop\n"); 3432 3433 status = ddi_getlongprop(DDI_DEV_T_NONE, 3434 dip, DDI_PROP_DONTPASS, "ranges", 3435 (caddr_t)&ranges, &rlen); 3436 3437 switch (status) { 3438 case DDI_PROP_SUCCESS: 3439 break; 3440 case DDI_PROP_NO_MEMORY: 3441 cardbus_err(dip, 1, 3442 "ranges present, but unable to get memory\n"); 3443 return (PCICFG_FAILURE); 3444 default: 3445 cardbus_err(dip, 8, "no ranges property - creating one\n"); 3446 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 3447 dip, "ranges", (int *)addition, 3448 sizeof (cardbus_range_t)/sizeof (int)) 3449 != DDI_SUCCESS) { 3450 cardbus_err(dip, 1, "Did'nt create ranges property\n"); 3451 return (PCICFG_FAILURE); 3452 } 3453 return (PCICFG_SUCCESS); 3454 } 3455 3456 /* 3457 * Allocate memory for the existing reg(s) plus one and then 3458 * build it. 3459 */ 3460 newreg = kmem_zalloc(rlen+sizeof (cardbus_range_t), KM_SLEEP); 3461 3462 bcopy(ranges, newreg, rlen); 3463 bcopy(addition, newreg + rlen, sizeof (cardbus_range_t)); 3464 3465 /* 3466 * Write out the new "ranges" property 3467 */ 3468 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3469 dip, "ranges", (int *)newreg, 3470 (rlen + sizeof (cardbus_range_t))/sizeof (int)); 3471 3472 #if defined(CARDBUS_DEBUG) 3473 cardbus_err(dip, 8, "cardbus_update_ranges_prop ranges property:\n"); 3474 3475 nrange = rlen / sizeof (cardbus_range_t); 3476 nr = (cardbus_range_t *)newreg; 3477 for (i = 0; i <= nrange; i++) { 3478 /* nrange is one higher for new entry */ 3479 cardbus_err(dip, 9, 3480 "\trange parent addr 0x%x.0x%x.0x%x " 3481 "child addr 0x%x.0x%x.0x%x size 0x%x.0x%x\n", 3482 nr->parent_hi, 3483 nr->parent_mid, nr->parent_lo, 3484 nr->child_hi, 3485 nr->child_mid, nr->child_lo, 3486 nr->size_hi, nr->size_lo); 3487 nr++; 3488 } 3489 #endif 3490 3491 kmem_free((caddr_t)newreg, rlen+sizeof (cardbus_range_t)); 3492 kmem_free((caddr_t)ranges, rlen); 3493 3494 return (PCICFG_SUCCESS); 3495 } 3496 3497 static int 3498 cardbus_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 3499 { 3500 int rlen; 3501 pci_regspec_t *reg; 3502 caddr_t newreg; 3503 uint32_t hiword; 3504 pci_regspec_t addition; 3505 uint32_t size; 3506 uint_t status; 3507 3508 status = ddi_getlongprop(DDI_DEV_T_NONE, 3509 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3510 3511 switch (status) { 3512 case DDI_PROP_SUCCESS: 3513 break; 3514 case DDI_PROP_NO_MEMORY: 3515 cardbus_err(dip, 1, "reg present, but unable to get memory\n"); 3516 return (PCICFG_FAILURE); 3517 default: 3518 cardbus_err(dip, 1, "no reg property\n"); 3519 return (PCICFG_FAILURE); 3520 } 3521 3522 /* 3523 * Allocate memory for the existing reg(s) plus one and then 3524 * build it. 3525 */ 3526 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3527 3528 /* 3529 * Build the regspec, then add it to the existing one(s) 3530 */ 3531 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3532 PCI_REG_DEV_G(reg->pci_phys_hi), 3533 PCI_REG_FUNC_G(reg->pci_phys_hi), 3534 reg_offset); 3535 3536 if (reg_offset == PCI_CONF_ROM) { 3537 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3538 hiword |= PCI_ADDR_MEM32; 3539 } else { 3540 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3541 3542 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3543 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3544 hiword |= PCI_ADDR_MEM32; 3545 } else if ((PCI_BASE_TYPE_M & regvalue) 3546 == PCI_BASE_TYPE_ALL) { 3547 /* 3548 * This is a 64 bit PCI memory space. 3549 * It needs to be allocated as 32 bit 3550 * for bus map purposes. 3551 */ 3552 hiword |= PCI_ADDR_MEM32; 3553 } 3554 } else { 3555 hiword |= PCI_ADDR_IO; 3556 } 3557 } 3558 3559 addition.pci_phys_hi = hiword; 3560 addition.pci_phys_mid = 0; 3561 addition.pci_phys_low = 0; 3562 addition.pci_size_hi = 0; 3563 addition.pci_size_low = size; 3564 3565 cardbus_err(dip, 8, 3566 "cardbus_update_reg_prop, phys_hi 0x%08x," 3567 " phys_mid 0x%08x, phys_low 0x%08x, size_hi 0x%08x," 3568 " size_low 0x%08x\n", hiword, 0, 0, 0, size); 3569 3570 bcopy(reg, newreg, rlen); 3571 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3572 3573 /* 3574 * Write out the new "reg" property 3575 */ 3576 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, 3577 dip, "reg", (int *)newreg, 3578 (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3579 3580 kmem_free((caddr_t)reg, rlen); 3581 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3582 3583 return (PCICFG_SUCCESS); 3584 } 3585 3586 /* 3587 * Setup the basic 1275 properties based on information found in the config 3588 * header of the PCI device 3589 */ 3590 static int 3591 cardbus_set_standard_props(dev_info_t *parent, dev_info_t *dip, 3592 ddi_acc_handle_t config_handle) 3593 { 3594 int ret; 3595 uint16_t val; 3596 uint32_t wordval; 3597 uint8_t byteval; 3598 3599 /* These two exists only for non-bridges */ 3600 if ((pci_config_get8(config_handle, 3601 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) { 3602 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3603 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3604 "min-grant", byteval)) != DDI_SUCCESS) { 3605 cardbus_err(dip, 1, "Failed to sent min-grant\n"); 3606 return (ret); 3607 } 3608 3609 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3610 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3611 "max-latency", byteval)) != DDI_SUCCESS) { 3612 return (ret); 3613 } 3614 } 3615 3616 /* 3617 * These should always exist and have the value of the 3618 * corresponding register value 3619 */ 3620 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3621 3622 /* 3623 * according to section 6.2.1 of revision 2 of the PCI local 3624 * bus specification - 0FFFFh is an invalid value for the vendor ID 3625 */ 3626 if (val == 0xffff) { 3627 cardbus_err(dip, 1, "Illegal vendor-id 0x%x\n", val); 3628 return (PCICFG_FAILURE); 3629 } 3630 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3631 "vendor-id", val)) != DDI_SUCCESS) { 3632 return (ret); 3633 } 3634 3635 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3636 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3637 "device-id", val)) != DDI_SUCCESS) { 3638 return (ret); 3639 } 3640 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3641 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3642 "revision-id", byteval)) != DDI_SUCCESS) { 3643 return (ret); 3644 } 3645 3646 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3647 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3648 3649 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3650 "class-code", wordval)) != DDI_SUCCESS) { 3651 return (ret); 3652 } 3653 val = (pci_config_get16(config_handle, 3654 PCI_CONF_STAT) & PCI_STAT_DEVSELT); 3655 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3656 "devsel-speed", val)) != DDI_SUCCESS) { 3657 return (ret); 3658 } 3659 3660 /* 3661 * The next three are bits set in the status register. The property is 3662 * present (but with no value other than its own existence) if the bit 3663 * is set, non-existent otherwise 3664 */ 3665 if (ddi_prop_exists(DDI_DEV_T_ANY, parent, DDI_PROP_DONTPASS, 3666 "fast-back-to-back") && 3667 pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC) { 3668 3669 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3670 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3671 return (ret); 3672 } 3673 } 3674 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ) { 3675 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3676 "66mhz-capable", 0)) != DDI_SUCCESS) { 3677 return (ret); 3678 } 3679 } 3680 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3681 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3682 "udf-supported", 0)) != DDI_SUCCESS) { 3683 return (ret); 3684 } 3685 } 3686 3687 /* 3688 * These next three are optional and are not present 3689 * if the corresponding register is zero. If the value 3690 * is non-zero then the property exists with the value 3691 * of the register. 3692 */ 3693 3694 /* look in the correct place for header type 2 */ 3695 byteval = pci_config_get8(config_handle, PCI_CONF_HEADER); 3696 if ((byteval & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3697 if ((val = pci_config_get16(config_handle, 3698 PCI_CBUS_SUBVENID)) != 0) { 3699 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3700 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3701 return (ret); 3702 } 3703 } 3704 if ((val = pci_config_get16(config_handle, 3705 PCI_CBUS_SUBSYSID)) != 0) { 3706 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3707 "subsystem-id", val)) != DDI_SUCCESS) { 3708 return (ret); 3709 } 3710 } 3711 } else { 3712 if ((val = pci_config_get16(config_handle, 3713 PCI_CONF_SUBVENID)) != 0) { 3714 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3715 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3716 return (ret); 3717 } 3718 } 3719 if ((val = pci_config_get16(config_handle, 3720 PCI_CONF_SUBSYSID)) != 0) { 3721 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3722 "subsystem-id", val)) != DDI_SUCCESS) { 3723 return (ret); 3724 } 3725 } 3726 } 3727 3728 if ((val = pci_config_get8(config_handle, 3729 PCI_CONF_CACHE_LINESZ)) != 0) { 3730 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3731 "cache-line-size", val)) != DDI_SUCCESS) { 3732 return (ret); 3733 } 3734 } 3735 3736 /* 3737 * If the Interrupt Pin register is non-zero then the 3738 * interrupts property exists 3739 */ 3740 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3741 /* 3742 * If interrupt pin is non-zero, 3743 * record the interrupt line used 3744 */ 3745 cardbus_err(dip, 8, "Adding interrupts property\n"); 3746 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3747 "interrupts", byteval)) != DDI_SUCCESS) { 3748 return (ret); 3749 } 3750 } 3751 return (PCICFG_SUCCESS); 3752 } 3753 3754 /* 3755 * Setup the basic properties required by the ISA node. 3756 */ 3757 static int 3758 cardbus_set_isa_props(dev_info_t *parent, dev_info_t *dip, 3759 char *name, char *compat[]) 3760 { 3761 int ret, n; 3762 3763 _NOTE(ARGUNUSED(parent)) 3764 3765 cardbus_err(dip, 8, "Adding interrupts property\n"); 3766 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3767 "interrupts", 1)) != DDI_SUCCESS) { 3768 return (ret); 3769 } 3770 3771 /* 3772 * The node name field needs to be filled in with the name 3773 */ 3774 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3775 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3776 return (PCICFG_FAILURE); 3777 } 3778 3779 /* 3780 * Create the compatible property as an array of pointers 3781 * to strings. Start with the buffer created above. 3782 */ 3783 n = 0; 3784 while (compat[n] != NULL) 3785 n++; 3786 3787 if (n != 0) 3788 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3789 "compatible", compat, n)) != DDI_SUCCESS) 3790 return (ret); 3791 3792 return (PCICFG_SUCCESS); 3793 } 3794 3795 static int 3796 cardbus_set_busnode_props(dev_info_t *dip) 3797 { 3798 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3799 3800 cardbus_force_stringprop(dip, "device_type", "pci"); 3801 3802 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3803 "#address-cells", 3) != DDI_SUCCESS) { 3804 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3805 } 3806 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3807 "#size-cells", 2) != DDI_SUCCESS) { 3808 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3809 } 3810 return (PCICFG_SUCCESS); 3811 } 3812 3813 static int 3814 cardbus_set_busnode_isaprops(dev_info_t *dip) 3815 { 3816 cardbus_err(dip, 6, "cardbus_set_busnode_props\n"); 3817 3818 cardbus_force_stringprop(dip, "device_type", "isa"); 3819 3820 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3821 "#address-cells", 2) != DDI_SUCCESS) { 3822 cardbus_err(dip, 4, "Failed to set #address-cells\n"); 3823 } 3824 if (ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3825 "#size-cells", 1) != DDI_SUCCESS) { 3826 cardbus_err(dip, 4, "Failed to set #size-cells\n"); 3827 } 3828 return (PCICFG_SUCCESS); 3829 } 3830 3831 /* 3832 * Use cb%x,%x rather than pci%x,%x so that we can use specific cardbus 3833 * drivers in /etc/driver_aliases if required 3834 */ 3835 static int 3836 cardbus_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle) 3837 { 3838 int ret; 3839 #ifndef _DONT_USE_1275_GENERIC_NAMES 3840 uint32_t wordval; 3841 #endif 3842 char *name; 3843 char buffer[64]; 3844 uint32_t classcode; 3845 char *compat[8]; 3846 int i, n; 3847 uint16_t subsysid, subvenid, devid, venid; 3848 uint8_t header_type; 3849 3850 /* 3851 * NOTE: These are for both a child and PCI-PCI bridge node 3852 */ 3853 #ifndef _DONT_USE_1275_GENERIC_NAMES 3854 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3855 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3856 #endif 3857 3858 /* Cardbus support */ 3859 venid = pci_config_get16(config_handle, PCI_CONF_VENID); 3860 devid = pci_config_get16(config_handle, PCI_CONF_DEVID); 3861 3862 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3863 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_TWO) { 3864 subvenid = pci_config_get16(config_handle, PCI_CBUS_SUBVENID); 3865 subsysid = pci_config_get16(config_handle, PCI_CBUS_SUBSYSID); 3866 } else { 3867 subvenid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3868 subsysid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3869 } 3870 3871 if (subsysid != 0) { 3872 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3873 } else { 3874 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3875 } 3876 3877 cardbus_err(dip, 8, "Childname is %s\n", buffer); 3878 3879 /* 3880 * In some environments, trying to use "generic" 1275 names is 3881 * not the convention. In those cases use the name as created 3882 * above. In all the rest of the cases, check to see if there 3883 * is a generic name first. 3884 */ 3885 #ifdef _DONT_USE_1275_GENERIC_NAMES 3886 name = buffer; 3887 #else 3888 if ((name = cardbus_get_class_name(wordval>>8)) == NULL) { 3889 /* 3890 * Set name to the above fabricated name 3891 */ 3892 name = buffer; 3893 } 3894 3895 cardbus_err(dip, 8, "Set nodename to %s\n", name); 3896 #endif 3897 3898 /* 3899 * The node name field needs to be filled in with the name 3900 */ 3901 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3902 cardbus_err(dip, 1, "Failed to set nodename for node\n"); 3903 return (PCICFG_FAILURE); 3904 } 3905 3906 /* 3907 * Create the compatible property as an array of pointers 3908 * to strings. Start with the cb name. 3909 */ 3910 n = 0; 3911 3912 if (subsysid != 0) { 3913 (void) sprintf(buffer, "cb%x,%x", subvenid, subsysid); 3914 } else { 3915 (void) sprintf(buffer, "cb%x,%x", venid, devid); 3916 } 3917 3918 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3919 (void) strcpy(compat[n++], buffer); 3920 3921 if (subsysid != 0) { 3922 /* 3923 * Add subsys numbers as pci compatible. 3924 */ 3925 (void) sprintf(buffer, "pci%x,%x", subvenid, subsysid); 3926 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3927 (void) strcpy(compat[n++], buffer); 3928 } 3929 3930 /* 3931 * Add in the VendorID/DeviceID compatible name. 3932 */ 3933 (void) sprintf(buffer, "pci%x,%x", venid, devid); 3934 3935 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3936 (void) strcpy(compat[n++], buffer); 3937 3938 classcode = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3939 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3940 3941 /* 3942 * Add in the Classcode 3943 */ 3944 (void) sprintf(buffer, "pciclass,%06x", classcode); 3945 3946 cardbus_err(dip, 8, "class code %s\n", buffer); 3947 3948 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3949 (void) strcpy(compat[n++], buffer); 3950 3951 if ((ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3952 "compatible", (char **)compat, n)) != DDI_SUCCESS) { 3953 return (ret); 3954 } 3955 3956 for (i = 0; i < n; i++) { 3957 kmem_free(compat[i], strlen(compat[i]) + 1); 3958 } 3959 3960 return (PCICFG_SUCCESS); 3961 } 3962 3963 /* 3964 * Program the bus numbers into the bridge 3965 */ 3966 static void 3967 cardbus_set_bus_numbers(ddi_acc_handle_t config_handle, 3968 uint_t primary, uint_t secondary) 3969 { 3970 cardbus_err(NULL, 8, 3971 "cardbus_set_bus_numbers [%d->%d]\n", primary, secondary); 3972 3973 /* 3974 * Primary bus# 3975 */ 3976 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3977 3978 /* 3979 * Secondary bus# 3980 */ 3981 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3982 3983 /* 3984 * Set the subordinate bus number to ff in order to pass through any 3985 * type 1 cycle with a bus number higher than the secondary bus# 3986 * Note that this is reduced once the probe is complete in the 3987 * cardbus_setup_bridge() function. 3988 */ 3989 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0xFF); 3990 } 3991 3992 static void 3993 enable_pci_isa_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 3994 { 3995 uint16_t comm, stat; 3996 3997 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 3998 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 3999 4000 /* 4001 * Enable memory, IO, bus mastership and error detection. 4002 */ 4003 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4004 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4005 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4006 "fast-back-to-back")) 4007 comm |= PCI_COMM_BACK2BACK_ENAB; 4008 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4009 cardbus_err(NULL, 8, 4010 "enable_pci_isa_bridge stat 0x%04x comm 0x%04x\n", stat, comm); 4011 4012 /* 4013 * ITE8888 Specific registers. 4014 */ 4015 pci_config_put8(config_handle, 0x50, 0x00); /* Timing Control */ 4016 pci_config_put8(config_handle, 0x52, 0x00); /* Master DMA Access */ 4017 pci_config_put8(config_handle, 0x53, 0x01); /* ROMCS */ 4018 } 4019 4020 static void 4021 enable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4022 { 4023 uint16_t comm, stat, bctrl; 4024 4025 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4026 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4027 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4028 4029 comm &= ~(PCI_COMM_IO | PCI_COMM_MAE); 4030 comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4031 4032 /* 4033 * Enable back to back. 4034 */ 4035 if (stat & PCI_STAT_FBBC) 4036 comm |= PCI_COMM_BACK2BACK_ENAB; 4037 4038 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4039 4040 /* 4041 * Reset the sub-ordinate bus. 4042 */ 4043 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4044 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4045 bctrl | PCI_BCNF_BCNTRL_RESET); 4046 else 4047 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4048 4049 /* 4050 * Enable error reporting. 4051 */ 4052 bctrl |= (PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4053 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4054 4055 /* 4056 * Enable back to back on secondary bus. 4057 */ 4058 if (stat & PCI_STAT_FBBC) 4059 bctrl |= PCI_BCNF_BCNTRL_B2B_ENAB; 4060 4061 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4062 cardbus_err(dip, 8, 4063 "enable_pci_pci_bridge stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4064 stat, comm, bctrl); 4065 } 4066 4067 static int cardbus_reset_wait = 20; 4068 4069 static void 4070 enable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4071 { 4072 uint16_t comm, stat, bctrl; 4073 4074 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4075 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4076 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4077 4078 /* 4079 * Don't mess with the command register on the cardbus bridge 4080 * itself. This should have been done when it's parent 4081 * did the setup. Some devices *require* certain things to 4082 * disabled, this can be done using the "command-preserve" 4083 * property and if we mess with it here it breaks that. 4084 * 4085 * comm |= (PCI_COMM_ME | PCI_COMM_PARITY_DETECT | 4086 * PCI_COMM_SERR_ENABLE); 4087 */ 4088 4089 /* 4090 * Reset the sub-ordinate bus. 4091 */ 4092 if (!(bctrl & PCI_BCNF_BCNTRL_RESET)) 4093 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, 4094 bctrl | PCI_BCNF_BCNTRL_RESET); 4095 else 4096 bctrl &= ~PCI_BCNF_BCNTRL_RESET; 4097 4098 /* 4099 * Turn off pre-fetch. 4100 */ 4101 bctrl &= ~(CB_BCNF_BCNTRL_MEM0_PREF | CB_BCNF_BCNTRL_MEM1_PREF | 4102 PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE); 4103 4104 /* 4105 * Enable error reporting. 4106 */ 4107 bctrl |= (PCI_BCNF_BCNTRL_MAST_AB_MODE | CB_BCNF_BCNTRL_WRITE_POST); 4108 if (comm & PCI_COMM_PARITY_DETECT) 4109 bctrl |= PCI_BCNF_BCNTRL_PARITY_ENABLE; 4110 if (comm & PCI_COMM_SERR_ENABLE) 4111 bctrl |= PCI_BCNF_BCNTRL_SERR_ENABLE; 4112 4113 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4114 pci_config_put8(config_handle, PCI_CBUS_LATENCY_TIMER, 4115 cardbus_latency_timer); 4116 4117 pci_config_put16(config_handle, PCI_CONF_STAT, stat); 4118 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4119 4120 cardbus_err(dip, 8, 4121 "enable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4122 stat, comm, bctrl); 4123 4124 /* after resetting the bridge, wait for everything to stablize */ 4125 delay(drv_usectohz(cardbus_reset_wait * 1000)); 4126 4127 } 4128 4129 static void 4130 disable_pci_pci_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4131 { 4132 uint16_t comm, bctrl; 4133 4134 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4135 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4136 4137 /* 4138 * Turn off subordinate bus access. 4139 */ 4140 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4141 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4142 4143 /* 4144 * Disable error reporting. 4145 */ 4146 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4147 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4148 comm = 0; 4149 4150 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4151 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4152 4153 cardbus_err(dip, 6, 4154 "disable_pci_pci_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4155 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4156 } 4157 4158 static void 4159 disable_cardbus_bridge(dev_info_t *dip, ddi_acc_handle_t config_handle) 4160 { 4161 uint16_t comm, bctrl; 4162 4163 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4164 bctrl = pci_config_get16(config_handle, PCI_CBUS_BRIDGE_CTRL); 4165 4166 /* 4167 * Turn off subordinate bus access. 4168 */ 4169 pci_config_put8(config_handle, PCI_BCNF_SECBUS, 0); 4170 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, 0); 4171 4172 /* 4173 * Disable error reporting. 4174 */ 4175 bctrl &= ~(PCI_BCNF_BCNTRL_PARITY_ENABLE | PCI_BCNF_BCNTRL_SERR_ENABLE | 4176 PCI_BCNF_BCNTRL_MAST_AB_MODE); 4177 4178 pci_config_put32(config_handle, PCI_CBUS_MEM_LIMIT0, 0); 4179 pci_config_put32(config_handle, PCI_CBUS_MEM_BASE0, 0); 4180 pci_config_put32(config_handle, PCI_CBUS_IO_LIMIT0, 0); 4181 pci_config_put32(config_handle, PCI_CBUS_IO_BASE0, 0); 4182 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4183 pci_config_put16(config_handle, PCI_CBUS_BRIDGE_CTRL, bctrl); 4184 4185 cardbus_err(dip, 6, 4186 "disable_cardbus_bridge() stat 0x%04x comm 0x%04x bctrl 0x%04x\n", 4187 pci_config_get16(config_handle, PCI_CONF_STAT), comm, bctrl); 4188 } 4189 4190 static void 4191 enable_cardbus_device(dev_info_t *dip, ddi_acc_handle_t config_handle) 4192 { 4193 uint16_t comm, stat; 4194 4195 stat = pci_config_get16(config_handle, PCI_CONF_STAT); 4196 comm = pci_config_get16(config_handle, PCI_CONF_COMM); 4197 4198 /* 4199 * Enable memory, IO, bus mastership and error detection. 4200 */ 4201 comm |= (PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO | 4202 PCI_COMM_PARITY_DETECT | PCI_COMM_SERR_ENABLE); 4203 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 4204 "fast-back-to-back")) 4205 comm |= PCI_COMM_BACK2BACK_ENAB; 4206 pci_config_put16(config_handle, PCI_CONF_COMM, comm); 4207 cardbus_err(NULL, 8, 4208 "enable_cardbus_device stat 0x%04x comm 0x%04x\n", stat, comm); 4209 } 4210 4211 static void 4212 disable_cardbus_device(ddi_acc_handle_t config_handle) 4213 { 4214 cardbus_err(NULL, 8, "disable_cardbus_device\n"); 4215 4216 /* 4217 * Turn off everything in the command register. 4218 */ 4219 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 4220 } 4221 4222 #ifndef _DONT_USE_1275_GENERIC_NAMES 4223 static char * 4224 cardbus_get_class_name(uint32_t classcode) 4225 { 4226 struct cardbus_name_entry *ptr; 4227 4228 for (ptr = &cardbus_class_lookup[0]; ptr->name != NULL; ptr++) { 4229 if (ptr->class_code == classcode) { 4230 return (ptr->name); 4231 } 4232 } 4233 return (NULL); 4234 } 4235 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 4236 4237 static void 4238 cardbus_force_boolprop(dev_info_t *dip, char *pname) 4239 { 4240 int ret; 4241 4242 if ((ret = ndi_prop_create_boolean(DDI_DEV_T_NONE, dip, 4243 pname)) != DDI_SUCCESS) { 4244 if (ret == DDI_PROP_NOT_FOUND) 4245 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4246 DDI_PROP_CANSLEEP, pname, 4247 (caddr_t)NULL, 0) != DDI_SUCCESS) 4248 cardbus_err(dip, 4, 4249 "Failed to set boolean property " 4250 "\"%s\"\n", pname); 4251 } 4252 } 4253 4254 static void 4255 cardbus_force_intprop(dev_info_t *dip, char *pname, int *pval, int len) 4256 { 4257 int ret; 4258 4259 if ((ret = ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 4260 pname, pval, len)) != DDI_SUCCESS) { 4261 if (ret == DDI_PROP_NOT_FOUND) 4262 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4263 DDI_PROP_CANSLEEP, pname, 4264 (caddr_t)pval, len*sizeof (int)) 4265 != DDI_SUCCESS) 4266 cardbus_err(dip, 4, 4267 "Failed to set int property \"%s\"\n", 4268 pname); 4269 } 4270 } 4271 4272 static void 4273 cardbus_force_stringprop(dev_info_t *dip, char *pname, char *pval) 4274 { 4275 int ret; 4276 4277 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 4278 pname, pval)) != DDI_SUCCESS) { 4279 if (ret == DDI_PROP_NOT_FOUND) 4280 if (ddi_prop_create(DDI_DEV_T_NONE, dip, 4281 DDI_PROP_CANSLEEP, pname, 4282 pval, strlen(pval) + 1) != DDI_SUCCESS) 4283 cardbus_err(dip, 4, 4284 "Failed to set string property " 4285 "\"%s\" to \"%s\"\n", 4286 pname, pval); 4287 } 4288 } 4289 4290 static void 4291 split_addr(char *naddr, int *dev, int *func) 4292 { 4293 char c; 4294 int *ip = dev; 4295 4296 *dev = 0; 4297 *func = 0; 4298 4299 while (c = *naddr++) { 4300 if (c == ',') { 4301 ip = func; 4302 continue; 4303 } 4304 if (c >= '0' && c <= '9') { 4305 *ip = (*ip * 16) + (c - '0'); 4306 } else if (c >= 'a' && c <= 'f') { 4307 *ip = (*ip * 16) + 10 + (c - 'a'); 4308 } else 4309 break; 4310 } 4311 } 4312 4313 #ifdef DEBUG 4314 static void 4315 cardbus_dump_common_config(ddi_acc_handle_t config_handle) 4316 { 4317 cardbus_err(NULL, 1, 4318 " Vendor ID = [0x%04x] " 4319 "Device ID = [0x%04x]\n", 4320 pci_config_get16(config_handle, PCI_CONF_VENID), 4321 pci_config_get16(config_handle, PCI_CONF_DEVID)); 4322 cardbus_err(NULL, 1, 4323 " Command REG = [0x%04x] " 4324 "Status REG = [0x%04x]\n", 4325 pci_config_get16(config_handle, PCI_CONF_COMM), 4326 pci_config_get16(config_handle, PCI_CONF_STAT)); 4327 cardbus_err(NULL, 1, 4328 " Revision ID = [0x%02x] " 4329 "Prog Class = [0x%02x]\n", 4330 pci_config_get8(config_handle, PCI_CONF_REVID), 4331 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 4332 cardbus_err(NULL, 1, 4333 " Dev Class = [0x%02x] " 4334 "Base Class = [0x%02x]\n", 4335 pci_config_get8(config_handle, PCI_CONF_SUBCLASS), 4336 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 4337 cardbus_err(NULL, 1, 4338 " Cache LnSz = [0x%02x] " 4339 "Latency Tmr = [0x%02x]\n", 4340 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ), 4341 pci_config_get8(config_handle, PCI_CONF_LATENCY_TIMER)); 4342 cardbus_err(NULL, 1, 4343 " Header Type = [0x%02x] " 4344 "BIST = [0x%02x]\n", 4345 pci_config_get8(config_handle, PCI_CONF_HEADER), 4346 pci_config_get8(config_handle, PCI_CONF_BIST)); 4347 } 4348 4349 static void 4350 cardbus_dump_device_config(ddi_acc_handle_t config_handle) 4351 { 4352 cardbus_dump_common_config(config_handle); 4353 4354 cardbus_err(NULL, 1, 4355 " BASE 0 = [0x%08x] BASE 1 = [0x%08x]\n", 4356 pci_config_get32(config_handle, PCI_CONF_BASE0), 4357 pci_config_get32(config_handle, PCI_CONF_BASE1)); 4358 cardbus_err(NULL, 1, 4359 " BASE 2 = [0x%08x] BASE 3 = [0x%08x]\n", 4360 pci_config_get32(config_handle, PCI_CONF_BASE2), 4361 pci_config_get32(config_handle, PCI_CONF_BASE3)); 4362 cardbus_err(NULL, 1, 4363 " BASE 4 = [0x%08x] BASE 5 = [0x%08x]\n", 4364 pci_config_get32(config_handle, PCI_CONF_BASE4), 4365 pci_config_get32(config_handle, PCI_CONF_BASE5)); 4366 cardbus_err(NULL, 1, 4367 " Cardbus CIS = [0x%08x] ROM = [0x%08x]\n", 4368 pci_config_get32(config_handle, PCI_CONF_CIS), 4369 pci_config_get32(config_handle, PCI_CONF_ROM)); 4370 cardbus_err(NULL, 1, 4371 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4372 pci_config_get16(config_handle, PCI_CONF_SUBVENID), 4373 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 4374 cardbus_err(NULL, 1, 4375 " I Line = [0x%02x] I Pin = [0x%02x]\n", 4376 pci_config_get8(config_handle, PCI_CONF_ILINE), 4377 pci_config_get8(config_handle, PCI_CONF_IPIN)); 4378 cardbus_err(NULL, 1, 4379 " Max Grant = [0x%02x] Max Latent = [0x%02x]\n", 4380 pci_config_get8(config_handle, PCI_CONF_MIN_G), 4381 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 4382 } 4383 4384 static void 4385 cardbus_dump_bridge_config(ddi_acc_handle_t config_handle, 4386 uint8_t header_type) 4387 { 4388 if (header_type == PCI_HEADER_PPB) { 4389 cardbus_dump_common_config(config_handle); 4390 cardbus_err(NULL, 1, 4391 "........................................\n"); 4392 } else { 4393 cardbus_dump_common_config(config_handle); 4394 cardbus_err(NULL, 1, 4395 " Mem Base = [0x%08x] CBus Status = [0x%04x]\n", 4396 pci_config_get32(config_handle, PCI_CBUS_SOCK_REG), 4397 pci_config_get16(config_handle, PCI_CBUS_SEC_STATUS)); 4398 } 4399 4400 cardbus_err(NULL, 1, 4401 " Pri Bus = [0x%02x] Sec Bus = [0x%02x]\n", 4402 pci_config_get8(config_handle, PCI_BCNF_PRIBUS), 4403 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 4404 cardbus_err(NULL, 1, 4405 " Sub Bus = [0x%02x] Sec Latency = [0x%02x]\n", 4406 pci_config_get8(config_handle, PCI_BCNF_SUBBUS), 4407 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 4408 4409 switch (header_type) { 4410 case PCI_HEADER_PPB: 4411 cardbus_err(NULL, 1, 4412 " I/O Base LO = [0x%02x] I/O Lim LO = [0x%02x]\n", 4413 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW), 4414 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 4415 cardbus_err(NULL, 1, 4416 " Sec. Status = [0x%04x]\n", 4417 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 4418 cardbus_err(NULL, 1, 4419 " Mem Base = [0x%04x] Mem Limit = [0x%04x]\n", 4420 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE), 4421 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 4422 cardbus_err(NULL, 1, 4423 " PF Mem Base = [0x%04x] PF Mem Lim = [0x%04x]\n", 4424 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW), 4425 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 4426 cardbus_err(NULL, 1, 4427 " PF Base HI = [0x%08x] PF Lim HI = [0x%08x]\n", 4428 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH), 4429 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 4430 cardbus_err(NULL, 1, 4431 " I/O Base HI = [0x%04x] I/O Lim HI = [0x%04x]\n", 4432 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI), 4433 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 4434 cardbus_err(NULL, 1, 4435 " ROM addr = [0x%08x]\n", 4436 pci_config_get32(config_handle, PCI_BCNF_ROM)); 4437 break; 4438 case PCI_HEADER_CARDBUS: 4439 cardbus_err(NULL, 1, 4440 " Mem Base 0 = [0x%08x] Mem Limit 0 = [0x%08x]\n", 4441 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE0), 4442 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT0)); 4443 cardbus_err(NULL, 1, 4444 " Mem Base 1 = [0x%08x] Mem Limit 1 = [0x%08x]\n", 4445 pci_config_get32(config_handle, PCI_CBUS_MEM_BASE1), 4446 pci_config_get32(config_handle, PCI_CBUS_MEM_LIMIT1)); 4447 cardbus_err(NULL, 1, 4448 " IO Base 0 = [0x%08x] IO Limit 0 = [0x%08x]\n", 4449 pci_config_get32(config_handle, PCI_CBUS_IO_BASE0), 4450 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT0)); 4451 cardbus_err(NULL, 1, 4452 " IO Base 1 = [0x%08x] IO Limit 1 = [0x%08x]\n", 4453 pci_config_get32(config_handle, PCI_CBUS_IO_BASE1), 4454 pci_config_get32(config_handle, PCI_CBUS_IO_LIMIT1)); 4455 break; 4456 } 4457 cardbus_err(NULL, 1, 4458 " Intr Line = [0x%02x] Intr Pin = [0x%02x]\n", 4459 pci_config_get8(config_handle, PCI_BCNF_ILINE), 4460 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 4461 cardbus_err(NULL, 1, 4462 " Bridge Ctrl = [0x%04x]\n", 4463 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 4464 4465 switch (header_type) { 4466 case PCI_HEADER_CARDBUS: 4467 cardbus_err(NULL, 1, 4468 " Sub VID = [0x%04x] Sub SID = [0x%04x]\n", 4469 pci_config_get16(config_handle, PCI_CBUS_SUBVENID), 4470 pci_config_get16(config_handle, PCI_CBUS_SUBSYSID)); 4471 /* LATER: TI1250 only */ 4472 cardbus_err(NULL, 1, 4473 " Sys Control = [0x%08x]\n", 4474 pci_config_get32(config_handle, 0x80)); 4475 } 4476 } 4477 4478 static void 4479 cardbus_dump_config(ddi_acc_handle_t config_handle) 4480 { 4481 uint8_t header_type = pci_config_get8(config_handle, 4482 PCI_CONF_HEADER) & PCI_HEADER_TYPE_M; 4483 4484 if (header_type == PCI_HEADER_PPB || header_type == PCI_HEADER_CARDBUS) 4485 cardbus_dump_bridge_config(config_handle, header_type); 4486 else 4487 cardbus_dump_device_config(config_handle); 4488 } 4489 4490 static void 4491 cardbus_dump_reg(dev_info_t *dip, const pci_regspec_t *regspec, int nelems) 4492 { 4493 /* int rlen = nelems * sizeof(pci_regspec_t); */ 4494 4495 cardbus_err(dip, 6, 4496 "cardbus_dump_reg: \"reg\" has %d elements\n", nelems); 4497 4498 #if defined(CARDBUS_DEBUG) 4499 if (cardbus_debug >= 1) { 4500 int i; 4501 uint32_t *regs = (uint32_t *)regspec; 4502 4503 for (i = 0; i < nelems; i++) { 4504 4505 cardbus_err(NULL, 6, 4506 "\t%d:%08x %08x %08x %08x %08x\n", 4507 i, regs[0], regs[1], regs[2], regs[3], regs[4]); 4508 } 4509 } 4510 #endif 4511 } 4512 4513 #endif 4514 4515 #if defined(CARDBUS_DEBUG) 4516 void 4517 cardbus_dump_children(dev_info_t *dip, int level) 4518 { 4519 dev_info_t *next; 4520 4521 cardbus_err(dip, 1, 4522 "\t%d: %s: 0x%p\n", level, ddi_node_name(dip), (void *) dip); 4523 for (next = ddi_get_child(dip); next; 4524 next = ddi_get_next_sibling(next)) 4525 cardbus_dump_children(next, level + 1); 4526 } 4527 4528 void 4529 cardbus_dump_family_tree(dev_info_t *dip) 4530 { 4531 cardbus_err(dip, 1, "0x%p family tree:\n", (void *) dip); 4532 cardbus_dump_children(dip, 1); 4533 } 4534 #endif 4535