1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/types.h> 35 36 37 /* 38 * First section: 39 * Identification of the various Broadcom chips 40 * 41 * Note: the various ID values are *not* all unique ;-( 42 * 43 * Note: the presence of an ID here does *not* imply that the chip is 44 * supported. At this time, only the 5703C, 5704C, and 5704S devices 45 * used on the motherboards of certain Sun products are supported. 46 * 47 * Note: the revision-id values in the PCI revision ID register are 48 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 49 */ 50 51 #define VENDOR_ID_BROADCOM 0x14e4 52 #define VENDOR_ID_SUN 0x108e 53 54 #define DEVICE_ID_5700 0x1644 55 #define DEVICE_ID_5700x 0x0003 56 #define DEVICE_ID_5701 0x1645 57 #define DEVICE_ID_5702 0x16a6 58 #define DEVICE_ID_5702fe 0x164d 59 #define DEVICE_ID_5703C 0x1647 60 #define DEVICE_ID_5703S 0x16a7 61 #define DEVICE_ID_5703 0x16c7 62 #define DEVICE_ID_5704C 0x1648 63 #define DEVICE_ID_5704S 0x16a8 64 #define DEVICE_ID_5704 0x1649 65 #define DEVICE_ID_5705C 0x1653 66 #define DEVICE_ID_5705_2 0x1654 67 #define DEVICE_ID_5705M 0x165d 68 #define DEVICE_ID_5705MA3 0x165e 69 #define DEVICE_ID_5705F 0x166e 70 #define DEVICE_ID_5706 0x164a 71 #define DEVICE_ID_5782 0x1696 72 #define DEVICE_ID_5787 0x169b 73 #define DEVICE_ID_5787M 0x1693 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5753 0x16fd 81 #define DEVICE_ID_5754 0x167a 82 #define DEVICE_ID_5755 0x167b 83 #define DEVICE_ID_5755M 0x1673 84 #define DEVICE_ID_5721 0x1659 85 #define DEVICE_ID_5722 0x165a 86 #define DEVICE_ID_5714C 0x1668 87 #define DEVICE_ID_5714S 0x1669 88 #define DEVICE_ID_5715C 0x1678 89 #define DEVICE_ID_5715S 0x1679 90 91 #define REVISION_ID_5700_B0 0x10 92 #define REVISION_ID_5700_B2 0x12 93 #define REVISION_ID_5700_B3 0x13 94 #define REVISION_ID_5700_C0 0x20 95 #define REVISION_ID_5700_C1 0x21 96 #define REVISION_ID_5700_C2 0x22 97 98 #define REVISION_ID_5701_A0 0x08 99 #define REVISION_ID_5701_A2 0x12 100 #define REVISION_ID_5701_A3 0x15 101 102 #define REVISION_ID_5702_A0 0x00 103 104 #define REVISION_ID_5703_A0 0x00 105 #define REVISION_ID_5703_A1 0x01 106 #define REVISION_ID_5703_A2 0x02 107 108 #define REVISION_ID_5704_A0 0x00 109 #define REVISION_ID_5704_A1 0x01 110 #define REVISION_ID_5704_A2 0x02 111 #define REVISION_ID_5704_A3 0x03 112 #define REVISION_ID_5704_B0 0x10 113 114 #define REVISION_ID_5705_A0 0x00 115 #define REVISION_ID_5705_A1 0x01 116 #define REVISION_ID_5705_A2 0x02 117 #define REVISION_ID_5705_A3 0x03 118 119 #define REVISION_ID_5721_A0 0x00 120 #define REVISION_ID_5721_A1 0x01 121 122 #define REVISION_ID_5751_A0 0x00 123 #define REVISION_ID_5751_A1 0x01 124 125 #define REVISION_ID_5714_A0 0x00 126 #define REVISION_ID_5714_A1 0x01 127 #define REVISION_ID_5714_A2 0xA2 128 #define REVISION_ID_5714_A3 0xA3 129 130 #define REVISION_ID_5715_A0 0x00 131 #define REVISION_ID_5715_A1 0x01 132 #define REVISION_ID_5715_A2 0xA2 133 134 #define REVISION_ID_5715S_A0 0x00 135 #define REVISION_ID_5715S_A1 0x01 136 137 #define REVISION_ID_5754_A0 0x00 138 #define REVISION_ID_5754_A1 0x01 139 140 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 141 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 142 (bgep->chipid.device == DEVICE_ID_5701) ||\ 143 (bgep->chipid.device == DEVICE_ID_5702) ||\ 144 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 145 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 146 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 147 (bgep->chipid.device == DEVICE_ID_5703) ||\ 148 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 149 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 150 (bgep->chipid.device == DEVICE_ID_5704)) 151 152 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 153 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 154 (bgep->chipid.device == DEVICE_ID_5702fe)) 155 156 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 157 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 158 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 159 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 160 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 161 (bgep->chipid.device == DEVICE_ID_5782) ||\ 162 (bgep->chipid.device == DEVICE_ID_5788) ||\ 163 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 164 (bgep->chipid.device == DEVICE_ID_5754) ||\ 165 (bgep->chipid.device == DEVICE_ID_5755) ||\ 166 (bgep->chipid.device == DEVICE_ID_5753)) 167 168 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 169 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 170 (bgep->chipid.device == DEVICE_ID_5751) ||\ 171 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 172 (bgep->chipid.device == DEVICE_ID_5752) ||\ 173 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 174 (bgep->chipid.device == DEVICE_ID_5789)) 175 176 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 177 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 178 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 179 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 180 (bgep->chipid.device == DEVICE_ID_5715S)) 181 182 /* 183 * Second section: 184 * Offsets of important registers & definitions for bits therein 185 */ 186 187 /* 188 * PCI-X registers & bits 189 */ 190 #define PCIX_CONF_COMM 0x42 191 #define PCIX_COMM_RELAXED 0x0002 192 193 /* 194 * Miscellaneous Host Control Register, in PCI config space 195 */ 196 #define PCI_CONF_BGE_MHCR 0x68 197 #define MHCR_CHIP_REV_MASK 0xffff0000 198 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 199 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 200 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 201 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 202 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 203 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 204 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 205 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 206 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 207 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 208 209 #define MHCR_CHIP_REV_5700_B0 0x71000000 210 #define MHCR_CHIP_REV_5700_B2 0x71020000 211 #define MHCR_CHIP_REV_5700_B3 0x71030000 212 #define MHCR_CHIP_REV_5700_C0 0x72000000 213 #define MHCR_CHIP_REV_5700_C1 0x72010000 214 #define MHCR_CHIP_REV_5700_C2 0x72020000 215 216 #define MHCR_CHIP_REV_5701_A0 0x00000000 217 #define MHCR_CHIP_REV_5701_A2 0x00020000 218 #define MHCR_CHIP_REV_5701_A3 0x00030000 219 #define MHCR_CHIP_REV_5701_A5 0x01050000 220 221 #define MHCR_CHIP_REV_5702_A0 0x10000000 222 #define MHCR_CHIP_REV_5702_A1 0x10010000 223 #define MHCR_CHIP_REV_5702_A2 0x10020000 224 225 #define MHCR_CHIP_REV_5703_A0 0x10000000 226 #define MHCR_CHIP_REV_5703_A1 0x10010000 227 #define MHCR_CHIP_REV_5703_A2 0x10020000 228 #define MHCR_CHIP_REV_5703_B0 0x11000000 229 #define MHCR_CHIP_REV_5703_B1 0x11010000 230 231 #define MHCR_CHIP_REV_5704_A0 0x20000000 232 #define MHCR_CHIP_REV_5704_A1 0x20010000 233 #define MHCR_CHIP_REV_5704_A2 0x20020000 234 #define MHCR_CHIP_REV_5704_A3 0x20030000 235 #define MHCR_CHIP_REV_5704_B0 0x21000000 236 237 #define MHCR_CHIP_REV_5705_A0 0x30000000 238 #define MHCR_CHIP_REV_5705_A1 0x30010000 239 #define MHCR_CHIP_REV_5705_A2 0x30020000 240 #define MHCR_CHIP_REV_5705_A3 0x30030000 241 #define MHCR_CHIP_REV_5705_A5 0x30050000 242 243 #define MHCR_CHIP_REV_5782_A0 0x30030000 244 #define MHCR_CHIP_REV_5782_A1 0x30030088 245 246 #define MHCR_CHIP_REV_5788_A1 0x30050000 247 248 #define MHCR_CHIP_REV_5751_A0 0x40000000 249 #define MHCR_CHIP_REV_5751_A1 0x40010000 250 251 #define MHCR_CHIP_REV_5721_A0 0x41000000 252 #define MHCR_CHIP_REV_5721_A1 0x41010000 253 254 #define MHCR_CHIP_REV_5714_A0 0x50000000 255 #define MHCR_CHIP_REV_5714_A1 0x90010000 256 257 #define MHCR_CHIP_REV_5715_A0 0x50000000 258 #define MHCR_CHIP_REV_5715_A1 0x90010000 259 260 #define MHCR_CHIP_REV_5715S_A0 0x50000000 261 #define MHCR_CHIP_REV_5715S_A1 0x90010000 262 263 #define MHCR_CHIP_REV_5754_A0 0xb0000000 264 #define MHCR_CHIP_REV_5754_A1 0xb0010000 265 266 #define MHCR_CHIP_REV_5787_A0 0xb0000000 267 #define MHCR_CHIP_REV_5787_A1 0xb0010000 268 #define MHCR_CHIP_REV_5787_A2 0xb0020000 269 270 #define MHCR_CHIP_REV_5755_A0 0xa0000000 271 #define MHCR_CHIP_REV_5755_A1 0xa0010000 272 273 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 274 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 275 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 276 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 277 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 278 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 279 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 280 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 281 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 282 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 283 #define MHCR_CHIP_ASIC_REV_5787 ((uint32_t)0xb << 28) 284 #define MHCR_CHIP_ASIC_REV_5755 ((uint32_t)0xa << 28) 285 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 286 287 288 /* 289 * PCI DMA read/write Control Register, in PCI config space 290 * 291 * Note that several fields previously defined here have been deleted 292 * as they are not implemented in the 5703/4. 293 * 294 * Note: the value of this register is critical. It is possible to 295 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 296 * by programming the wrong value. The value #defined below has been 297 * tested and shown to avoid all known problems. If it is to be changed, 298 * correct operation must be reverified on all supported platforms. 299 * 300 * In particular, we set both watermark fields to 2xCacheLineSize (128) 301 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 302 * with Tomatillo's internal pipelines, that otherwise result in stalls, 303 * repeated retries, and DTOs. 304 */ 305 #define PCI_CONF_BGE_PDRWCR 0x6c 306 #define PDRWCR_RWCMD_MASK 0xFF000000 307 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 308 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 309 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 310 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 311 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 312 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 313 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 314 315 /* 316 * These are the actual values to be put into the fields shown above 317 */ 318 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 319 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 320 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 321 #define PDRWCR_MIN_BEATS 0x00000000 322 323 #define PDRWCR_VAR_DEFAULT 0x761b0000 324 #define PDRWCR_VAR_5721 0x76180000 325 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 326 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 327 328 /* 329 * PCI State Register, in PCI config space 330 * 331 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 332 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 333 */ 334 #define PCI_CONF_BGE_PCISTATE 0x70 335 #define PCISTATE_RETRY_SAME_DMA 0x00002000 336 #define PCISTATE_FLAT_VIEW 0x00000100 337 #define PCISTATE_EXT_ROM_RETRY 0x00000040 338 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 339 #define PCISTATE_BUS_IS_32_BIT 0x00000010 340 #define PCISTATE_BUS_IS_FAST 0x00000008 341 #define PCISTATE_BUS_IS_PCI 0x00000004 342 #define PCISTATE_INTA_STATE 0x00000002 343 #define PCISTATE_FORCE_RESET 0x00000001 344 345 /* 346 * PCI Clock Control Register, in PCI config space 347 */ 348 #define PCI_CONF_BGE_CLKCTL 0x74 349 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 350 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 351 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 352 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 353 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 354 #define CLKCTL_PCIE_A0_FIX 0x00101000 355 356 /* 357 * Dual MAC Control Register, in PCI config space 358 */ 359 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 360 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 361 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 362 363 /* 364 * Register Indirect Access Address Register, 0x78 in PCI config 365 * space. Once this is set, accesses to the Register Indirect 366 * Access Data Register (0x80) refer to the register whose address 367 * is given by *this* register. This allows access to all the 368 * operating registers, while using only config space accesses. 369 * 370 * Note that the address written to the RIIAR should lie in one 371 * of the following ranges: 372 * 0x00000000 <= address < 0x00008000 (regular registers) 373 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 374 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 375 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 376 */ 377 #define PCI_CONF_BGE_RIAAR 0x78 378 #define PCI_CONF_BGE_RIADR 0x80 379 380 #define RIAAR_REGISTER_MIN 0x00000000 381 #define RIAAR_REGISTER_MAX 0x00008000 382 #define RIAAR_RX_SCRATCH_MIN 0x00030000 383 #define RIAAR_RX_SCRATCH_MAX 0x00034000 384 #define RIAAR_TX_SCRATCH_MIN 0x00034000 385 #define RIAAR_TX_SCRATCH_MAX 0x00038000 386 #define RIAAR_RXROM_MIN 0x00038000 387 #define RIAAR_RXROM_MAX 0x00038800 388 389 /* 390 * Memory Window Base Address Register, 0x7c in PCI config space 391 * Once this is set, accesses to the Memory Window Data Access Register 392 * (0x84) refer to the word of NIC-local memory whose address is given 393 * by this register. When used in this way, the whole of the address 394 * written to this register is significant. 395 * 396 * This register also provides the 32K-aligned base address for a 32K 397 * region of NIC-local memory that the host can directly address in 398 * the upper 32K of the 64K of PCI memory space allocated to the chip. 399 * In this case, the bottom 15 bits of the register are ignored. 400 * 401 * Note that the address written to the MWBAR should lie in the range 402 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 403 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 404 * memory were present, but it's only supported on the 5700, not the 405 * 5701/5703/5704. 406 */ 407 #define PCI_CONF_BGE_MWBAR 0x7c 408 #define PCI_CONF_BGE_MWDAR 0x84 409 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 410 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 411 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 412 413 /* 414 * The PCI express device control register and device status register 415 * which are only applicable on BCM5751 and BCM5721. 416 */ 417 #define PCI_CONF_DEV_CTRL 0xd8 418 #define READ_REQ_SIZE_MAX 0x5000 419 #define DEV_CTRL_NO_SNOOP 0x0800 420 #define DEV_CTRL_RELAXED 0x0010 421 422 #define PCI_CONF_DEV_STUS 0xda 423 #define DEVICE_ERROR_STUS 0xf 424 425 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 426 427 /* 428 * Where to find things in NIC-local (on-chip) memory 429 */ 430 #define NIC_MEM_SEND_RINGS 0x0100 431 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 432 #define NIC_MEM_RECV_RINGS 0x0200 433 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 434 #define NIC_MEM_STATISTICS 0x0300 435 #define NIC_MEM_STATISTICS_SIZE 0x0800 436 #define NIC_MEM_STATUS_BLOCK 0x0b00 437 #define NIC_MEM_STATUS_SIZE 0x0050 438 #define NIC_MEM_GENCOMM 0x0b50 439 440 441 /* 442 * Note: the (non-bogus) values below are appropriate for systems 443 * without external memory. They would be different on a 5700 with 444 * external memory. 445 * 446 * Note: The higher send ring addresses and the mini ring shadow 447 * buffer address are dummies - systems without external memory 448 * are limited to 4 send rings and no mini receive ring. 449 */ 450 #define NIC_MEM_SHADOW_DMA 0x2000 451 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 452 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 453 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 454 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 455 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 456 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 457 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 458 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 459 460 /* 461 * Put this in the GENCOMM port to tell the firmware not to run PXE 462 */ 463 #define T3_MAGIC_NUMBER 0x4b657654u 464 465 /* 466 * The remaining registers appear in the low 32K of regular 467 * PCI Memory Address Space 468 */ 469 470 /* 471 * All the state machine control registers below have at least a 472 * <RESET> bit and an <ENABLE> bit as defined below. Some also 473 * have an <ATTN_ENABLE> bit. 474 */ 475 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 476 #define STATE_MACHINE_ENABLE_BIT 0x00000002 477 #define STATE_MACHINE_RESET_BIT 0x00000001 478 479 #define TRANSMIT_MAC_MODE_REG 0x045c 480 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 481 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 482 #define SEND_BD_SELECTOR_MODE_REG 0x1400 483 #define SEND_BD_INITIATOR_MODE_REG 0x1800 484 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 485 486 #define RECEIVE_MAC_MODE_REG 0x0468 487 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 488 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 489 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 490 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 491 #define RCV_BD_COMPLETION_MODE_REG 0x3000 492 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 493 494 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 495 #define HOST_COALESCE_MODE_REG 0x3c00 496 #define MEMORY_ARBITER_MODE_REG 0x4000 497 #define BUFFER_MANAGER_MODE_REG 0x4400 498 #define READ_DMA_MODE_REG 0x4800 499 #define WRITE_DMA_MODE_REG 0x4c00 500 #define DMA_COMPLETION_MODE_REG 0x6400 501 502 /* 503 * Other bits in some of the above state machine control registers 504 */ 505 506 /* 507 * Transmit MAC Mode Register 508 * (TRANSMIT_MAC_MODE_REG, 0x045c) 509 */ 510 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 511 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 512 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 513 514 /* 515 * Receive MAC Mode Register 516 * (RECEIVE_MAC_MODE_REG, 0x0468) 517 */ 518 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 519 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 520 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 521 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 522 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 523 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 524 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 525 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 526 527 /* 528 * Receive BD Initiator Mode Register 529 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 530 * 531 * Each of these bits controls whether ATTN is asserted 532 * on a particular condition 533 */ 534 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 535 536 /* 537 * Receive Data & Receive BD Initiator Mode Register 538 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 539 * 540 * Each of these bits controls whether ATTN is asserted 541 * on a particular condition 542 */ 543 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 544 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 545 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 546 547 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 548 549 /* 550 * Host Coalescing Mode Control Register 551 * (HOST_COALESCE_MODE_REG, 0x3c00) 552 */ 553 #define COALESCE_64_BYTE_RINGS 12 554 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 555 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 556 #define COALESCE_CLR_TICKS_TX 0x00000400 557 #define COALESCE_CLR_TICKS_RX 0x00000200 558 #define COALESCE_32_BYTE_STATUS 0x00000100 559 #define COALESCE_64_BYTE_STATUS 0x00000080 560 #define COALESCE_NOW 0x00000008 561 562 /* 563 * Memory Arbiter Mode Register 564 * (MEMORY_ARBITER_MODE_REG, 0x4000) 565 */ 566 #define MEMORY_ARBITER_ENABLE 0x00000002 567 568 /* 569 * Buffer Manager Mode Register 570 * (BUFFER_MANAGER_MODE_REG, 0x4400) 571 * 572 * In addition to the usual error-attn common to most state machines 573 * this register has a separate bit for attn on running-low-on-mbufs 574 */ 575 #define BUFF_MGR_TEST_MODE 0x00000008 576 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 577 578 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 579 580 /* 581 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 582 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 583 * 584 * These registers each contain a 2-bit priority field, which controls 585 * the relative priority of that type of DMA (read vs. write vs. MSI), 586 * and a set of bits that control whether ATTN is asserted on each 587 * particular condition 588 */ 589 #define DMA_PRIORITY_MASK 0xc0000000 590 #define DMA_PRIORITY_SHIFT 30 591 #define ALL_DMA_ATTN_BITS 0x000003fc 592 593 /* 594 * BCM5755, 5755M, 5906, 5906M only 595 * 1 - Enable Fix. Device will send out the status block before 596 * the interrupt message 597 * 0 - Disable fix. Device will send out the interrupt message 598 * before the status block 599 */ 600 #define DMA_STATUS_TAG_FIX_CQ12384 0x20000000 601 602 /* 603 * End of state machine control register definitions 604 */ 605 606 607 /* 608 * Mailbox Registers (8 bytes each, but high half unused) 609 */ 610 #define INTERRUPT_MBOX_0_REG 0x0200 611 #define INTERRUPT_MBOX_1_REG 0x0208 612 #define INTERRUPT_MBOX_2_REG 0x0210 613 #define INTERRUPT_MBOX_3_REG 0x0218 614 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 615 616 /* 617 * Ring Producer/Consumer Index (Mailbox) Registers 618 */ 619 #define RECV_STD_PROD_INDEX_REG 0x0268 620 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 621 #define RECV_MINI_PROD_INDEX_REG 0x0278 622 #define RECV_RING_CONS_INDEX_REGS 0x0280 623 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 624 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 625 626 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 627 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 628 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 629 630 /* 631 * Ethernet MAC Mode Register 632 */ 633 #define ETHERNET_MAC_MODE_REG 0x0400 634 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 635 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 636 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 637 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 638 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 639 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 640 #define ETHERNET_MODE_SEND_CFGS 0x00020000 641 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 642 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 643 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 644 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 645 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 646 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 647 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 648 #define ETHERNET_MODE_MAX_DEFER 0x00000200 649 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 650 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 651 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 652 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 653 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 654 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 655 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 656 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 657 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 658 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 659 660 /* 661 * Ethernet MAC Status & Event Registers 662 */ 663 #define ETHERNET_MAC_STATUS_REG 0x0404 664 #define ETHERNET_STATUS_MI_INT 0x00800000 665 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 666 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 667 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 668 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 669 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 670 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 671 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 672 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 673 674 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 675 #define ETHERNET_EVENT_MI_INT 0x00800000 676 #define ETHERNET_EVENT_LINK_INT 0x00001000 677 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 678 679 /* 680 * Ethernet MAC LED Control Register 681 * 682 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 683 * the external LED driver circuitry is wired up to assume that this mode 684 * will always be selected. Software must not change it! 685 */ 686 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 687 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 688 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 689 #define LED_CONTROL_LED_MODE_MASK 0x00001800 690 #define LED_CONTROL_LED_MODE_5700 0x00000000 691 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 692 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 693 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 694 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 695 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 696 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 697 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 698 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 699 #define LED_CONTROL_TRAFFIC_LED 0x00000020 700 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 701 #define LED_CONTROL_10MBPS_LED 0x00000008 702 #define LED_CONTROL_100MBPS_LED 0x00000004 703 #define LED_CONTROL_1000MBPS_LED 0x00000002 704 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 705 #define LED_CONTROL_DEFAULT 0x02000800 706 707 /* 708 * MAC Address registers 709 * 710 * These four eight-byte registers each hold one unicast address 711 * (six bytes), right justified & zero-filled on the left. 712 * They will normally all be set to the same value, as a station 713 * usually only has one h/w address. The value in register 0 is 714 * used for pause packets; any of the four can be specified for 715 * substitution into other transmitted packets if required. 716 */ 717 #define MAC_ADDRESS_0_REG 0x0410 718 #define MAC_ADDRESS_1_REG 0x0418 719 #define MAC_ADDRESS_2_REG 0x0420 720 #define MAC_ADDRESS_3_REG 0x0428 721 722 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 723 #define MAC_ADDRESS_REGS_MAX 4 724 725 /* 726 * More MAC Registers ... 727 */ 728 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 729 #define MAC_RX_MTU_SIZE_REG 0x043c 730 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 731 #define MAC_TX_LENGTHS_REG 0x0464 732 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 733 734 /* 735 * MII access registers 736 */ 737 #define MI_COMMS_REG 0x044c 738 #define MI_COMMS_START 0x20000000 739 #define MI_COMMS_READ_FAILED 0x10000000 740 #define MI_COMMS_COMMAND_MASK 0x0c000000 741 #define MI_COMMS_COMMAND_READ 0x08000000 742 #define MI_COMMS_COMMAND_WRITE 0x04000000 743 #define MI_COMMS_ADDRESS_MASK 0x03e00000 744 #define MI_COMMS_ADDRESS_SHIFT 21 745 #define MI_COMMS_REGISTER_MASK 0x001f0000 746 #define MI_COMMS_REGISTER_SHIFT 16 747 #define MI_COMMS_DATA_MASK 0x0000ffff 748 #define MI_COMMS_DATA_SHIFT 0 749 750 #define MI_STATUS_REG 0x0450 751 #define MI_STATUS_10MBPS 0x00000002 752 #define MI_STATUS_LINK 0x00000001 753 754 #define MI_MODE_REG 0x0454 755 #define MI_MODE_CLOCK_MASK 0x001f0000 756 #define MI_MODE_AUTOPOLL 0x00000010 757 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 758 #define MI_MODE_DEFAULT 0x000c0000 759 760 #define MI_AUTOPOLL_STATUS_REG 0x0458 761 #define MI_AUTOPOLL_ERROR 0x00000001 762 763 #define TRANSMIT_MAC_STATUS_REG 0x0460 764 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 765 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 766 #define TRANSMIT_STATUS_LINK_UP 0x00000008 767 #define TRANSMIT_STATUS_SENT_XON 0x00000004 768 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 769 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 770 771 #define RECEIVE_MAC_STATUS_REG 0x046c 772 #define RECEIVE_STATUS_RCVD_XON 0x00000004 773 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 774 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 775 776 /* 777 * These four-byte registers constitute a hash table for deciding 778 * whether to accept incoming multicast packets. The bits are 779 * numbered in big-endian fashion, from hash 0 => the MSB of 780 * register 0 to hash 127 => the LSB of the highest-numbered 781 * register. 782 * 783 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 784 * enabled by setting the appropriate bit in the Rx MAC mode 785 * register. Otherwise, and on all earlier chips, the table 786 * is only 128 bits (registers 0-3). 787 */ 788 #define MAC_HASH_0_REG 0x0470 789 #define MAC_HASH_1_REG 0x0474 790 #define MAC_HASH_2_REG 0x0478 791 #define MAC_HASH_3_REG 0x047c 792 #define MAC_HASH_4_REG 0x???? 793 #define MAC_HASH_5_REG 0x???? 794 #define MAC_HASH_6_REG 0x???? 795 #define MAC_HASH_7_REG 0x???? 796 #define MAC_HASH_REG(n) (0x470+4*(n)) 797 798 /* 799 * Receive Rules Registers: 16 pairs of control+mask/value pairs 800 */ 801 #define RCV_RULES_CONTROL_0_REG 0x0480 802 #define RCV_RULES_MASK_0_REG 0x0484 803 #define RCV_RULES_CONTROL_15_REG 0x04f8 804 #define RCV_RULES_MASK_15_REG 0x04fc 805 #define RCV_RULES_CONFIG_REG 0x0500 806 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 807 808 #define RECV_RULES_NUM_MAX 16 809 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 810 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 811 812 #define RECV_RULE_CTL_ENABLE 0x80000000 813 #define RECV_RULE_CTL_AND 0x40000000 814 #define RECV_RULE_CTL_P1 0x20000000 815 #define RECV_RULE_CTL_P2 0x10000000 816 #define RECV_RULE_CTL_P3 0x08000000 817 #define RECV_RULE_CTL_MASK 0x04000000 818 #define RECV_RULE_CTL_DISCARD 0x02000000 819 #define RECV_RULE_CTL_MAP 0x01000000 820 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 821 #define RECV_RULE_CTL_OP 0x00030000 822 #define RECV_RULE_CTL_OP_EQ 0x00000000 823 #define RECV_RULE_CTL_OP_NEQ 0x00010000 824 #define RECV_RULE_CTL_OP_GREAT 0x00020000 825 #define RECV_RULE_CTL_OP_LESS 0x00030000 826 #define RECV_RULE_CTL_HEADER 0x0000e000 827 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 828 #define RECV_RULE_CTL_HEADER_IP 0x00002000 829 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 830 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 831 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 832 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 833 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 834 RECV_RULE_CTL_CLASS_BITS) 835 #define RECV_RULE_CTL_OFFSET 0x000000ff 836 837 /* 838 * Receive Rules definition 839 */ 840 #define RULE_MATCH_TO_RING 2 841 /* ring that traffic will go into when recv rule matches. */ 842 /* value is between 1 and 16, not 0 and 15 */ 843 844 #define IPHEADER_PROTO_OFFSET 0x08 845 #define IPHEADER_SIP_OFFSET 0x0c 846 847 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 848 RECV_RULE_CTL_OP_EQ | \ 849 RECV_RULE_CTL_HEADER_IP | \ 850 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 851 IPHEADER_PROTO_OFFSET) 852 #define RULE_TCP_MASK_VALUE 0x00ff0006 853 #define RULE_UDP_MASK_VALUE 0x00ff0011 854 #define RULE_ICMP_MASK_VALUE 0x00ff0001 855 856 #define RULE_SIP_ADDR 0x0a000001 857 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 858 859 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 860 RECV_RULE_CTL_HEADER_IP | \ 861 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 862 IPHEADER_SIP_OFFSET) 863 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 864 865 /* 866 * 1000BaseX low-level access registers 867 */ 868 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 869 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 870 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 871 #define TX_1000BASEX_AUTONEG_REG 0x0444 872 #define RX_1000BASEX_AUTONEG_REG 0x0448 873 874 /* 875 * Autoneg code bits for the 1000BASE-X AUTONEG registers 876 */ 877 #define AUTONEG_CODE_PAUSE 0x00008000 878 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 879 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 880 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 881 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 882 #define AUTONEG_CODE_FAULT_MASK 0x00000030 883 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 884 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 885 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 886 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 887 888 /* 889 * SerDes Registers (5703S/5704S only) 890 */ 891 #define SERDES_CONTROL_REG 0x0590 892 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 893 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 894 #define SERDES_CONTROL_TX_DISABLE 0x00004000 895 #define SERDES_STATUS_REG 0x0594 896 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 897 #define SERDES_STATUS_RXSTAT 0x000000ff 898 899 /* 900 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 901 */ 902 #define STAT_IFHCOUT_OCTETS_REG 0x0800 903 #define STAT_ETHER_COLLIS_REG 0x0808 904 #define STAT_OUTXON_SENT_REG 0x080c 905 #define STAT_OUTXOFF_SENT_REG 0x0810 906 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 907 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 908 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 909 #define STAT_DOT3_DEFERED_TX_REG 0x0824 910 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 911 #define STAT_DOT3_LATE_COLLI_REG 0x0830 912 #define STAT_IFHCOUT_UPKGS_REG 0x086c 913 #define STAT_IFHCOUT_MPKGS_REG 0x0870 914 #define STAT_IFHCOUT_BPKGS_REG 0x0874 915 916 #define STAT_IFHCIN_OCTETS_REG 0x0880 917 #define STAT_ETHER_FRAGMENT_REG 0x0888 918 #define STAT_IFHCIN_UPKGS_REG 0x088c 919 #define STAT_IFHCIN_MPKGS_REG 0x0890 920 #define STAT_IFHCIN_BPKGS_REG 0x0894 921 922 #define STAT_DOT3_FCS_ERR_REG 0x0898 923 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 924 #define STAT_XON_PAUSE_RX_REG 0x08a0 925 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 926 #define STAT_MAC_CTRL_RX_REG 0x08a8 927 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 928 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 929 #define STAT_ETHER_JABBERS_REG 0x08b4 930 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 931 #define SIZE_OF_STATISTIC_REG 0x1B 932 /* 933 * Send Data Initiator Registers 934 */ 935 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 936 #define SEND_INIT_STATS_ZERO 0x00000010 937 #define SEND_INIT_STATS_FLUSH 0x00000008 938 #define SEND_INIT_STATS_CLEAR 0x00000004 939 #define SEND_INIT_STATS_FASTER 0x00000002 940 #define SEND_INIT_STATS_ENABLE 0x00000001 941 942 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 943 944 /* 945 * Send Buffer Descriptor Selector Control Registers 946 */ 947 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 948 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 949 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 950 951 /* 952 * Receive List Placement Registers 953 */ 954 #define RCV_LP_CONFIG_REG 0x2010 955 #define RCV_LP_CONFIG_DEFAULT 0x00000009 956 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 957 958 #define RCV_LP_STATS_CONTROL_REG 0x2014 959 #define RCV_LP_STATS_ZERO 0x00000010 960 #define RCV_LP_STATS_FLUSH 0x00000008 961 #define RCV_LP_STATS_CLEAR 0x00000004 962 #define RCV_LP_STATS_FASTER 0x00000002 963 #define RCV_LP_STATS_ENABLE 0x00000001 964 965 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 966 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 967 968 /* 969 * Receive Data & BD Initiator Registers 970 */ 971 #define RCV_INITIATOR_STATUS_REG 0x2404 972 973 /* 974 * Receive Buffer Descriptor Ring Control Block Registers 975 * NB: sixteen bytes (128 bits) each 976 */ 977 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 978 #define STD_RCV_BD_RING_RCB_REG 0x2450 979 #define MINI_RCV_BD_RING_RCB_REG 0x2460 980 981 /* 982 * Receive Buffer Descriptor Ring Replenish Threshold Registers 983 */ 984 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 985 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 986 #define STD_RCV_BD_REPLENISH_REG 0x2c18 987 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 988 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 989 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 990 991 /* 992 * Host Coalescing Engine Control Registers 993 */ 994 #define RCV_COALESCE_TICKS_REG 0x3c08 995 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 996 #define SEND_COALESCE_TICKS_REG 0x3c0c 997 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 998 #define RCV_COALESCE_MAX_BD_REG 0x3c10 999 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1000 #define SEND_COALESCE_MAX_BD_REG 0x3c14 1001 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 1002 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 1003 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1004 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 1005 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 1006 #define RCV_COALESCE_INT_BD_REG 0x3c20 1007 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1008 #define SEND_COALESCE_INT_BD_REG 0x3c24 1009 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 1010 #define STATISTICS_TICKS_REG 0x3c28 1011 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 1012 #define STATISTICS_HOST_ADDR_REG 0x3c30 1013 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 1014 #define STATISTICS_BASE_ADDR_REG 0x3c40 1015 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 1016 #define FLOW_ATTN_REG 0x3c48 1017 1018 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 1019 #define NIC_STD_RECV_INDEX_REG 0x3c54 1020 #define NIC_MINI_RECV_INDEX_REG 0x3c58 1021 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 1022 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 1023 1024 /* 1025 * Mbuf Pool Initialisation & Watermark Registers 1026 * 1027 * There are some conflicts in the PRM; compare the recommendations 1028 * on pp. 115, 236, and 339. The values here were recommended by 1029 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1030 */ 1031 #define BUFFER_MANAGER_STATUS_REG 0x4404 1032 #define MBUF_POOL_BASE_REG 0x4408 1033 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1034 #define MBUF_POOL_BASE_5721 0x00010000 1035 #define MBUF_POOL_BASE_5704 0x00010000 1036 #define MBUF_POOL_BASE_5705 0x00010000 1037 #define MBUF_POOL_LENGTH_REG 0x440c 1038 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1039 #define MBUF_POOL_LENGTH_5704 0x00010000 1040 #define MBUF_POOL_LENGTH_5705 0x00008000 1041 #define MBUF_POOL_LENGTH_5721 0x00008000 1042 #define RDMA_MBUF_LOWAT_REG 0x4410 1043 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1044 #define RDMA_MBUF_LOWAT_5705 0x00000000 1045 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1046 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1047 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1048 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1049 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1050 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1051 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1052 #define MBUF_HIWAT_REG 0x4418 1053 #define MBUF_HIWAT_DEFAULT 0x00000060 1054 #define MBUF_HIWAT_5705 0x00000060 1055 #define MBUF_HIWAT_JUMBO 0x0000017c 1056 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1057 1058 /* 1059 * DMA Descriptor Pool Initialisation & Watermark Registers 1060 */ 1061 #define DMAD_POOL_BASE_REG 0x442c 1062 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1063 #define DMAD_POOL_LENGTH_REG 0x4430 1064 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1065 #define DMAD_POOL_LOWAT_REG 0x4434 1066 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1067 #define DMAD_POOL_HIWAT_REG 0x4438 1068 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1069 1070 /* 1071 * More threshold/watermark registers ... 1072 */ 1073 #define RECV_FLOW_THRESHOLD_REG 0x4458 1074 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1075 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1076 1077 /* 1078 * Read/Write DMA Status Registers 1079 */ 1080 #define READ_DMA_STATUS_REG 0x4804 1081 #define WRITE_DMA_STATUS_REG 0x4c04 1082 1083 /* 1084 * RX/TX RISC Registers 1085 */ 1086 #define RX_RISC_MODE_REG 0x5000 1087 #define RX_RISC_STATE_REG 0x5004 1088 #define RX_RISC_PC_REG 0x501c 1089 #define TX_RISC_MODE_REG 0x5400 1090 #define TX_RISC_STATE_REG 0x5404 1091 #define TX_RISC_PC_REG 0x541c 1092 1093 #define FTQ_RESET_REG 0x5c00 1094 1095 #define MSI_MODE_REG 0x6000 1096 #define MSI_PRI_HIGHEST 0xc0000000 1097 #define MSI_MSI_ENABLE 0x00000002 1098 #define MSI_ERROR_ATTENTION 0x0000001c 1099 1100 #define MSI_STATUS_REG 0x6004 1101 1102 #define MODE_CONTROL_REG 0x6800 1103 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1104 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1105 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1106 #define MODE_INT_ON_DMA_ATTN 0x08000000 1107 #define MODE_INT_ON_MAC_ATTN 0x04000000 1108 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1109 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1110 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1111 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1112 #define MODE_HOST_SEND_BDS 0x00020000 1113 #define MODE_HOST_STACK_UP 0x00010000 1114 #define MODE_FORCE_32_BIT_PCI 0x00008000 1115 #define MODE_NO_INT_ON_RECV 0x00004000 1116 #define MODE_NO_INT_ON_SEND 0x00002000 1117 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1118 #define MODE_NO_CRC 0x00000400 1119 #define MODE_NO_FRAME_CRACKING 0x00000200 1120 #define MODE_WORD_SWAP_FRAME 0x00000020 1121 #define MODE_BYTE_SWAP_FRAME 0x00000010 1122 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1123 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1124 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1125 1126 /* 1127 * Miscellaneous Configuration Register 1128 * 1129 * This contains various bits relating to power control (which differ 1130 * among different members of the chip family), but the important bits 1131 * for our purposes are the RESET bit and the Timer Prescaler field. 1132 * 1133 * The RESET bit in this register serves to reset the whole chip, even 1134 * including the PCI interface(!) Once it's set, the chip will not 1135 * respond to ANY accesses -- not even CONFIG space -- until the reset 1136 * completes internally. According to the PRM, this should take less 1137 * than 100us. Any access during this period will get a bus error. 1138 * 1139 * The Timer Prescaler field must be programmed so that the timer period 1140 * is as near as possible to 1us. The value in this field should be 1141 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1142 * the Core Clock should always be 66MHz (independently of the bus speed, 1143 * at least for PCI rather than PCI-X), so this register must be set to 1144 * the value 0x82 ((66-1) << 1). 1145 */ 1146 #define CORE_CLOCK_MHZ 66 1147 #define MISC_CONFIG_REG 0x6804 1148 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1149 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1150 #define MISC_CONFIG_POWERDOWN 0x00100000 1151 #define MISC_CONFIG_POWER_STATE 0x00060000 1152 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1153 #define MISC_CONFIG_RESET_BIT 0x00000001 1154 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1155 1156 /* 1157 * Miscellaneous Local Control Register (MLCR) 1158 */ 1159 #define MISC_LOCAL_CONTROL_REG 0x6808 1160 #define MLCR_PCI_CTRL_SELECT 0x10000000 1161 #define MLCR_LEGACY_PCI_MODE 0x08000000 1162 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1163 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1164 #define MLCR_SSRAM_TYPE 0x00400000 1165 #define MLCR_BANK_SELECT 0x00200000 1166 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1167 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1168 1169 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1170 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1171 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1172 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1173 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1174 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1175 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1176 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1177 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1178 1179 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1180 #define MLCR_SET_INT 0x00000004 /* W/O */ 1181 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1182 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1183 1184 /* 1185 * This value defines all GPIO bits as INPUTS, but sets their default 1186 * values as outputs to HIGH, on the assumption that external circuits 1187 * (if any) will probably be active-LOW with passive pullups. 1188 * 1189 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1190 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1191 * enable writing. Otherwise, the SEEPROM is protected. 1192 */ 1193 #define MLCR_DEFAULT 0x0101c000 1194 #define MLCR_DEFAULT_5714 0x1901c000 1195 1196 /* 1197 * Serial EEPROM Data/Address Registers (auto-access mode) 1198 */ 1199 #define SERIAL_EEPROM_DATA_REG 0x683c 1200 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1201 #define SEEPROM_ACCESS_READ 0x80000000 1202 #define SEEPROM_ACCESS_WRITE 0x00000000 1203 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1204 #define SEEPROM_ACCESS_RESET 0x20000000 1205 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1206 #define SEEPROM_ACCESS_START 0x02000000 1207 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1208 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1209 1210 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1211 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1212 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1213 1214 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1215 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1216 1217 /* 1218 * "Linearised" address mask, treating multiple devices as consecutive 1219 */ 1220 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1221 1222 /* 1223 * Non-Volatile Memory Interface Registers 1224 * Note: on chips that support the flash interface (5702+), flash is the 1225 * default and the legacy seeprom interface must be explicitly enabled 1226 * if required. On older chips (5700/01), SEEPROM is the default (and 1227 * only) non-volatile memory available, and these registers don't exist! 1228 */ 1229 #define NVM_FLASH_CMD_REG 0x7000 1230 #define NVM_FLASH_CMD_LAST 0x00000100 1231 #define NVM_FLASH_CMD_FIRST 0x00000080 1232 #define NVM_FLASH_CMD_RD 0x00000000 1233 #define NVM_FLASH_CMD_WR 0x00000020 1234 #define NVM_FLASH_CMD_DOIT 0x00000010 1235 #define NVM_FLASH_CMD_DONE 0x00000008 1236 1237 #define NVM_FLASH_WRITE_REG 0x7008 1238 #define NVM_FLASH_READ_REG 0x7010 1239 1240 #define NVM_FLASH_ADDR_REG 0x700c 1241 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1242 1243 #define NVM_CONFIG1_REG 0x7014 1244 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1245 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1246 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1247 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1248 #define NVM_CFG1_FLASH_MODE 0x00000001 1249 1250 #define NVM_SW_ARBITRATION_REG 0x7020 1251 #define NVM_READ_REQ3 0X00008000 1252 #define NVM_READ_REQ2 0X00004000 1253 #define NVM_READ_REQ1 0X00002000 1254 #define NVM_READ_REQ0 0X00001000 1255 #define NVM_WON_REQ3 0X00000800 1256 #define NVM_WON_REQ2 0X00000400 1257 #define NVM_WON_REQ1 0X00000200 1258 #define NVM_WON_REQ0 0X00000100 1259 #define NVM_RESET_REQ3 0X00000080 1260 #define NVM_RESET_REQ2 0X00000040 1261 #define NVM_RESET_REQ1 0X00000020 1262 #define NVM_RESET_REQ0 0X00000010 1263 #define NVM_SET_REQ3 0X00000008 1264 #define NVM_SET_REQ2 0X00000004 1265 #define NVM_SET_REQ1 0X00000002 1266 #define NVM_SET_REQ0 0X00000001 1267 1268 /* 1269 * NVM access register 1270 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1271 * and BCM5715 only. 1272 */ 1273 #define NVM_ACCESS_REG 0X7024 1274 #define NVM_WRITE_ENABLE 0X00000002 1275 #define NVM_ACCESS_ENABLE 0X00000001 1276 1277 /* 1278 * TLP Control Register 1279 * Applicable to BCM5721 and BCM5751 only 1280 */ 1281 #define TLP_CONTROL_REG 0x7c00 1282 #define TLP_DATA_FIFO_PROTECT 0x02000000 1283 1284 /* 1285 * PHY Test Control Register 1286 * Applicable to BCM5721 and BCM5751 only 1287 */ 1288 #define PHY_TEST_CTRL_REG 0x7e2c 1289 #define PHY_PCIE_SCRAM_MODE 0x20 1290 #define PHY_PCIE_LTASS_MODE 0x40 1291 1292 /* 1293 * The internal firmware expects a certain layout of the non-volatile 1294 * memory (if fitted), and will check for it during startup, and use the 1295 * contents to initialise various internal parameters if it looks good. 1296 * 1297 * The offsets and field definitions below refer to where to find some 1298 * important values, and how to interpret them ... 1299 */ 1300 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1301 1302 /* 1303 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1304 */ 1305 1306 #define MII_AN_LPNXTPG 8 1307 #define MII_1000BASE_T_CONTROL 9 1308 #define MII_1000BASE_T_STATUS 10 1309 #define MII_IEEE_EXT_STATUS 15 1310 1311 /* 1312 * New bits in the MII_CONTROL register 1313 */ 1314 #define MII_CONTROL_1000MB 0x0040 1315 1316 /* 1317 * New bits in the MII_AN_ADVERT register 1318 */ 1319 #define MII_ABILITY_ASYM_PAUSE 0x0800 1320 #define MII_ABILITY_PAUSE 0x0400 1321 1322 /* 1323 * Values for the <selector> field of the MII_AN_ADVERT register 1324 */ 1325 #define MII_AN_SELECTOR_8023 0x0001 1326 1327 /* 1328 * Bits in the MII_1000BASE_T_CONTROL register 1329 * 1330 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1331 * (otherwise, roles are automatically negotiated). When this bit is set, 1332 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1333 */ 1334 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1335 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1336 #define MII_1000BT_CTL_ADV_FDX 0x0200 1337 #define MII_1000BT_CTL_ADV_HDX 0x0100 1338 1339 /* 1340 * Bits in the MII_1000BASE_T_STATUS register 1341 */ 1342 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1343 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1344 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1345 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1346 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1347 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1348 1349 /* 1350 * Vendor-specific MII registers 1351 */ 1352 #define MII_EXT_CONTROL MII_VENDOR(0) 1353 #define MII_EXT_STATUS MII_VENDOR(1) 1354 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1355 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1356 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1357 #define MII_AUX_CONTROL MII_VENDOR(8) 1358 #define MII_AUX_STATUS MII_VENDOR(9) 1359 #define MII_INTR_STATUS MII_VENDOR(10) 1360 #define MII_INTR_MASK MII_VENDOR(11) 1361 #define MII_HCD_STATUS MII_VENDOR(13) 1362 1363 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1364 1365 /* 1366 * Bits in the MII_EXT_CONTROL register 1367 */ 1368 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1369 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1370 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1371 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1372 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1373 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1374 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1375 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1376 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1377 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1378 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1379 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1380 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1381 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1382 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1383 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1384 1385 /* 1386 * Bits in the MII_EXT_STATUS register 1387 */ 1388 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1389 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1390 #define MII_EXT_STAT_MDIX_STATE 0x2000 1391 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1392 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1393 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1394 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1395 #define MII_EXT_STAT_LINK_STATUS 0x0100 1396 #define MII_EXT_STAT_CRC_ERROR 0x0080 1397 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1398 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1399 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1400 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1401 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1402 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1403 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1404 1405 /* 1406 * The AUX CONTROL register is seriously weird! 1407 * 1408 * It hides (up to) eight 'shadow' registers. When writing, which one 1409 * of them is written is determined by the low-order bits of the data 1410 * written(!), but when reading, which one is read is determined by the 1411 * value previously written to (part of) one of the shadow registers!!! 1412 */ 1413 1414 /* 1415 * Shadow register numbers 1416 */ 1417 #define MII_AUX_CTRL_NORMAL 0 1418 #define MII_AUX_CTRL_10BASE_T 1 1419 #define MII_AUX_CTRL_POWER 2 1420 #define MII_AUX_CTRL_TEST_1 4 1421 #define MII_AUX_CTRL_MISC 7 1422 1423 /* 1424 * Selected bits in some of the shadow registers ... 1425 */ 1426 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1427 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1428 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1429 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1430 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1431 1432 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1433 1434 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1435 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1436 1437 /* 1438 * Write this value to the AUX control register 1439 * to select which shadow register will be read 1440 */ 1441 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1442 1443 /* 1444 * Bits in the MII_AUX_STATUS register 1445 */ 1446 #define MII_AUX_STATUS_MODE_MASK 0x0700 1447 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1448 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1449 #define MII_AUX_STATUS_MODE_100_F 0x0500 1450 #define MII_AUX_STATUS_MODE_100_4 0x0400 1451 #define MII_AUX_STATUS_MODE_100_H 0x0300 1452 #define MII_AUX_STATUS_MODE_10_F 0x0200 1453 #define MII_AUX_STATUS_MODE_10_H 0x0100 1454 #define MII_AUX_STATUS_MODE_NONE 0x0000 1455 #define MII_AUX_STATUS_MODE_SHIFT 8 1456 1457 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1458 #define MII_AUX_STATUS_REM_FAULT 0x0040 1459 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1460 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1461 1462 #define MII_AUX_STATUS_LINKUP 0x0004 1463 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1464 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1465 1466 /* 1467 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1468 */ 1469 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1470 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1471 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1472 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1473 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1474 1475 1476 /* 1477 * Third section: 1478 * Hardware-defined data structures 1479 * 1480 * Note that the chip is naturally BIG-endian, so, for a big-endian 1481 * host, the structures defined below match those described in the PRM. 1482 * For little-endian hosts, some structures have to be swapped around. 1483 */ 1484 1485 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1486 #error Host endianness not defined 1487 #endif 1488 1489 /* 1490 * Architectural constants: absolute maximum numbers of each type of ring 1491 */ 1492 #ifdef BGE_EXT_MEM 1493 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1494 #else 1495 #define BGE_SEND_RINGS_MAX 4 1496 #endif 1497 #define BGE_SEND_RINGS_MAX_5705 1 1498 #define BGE_RECV_RINGS_MAX 16 1499 #define BGE_RECV_RINGS_MAX_5705 1 1500 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1501 /* only with ext mem) */ 1502 1503 #define BGE_SEND_SLOTS_MAX 512 1504 #define BGE_STD_SLOTS_MAX 512 1505 #define BGE_JUMBO_SLOTS_MAX 256 1506 #define BGE_MINI_SLOTS_MAX 1024 1507 #define BGE_RECV_SLOTS_MAX 2048 1508 #define BGE_RECV_SLOTS_5705 512 1509 #define BGE_RECV_SLOTS_5782 512 1510 #define BGE_RECV_SLOTS_5721 512 1511 1512 /* 1513 * Hardware-defined Ring Control Block 1514 */ 1515 typedef struct { 1516 uint64_t host_ring_addr; 1517 #ifdef _BIG_ENDIAN 1518 uint16_t max_len; 1519 uint16_t flags; 1520 uint32_t nic_ring_addr; 1521 #else 1522 uint32_t nic_ring_addr; 1523 uint16_t flags; 1524 uint16_t max_len; 1525 #endif /* _BIG_ENDIAN */ 1526 } bge_rcb_t; 1527 1528 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1529 #define RCB_FLAG_RING_DISABLED 0x0002 1530 1531 /* 1532 * Hardware-defined Send Buffer Descriptor 1533 */ 1534 typedef struct { 1535 uint64_t host_buf_addr; 1536 #ifdef _BIG_ENDIAN 1537 uint16_t len; 1538 uint16_t flags; 1539 uint16_t reserved; 1540 uint16_t vlan_tci; 1541 #else 1542 uint16_t vlan_tci; 1543 uint16_t reserved; 1544 uint16_t flags; 1545 uint16_t len; 1546 #endif /* _BIG_ENDIAN */ 1547 } bge_sbd_t; 1548 1549 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1550 #define SBD_FLAG_IP_CKSUM 0x0002 1551 #define SBD_FLAG_PACKET_END 0x0004 1552 #define SBD_FLAG_IP_FRAG 0x0008 1553 #define SBD_FLAG_IP_FRAG_END 0x0010 1554 1555 #define SBD_FLAG_VLAN_TAG 0x0040 1556 #define SBD_FLAG_COAL_NOW 0x0080 1557 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1558 #define SBD_FLAG_CPU_POST_DMA 0x0200 1559 1560 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1561 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1562 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1563 1564 /* 1565 * Hardware-defined Receive Buffer Descriptor 1566 */ 1567 typedef struct { 1568 uint64_t host_buf_addr; 1569 #ifdef _BIG_ENDIAN 1570 uint16_t index; 1571 uint16_t len; 1572 uint16_t type; 1573 uint16_t flags; 1574 uint16_t ip_cksum; 1575 uint16_t tcp_udp_cksum; 1576 uint16_t error_flag; 1577 uint16_t vlan_tci; 1578 uint32_t reserved; 1579 uint32_t opaque; 1580 #else 1581 uint16_t flags; 1582 uint16_t type; 1583 uint16_t len; 1584 uint16_t index; 1585 uint16_t vlan_tci; 1586 uint16_t error_flag; 1587 uint16_t tcp_udp_cksum; 1588 uint16_t ip_cksum; 1589 uint32_t opaque; 1590 uint32_t reserved; 1591 #endif /* _BIG_ENDIAN */ 1592 } bge_rbd_t; 1593 1594 #define RBD_FLAG_STD_RING 0x0000 1595 #define RBD_FLAG_PACKET_END 0x0004 1596 1597 #define RBD_FLAG_JUMBO_RING 0x0020 1598 #define RBD_FLAG_VLAN_TAG 0x0040 1599 1600 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1601 #define RBD_FLAG_MINI_RING 0x0800 1602 #define RBD_FLAG_IP_CHECKSUM 0x1000 1603 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1604 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1605 1606 #define RBD_FLAG_DEFAULT 0x0000 1607 1608 #define RBD_ERROR_BAD_CRC 0x00010000 1609 #define RBD_ERROR_COLL_DETECT 0x00020000 1610 #define RBD_ERROR_LINK_LOST 0x00040000 1611 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1612 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1613 #define RBD_ERROR_MAC_ABORT 0x00200000 1614 #define RBD_ERROR_LEN_LESS_64 0x00400000 1615 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1616 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1617 1618 /* 1619 * Hardware-defined Status Block,Size of status block 1620 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1621 * alignment.For BCM5705/5788/5721/5751/5752/5714 1622 * and 5715,there is only 1 recv and send ring index,but 1623 * driver defined 16 indexs here,please pay attention only 1624 * one ring is enabled in these chipsets. 1625 */ 1626 typedef struct { 1627 uint64_t flags_n_tag; 1628 uint16_t buff_cons_index[4]; 1629 struct { 1630 #ifdef _BIG_ENDIAN 1631 uint16_t send_cons_index; 1632 uint16_t recv_prod_index; 1633 #else 1634 uint16_t recv_prod_index; 1635 uint16_t send_cons_index; 1636 #endif /* _BIG_ENDIAN */ 1637 } index[16]; 1638 } bge_status_t; 1639 1640 /* 1641 * Hardware-defined Receive BD Rule 1642 */ 1643 typedef struct { 1644 uint32_t control; 1645 uint32_t mask_value; 1646 } bge_recv_rule_t; 1647 1648 /* 1649 * Indexes into the <buff_cons_index> array 1650 */ 1651 #ifdef _BIG_ENDIAN 1652 #define STATUS_STD_BUFF_CONS_INDEX 0 1653 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1654 #define STATUS_MINI_BUFF_CONS_INDEX 3 1655 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1656 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1657 #else 1658 #define STATUS_STD_BUFF_CONS_INDEX 3 1659 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1660 #define STATUS_MINI_BUFF_CONS_INDEX 0 1661 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1662 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1663 #endif /* _BIG_ENDIAN */ 1664 1665 /* 1666 * Bits in the <flags_n_tag> word 1667 */ 1668 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1669 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1670 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1671 #define STATUS_TAG_MASK 0x00000000000000FFull 1672 1673 /* 1674 * The tag from the status block is fed back to Interrupt Mailbox 0 1675 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1676 * lets the chip know what updates have been processed, so it can 1677 * reassert its interrupt if more updates have occurred since. 1678 * 1679 * These macros extract the tag from the <flags_n_tag> word, shift 1680 * it to the proper position in the Mailbox register, and provide 1681 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1682 * or enable interrupts 1683 */ 1684 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1685 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1686 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1687 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1688 1689 /* 1690 * Hardware-defined Statistics Block Offsets 1691 * 1692 * These are given in the manual as addresses in NIC memory, starting 1693 * from the NIC statistics area base address of 0x300; but here we 1694 * convert them into indexes into an array of (uint64_t)s, so we can 1695 * use them directly for accessing the copy of the statistics block 1696 * that the chip DMAs into main memory ... 1697 */ 1698 1699 #define KS_BASE 0x300 1700 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1701 1702 typedef enum { 1703 KS_ifHCInOctets = KS_ADDR(0x400), 1704 KS_etherStatsFragments = KS_ADDR(0x410), 1705 KS_ifHCInUcastPkts, 1706 KS_ifHCInMulticastPkts, 1707 KS_ifHCInBroadcastPkts, 1708 KS_dot3StatsFCSErrors, 1709 KS_dot3StatsAlignmentErrors, 1710 KS_xonPauseFramesReceived, 1711 KS_xoffPauseFramesReceived, 1712 KS_macControlFramesReceived, 1713 KS_xoffStateEntered, 1714 KS_dot3StatsFrameTooLongs, 1715 KS_etherStatsJabbers, 1716 KS_etherStatsUndersizePkts, 1717 KS_inRangeLengthError, 1718 KS_outRangeLengthError, 1719 KS_etherStatsPkts64Octets, 1720 KS_etherStatsPkts65to127Octets, 1721 KS_etherStatsPkts128to255Octets, 1722 KS_etherStatsPkts256to511Octets, 1723 KS_etherStatsPkts512to1023Octets, 1724 KS_etherStatsPkts1024to1518Octets, 1725 KS_etherStatsPkts1519to2047Octets, 1726 KS_etherStatsPkts2048to4095Octets, 1727 KS_etherStatsPkts4096to8191Octets, 1728 KS_etherStatsPkts8192to9022Octets, 1729 1730 KS_ifHCOutOctets = KS_ADDR(0x600), 1731 KS_etherStatsCollisions = KS_ADDR(0x610), 1732 KS_outXonSent, 1733 KS_outXoffSent, 1734 KS_flowControlDone, 1735 KS_dot3StatsInternalMacTransmitErrors, 1736 KS_dot3StatsSingleCollisionFrames, 1737 KS_dot3StatsMultipleCollisionFrames, 1738 KS_dot3StatsDeferredTransmissions, 1739 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1740 KS_dot3StatsLateCollisions, 1741 KS_dot3Collided2Times, 1742 KS_dot3Collided3Times, 1743 KS_dot3Collided4Times, 1744 KS_dot3Collided5Times, 1745 KS_dot3Collided6Times, 1746 KS_dot3Collided7Times, 1747 KS_dot3Collided8Times, 1748 KS_dot3Collided9Times, 1749 KS_dot3Collided10Times, 1750 KS_dot3Collided11Times, 1751 KS_dot3Collided12Times, 1752 KS_dot3Collided13Times, 1753 KS_dot3Collided14Times, 1754 KS_dot3Collided15Times, 1755 KS_ifHCOutUcastPkts, 1756 KS_ifHCOutMulticastPkts, 1757 KS_ifHCOutBroadcastPkts, 1758 KS_dot3StatsCarrierSenseErrors, 1759 KS_ifOutDiscards, 1760 KS_ifOutErrors, 1761 1762 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1763 KS_COSIfHCInPkts_2, 1764 KS_COSIfHCInPkts_3, 1765 KS_COSIfHCInPkts_4, 1766 KS_COSIfHCInPkts_5, 1767 KS_COSIfHCInPkts_6, 1768 KS_COSIfHCInPkts_7, 1769 KS_COSIfHCInPkts_8, 1770 KS_COSIfHCInPkts_9, 1771 KS_COSIfHCInPkts_10, 1772 KS_COSIfHCInPkts_11, 1773 KS_COSIfHCInPkts_12, 1774 KS_COSIfHCInPkts_13, 1775 KS_COSIfHCInPkts_14, 1776 KS_COSIfHCInPkts_15, 1777 KS_COSIfHCInPkts_16, 1778 KS_COSFramesDroppedDueToFilters, 1779 KS_nicDmaWriteQueueFull, 1780 KS_nicDmaWriteHighPriQueueFull, 1781 KS_nicNoMoreRxBDs, 1782 KS_ifInDiscards, 1783 KS_ifInErrors, 1784 KS_nicRecvThresholdHit, 1785 1786 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1787 KS_COSIfHCOutPkts_2, 1788 KS_COSIfHCOutPkts_3, 1789 KS_COSIfHCOutPkts_4, 1790 KS_COSIfHCOutPkts_5, 1791 KS_COSIfHCOutPkts_6, 1792 KS_COSIfHCOutPkts_7, 1793 KS_COSIfHCOutPkts_8, 1794 KS_COSIfHCOutPkts_9, 1795 KS_COSIfHCOutPkts_10, 1796 KS_COSIfHCOutPkts_11, 1797 KS_COSIfHCOutPkts_12, 1798 KS_COSIfHCOutPkts_13, 1799 KS_COSIfHCOutPkts_14, 1800 KS_COSIfHCOutPkts_15, 1801 KS_COSIfHCOutPkts_16, 1802 KS_nicDmaReadQueueFull, 1803 KS_nicDmaReadHighPriQueueFull, 1804 KS_nicSendDataCompQueueFull, 1805 KS_nicRingSetSendProdIndex, 1806 KS_nicRingStatusUpdate, 1807 KS_nicInterrupts, 1808 KS_nicAvoidedInterrupts, 1809 KS_nicSendThresholdHit, 1810 1811 KS_STATS_SIZE = KS_ADDR(0xb00) 1812 } bge_stats_offset_t; 1813 1814 /* 1815 * Hardware-defined Statistics Block 1816 * 1817 * Another view of the statistic block, as a array and a structure ... 1818 */ 1819 1820 typedef union { 1821 uint64_t a[KS_STATS_SIZE]; 1822 struct { 1823 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1824 1825 uint64_t ifHCInOctets; /* 0x0400 */ 1826 uint64_t spare2[1]; 1827 uint64_t etherStatsFragments; 1828 uint64_t ifHCInUcastPkts; 1829 uint64_t ifHCInMulticastPkts; 1830 uint64_t ifHCInBroadcastPkts; 1831 uint64_t dot3StatsFCSErrors; 1832 uint64_t dot3StatsAlignmentErrors; 1833 uint64_t xonPauseFramesReceived; 1834 uint64_t xoffPauseFramesReceived; 1835 uint64_t macControlFramesReceived; 1836 uint64_t xoffStateEntered; 1837 uint64_t dot3StatsFrameTooLongs; 1838 uint64_t etherStatsJabbers; 1839 uint64_t etherStatsUndersizePkts; 1840 uint64_t inRangeLengthError; 1841 uint64_t outRangeLengthError; 1842 uint64_t etherStatsPkts64Octets; 1843 uint64_t etherStatsPkts65to127Octets; 1844 uint64_t etherStatsPkts128to255Octets; 1845 uint64_t etherStatsPkts256to511Octets; 1846 uint64_t etherStatsPkts512to1023Octets; 1847 uint64_t etherStatsPkts1024to1518Octets; 1848 uint64_t etherStatsPkts1519to2047Octets; 1849 uint64_t etherStatsPkts2048to4095Octets; 1850 uint64_t etherStatsPkts4096to8191Octets; 1851 uint64_t etherStatsPkts8192to9022Octets; 1852 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1853 1854 uint64_t ifHCOutOctets; /* 0x0600 */ 1855 uint64_t spare4[1]; 1856 uint64_t etherStatsCollisions; 1857 uint64_t outXonSent; 1858 uint64_t outXoffSent; 1859 uint64_t flowControlDone; 1860 uint64_t dot3StatsInternalMacTransmitErrors; 1861 uint64_t dot3StatsSingleCollisionFrames; 1862 uint64_t dot3StatsMultipleCollisionFrames; 1863 uint64_t dot3StatsDeferredTransmissions; 1864 uint64_t spare5[1]; 1865 uint64_t dot3StatsExcessiveCollisions; 1866 uint64_t dot3StatsLateCollisions; 1867 uint64_t dot3Collided2Times; 1868 uint64_t dot3Collided3Times; 1869 uint64_t dot3Collided4Times; 1870 uint64_t dot3Collided5Times; 1871 uint64_t dot3Collided6Times; 1872 uint64_t dot3Collided7Times; 1873 uint64_t dot3Collided8Times; 1874 uint64_t dot3Collided9Times; 1875 uint64_t dot3Collided10Times; 1876 uint64_t dot3Collided11Times; 1877 uint64_t dot3Collided12Times; 1878 uint64_t dot3Collided13Times; 1879 uint64_t dot3Collided14Times; 1880 uint64_t dot3Collided15Times; 1881 uint64_t ifHCOutUcastPkts; 1882 uint64_t ifHCOutMulticastPkts; 1883 uint64_t ifHCOutBroadcastPkts; 1884 uint64_t dot3StatsCarrierSenseErrors; 1885 uint64_t ifOutDiscards; 1886 uint64_t ifOutErrors; 1887 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1888 1889 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1890 uint64_t COSFramesDroppedDueToFilters; 1891 uint64_t nicDmaWriteQueueFull; 1892 uint64_t nicDmaWriteHighPriQueueFull; 1893 uint64_t nicNoMoreRxBDs; 1894 uint64_t ifInDiscards; 1895 uint64_t ifInErrors; 1896 uint64_t nicRecvThresholdHit; 1897 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1898 1899 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1900 uint64_t nicDmaReadQueueFull; 1901 uint64_t nicDmaReadHighPriQueueFull; 1902 uint64_t nicSendDataCompQueueFull; 1903 uint64_t nicRingSetSendProdIndex; 1904 uint64_t nicRingStatusUpdate; 1905 uint64_t nicInterrupts; 1906 uint64_t nicAvoidedInterrupts; 1907 uint64_t nicSendThresholdHit; 1908 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1909 } s; 1910 } bge_statistics_t; 1911 1912 #define KS_STAT_REG_SIZE (0x1B) 1913 #define KS_STAT_REG_BASE (0x800) 1914 1915 typedef struct { 1916 uint32_t ifHCOutOctets; 1917 uint32_t etherStatsCollisions; 1918 uint32_t outXonSent; 1919 uint32_t outXoffSent; 1920 uint32_t dot3StatsInternalMacTransmitErrors; 1921 uint32_t dot3StatsSingleCollisionFrames; 1922 uint32_t dot3StatsMultipleCollisionFrames; 1923 uint32_t dot3StatsDeferredTransmissions; 1924 uint32_t dot3StatsExcessiveCollisions; 1925 uint32_t dot3StatsLateCollisions; 1926 uint32_t ifHCOutUcastPkts; 1927 uint32_t ifHCOutMulticastPkts; 1928 uint32_t ifHCOutBroadcastPkts; 1929 uint32_t ifHCInOctets; 1930 uint32_t etherStatsFragments; 1931 uint32_t ifHCInUcastPkts; 1932 uint32_t ifHCInMulticastPkts; 1933 uint32_t ifHCInBroadcastPkts; 1934 uint32_t dot3StatsFCSErrors; 1935 uint32_t dot3StatsAlignmentErrors; 1936 uint32_t xonPauseFramesReceived; 1937 uint32_t xoffPauseFramesReceived; 1938 uint32_t macControlFramesReceived; 1939 uint32_t xoffStateEntered; 1940 uint32_t dot3StatsFrameTooLongs; 1941 uint32_t etherStatsJabbers; 1942 uint32_t etherStatsUndersizePkts; 1943 } bge_statistics_reg_t; 1944 1945 1946 #ifdef BGE_IPMI_ASF 1947 1948 /* 1949 * Device internal memory entries 1950 */ 1951 1952 #define BGE_FIRMWARE_MAILBOX 0x0b50 1953 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1954 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1955 1956 1957 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1958 #define BGE_NIC_DATA_SIG 0x4b657654 1959 1960 1961 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1962 1963 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1964 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1965 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1966 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1967 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1968 1969 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1970 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1971 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1972 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1973 1974 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1975 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1976 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1977 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1978 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1979 #define BGE_NIC_CFG_MINI_PCI 0x001000 1980 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1981 #define BGE_NIC_CFG_5753_12x12 0x100000 1982 1983 1984 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1985 1986 1987 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1988 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1989 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1990 1991 1992 #define BGE_CMD_MAILBOX 0x0b78 1993 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1994 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1995 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1996 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1997 1998 1999 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 2000 #define BGE_CMD_DATA_MAILBOX 0x0b80 2001 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 2002 2003 #define BGE_DRV_STATE_MAILBOX 0x0c04 2004 #define BGE_DRV_STATE_START 0x00000001 2005 #define BGE_DRV_STATE_START_DONE 0x80000001 2006 #define BGE_DRV_STATE_UNLOAD 0x00000002 2007 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 2008 #define BGE_DRV_STATE_WOL 0x00000003 2009 #define BGE_DRV_STATE_SUSPEND 0x00000004 2010 2011 2012 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 2013 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 2014 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 2015 2016 2017 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 2018 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 2019 2020 2021 /* 2022 * RX-RISC event register 2023 */ 2024 #define RX_RISC_EVENT_REG 0x6810 2025 #define RRER_ASF_EVENT 0x4000 2026 2027 #endif /* BGE_IPMI_ASF */ 2028 2029 #ifdef __cplusplus 2030 } 2031 #endif 2032 2033 #endif /* _BGE_HW_H */ 2034