1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/sysmacros.h> 31 #include <sys/sunddi.h> 32 #include <sys/esunddi.h> 33 #include <sys/platform_module.h> 34 #include <sys/errno.h> 35 #include <sys/lgrp.h> 36 #include <sys/memnode.h> 37 #include <sys/promif.h> 38 39 int (*p2get_mem_unum)(int, uint64_t, char *, int, int *); 40 41 void 42 startup_platform(void) 43 { 44 } 45 46 int 47 set_platform_tsb_spares() 48 { 49 return (0); 50 } 51 52 void 53 set_platform_defaults(void) 54 { 55 } 56 57 /* 58 * Definitions for accessing the pci config space of the isa node 59 * of Southbridge. 60 */ 61 #define SCHUMACHER_ISA_PATHNAME "/pci@1e,600000/isa@7" 62 static ddi_acc_handle_t isa_handle; /* handle for isa pci space */ 63 64 65 void 66 load_platform_drivers(void) 67 { 68 dev_info_t *dip; /* dip of the isa driver */ 69 70 /* 71 * Install 'us' driver. 72 */ 73 (void) i_ddi_attach_hw_nodes("us"); 74 75 /* 76 * mc-us3i must stay loaded for plat_get_mem_unum() 77 */ 78 if (i_ddi_attach_hw_nodes("mc-us3i") != DDI_SUCCESS) 79 cmn_err(CE_WARN, "mc-us3i driver failed to install"); 80 (void) ddi_hold_driver(ddi_name_to_major("mc-us3i")); 81 82 /* 83 * Install Isa driver. This is required for the southbridge IDE 84 * workaround - to reset the IDE channel during IDE bus reset. 85 * Panic the system in case ISA driver could not be loaded or 86 * any problem in accessing its pci config space. Since the register 87 * to reset the channel for IDE is in ISA config space!. 88 */ 89 90 dip = e_ddi_hold_devi_by_path(SCHUMACHER_ISA_PATHNAME, 0); 91 if (dip == NULL) { 92 cmn_err(CE_PANIC, "Could not install the isa driver\n"); 93 return; 94 } 95 96 if (pci_config_setup(dip, &isa_handle) != DDI_SUCCESS) { 97 cmn_err(CE_PANIC, "Could not get the config space of isa\n"); 98 return; 99 } 100 } 101 102 /* 103 * This routine provides a workaround for a bug in the SB chip which 104 * can cause data corruption. Will be invoked from the IDE HBA driver for 105 * Acer SouthBridge at the time of IDE bus reset. 106 */ 107 /*ARGSUSED*/ 108 int 109 plat_ide_chipreset(dev_info_t *dip, int chno) 110 { 111 uint8_t val; 112 int ret = DDI_SUCCESS; 113 114 if (isa_handle == NULL) { 115 return (DDI_FAILURE); 116 } 117 118 val = pci_config_get8(isa_handle, 0x58); 119 /* 120 * The dip passed as the argument is not used here. 121 * This will be needed for platforms which have multiple on-board SB, 122 * The dip passed will be used to match the corresponding ISA node. 123 */ 124 switch (chno) { 125 case 0: 126 /* 127 * First disable the primary channel then re-enable it. 128 * As per ALI no wait should be required in between have 129 * given 1ms delay in between to be on safer side. 130 * bit 2 of register 0x58 when 0 disable the channel 0. 131 * bit 2 of register 0x58 when 1 enables the channel 0. 132 */ 133 pci_config_put8(isa_handle, 0x58, val & 0xFB); 134 drv_usecwait(1000); 135 pci_config_put8(isa_handle, 0x58, val); 136 break; 137 case 1: 138 /* 139 * bit 3 of register 0x58 when 0 disable the channel 1. 140 * bit 3 of register 0x58 when 1 enables the channel 1. 141 */ 142 pci_config_put8(isa_handle, 0x58, val & 0xF7); 143 drv_usecwait(1000); 144 pci_config_put8(isa_handle, 0x58, val); 145 break; 146 default: 147 /* 148 * Unknown channel number passed. Return failure. 149 */ 150 ret = DDI_FAILURE; 151 } 152 153 return (ret); 154 } 155 156 157 /*ARGSUSED*/ 158 int 159 plat_cpu_poweron(struct cpu *cp) 160 { 161 return (ENOTSUP); /* not supported on this platform */ 162 } 163 164 /*ARGSUSED*/ 165 int 166 plat_cpu_poweroff(struct cpu *cp) 167 { 168 return (ENOTSUP); /* not supported on this platform */ 169 } 170 171 /*ARGSUSED*/ 172 void 173 plat_freelist_process(int mnode) 174 { 175 } 176 177 char *platform_module_list[] = { 178 (char *)0 179 }; 180 181 /*ARGSUSED*/ 182 void 183 plat_tod_fault(enum tod_fault_type tod_bad) 184 { 185 } 186 187 /*ARGSUSED*/ 188 int 189 plat_get_mem_unum(int synd_code, uint64_t flt_addr, int flt_bus_id, 190 int flt_in_memory, ushort_t flt_status, char *buf, int buflen, int *lenp) 191 { 192 if (flt_in_memory && (p2get_mem_unum != NULL)) 193 return (p2get_mem_unum(synd_code, P2ALIGN(flt_addr, 8), 194 buf, buflen, lenp)); 195 else 196 return (ENOTSUP); 197 } 198 199 /*ARGSUSED*/ 200 int 201 plat_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 202 { 203 if (snprintf(buf, buflen, "MB") >= buflen) { 204 return (ENOSPC); 205 } else { 206 *lenp = strlen(buf); 207 return (0); 208 } 209 } 210 211 /* 212 * Fiesta support for lgroups. 213 * 214 * On fiesta platform, an lgroup platform handle == CPU id 215 */ 216 217 /* 218 * Macro for extracting the CPU number from the CPU id 219 */ 220 #define CPUID_TO_LGRP(id) ((id) & 0x7) 221 #define SCHUMACHER_MC_SHIFT 36 222 223 /* 224 * Return the platform handle for the lgroup containing the given CPU 225 */ 226 lgrp_handle_t 227 plat_lgrp_cpu_to_hand(processorid_t id) 228 { 229 return (CPUID_TO_LGRP(id)); 230 } 231 232 /* 233 * Platform specific lgroup initialization 234 */ 235 void 236 plat_lgrp_init(void) 237 { 238 pnode_t curnode; 239 char tmp_name[MAXSYSNAME]; 240 int portid; 241 int cpucnt = 0; 242 int max_portid = -1; 243 extern uint32_t lgrp_expand_proc_thresh; 244 extern uint32_t lgrp_expand_proc_diff; 245 extern pgcnt_t lgrp_mem_free_thresh; 246 extern uint32_t lgrp_loadavg_tolerance; 247 extern uint32_t lgrp_loadavg_max_effect; 248 extern uint32_t lgrp_load_thresh; 249 extern lgrp_mem_policy_t lgrp_mem_policy_root; 250 251 /* 252 * Count the number of CPUs installed to determine if 253 * NUMA optimization should be enabled or not. 254 * 255 * All CPU nodes reside in the root node and have a 256 * device type "cpu". 257 */ 258 curnode = prom_rootnode(); 259 for (curnode = prom_childnode(curnode); curnode; 260 curnode = prom_nextnode(curnode)) { 261 bzero(tmp_name, MAXSYSNAME); 262 if (prom_getprop(curnode, OBP_NAME, (caddr_t)tmp_name) == -1 || 263 prom_getprop(curnode, OBP_DEVICETYPE, tmp_name) == -1 || 264 strcmp(tmp_name, "cpu") != 0) 265 continue; 266 267 cpucnt++; 268 if (prom_getprop(curnode, "portid", (caddr_t)&portid) != -1 && 269 portid > max_portid) 270 max_portid = portid; 271 } 272 if (cpucnt <= 1) 273 max_mem_nodes = 1; 274 else if (max_portid >= 0 && max_portid < MAX_MEM_NODES) 275 max_mem_nodes = max_portid + 1; 276 277 /* 278 * Set tuneables for fiesta architecture 279 * 280 * lgrp_expand_proc_thresh is the minimum load on the lgroups 281 * this process is currently running on before considering 282 * expanding threads to another lgroup. 283 * 284 * lgrp_expand_proc_diff determines how much less the remote lgroup 285 * must be loaded before expanding to it. 286 * 287 * Optimize for memory bandwidth by spreading multi-threaded 288 * program to different lgroups. 289 */ 290 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 291 lgrp_expand_proc_diff = lgrp_loadavg_max_effect / 2; 292 lgrp_loadavg_tolerance = lgrp_loadavg_max_effect / 2; 293 lgrp_mem_free_thresh = 1; /* home lgrp must have some memory */ 294 lgrp_expand_proc_thresh = lgrp_loadavg_max_effect - 1; 295 lgrp_mem_policy_root = LGRP_MEM_POLICY_NEXT; 296 lgrp_load_thresh = 0; 297 298 mem_node_pfn_shift = SCHUMACHER_MC_SHIFT - MMU_PAGESHIFT; 299 } 300 301 /* 302 * Return latency between "from" and "to" lgroups 303 * 304 * This latency number can only be used for relative comparison 305 * between lgroups on the running system, cannot be used across platforms, 306 * and may not reflect the actual latency. It is platform and implementation 307 * specific, so platform gets to decide its value. It would be nice if the 308 * number was at least proportional to make comparisons more meaningful though. 309 * NOTE: The numbers below are supposed to be load latencies for uncached 310 * memory divided by 10. 311 */ 312 int 313 plat_lgrp_latency(lgrp_handle_t from, lgrp_handle_t to) 314 { 315 /* 316 * Return remote latency when there are more than two lgroups 317 * (root and child) and getting latency between two different 318 * lgroups or root is involved 319 */ 320 if (lgrp_optimizations() && (from != to || 321 from == LGRP_DEFAULT_HANDLE || to == LGRP_DEFAULT_HANDLE)) 322 return (17); 323 else 324 return (12); 325 } 326 327 int 328 plat_pfn_to_mem_node(pfn_t pfn) 329 { 330 ASSERT(max_mem_nodes > 1); 331 return (pfn >> mem_node_pfn_shift); 332 } 333 334 /* 335 * Assign memnode to lgroups 336 */ 337 void 338 plat_fill_mc(pnode_t nodeid) 339 { 340 int portid; 341 342 /* 343 * Schumacher memory controller portid == global CPU id 344 */ 345 if ((prom_getprop(nodeid, "portid", (caddr_t)&portid) == -1) || 346 (portid < 0)) 347 return; 348 349 if (portid < max_mem_nodes) 350 plat_assign_lgrphand_to_mem_node(portid, portid); 351 } 352