1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/sysmacros.h> 31 #include <sys/archsystm.h> 32 #include <sys/vmsystm.h> 33 #include <sys/machparam.h> 34 #include <sys/machsystm.h> 35 #include <vm/vm_dep.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/seg_kmem.h> 38 #include <sys/cmn_err.h> 39 #include <sys/debug.h> 40 #include <sys/cpu_module.h> 41 #include <sys/sysmacros.h> 42 #include <sys/panic.h> 43 44 /* 45 * Note that 'Cheetah PRM' refers to: 46 * SPARC V9 JPS1 Implementation Supplement: Sun UltraSPARC-III 47 */ 48 49 /* 50 * pan_disable_ism_large_pages and pan_disable_large_pages are the Panther- 51 * specific versions of disable_ism_large_pages and disable_large_pages, 52 * and feed back into those two hat variables at hat initialization time, 53 * for Panther-only systems. 54 * 55 * chpjag_disable_ism_large_pages is the Ch/Jaguar-specific version of 56 * disable_ism_large_pages. Ditto for chjag_disable_large_pages. 57 */ 58 static int panther_only = 0; 59 60 static int pan_disable_ism_large_pages = ((1 << TTE64K) | 61 (1 << TTE512K) | (1 << TTE256M)); 62 static int pan_disable_large_pages = (1 << TTE256M); 63 static int pan_disable_auto_large_pages = ((1 << TTE64K) | 64 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE256M)); 65 66 static int chjag_disable_ism_large_pages = ((1 << TTE64K) | 67 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 68 static int chjag_disable_large_pages = ((1 << TTE32M) | (1 << TTE256M)); 69 static int chjag_disable_auto_large_pages = ((1 << TTE64K) | 70 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 71 72 /* 73 * The function returns the USIII-IV mmu-specific values for the 74 * hat's disable_large_pages and disable_ism_large_pages variables. 75 * Currently the hat's disable_large_pages and disable_ism_large_pages 76 * already contain the generic sparc 4 page size info, and the return 77 * values are or'd with those values. 78 */ 79 int 80 mmu_large_pages_disabled(uint_t flag) 81 { 82 int pages_disable = 0; 83 84 if (panther_only) { 85 if (flag == HAT_LOAD) { 86 pages_disable = pan_disable_large_pages; 87 } else if (flag == HAT_LOAD_SHARE) { 88 pages_disable = pan_disable_ism_large_pages; 89 } else if (flag == HAT_LOAD_AUTOLPG) { 90 pages_disable = pan_disable_auto_large_pages; 91 } 92 } else { 93 if (flag == HAT_LOAD) { 94 pages_disable = chjag_disable_large_pages; 95 } else if (flag == HAT_LOAD_SHARE) { 96 pages_disable = chjag_disable_ism_large_pages; 97 } else if (flag == HAT_LOAD_AUTOLPG) { 98 pages_disable = chjag_disable_auto_large_pages; 99 } 100 } 101 return (pages_disable); 102 } 103 104 #if defined(CPU_IMP_DUAL_PAGESIZE) 105 /* 106 * If a platform is running with only Ch+ or Jaguar, and then someone DR's 107 * in a Panther board, the Panther mmu will not like it if one of the already 108 * running threads is context switched to the Panther and tries to program 109 * a 512K or 4M page into the T512_1. So make these platforms pay the price 110 * and follow the Panther DTLB restrictions by default. :) 111 * The mmu_init_mmu_page_sizes code below takes care of heterogeneous 112 * platforms that don't support DR, like daktari. 113 * 114 * The effect of these restrictions is to limit the allowable values in 115 * sfmmu_pgsz[0] and sfmmu_pgsz[1], since these hat variables are used in 116 * mmu_set_ctx_page_sizes to set up the values in the sfmmu_cext that 117 * are used at context switch time. The value in sfmmu_pgsz[0] is used in 118 * P_pgsz0 and sfmmu_pgsz[1] is used in P_pgsz1, as per Figure F-1-1 119 * IMMU and DMMU Primary Context Register in the Panther Implementation 120 * Supplement and Table 15-21 DMMU Primary Context Register in the 121 * Cheetah+ Delta PRM. 122 */ 123 #ifdef MIXEDCPU_DR_SUPPORTED 124 int panther_dtlb_restrictions = 1; 125 #else 126 int panther_dtlb_restrictions = 0; 127 #endif /* MIXEDCPU_DR_SUPPORTED */ 128 129 /* 130 * init_mmu_page_sizes is set to one after the bootup time initialization 131 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 132 * valid value. 133 */ 134 int init_mmu_page_sizes = 0; 135 136 /* 137 * mmu_init_large_pages is called with the desired ism_pagesize parameter, 138 * for Panther-only systems. It may be called from set_platform_defaults, 139 * if some value other than 32M is desired, for Panther-only systems. 140 * mmu_ism_pagesize is the tunable. If it has a bad value, then only warn, 141 * since it would be bad form to panic due 142 * to a user typo. 143 * 144 * The function re-initializes the pan_disable_ism_large_pages and 145 * pan_disable_large_pages variables, which are closely related. 146 * Aka, if 32M is the desired [D]ISM page sizes, then 256M cannot be allowed 147 * for non-ISM large page usage, or DTLB conflict will occur. Please see the 148 * Panther PRM for additional DTLB technical info. 149 */ 150 void 151 mmu_init_large_pages(size_t ism_pagesize) 152 { 153 if (cpu_impl_dual_pgsz == 0) { /* disable_dual_pgsz flag */ 154 pan_disable_ism_large_pages = ((1 << TTE64K) | 155 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 156 pan_disable_large_pages = ((1 << TTE32M) | (1 << TTE256M)); 157 auto_lpg_maxszc = TTE4M; 158 return; 159 } 160 161 switch (ism_pagesize) { 162 case MMU_PAGESIZE4M: 163 pan_disable_ism_large_pages = ((1 << TTE64K) | 164 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 165 pan_disable_large_pages = (1 << TTE256M); 166 pan_disable_auto_large_pages = ((1 << TTE64K) | 167 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 168 auto_lpg_maxszc = TTE4M; 169 break; 170 case MMU_PAGESIZE32M: 171 pan_disable_ism_large_pages = ((1 << TTE64K) | 172 (1 << TTE512K) | (1 << TTE256M)); 173 pan_disable_large_pages = (1 << TTE256M); 174 pan_disable_auto_large_pages = ((1 << TTE64K) | 175 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE256M)); 176 auto_lpg_maxszc = TTE32M; 177 break; 178 case MMU_PAGESIZE256M: 179 pan_disable_ism_large_pages = ((1 << TTE64K) | 180 (1 << TTE512K) | (1 << TTE32M)); 181 pan_disable_large_pages = (1 << TTE32M); 182 pan_disable_auto_large_pages = ((1 << TTE64K) | 183 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M)); 184 auto_lpg_maxszc = TTE256M; 185 break; 186 default: 187 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 188 ism_pagesize); 189 break; 190 } 191 } 192 193 /* 194 * Re-initialize mmu_page_sizes and friends, for Panther mmu support. 195 * Called during very early bootup from check_cpus_set(). 196 * Can be called to verify that mmu_page_sizes are set up correctly. 197 * Note that ncpus is not initialized at this point in the bootup sequence. 198 */ 199 int 200 mmu_init_mmu_page_sizes(int cinfo) 201 { 202 int npanther = cinfo; 203 204 if (!init_mmu_page_sizes) { 205 if (npanther == ncpunode) { 206 mmu_page_sizes = MMU_PAGE_SIZES; 207 mmu_hashcnt = MAX_HASHCNT; 208 mmu_ism_pagesize = MMU_PAGESIZE32M; 209 mmu_exported_pagesize_mask = (1 << TTE8K) | 210 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 211 (1 << TTE32M) | (1 << TTE256M); 212 panther_dtlb_restrictions = 1; 213 panther_only = 1; 214 auto_lpg_maxszc = TTE32M; 215 } else if (npanther > 0) { 216 panther_dtlb_restrictions = 1; 217 } 218 init_mmu_page_sizes = 1; 219 return (0); 220 } 221 return (1); 222 } 223 224 225 /* Cheetah+ and later worst case DTLB parameters */ 226 #ifndef LOCKED_DTLB_ENTRIES 227 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 228 #endif 229 #define TOTAL_DTLB_ENTRIES 16 230 #define AVAIL_32M_ENTRIES 0 231 #define AVAIL_256M_ENTRIES 0 232 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 233 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 234 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 235 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 236 AVAIL_32M_ENTRIES, AVAIL_256M_ENTRIES }; 237 238 /*ARGSUSED*/ 239 uint_t 240 mmu_preferred_pgsz(struct hat *hat, caddr_t addr, size_t len) 241 { 242 sfmmu_t *sfmmup = (sfmmu_t *)hat; 243 uint_t pgsz0, pgsz1; 244 uint_t szc, maxszc = mmu_page_sizes - 1; 245 size_t pgsz; 246 extern int disable_auto_large_pages; 247 248 pgsz0 = (uint_t)sfmmup->sfmmu_pgsz[0]; 249 pgsz1 = (uint_t)sfmmup->sfmmu_pgsz[1]; 250 251 /* 252 * If either of the TLBs are reprogrammed, choose 253 * the largest mapping size as the preferred size, 254 * if it fits the size and alignment constraints. 255 * Else return the largest mapping size that fits, 256 * if neither TLB is reprogrammed. 257 */ 258 if (pgsz0 > TTE8K || pgsz1 > TTE8K) { 259 if (pgsz1 > pgsz0) { /* First try pgsz1 */ 260 pgsz = hw_page_array[pgsz1].hp_size; 261 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 262 return (pgsz1); 263 } 264 if (pgsz0 > TTE8K) { /* Then try pgsz0, if !TTE8K */ 265 pgsz = hw_page_array[pgsz0].hp_size; 266 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 267 return (pgsz0); 268 } 269 } else { /* Otherwise pick best fit if neither TLB is reprogrammed. */ 270 for (szc = maxszc; szc > TTE8K; szc--) { 271 if (disable_auto_large_pages & (1 << szc)) 272 continue; 273 274 pgsz = hw_page_array[szc].hp_size; 275 if ((len >= pgsz) && IS_P2ALIGNED(addr, pgsz)) 276 return (szc); 277 } 278 } 279 return (TTE8K); 280 } 281 282 /* 283 * The purpose of this code is to indirectly reorganize the sfmmu_pgsz array 284 * in order to handle the Panther mmu DTLB requirements. Panther only supports 285 * the 32M/256M pages in the T512_1 and not in the T16, so the Panther cpu 286 * can only support one of the two largest page sizes at a time (efficiently). 287 * Panther only supports 512K and 4M pages in the T512_0, and 32M/256M pages 288 * in the T512_1. So check the sfmmu flags and ttecnt before enabling 289 * the T512_1 for 32M or 256M page sizes, and make sure that 512K and 4M 290 * requests go to the T512_0. 291 * 292 * The tmp_pgsz array comes into this routine in sorted order, as it is 293 * sorted from largest to smallest #pages per pagesize in use by the hat code, 294 * and leaves with the Panther mmu DTLB requirements satisfied. Note that 295 * when the array leaves this function it may not contain all of the page 296 * size codes that it had coming into the function. 297 * 298 * Note that for DISM the flag can be set but the ttecnt can be 0, if we 299 * didn't fault any pages in. This allows the t512_1 to be reprogrammed, 300 * because the T16 does not support the two giant page sizes. ouch. 301 */ 302 void 303 mmu_fixup_large_pages(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz) 304 { 305 uint_t pgsz0 = tmp_pgsz[0]; 306 uint_t pgsz1 = tmp_pgsz[1]; 307 uint_t spgsz; 308 309 /* 310 * Don't program 2nd dtlb for kernel and ism hat 311 */ 312 ASSERT(hat->sfmmu_ismhat == NULL); 313 ASSERT(hat != ksfmmup); 314 ASSERT(cpu_impl_dual_pgsz == 1); 315 316 ASSERT((!SFMMU_FLAGS_ISSET(hat, HAT_32M_FLAG)) || 317 (!SFMMU_FLAGS_ISSET(hat, HAT_256M_FLAG))); 318 319 if ((SFMMU_FLAGS_ISSET(hat, HAT_32M_FLAG)) || (ttecnt[TTE32M] != 0)) { 320 spgsz = pgsz1; 321 pgsz1 = TTE32M; 322 if (pgsz0 == TTE32M) 323 pgsz0 = spgsz; 324 } else if ((SFMMU_FLAGS_ISSET(hat, HAT_256M_FLAG)) || 325 (ttecnt[TTE256M] != 0)) { 326 spgsz = pgsz1; 327 pgsz1 = TTE256M; 328 if (pgsz0 == TTE256M) 329 pgsz0 = spgsz; 330 } else if ((pgsz1 == TTE512K) || (pgsz1 == TTE4M)) { 331 if ((pgsz0 != TTE512K) && (pgsz0 != TTE4M)) { 332 spgsz = pgsz0; 333 pgsz0 = pgsz1; 334 pgsz1 = spgsz; 335 } else { 336 pgsz1 = page_szc(MMU_PAGESIZE); 337 } 338 } 339 /* 340 * This implements PAGESIZE programming of the T8s 341 * if large TTE counts don't exceed the thresholds. 342 */ 343 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 344 pgsz0 = page_szc(MMU_PAGESIZE); 345 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 346 pgsz1 = page_szc(MMU_PAGESIZE); 347 tmp_pgsz[0] = pgsz0; 348 tmp_pgsz[1] = pgsz1; 349 } 350 351 /* 352 * Function to set up the page size values used to reprogram the DTLBs, 353 * when page sizes used by a process change significantly. 354 */ 355 void 356 mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz) 357 { 358 uint_t pgsz0, pgsz1; 359 360 /* 361 * Don't program 2nd dtlb for kernel and ism hat 362 */ 363 ASSERT(hat->sfmmu_ismhat == NULL); 364 ASSERT(hat != ksfmmup); 365 366 if (cpu_impl_dual_pgsz == 0) /* disable_dual_pgsz flag */ 367 return; 368 369 /* 370 * hat->sfmmu_pgsz[] is an array whose elements 371 * contain a sorted order of page sizes. Element 372 * 0 is the most commonly used page size, followed 373 * by element 1, and so on. 374 * 375 * ttecnt[] is an array of per-page-size page counts 376 * mapped into the process. 377 * 378 * If the HAT's choice for page sizes is unsuitable, 379 * we can override it here. The new values written 380 * to the array will be handed back to us later to 381 * do the actual programming of the TLB hardware. 382 * 383 * The policy we use for programming the dual T8s on 384 * Cheetah+ and beyond is as follows: 385 * 386 * We have two programmable TLBs, so we look at 387 * the two most common page sizes in the array, which 388 * have already been computed for us by the HAT. 389 * If the TTE count of either of a preferred page size 390 * exceeds the number of unlocked T16 entries, 391 * we reprogram one of the T8s to that page size 392 * to avoid thrashing in the T16. Else we program 393 * that T8 to the base page size. Note that we do 394 * not force either T8 to be the base page size if a 395 * process is using more than two page sizes. Policy 396 * decisions about which page sizes are best to use are 397 * left to the upper layers. 398 * 399 * Note that for Panther, 4M and 512K pages need to be 400 * programmed into T512_0, and 32M and 256M into T512_1, 401 * so we don't want to go through the MIN/MAX code. 402 * For partial-Panther systems, we still want to make sure 403 * that 4M and 512K page sizes NEVER get into the T512_1. 404 * Since the DTLB flags are not set up on a per-cpu basis, 405 * Panther rules must be applied for mixed Panther/Cheetah+/ 406 * Jaguar configurations. 407 */ 408 if (panther_dtlb_restrictions) { 409 if ((tmp_pgsz[1] == TTE512K) || (tmp_pgsz[1] == TTE4M)) { 410 if ((tmp_pgsz[0] != TTE512K) && 411 (tmp_pgsz[0] != TTE4M)) { 412 pgsz1 = tmp_pgsz[0]; 413 pgsz0 = tmp_pgsz[1]; 414 } else { 415 pgsz0 = tmp_pgsz[0]; 416 pgsz1 = page_szc(MMU_PAGESIZE); 417 } 418 } else { 419 pgsz0 = tmp_pgsz[0]; 420 pgsz1 = tmp_pgsz[1]; 421 } 422 } else { 423 pgsz0 = MIN(tmp_pgsz[0], tmp_pgsz[1]); 424 pgsz1 = MAX(tmp_pgsz[0], tmp_pgsz[1]); 425 } 426 427 /* 428 * This implements PAGESIZE programming of the T8s 429 * if large TTE counts don't exceed the thresholds. 430 */ 431 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 432 pgsz0 = page_szc(MMU_PAGESIZE); 433 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 434 pgsz1 = page_szc(MMU_PAGESIZE); 435 tmp_pgsz[0] = pgsz0; 436 tmp_pgsz[1] = pgsz1; 437 } 438 439 /* 440 * The HAT calls this function when an MMU context is allocated so that we 441 * can reprogram the large TLBs appropriately for the new process using 442 * the context. 443 * 444 * The caller must hold the HAT lock. 445 */ 446 void 447 mmu_set_ctx_page_sizes(struct hat *hat) 448 { 449 uint_t pgsz0, pgsz1; 450 uint_t new_cext; 451 452 ASSERT(sfmmu_hat_lock_held(hat)); 453 ASSERT(hat != ksfmmup); 454 455 if (cpu_impl_dual_pgsz == 0) /* disable_dual_pgsz flag */ 456 return; 457 458 /* 459 * If supported, reprogram the TLBs to a larger pagesize. 460 */ 461 pgsz0 = hat->sfmmu_pgsz[0]; 462 pgsz1 = hat->sfmmu_pgsz[1]; 463 ASSERT(pgsz0 < mmu_page_sizes); 464 ASSERT(pgsz1 < mmu_page_sizes); 465 #ifdef DEBUG 466 if (panther_dtlb_restrictions) { 467 ASSERT(pgsz1 != TTE512K); 468 ASSERT(pgsz1 != TTE4M); 469 } 470 if (panther_only) { 471 ASSERT(pgsz0 != TTE32M); 472 ASSERT(pgsz0 != TTE256M); 473 } 474 #endif /* DEBUG */ 475 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 476 if (hat->sfmmu_cext != new_cext) { 477 #ifdef DEBUG 478 int i; 479 /* 480 * assert cnum should be invalid, this is because pagesize 481 * can only be changed after a proc's ctxs are invalidated. 482 */ 483 for (i = 0; i < max_mmu_ctxdoms; i++) { 484 ASSERT(hat->sfmmu_ctxs[i].cnum == INVALID_CONTEXT); 485 } 486 #endif /* DEBUG */ 487 hat->sfmmu_cext = new_cext; 488 } 489 490 /* 491 * sfmmu_setctx_sec() will take care of the 492 * rest of the chores reprogramming the hat->sfmmu_cext 493 * page size values into the DTLBs. 494 */ 495 } 496 497 /* 498 * This function assumes that there are either four or six supported page 499 * sizes and at most two programmable TLBs, so we need to decide which 500 * page sizes are most important and then adjust the TLB page sizes 501 * accordingly (if supported). 502 * 503 * If these assumptions change, this function will need to be 504 * updated to support whatever the new limits are. 505 */ 506 void 507 mmu_check_page_sizes(sfmmu_t *sfmmup, uint64_t *ttecnt) 508 { 509 uint64_t sortcnt[MMU_PAGE_SIZES]; 510 uint8_t tmp_pgsz[MMU_PAGE_SIZES]; 511 uint8_t i, j, max; 512 uint16_t oldval, newval; 513 514 /* 515 * We only consider reprogramming the TLBs if one or more of 516 * the two most used page sizes changes and we're using 517 * large pages in this process, except for Panther 32M/256M pages, 518 * which the Panther T16 does not support. 519 */ 520 if (sfmmup->sfmmu_flags & HAT_LGPG_FLAGS) { 521 /* Sort page sizes. */ 522 for (i = 0; i < mmu_page_sizes; i++) { 523 sortcnt[i] = ttecnt[i]; 524 } 525 for (j = 0; j < mmu_page_sizes; j++) { 526 for (i = mmu_page_sizes - 1, max = 0; i > 0; i--) { 527 if (sortcnt[i] > sortcnt[max]) 528 max = i; 529 } 530 tmp_pgsz[j] = max; 531 sortcnt[max] = 0; 532 } 533 534 /* 535 * Handle Panther page dtlb calcs separately. The check 536 * for actual or potential 32M/256M pages must occur 537 * every time due to lack of T16 support for them. 538 * The sort works fine for Ch+/Jag, but Panther has 539 * pagesize restrictions for both DTLBs. 540 */ 541 oldval = sfmmup->sfmmu_pgsz[0] << 8 | sfmmup->sfmmu_pgsz[1]; 542 543 if (panther_only) { 544 mmu_fixup_large_pages(sfmmup, ttecnt, tmp_pgsz); 545 } else { 546 /* Check 2 largest values after the sort. */ 547 mmu_setup_page_sizes(sfmmup, ttecnt, tmp_pgsz); 548 } 549 newval = tmp_pgsz[0] << 8 | tmp_pgsz[1]; 550 if (newval != oldval) { 551 sfmmu_reprog_pgsz_arr(sfmmup, tmp_pgsz); 552 } 553 } 554 } 555 556 #endif /* CPU_IMP_DUAL_PAGESIZE */ 557 558 struct heap_lp_page_size { 559 int impl; 560 uint_t tte; 561 int use_dt512; 562 }; 563 564 struct heap_lp_page_size heap_lp_pgsz[] = { 565 566 {CHEETAH_IMPL, TTE8K, 0}, /* default */ 567 {CHEETAH_IMPL, TTE64K, 0}, 568 {CHEETAH_IMPL, TTE4M, 0}, 569 570 { CHEETAH_PLUS_IMPL, TTE4M, 1 }, /* default */ 571 { CHEETAH_PLUS_IMPL, TTE4M, 0 }, 572 { CHEETAH_PLUS_IMPL, TTE64K, 1 }, 573 { CHEETAH_PLUS_IMPL, TTE64K, 0 }, 574 { CHEETAH_PLUS_IMPL, TTE8K, 0 }, 575 576 { JALAPENO_IMPL, TTE4M, 1 }, /* default */ 577 { JALAPENO_IMPL, TTE4M, 0 }, 578 { JALAPENO_IMPL, TTE64K, 1 }, 579 { JALAPENO_IMPL, TTE64K, 0 }, 580 { JALAPENO_IMPL, TTE8K, 0 }, 581 582 { JAGUAR_IMPL, TTE4M, 1 }, /* default */ 583 { JAGUAR_IMPL, TTE4M, 0 }, 584 { JAGUAR_IMPL, TTE64K, 1 }, 585 { JAGUAR_IMPL, TTE64K, 0 }, 586 { JAGUAR_IMPL, TTE8K, 0 }, 587 588 { SERRANO_IMPL, TTE4M, 1 }, /* default */ 589 { SERRANO_IMPL, TTE4M, 0 }, 590 { SERRANO_IMPL, TTE64K, 1 }, 591 { SERRANO_IMPL, TTE64K, 0 }, 592 { SERRANO_IMPL, TTE8K, 0 }, 593 594 { PANTHER_IMPL, TTE4M, 1 }, /* default */ 595 { PANTHER_IMPL, TTE4M, 0 }, 596 { PANTHER_IMPL, TTE64K, 1 }, 597 { PANTHER_IMPL, TTE64K, 0 }, 598 { PANTHER_IMPL, TTE8K, 0 } 599 }; 600 601 int heaplp_use_dt512 = -1; 602 603 void 604 mmu_init_kernel_pgsz(struct hat *hat) 605 { 606 uint_t tte = page_szc(segkmem_lpsize); 607 uchar_t new_cext_primary, new_cext_nucleus; 608 609 if (heaplp_use_dt512 == 0 || tte > TTE4M) { 610 /* do not reprogram dt512 tlb */ 611 tte = TTE8K; 612 } 613 614 new_cext_nucleus = TAGACCEXT_MKSZPAIR(tte, TTE8K); 615 new_cext_primary = TAGACCEXT_MKSZPAIR(TTE8K, tte); 616 617 hat->sfmmu_cext = new_cext_primary; 618 kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) | 619 ((uint64_t)new_cext_primary << CTXREG_EXT_SHIFT); 620 mmu_init_kcontext(); 621 } 622 623 size_t 624 mmu_get_kernel_lpsize(size_t lpsize) 625 { 626 struct heap_lp_page_size *p_lpgsz, *pend_lpgsz; 627 int impl = cpunodes[getprocessorid()].implementation; 628 uint_t tte = TTE8K; 629 630 if (cpu_impl_dual_pgsz == 0) { 631 heaplp_use_dt512 = 0; 632 return (MMU_PAGESIZE); 633 } 634 635 pend_lpgsz = (struct heap_lp_page_size *) 636 ((char *)heap_lp_pgsz + sizeof (heap_lp_pgsz)); 637 638 /* search for a valid segkmem_lpsize */ 639 for (p_lpgsz = heap_lp_pgsz; p_lpgsz < pend_lpgsz; p_lpgsz++) { 640 if (impl != p_lpgsz->impl) 641 continue; 642 643 if (lpsize == 0) { 644 /* 645 * no setting for segkmem_lpsize in /etc/system 646 * use default from the table 647 */ 648 tte = p_lpgsz->tte; 649 heaplp_use_dt512 = p_lpgsz->use_dt512; 650 break; 651 } 652 653 if (lpsize == TTEBYTES(p_lpgsz->tte) && 654 (heaplp_use_dt512 == -1 || 655 heaplp_use_dt512 == p_lpgsz->use_dt512)) { 656 657 tte = p_lpgsz->tte; 658 heaplp_use_dt512 = p_lpgsz->use_dt512; 659 660 /* found a match */ 661 break; 662 } 663 } 664 665 if (p_lpgsz == pend_lpgsz) { 666 /* nothing found: disable large page kernel heap */ 667 tte = TTE8K; 668 heaplp_use_dt512 = 0; 669 } 670 671 lpsize = TTEBYTES(tte); 672 673 return (lpsize); 674 } 675