1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI configuration space access routines 31 */ 32 33 #include <sys/systm.h> 34 #include <sys/psw.h> 35 #include <sys/bootconf.h> 36 #include <sys/reboot.h> 37 #include <sys/pci_impl.h> 38 #include <sys/pci_cfgspace.h> 39 #include <sys/pci_cfgspace_impl.h> 40 #if defined(__xpv) 41 #include <sys/hypervisor.h> 42 int pci_max_nbus = 0xFE; 43 #endif 44 45 46 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN; 47 int pci_bios_nbus; 48 int pci_bios_mech; 49 int pci_bios_vers; 50 51 /* 52 * These two variables can be used to force a configuration mechanism or 53 * to force which function is used to probe for the presence of the PCI bus. 54 */ 55 int PCI_CFG_TYPE = 0; 56 int PCI_PROBE_TYPE = 0; 57 58 /* 59 * These function pointers lead to the actual implementation routines 60 * for configuration space access. Normally they lead to either the 61 * pci_mech1_* or pci_mech2_* routines, but they can also lead to 62 * routines that work around chipset bugs. 63 */ 64 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg); 65 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg); 66 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg); 67 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val); 68 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val); 69 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val); 70 71 /* 72 * Internal routines 73 */ 74 static int pci_check(void); 75 76 #if !defined(__xpv) 77 static int pci_check_bios(void); 78 static int pci_get_cfg_type(void); 79 #endif 80 81 /* all config-space access routines share this one... */ 82 kmutex_t pcicfg_mutex; 83 84 /* ..except Orion and Neptune, which have to have their own */ 85 kmutex_t pcicfg_chipset_mutex; 86 87 void 88 pci_cfgspace_init(void) 89 { 90 mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN, 91 (ddi_iblock_cookie_t)ipltospl(15)); 92 mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN, 93 (ddi_iblock_cookie_t)ipltospl(15)); 94 if (!pci_check()) { 95 mutex_destroy(&pcicfg_mutex); 96 mutex_destroy(&pcicfg_chipset_mutex); 97 } 98 } 99 100 /* 101 * This code determines if this system supports PCI and which 102 * type of configuration access method is used 103 */ 104 105 static int 106 pci_check(void) 107 { 108 /* 109 * Only do this once. NB: If this is not a PCI system, and we 110 * get called twice, we can't detect it and will probably die 111 * horribly when we try to ask the BIOS whether PCI is present. 112 * This code is safe *ONLY* during system startup when the 113 * BIOS is still available. 114 */ 115 if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN) 116 return (TRUE); 117 118 #if defined(__xpv) 119 /* 120 * only support PCI config mechanism 1 in i86xpv. This should be fine 121 * since the other ones are workarounds for old broken H/W which won't 122 * be supported in i86xpv anyway. 123 */ 124 if (DOMAIN_IS_INITDOMAIN(xen_info)) { 125 pci_bios_cfg_type = PCI_MECHANISM_1; 126 pci_getb_func = pci_mech1_getb; 127 pci_getw_func = pci_mech1_getw; 128 pci_getl_func = pci_mech1_getl; 129 pci_putb_func = pci_mech1_putb; 130 pci_putw_func = pci_mech1_putw; 131 pci_putl_func = pci_mech1_putl; 132 133 /* 134 * Since we can't get the BIOS info in i86xpv, we will do an 135 * exhaustive search of all PCI buses. We have to do this until 136 * we start using the PCI information in ACPI. 137 */ 138 pci_bios_nbus = pci_max_nbus; 139 } 140 141 return (TRUE); 142 #else /* !__xpv */ 143 144 pci_bios_cfg_type = pci_check_bios(); 145 146 if (pci_bios_cfg_type == PCI_MECHANISM_NONE) 147 pci_bios_cfg_type = PCI_MECHANISM_1; /* default to mech 1 */ 148 149 switch (pci_get_cfg_type()) { 150 case PCI_MECHANISM_1: 151 if (pci_is_broken_orion()) { 152 pci_getb_func = pci_orion_getb; 153 pci_getw_func = pci_orion_getw; 154 pci_getl_func = pci_orion_getl; 155 pci_putb_func = pci_orion_putb; 156 pci_putw_func = pci_orion_putw; 157 pci_putl_func = pci_orion_putl; 158 } else { 159 pci_getb_func = pci_mech1_getb; 160 pci_getw_func = pci_mech1_getw; 161 pci_getl_func = pci_mech1_getl; 162 pci_putb_func = pci_mech1_putb; 163 pci_putw_func = pci_mech1_putw; 164 pci_putl_func = pci_mech1_putl; 165 } 166 break; 167 168 case PCI_MECHANISM_2: 169 if (pci_check_neptune()) { 170 /* 171 * The BIOS for some systems with the Intel 172 * Neptune chipset seem to default to #2 even 173 * though the chipset can do #1. Override 174 * the BIOS so that MP systems will work 175 * correctly. 176 */ 177 178 pci_getb_func = pci_neptune_getb; 179 pci_getw_func = pci_neptune_getw; 180 pci_getl_func = pci_neptune_getl; 181 pci_putb_func = pci_neptune_putb; 182 pci_putw_func = pci_neptune_putw; 183 pci_putl_func = pci_neptune_putl; 184 } else { 185 pci_getb_func = pci_mech2_getb; 186 pci_getw_func = pci_mech2_getw; 187 pci_getl_func = pci_mech2_getl; 188 pci_putb_func = pci_mech2_putb; 189 pci_putw_func = pci_mech2_putw; 190 pci_putl_func = pci_mech2_putl; 191 } 192 break; 193 194 default: 195 return (FALSE); 196 } 197 198 return (TRUE); 199 #endif /* __xpv */ 200 } 201 202 #if !defined(__xpv) 203 204 static int 205 pci_check_bios(void) 206 { 207 struct bop_regs regs; 208 uint32_t carryflag; 209 uint16_t ax, dx; 210 211 bzero(®s, sizeof (regs)); 212 regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT; 213 214 BOP_DOINT(bootops, 0x1a, ®s); 215 carryflag = regs.eflags & PS_C; 216 ax = regs.eax.word.ax; 217 dx = regs.edx.word.dx; 218 219 /* the carry flag must not be set */ 220 if (carryflag != 0) 221 return (PCI_MECHANISM_NONE); 222 223 if (dx != ('P' | 'C'<<8)) 224 return (PCI_MECHANISM_NONE); 225 226 /* ah (the high byte of ax) must be zero */ 227 if ((ax & 0xff00) != 0) 228 return (PCI_MECHANISM_NONE); 229 230 pci_bios_mech = (ax & 0x3); 231 pci_bios_vers = regs.ebx.word.bx; 232 pci_bios_nbus = (regs.ecx.word.cx & 0xff); 233 234 switch (pci_bios_mech) { 235 default: /* ?!? */ 236 case 0: /* supports neither? */ 237 return (PCI_MECHANISM_NONE); 238 239 case 1: 240 case 3: /* supports both */ 241 return (PCI_MECHANISM_1); 242 243 case 2: 244 return (PCI_MECHANISM_2); 245 } 246 } 247 248 static int 249 pci_get_cfg_type(void) 250 { 251 /* Check to see if the config mechanism has been set in /etc/system */ 252 switch (PCI_CFG_TYPE) { 253 default: 254 case 0: 255 break; 256 case 1: 257 return (PCI_MECHANISM_1); 258 case 2: 259 return (PCI_MECHANISM_2); 260 case -1: 261 return (PCI_MECHANISM_NONE); 262 } 263 264 /* call one of the PCI detection algorithms */ 265 switch (PCI_PROBE_TYPE) { 266 default: 267 case 0: 268 /* From pci_check() and pci_check_bios() */ 269 return (pci_bios_cfg_type); 270 case -1: 271 return (PCI_MECHANISM_NONE); 272 } 273 } 274 275 #endif /* __xpv */ 276