1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2002-2005 Neterion, Inc. 29 * All right Reserved. 30 * 31 * FileName : xgell.h 32 * 33 * Description: Link Layer driver declaration 34 * 35 */ 36 37 #ifndef _SYS_XGELL_H 38 #define _SYS_XGELL_H 39 40 #include <sys/types.h> 41 #include <sys/errno.h> 42 #include <sys/param.h> 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/strsubr.h> 46 #include <sys/kmem.h> 47 #include <sys/conf.h> 48 #include <sys/devops.h> 49 #include <sys/ksynch.h> 50 #include <sys/stat.h> 51 #include <sys/modctl.h> 52 #include <sys/debug.h> 53 #include <sys/pci.h> 54 #include <sys/ethernet.h> 55 #include <sys/vlan.h> 56 #include <sys/dlpi.h> 57 #include <sys/taskq.h> 58 #include <sys/cyclic.h> 59 60 #include <sys/pattr.h> 61 #include <sys/strsun.h> 62 63 #include <sys/mac.h> 64 #include <sys/mac_ether.h> 65 66 #ifdef __cplusplus 67 extern "C" { 68 #endif 69 70 #define XGELL_DESC "Xframe I/II 10Gb Ethernet" 71 #define XGELL_IFNAME "xge" 72 #define XGELL_TX_LEVEL_LOW 8 73 #define XGELL_TX_LEVEL_HIGH 32 74 #define XGELL_TX_LEVEL_CHECK 3 75 #define XGELL_MAX_RING_DEFAULT 8 76 #define XGELL_MAX_FIFO_DEFAULT 1 77 78 #include <xgehal.h> 79 80 /* 81 * The definition of XGELL_RX_BUFFER_RECYCLE_CACHE is an experimental value. 82 * With this value, the lock contention between xgell_rx_buffer_recycle() 83 * and xgell_rx_1b_compl() is reduced to great extent. And multiple rx rings 84 * alleviate the lock contention further since each rx ring has its own mutex. 85 */ 86 #define XGELL_RX_BUFFER_RECYCLE_CACHE XGE_HAL_RING_RXDS_PER_BLOCK(1) * 2 87 #define MSG_SIZE 64 88 89 /* 90 * These default values can be overridden by vaules in xge.conf. 91 * In xge.conf user has to specify actual (not percentages) values. 92 */ 93 #define XGELL_RX_BUFFER_TOTAL XGE_HAL_RING_RXDS_PER_BLOCK(1) * 6 94 #define XGELL_RX_BUFFER_POST_HIWAT XGE_HAL_RING_RXDS_PER_BLOCK(1) * 5 95 96 /* Control driver to copy or DMA received packets */ 97 #define XGELL_RX_DMA_LOWAT 256 98 99 #define XGELL_RING_MAIN_QID 0 100 101 #if defined(__x86) 102 #define XGELL_TX_DMA_LOWAT 128 103 #else 104 #define XGELL_TX_DMA_LOWAT 512 105 #endif 106 107 /* 108 * Try to collapse up to XGELL_RX_PKT_BURST packets into single mblk 109 * sequence before mac_rx() is called. 110 */ 111 #define XGELL_RX_PKT_BURST 32 112 113 /* About 1s */ 114 #define XGE_DEV_POLL_TICKS drv_usectohz(1000000) 115 116 #define XGELL_LSO_MAXLEN 65535 117 #define XGELL_CONF_ENABLE_BY_DEFAULT 1 118 #define XGELL_CONF_DISABLE_BY_DEFAULT 0 119 120 /* LRO configuration */ 121 #define XGE_HAL_DEFAULT_LRO_SG_SIZE 2 /* <=2 LRO fix not required */ 122 #define XGE_HAL_DEFAULT_LRO_FRM_LEN 65535 123 124 /* 125 * Default values for tunables used in HAL. Please refer to xgehal-config.h 126 * for more details. 127 */ 128 #define XGE_HAL_DEFAULT_USE_HARDCODE -1 129 130 /* Bimodal adaptive schema defaults - ENABLED */ 131 #define XGE_HAL_DEFAULT_BIMODAL_INTERRUPTS -1 132 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_LO_US 24 133 #define XGE_HAL_DEFAULT_BIMODAL_TIMER_HI_US 256 134 135 /* Interrupt moderation/utilization defaults */ 136 #define XGE_HAL_DEFAULT_TX_URANGE_A 5 137 #define XGE_HAL_DEFAULT_TX_URANGE_B 15 138 #define XGE_HAL_DEFAULT_TX_URANGE_C 30 139 #define XGE_HAL_DEFAULT_TX_UFC_A 15 140 #define XGE_HAL_DEFAULT_TX_UFC_B 30 141 #define XGE_HAL_DEFAULT_TX_UFC_C 45 142 #define XGE_HAL_DEFAULT_TX_UFC_D 60 143 #define XGE_HAL_DEFAULT_TX_TIMER_CI_EN 1 144 #define XGE_HAL_DEFAULT_TX_TIMER_AC_EN 1 145 #define XGE_HAL_DEFAULT_TX_TIMER_VAL 10000 146 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_B 512 /* bimodal */ 147 #define XGE_HAL_DEFAULT_INDICATE_MAX_PKTS_N 256 /* normal UFC */ 148 #define XGE_HAL_DEFAULT_RX_URANGE_A 10 149 #define XGE_HAL_DEFAULT_RX_URANGE_B 30 150 #define XGE_HAL_DEFAULT_RX_URANGE_C 50 151 #define XGE_HAL_DEFAULT_RX_UFC_A 1 152 #define XGE_HAL_DEFAULT_RX_UFC_B_J 2 153 #define XGE_HAL_DEFAULT_RX_UFC_B_N 8 154 #define XGE_HAL_DEFAULT_RX_UFC_C_J 4 155 #define XGE_HAL_DEFAULT_RX_UFC_C_N 16 156 #define XGE_HAL_DEFAULT_RX_UFC_D 32 157 #define XGE_HAL_DEFAULT_RX_TIMER_AC_EN 1 158 #define XGE_HAL_DEFAULT_RX_TIMER_VAL 384 159 160 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_J 2048 161 #define XGE_HAL_DEFAULT_FIFO_QUEUE_LENGTH_N 4096 162 #define XGE_HAL_DEFAULT_FIFO_QUEUE_INTR 0 163 #define XGE_HAL_DEFAULT_FIFO_RESERVE_THRESHOLD 0 164 #define XGE_HAL_DEFAULT_FIFO_MEMBLOCK_SIZE PAGESIZE 165 166 /* 167 * This will force HAL to allocate extra copied buffer per TXDL which 168 * size calculated by formula: 169 * 170 * (ALIGNMENT_SIZE * ALIGNED_FRAGS) 171 */ 172 #define XGE_HAL_DEFAULT_FIFO_ALIGNMENT_SIZE 4096 173 #define XGE_HAL_DEFAULT_FIFO_MAX_ALIGNED_FRAGS 1 174 #if defined(__x86) 175 #define XGE_HAL_DEFAULT_FIFO_FRAGS 128 176 #else 177 #define XGE_HAL_DEFAULT_FIFO_FRAGS 64 178 #endif 179 #define XGE_HAL_DEFAULT_FIFO_FRAGS_THRESHOLD 18 180 181 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_J 2 182 #define XGE_HAL_DEFAULT_RING_QUEUE_BLOCKS_N 2 183 #define XGE_HAL_RING_QUEUE_BUFFER_MODE_DEFAULT 1 184 #define XGE_HAL_DEFAULT_BACKOFF_INTERVAL_US 64 185 #define XGE_HAL_DEFAULT_RING_PRIORITY 0 186 #define XGE_HAL_DEFAULT_RING_MEMBLOCK_SIZE PAGESIZE 187 188 #define XGE_HAL_DEFAULT_RING_NUM 8 189 #define XGE_HAL_DEFAULT_TMAC_UTIL_PERIOD 5 190 #define XGE_HAL_DEFAULT_RMAC_UTIL_PERIOD 5 191 #define XGE_HAL_DEFAULT_RMAC_HIGH_PTIME 65535 192 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q0Q3 187 193 #define XGE_HAL_DEFAULT_MC_PAUSE_THRESHOLD_Q4Q7 187 194 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_EN 1 195 #define XGE_HAL_DEFAULT_RMAC_PAUSE_GEN_DIS 0 196 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_EN 1 197 #define XGE_HAL_DEFAULT_RMAC_PAUSE_RCV_DIS 0 198 #define XGE_HAL_DEFAULT_INITIAL_MTU XGE_HAL_DEFAULT_MTU /* 1500 */ 199 #define XGE_HAL_DEFAULT_ISR_POLLING_CNT 0 200 #define XGE_HAL_DEFAULT_LATENCY_TIMER 255 201 #define XGE_HAL_DEFAULT_SHARED_SPLITS 0 202 #define XGE_HAL_DEFAULT_STATS_REFRESH_TIME 1 203 204 #if defined(__sparc) 205 #define XGE_HAL_DEFAULT_MMRB_COUNT \ 206 XGE_HAL_MAX_MMRB_COUNT 207 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION \ 208 XGE_HAL_EIGHT_SPLIT_TRANSACTION 209 #else 210 #define XGE_HAL_DEFAULT_MMRB_COUNT 1 /* 1k */ 211 #define XGE_HAL_DEFAULT_SPLIT_TRANSACTION \ 212 XGE_HAL_TWO_SPLIT_TRANSACTION 213 #endif 214 215 /* 216 * default the size of buffers allocated for ndd interface functions 217 */ 218 #define XGELL_STATS_BUFSIZE 8192 219 #define XGELL_PCICONF_BUFSIZE 2048 220 #define XGELL_ABOUT_BUFSIZE 512 221 #define XGELL_IOCTL_BUFSIZE 64 222 #define XGELL_DEVCONF_BUFSIZE 8192 223 224 /* 225 * xgell_event_e 226 * 227 * This enumeration derived from xgehal_event_e. It extends it 228 * for the reason to get serialized context. 229 */ 230 /* Renamb the macro from HAL */ 231 #define XGELL_EVENT_BASE XGE_LL_EVENT_BASE 232 typedef enum xgell_event_e { 233 /* LL events */ 234 XGELL_EVENT_RESCHED_NEEDED = XGELL_EVENT_BASE + 1, 235 } xgell_event_e; 236 237 typedef struct { 238 int rx_pkt_burst; 239 int rx_buffer_total; 240 int rx_buffer_post_hiwat; 241 int rx_dma_lowat; 242 int tx_dma_lowat; 243 int msix_enable; 244 int lso_enable; 245 } xgell_config_t; 246 247 typedef struct xgell_ring xgell_ring_t; 248 typedef struct xgell_fifo xgell_fifo_t; 249 250 typedef struct xgell_rx_buffer_t { 251 struct xgell_rx_buffer_t *next; 252 void *vaddr; 253 dma_addr_t dma_addr; 254 ddi_dma_handle_t dma_handle; 255 ddi_acc_handle_t dma_acch; 256 xgell_ring_t *ring; 257 frtn_t frtn; 258 } xgell_rx_buffer_t; 259 260 /* Buffer pool for all rings */ 261 typedef struct xgell_rx_buffer_pool_t { 262 uint_t total; /* total buffers */ 263 uint_t size; /* buffer size */ 264 xgell_rx_buffer_t *head; /* header pointer */ 265 uint_t free; /* free buffers */ 266 uint_t post; /* posted buffers */ 267 uint_t post_hiwat; /* hiwat to stop post */ 268 spinlock_t pool_lock; /* buffer pool lock */ 269 xgell_rx_buffer_t *recycle_head; /* recycle list's head */ 270 xgell_rx_buffer_t *recycle_tail; /* recycle list's tail */ 271 uint_t recycle; /* # of rx buffers recycled */ 272 spinlock_t recycle_lock; /* buffer recycle lock */ 273 } xgell_rx_buffer_pool_t; 274 275 typedef struct xgelldev xgelldev_t; 276 277 struct xgell_ring { 278 xge_hal_channel_h channelh; 279 xgelldev_t *lldev; 280 mac_resource_handle_t handle; /* per ring cookie */ 281 xgell_rx_buffer_pool_t bf_pool; 282 }; 283 284 struct xgell_fifo { 285 xge_hal_channel_h channelh; 286 xgelldev_t *lldev; 287 int level_low; 288 }; 289 290 struct xgelldev { 291 caddr_t ndp; 292 mac_handle_t mh; 293 int instance; 294 dev_info_t *dev_info; 295 xge_hal_device_h devh; 296 xgell_ring_t rings[XGE_HAL_MAX_RING_NUM]; 297 xgell_fifo_t fifos[XGE_HAL_MAX_FIFO_NUM]; 298 int resched_avail; 299 int resched_send; 300 int resched_retry; 301 int tx_copied_max; 302 volatile int is_initialized; 303 xgell_config_t config; 304 volatile int in_reset; 305 timeout_id_t timeout_id; 306 kmutex_t genlock; 307 ddi_intr_handle_t *intr_table; 308 uint_t intr_table_size; 309 int intr_type; 310 int intr_cnt; 311 uint_t intr_pri; 312 int intr_cap; 313 }; 314 315 typedef struct { 316 mblk_t *mblk; 317 ddi_dma_handle_t dma_handles[XGE_HAL_DEFAULT_FIFO_FRAGS]; 318 int handle_cnt; 319 } xgell_txd_priv_t; 320 321 typedef struct { 322 xgell_rx_buffer_t *rx_buffer; 323 } xgell_rxd_priv_t; 324 325 int xgell_device_alloc(xge_hal_device_h devh, dev_info_t *dev_info, 326 xgelldev_t **lldev_out); 327 328 void xgell_device_free(xgelldev_t *lldev); 329 330 int xgell_device_register(xgelldev_t *lldev, xgell_config_t *config); 331 332 int xgell_device_unregister(xgelldev_t *lldev); 333 334 void xgell_callback_link_up(void *userdata); 335 336 void xgell_callback_link_down(void *userdata); 337 338 int xgell_onerr_reset(xgelldev_t *lldev); 339 340 void xge_device_poll_now(void *data); 341 342 int xge_add_intrs(xgelldev_t *lldev); 343 344 int xge_enable_intrs(xgelldev_t *lldev); 345 346 void xge_disable_intrs(xgelldev_t *lldev); 347 348 void xge_rem_intrs(xgelldev_t *lldev); 349 350 351 352 353 #ifdef __cplusplus 354 } 355 #endif 356 357 #endif /* _SYS_XGELL_H */ 358