xref: /titanic_41/usr/src/uts/common/io/bge/bge_chip2.c (revision b32499b769ecd9a0e4fac57cbd5f1aa5547df310)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved.
24  */
25 
26 #include "bge_impl.h"
27 
28 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
29 
30 /*
31  * Future features ... ?
32  */
33 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
34 #define	BGE_IND_IO32	1	/* indirect access code		*/
35 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
36 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
37 
38 /*
39  * BGE MSI tunable:
40  *
41  * By default MSI is enabled on all supported platforms but it is disabled
42  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
43  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
44  */
45 boolean_t bge_enable_msi = B_TRUE;
46 
47 /*
48  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
49  */
50 boolean_t bge_relaxed_ordering = B_TRUE;
51 
52 /*
53  * Property names
54  */
55 static char knownids_propname[] = "bge-known-subsystems";
56 
57 /*
58  * Patchable globals:
59  *
60  *	bge_autorecover
61  *		Enables/disables automatic recovery after fault detection
62  *
63  *	bge_mlcr_default
64  *		Value to program into the MLCR; controls the chip's GPIO pins
65  *
66  *	bge_dma_{rd,wr}prio
67  *		Relative priorities of DMA reads & DMA writes respectively.
68  *		These may each be patched to any value 0-3.  Equal values
69  *		will give "fair" (round-robin) arbitration for PCI access.
70  *		Unequal values will give one or the other function priority.
71  *
72  *	bge_dma_rwctrl
73  *		Value to put in the Read/Write DMA control register.  See
74  *	        the Broadcom PRM for things you can fiddle with in this
75  *		register ...
76  *
77  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
78  *		Send/receive interrupt coalescing parameters.  Counts are
79  *		#s of descriptors, ticks are in microseconds.  *norm* values
80  *		apply between status updates/interrupts; the *intr* values
81  *		refer to the 'during-interrupt' versions - see the PRM.
82  *
83  *		NOTE: these values have been determined by measurement. They
84  *		differ significantly from the values recommended in the PRM.
85  */
86 static uint32_t bge_autorecover = 1;
87 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
88 
89 static uint32_t bge_dma_rdprio = 1;
90 static uint32_t bge_dma_wrprio = 0;
91 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
92 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
93 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
94 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
95 
96 uint32_t bge_rx_ticks_norm = 128;
97 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
98 uint32_t bge_rx_count_norm = 8;
99 uint32_t bge_tx_count_norm = 128;
100 
101 static uint32_t bge_rx_ticks_intr = 128;
102 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
103 static uint32_t bge_rx_count_intr = 2;
104 static uint32_t bge_tx_count_intr = 0;
105 
106 /*
107  * Memory pool configuration parameters.
108  *
109  * These are generally specific to each member of the chip family, since
110  * each one may have a different memory size/configuration.
111  *
112  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
113  * the driver from programming the various registers; instead they are left
114  * at their hardware defaults.  This is the preferred option for later chips
115  * (5705+), whereas the older chips *required* these registers to be set,
116  * since the h/w default was 0 ;-(
117  */
118 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
119 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
120 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
121 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
122 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
123 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
124 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
125 static uint32_t bge_mbuf_pool_len_5721	= 0;
126 
127 /*
128  * Various high and low water marks, thresholds, etc ...
129  *
130  * Note: these are taken from revision 7 of the PRM, and some are different
131  * from both the values in earlier PRMs *and* those determined experimentally
132  * and used in earlier versions of this driver ...
133  */
134 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
135 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
136 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
137 
138 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
139 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
140 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
141 
142 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
143 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
144 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
145 
146 static uint32_t	bge_watchdog_count	= 1 << 16;
147 static uint16_t bge_dma_miss_limit	= 20;
148 
149 static uint32_t bge_stop_start_on_sync	= 0;
150 
151 /*
152  * bge_intr_max_loop controls the maximum loop number within bge_intr.
153  * When loading NIC with heavy network traffic, it is useful.
154  * Increasing this value could have positive effect to throughput,
155  * but it might also increase ticks of a bge ISR stick on CPU, which might
156  * lead to bad UI interactive experience. So tune this with caution.
157  */
158 static int bge_intr_max_loop = 1;
159 
160 /*
161  * ========== Low-level chip & ring buffer manipulation ==========
162  */
163 
164 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
165 
166 
167 /*
168  * Config space read-modify-write routines
169  */
170 
171 #if	BGE_CFG_IO8
172 
173 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
174 #pragma	inline(bge_cfg_clr16)
175 
176 static void
177 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
178 {
179 	uint16_t regval;
180 
181 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
182 	    (void *)bgep, regno, bits));
183 
184 	regval = pci_config_get16(bgep->cfg_handle, regno);
185 
186 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
187 	    (void *)bgep, regno, bits, regval, regval & ~bits));
188 
189 	regval &= ~bits;
190 	pci_config_put16(bgep->cfg_handle, regno, regval);
191 }
192 
193 #endif	/* BGE_CFG_IO8 */
194 
195 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
196 #pragma	inline(bge_cfg_clr32)
197 
198 static void
199 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
200 {
201 	uint32_t regval;
202 
203 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
204 	    (void *)bgep, regno, bits));
205 
206 	regval = pci_config_get32(bgep->cfg_handle, regno);
207 
208 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
209 	    (void *)bgep, regno, bits, regval, regval & ~bits));
210 
211 	regval &= ~bits;
212 	pci_config_put32(bgep->cfg_handle, regno, regval);
213 }
214 
215 #if	BGE_IND_IO32
216 
217 /*
218  * Indirect access to registers & RISC scratchpads, using config space
219  * accesses only.
220  *
221  * This isn't currently used, but someday we might want to use it for
222  * restoring the Subsystem Device/Vendor registers (which aren't directly
223  * writable in Config Space), or for downloading firmware into the RISCs
224  *
225  * In any case there are endian issues to be resolved before this code is
226  * enabled; the bizarre way that bytes get twisted by this chip AND by
227  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
228  * it's been thoroughly tested for all access sizes on all supported
229  * architectures (SPARC *and* x86!).
230  */
231 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
232 #pragma	inline(bge_ind_get32)
233 
234 uint32_t
235 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
236 {
237 	uint32_t val;
238 
239 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
240 
241 #ifdef __sparc
242 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
243 		regno = LE_32(regno);
244 #endif
245 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
246 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
247 
248 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
249 	    (void *)bgep, regno, val));
250 
251 	val = LE_32(val);
252 
253 	return (val);
254 }
255 
256 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
257 #pragma	inline(bge_ind_put32)
258 
259 void
260 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
261 {
262 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
263 	    (void *)bgep, regno, val));
264 
265 	val = LE_32(val);
266 #ifdef __sparc
267 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
268 		regno = LE_32(regno);
269 #endif
270 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
271 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
272 }
273 
274 #endif	/* BGE_IND_IO32 */
275 
276 #if	BGE_DEBUGGING
277 
278 static void bge_pci_check(bge_t *bgep);
279 #pragma	no_inline(bge_pci_check)
280 
281 static void
282 bge_pci_check(bge_t *bgep)
283 {
284 	uint16_t pcistatus;
285 
286 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
287 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
288 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
289 		    (void *)bgep, pcistatus));
290 }
291 
292 #endif	/* BGE_DEBUGGING */
293 
294 /*
295  * Perform first-stage chip (re-)initialisation, using only config-space
296  * accesses:
297  *
298  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
299  *   returning the data in the structure pointed to by <idp>.
300  * + Configure the target-mode endianness (swap) options.
301  * + Disable interrupts and enable Memory Space accesses.
302  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
303  *
304  * This sequence is adapted from Broadcom document 570X-PG102-R,
305  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
306  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
307  *
308  * This function MUST be called before any non-config-space accesses
309  * are made; on this first call <enable_dma> is B_FALSE, and it
310  * effectively performs steps 3-1(!) of the initialisation sequence
311  * (the rest are not required but should be harmless).
312  *
313  * It MUST also be called after a chip reset, as this disables
314  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
315  * it is effectively performing steps 6-8.
316  */
317 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
318 #pragma	no_inline(bge_chip_cfg_init)
319 
320 void
321 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
322 {
323 	ddi_acc_handle_t handle;
324 	uint16_t command;
325 	uint32_t mhcr;
326 	uint16_t value16;
327 	int i;
328 
329 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
330 	    (void *)bgep, (void *)cidp, enable_dma));
331 
332 	/*
333 	 * Step 3: save PCI cache line size and subsystem vendor ID
334 	 *
335 	 * Read all the config-space registers that characterise the
336 	 * chip, specifically vendor/device/revision/subsystem vendor
337 	 * and subsystem device id.  We expect (but don't check) that
338 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
339 	 *
340 	 * Also save all bus-transaction related registers (cache-line
341 	 * size, bus-grant/latency parameters, etc).  Some of these are
342 	 * cleared by reset, so we'll have to restore them later.  This
343 	 * comes from the Broadcom document 570X-PG102-R ...
344 	 *
345 	 * Note: Broadcom document 570X-PG102-R seems to be in error
346 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
347 	 * Subsystem (Device) ID registers, which are the opposite way
348 	 * round according to the PCI standard.  For good measure, we
349 	 * save/restore both anyway.
350 	 */
351 	handle = bgep->cfg_handle;
352 
353 	/*
354 	 * For some chipsets (e.g., BCM5718), if MHCR_ENABLE_ENDIAN_BYTE_SWAP
355 	 * has been set in PCI_CONF_COMM already, we need to write the
356 	 * byte-swapped value to it. So we just write zero first for simplicity.
357 	 */
358 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
359 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
360 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
361 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
362 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
363 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
364 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
365 
366 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
367 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
368 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
369 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
370 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
371 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
372 
373 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
374 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
375 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
376 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
377 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
378 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
379 	    cidp->vendor, cidp->device, cidp->revision));
380 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
381 	    cidp->subven, cidp->subdev, cidp->asic_rev));
382 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
383 	    cidp->clsize, cidp->latency, cidp->command));
384 
385 	/*
386 	 * Step 2 (also step 6): disable and clear interrupts.
387 	 * Steps 11-13: configure PIO endianness options, and enable
388 	 * indirect register access.  We'll also select any other
389 	 * options controlled by the MHCR (e.g. tagged status, mask
390 	 * interrupt mode) at this stage ...
391 	 *
392 	 * Note: internally, the chip is 64-bit and BIG-endian, but
393 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
394 	 * it normally swaps bytes around at the PCI interface.
395 	 * However, the PCI host bridge on SPARC systems normally
396 	 * swaps the byte lanes around too, since SPARCs are also
397 	 * BIG-endian.  So it turns out that on SPARC, the right
398 	 * option is to tell the chip to swap (and the host bridge
399 	 * will swap back again), whereas on x86 we ask the chip
400 	 * NOT to swap, so the natural little-endianness of the
401 	 * PCI bus is assumed.  Then the only thing that doesn't
402 	 * automatically work right is access to an 8-byte register
403 	 * by a little-endian host; but we don't want to set the
404 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
405 	 * accesses don't go where expected ;-(  So we live with
406 	 * that, and perform word-swaps in software in the few cases
407 	 * where a chip register is defined as an 8-byte value --
408 	 * see the code below for details ...
409 	 *
410 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
411 	 * very clear in the register description in the PRM, but
412 	 * Broadcom document 570X-PG104-R page 248 explains a little
413 	 * more (under "Broadcom Mask Mode").  The bit changes the way
414 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
415 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
416 	 * way as the 5700 did, which isn't very convenient.  Setting
417 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
418 	 * bit do just what its name says -- MASK the PCI #INTA output
419 	 * (i.e. deassert the signal at the pin) leaving all internal
420 	 * state unchanged.  This is much more convenient for our
421 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
422 	 *
423 	 * Note: the inconvenient semantics of the interrupt mailbox
424 	 * (nonzero disables and acknowledges/clears the interrupt,
425 	 * zero enables AND CLEARS it) would make race conditions
426 	 * likely in the interrupt handler:
427 	 *
428 	 * (1)	acknowledge & disable interrupts
429 	 * (2)	while (more to do)
430 	 * 		process packets
431 	 * (3)	enable interrupts -- also clears pending
432 	 *
433 	 * If the chip received more packets and internally generated
434 	 * an interrupt between the check at (2) and the mbox write
435 	 * at (3), this interrupt would be lost :-(
436 	 *
437 	 * The best way to avoid this is to use TAGGED STATUS mode,
438 	 * where the chip includes a unique tag in each status block
439 	 * update, and the host, when re-enabling interrupts, passes
440 	 * the last tag it saw back to the chip; then the chip can
441 	 * see whether the host is truly up to date, and regenerate
442 	 * its interrupt if not.
443 	 */
444 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
445 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
446 	    MHCR_MASK_INTERRUPT_MODE |
447 	    MHCR_CLEAR_INTERRUPT_INTA;
448 
449 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
450 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
451 
452 #ifdef	_BIG_ENDIAN
453 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
454 #endif	/* _BIG_ENDIAN */
455 
456 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
457 		pci_config_put32(handle, PCI_CONF_BGE_MHCR, 0);
458 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
459 
460 #ifdef BGE_IPMI_ASF
461 	bgep->asf_wordswapped = B_FALSE;
462 #endif
463 	/*
464 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
465 	 *			 Disable Memory Write/Invalidate
466 	 *			 Enable or disable Bus Mastering
467 	 *
468 	 * Note that all other bits are taken from the original value saved
469 	 * the first time through here, rather than from the current register
470 	 * value, 'cos that will have been cleared by a soft RESET since.
471 	 * In this way we preserve the OBP/nexus-parent's preferred settings
472 	 * of the parity-error and system-error enable bits across multiple
473 	 * chip RESETs.
474 	 */
475 	command = bgep->chipid.command | PCI_COMM_MAE;
476 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
477 	if (enable_dma)
478 		command |= PCI_COMM_ME;
479 	/*
480 	 * on BCM5714 revision A0, false parity error gets generated
481 	 * due to a logic bug. Provide a workaround by disabling parity
482 	 * error.
483 	 */
484 	if (((cidp->device == DEVICE_ID_5714C) ||
485 	    (cidp->device == DEVICE_ID_5714S)) &&
486 	    (cidp->revision == REVISION_ID_5714_A0)) {
487 		command &= ~PCI_COMM_PARITY_DETECT;
488 	}
489 	pci_config_put16(handle, PCI_CONF_COMM, command);
490 
491 	/*
492 	 * On some PCI-E device, there were instances when
493 	 * the device was still link training.
494 	 */
495 	if (bgep->chipid.pci_type == BGE_PCI_E) {
496 		i = 0;
497 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
498 		while ((value16 != command) && (i < 100)) {
499 			drv_usecwait(200);
500 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
501 			++i;
502 		}
503 	}
504 
505 	/*
506 	 * Clear any remaining error status bits
507 	 */
508 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
509 
510 	/*
511 	 * Do following if and only if the device is NOT BCM5714C OR
512 	 * BCM5715C
513 	 */
514 	if (!((cidp->device == DEVICE_ID_5714C) ||
515 	    (cidp->device == DEVICE_ID_5715C))) {
516 		/*
517 		 * Make sure these indirect-access registers are sane
518 		 * rather than random after power-up or reset
519 		 */
520 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
521 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
522 	}
523 	/*
524 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
525 	 */
526 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
527 
528 	if (cidp->pci_type == BGE_PCI_E) {
529 		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
530 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
531 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
532 		} else
533 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
534 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
535 	}
536 }
537 
538 #ifdef __amd64
539 /*
540  * Distinguish CPU types
541  *
542  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
543  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
544  * for PCI-Express based network interface card. This is the work-around
545  * for those nics.
546  */
547 static boolean_t bge_get_em64t_type(void);
548 #pragma	inline(bge_get_em64t_type)
549 
550 static boolean_t
551 bge_get_em64t_type(void)
552 {
553 
554 	return (x86_vendor == X86_VENDOR_Intel);
555 }
556 #endif
557 
558 /*
559  * Operating register get/set access routines
560  */
561 
562 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
563 #pragma	inline(bge_reg_get32)
564 
565 uint32_t
566 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
567 {
568 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
569 	    (void *)bgep, regno));
570 
571 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
572 }
573 
574 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
575 #pragma	inline(bge_reg_put32)
576 
577 void
578 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
579 {
580 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
581 	    (void *)bgep, regno, data));
582 
583 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
584 	BGE_PCICHK(bgep);
585 }
586 
587 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
588 #pragma	inline(bge_reg_set32)
589 
590 void
591 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
592 {
593 	uint32_t regval;
594 
595 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
596 	    (void *)bgep, regno, bits));
597 
598 	regval = bge_reg_get32(bgep, regno);
599 	regval |= bits;
600 	bge_reg_put32(bgep, regno, regval);
601 }
602 
603 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
604 #pragma	inline(bge_reg_clr32)
605 
606 void
607 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
608 {
609 	uint32_t regval;
610 
611 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
612 	    (void *)bgep, regno, bits));
613 
614 	regval = bge_reg_get32(bgep, regno);
615 	regval &= ~bits;
616 	bge_reg_put32(bgep, regno, regval);
617 }
618 
619 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
620 #pragma	inline(bge_reg_get64)
621 
622 static uint64_t
623 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
624 {
625 	uint64_t regval;
626 
627 #ifdef	__amd64
628 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
629 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
630 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
631 		regval <<= 32;
632 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
633 	} else {
634 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
635 	}
636 #elif defined(__sparc)
637 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
638 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
639 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
640 		regval <<= 32;
641 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
642 	} else {
643 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
644 	}
645 #else
646 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
647 #endif
648 
649 #ifdef	_LITTLE_ENDIAN
650 	regval = (regval >> 32) | (regval << 32);
651 #endif	/* _LITTLE_ENDIAN */
652 
653 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
654 	    (void *)bgep, regno, regval));
655 
656 	return (regval);
657 }
658 
659 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
660 #pragma	inline(bge_reg_put64)
661 
662 static void
663 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
664 {
665 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
666 	    (void *)bgep, regno, data));
667 
668 #ifdef	_LITTLE_ENDIAN
669 	data = ((data >> 32) | (data << 32));
670 #endif	/* _LITTLE_ENDIAN */
671 
672 #ifdef	__amd64
673 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
674 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
675 		ddi_put32(bgep->io_handle,
676 		    PIO_ADDR(bgep, regno), (uint32_t)data);
677 		BGE_PCICHK(bgep);
678 		ddi_put32(bgep->io_handle,
679 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
680 
681 	} else {
682 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
683 	}
684 #elif defined(__sparc)
685 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
686 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
687 		ddi_put32(bgep->io_handle,
688 		    PIO_ADDR(bgep, regno + 4), (uint32_t)data);
689 		BGE_PCICHK(bgep);
690 		ddi_put32(bgep->io_handle,
691 		    PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
692 	} else {
693 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
694 	}
695 #else
696 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
697 #endif
698 
699 	BGE_PCICHK(bgep);
700 }
701 
702 /*
703  * The DDI doesn't provide get/put functions for 128 bit data
704  * so we put RCBs out as two 64-bit chunks instead.
705  */
706 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
707 #pragma	inline(bge_reg_putrcb)
708 
709 static void
710 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
711 {
712 	uint64_t *p;
713 
714 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
715 	    (void *)bgep, addr, rcbp->host_ring_addr,
716 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
717 
718 	ASSERT((addr % sizeof (*rcbp)) == 0);
719 
720 	p = (void *)rcbp;
721 	bge_reg_put64(bgep, addr, *p++);
722 	bge_reg_put64(bgep, addr+8, *p);
723 }
724 
725 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
726 #pragma	inline(bge_mbx_put)
727 
728 void
729 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
730 {
731 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
732 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
733 
734 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
735 	    (void *)bgep, regno, data));
736 
737 	/*
738 	 * Mailbox registers are nominally 64 bits on the 5701, but
739 	 * the MSW isn't used.  On the 5703, they're only 32 bits
740 	 * anyway.  So here we just write the lower(!) 32 bits -
741 	 * remembering that the chip is big-endian, even though the
742 	 * PCI bus is little-endian ...
743 	 */
744 #ifdef	_BIG_ENDIAN
745 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
746 #else
747 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
748 #endif	/* _BIG_ENDIAN */
749 	BGE_PCICHK(bgep);
750 }
751 
752 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
753 #pragma inline(bge_mbx_get)
754 
755 uint32_t
756 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
757 {
758 	uint32_t val32;
759 
760 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
761 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
762 
763 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
764 	    (void *)bgep, regno));
765 
766 #ifdef	_BIG_ENDIAN
767 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
768 #else
769 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
770 #endif	/* _BIG_ENDIAN */
771 	BGE_PCICHK(bgep);
772 
773 	BGE_DEBUG(("bge_mbx_get($%p, 0x%lx) => 0x%08x",
774 	    (void *)bgep, regno, val32));
775 
776 	return (val32);
777 }
778 
779 
780 #if	BGE_DEBUGGING
781 
782 void bge_led_mark(bge_t *bgep);
783 #pragma	no_inline(bge_led_mark)
784 
785 void
786 bge_led_mark(bge_t *bgep)
787 {
788 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
789 	    LED_CONTROL_1000MBPS_LED |
790 	    LED_CONTROL_100MBPS_LED |
791 	    LED_CONTROL_10MBPS_LED;
792 
793 	/*
794 	 * Blink all three LINK LEDs on simultaneously, then all off,
795 	 * then restore to automatic hardware control.  This is used
796 	 * in laboratory testing to trigger a logic analyser or scope.
797 	 */
798 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
799 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
800 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
801 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
802 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
803 }
804 
805 #endif	/* BGE_DEBUGGING */
806 
807 /*
808  * NIC on-chip memory access routines
809  *
810  * Only 32K of NIC memory is visible at a time, controlled by the
811  * Memory Window Base Address Register (in PCI config space).  Once
812  * this is set, the 32K region of NIC-local memory that it refers
813  * to can be directly addressed in the upper 32K of the 64K of PCI
814  * memory space used for the device.
815  */
816 
817 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
818 #pragma	inline(bge_nic_setwin)
819 
820 static void
821 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
822 {
823 	chip_id_t *cidp;
824 
825 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
826 	    (void *)bgep, base));
827 
828 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
829 
830 	/*
831 	 * Don't do repeated zero data writes,
832 	 * if the device is BCM5714C/15C.
833 	 */
834 	cidp = &bgep->chipid;
835 	if ((cidp->device == DEVICE_ID_5714C) ||
836 	    (cidp->device == DEVICE_ID_5715C)) {
837 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
838 			return;
839 		/* Adjust lastWriteZeroData */
840 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
841 		    B_TRUE : B_FALSE);
842 	}
843 #ifdef __sparc
844 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
845 		base = LE_32(base);
846 #endif
847 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
848 }
849 
850 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
851 #pragma	inline(bge_nic_get32)
852 
853 static uint32_t
854 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
855 {
856 	uint32_t data;
857 
858 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
859 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
860 		/* workaround for word swap error */
861 		if (addr & 4)
862 			addr = addr - 4;
863 		else
864 			addr = addr + 4;
865 	}
866 #endif
867 
868 #ifdef __sparc
869 	data = bge_nic_read32(bgep, addr);
870 #else
871 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
872 	addr &= MWBAR_GRANULE_MASK;
873 	addr += NIC_MEM_WINDOW_OFFSET;
874 
875 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
876 #endif
877 
878 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
879 	    (void *)bgep, addr, data));
880 
881 	return (data);
882 }
883 
884 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
885 #pragma inline(bge_nic_put32)
886 
887 void
888 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
889 {
890 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
891 	    (void *)bgep, addr, data));
892 
893 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
894 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
895 		/* workaround for word swap error */
896 		if (addr & 4)
897 			addr = addr - 4;
898 		else
899 			addr = addr + 4;
900 	}
901 #endif
902 
903 #ifdef __sparc
904 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
905 		addr = LE_32(addr);
906 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
907 	data = LE_32(data);
908 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
909 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
910 #else
911 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
912 	addr &= MWBAR_GRANULE_MASK;
913 	addr += NIC_MEM_WINDOW_OFFSET;
914 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
915 	BGE_PCICHK(bgep);
916 #endif
917 }
918 
919 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
920 #pragma	inline(bge_nic_get64)
921 
922 static uint64_t
923 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
924 {
925 	uint64_t data;
926 
927 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
928 	addr &= MWBAR_GRANULE_MASK;
929 	addr += NIC_MEM_WINDOW_OFFSET;
930 
931 #ifdef	__amd64
932 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
933 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
934 		data = ddi_get32(bgep->io_handle,
935 		    PIO_ADDR(bgep, addr + 4));
936 		data <<= 32;
937 		data |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
938 	} else {
939 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
940 	}
941 #elif defined(__sparc)
942 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
943 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
944 		data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
945 		data <<= 32;
946 		data |= ddi_get32(bgep->io_handle,
947 		    PIO_ADDR(bgep, addr + 4));
948 	} else {
949 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
950 	}
951 #else
952 	data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
953 #endif
954 
955 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
956 	    (void *)bgep, addr, data));
957 
958 	return (data);
959 }
960 
961 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
962 #pragma	inline(bge_nic_put64)
963 
964 static void
965 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
966 {
967 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
968 	    (void *)bgep, addr, data));
969 
970 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
971 	addr &= MWBAR_GRANULE_MASK;
972 	addr += NIC_MEM_WINDOW_OFFSET;
973 
974 #ifdef	__amd64
975 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
976 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
977 		ddi_put32(bgep->io_handle,
978 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
979 		BGE_PCICHK(bgep);
980 		ddi_put32(bgep->io_handle,
981 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
982 	} else {
983 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
984 	}
985 #elif defined(__sparc)
986 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
987 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
988 		ddi_put32(bgep->io_handle,
989 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
990 		BGE_PCICHK(bgep);
991 		ddi_put32(bgep->io_handle,
992 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
993 	} else {
994 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
995 	}
996 #else
997 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
998 #endif
999 
1000 	BGE_PCICHK(bgep);
1001 }
1002 
1003 /*
1004  * The DDI doesn't provide get/put functions for 128 bit data
1005  * so we put RCBs out as two 64-bit chunks instead.
1006  */
1007 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
1008 #pragma	inline(bge_nic_putrcb)
1009 
1010 static void
1011 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
1012 {
1013 	uint64_t *p;
1014 
1015 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
1016 	    (void *)bgep, addr, rcbp->host_ring_addr,
1017 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
1018 
1019 	ASSERT((addr % sizeof (*rcbp)) == 0);
1020 
1021 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1022 	addr &= MWBAR_GRANULE_MASK;
1023 	addr += NIC_MEM_WINDOW_OFFSET;
1024 
1025 	p = (void *)rcbp;
1026 #ifdef	__amd64
1027 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type() ||
1028 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1029 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1030 		    (uint32_t)(*p));
1031 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1032 		    (uint32_t)(*p++ >> 32));
1033 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1034 		    (uint32_t)(*p));
1035 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1036 		    (uint32_t)(*p >> 32));
1037 
1038 	} else {
1039 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1040 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1041 	}
1042 #elif defined(__sparc)
1043 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1044 	    DEVICE_5717_SERIES_CHIPSETS(bgep)) {
1045 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1046 		    (uint32_t)(*p));
1047 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1048 		    (uint32_t)(*p++ >> 32));
1049 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1050 		    (uint32_t)(*p));
1051 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1052 		    (uint32_t)(*p >> 32));
1053 	} else {
1054 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1055 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1056 	}
1057 #else
1058 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1059 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1060 #endif
1061 
1062 	BGE_PCICHK(bgep);
1063 }
1064 
1065 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1066 #pragma	inline(bge_nic_zero)
1067 
1068 static void
1069 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1070 {
1071 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1072 	    (void *)bgep, addr, nbytes));
1073 
1074 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1075 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1076 
1077 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1078 	addr &= MWBAR_GRANULE_MASK;
1079 	addr += NIC_MEM_WINDOW_OFFSET;
1080 
1081 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1082 	    nbytes, 1, DDI_DATA_SZ08_ACC);
1083 	BGE_PCICHK(bgep);
1084 }
1085 
1086 /*
1087  * MII (PHY) register get/set access routines
1088  *
1089  * These use the chip's MII auto-access method, controlled by the
1090  * MII Communication register at 0x044c, so the CPU doesn't have
1091  * to fiddle with the individual bits.
1092  */
1093 
1094 #undef	BGE_DBG
1095 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1096 
1097 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1098 				uint16_t data, uint32_t cmd);
1099 #pragma	no_inline(bge_mii_access)
1100 
1101 static uint16_t
1102 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1103 {
1104 	uint32_t timeout;
1105 	uint32_t regval1;
1106 	uint32_t regval2;
1107 
1108 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1109 	    (void *)bgep, regno, data, cmd));
1110 
1111 	ASSERT(mutex_owned(bgep->genlock));
1112 
1113 	/*
1114 	 * Assemble the command ...
1115 	 */
1116 	cmd |= data << MI_COMMS_DATA_SHIFT;
1117 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1118 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1119 	cmd |= MI_COMMS_START;
1120 
1121 	/*
1122 	 * Wait for any command already in progress ...
1123 	 *
1124 	 * Note: this *shouldn't* ever find that there is a command
1125 	 * in progress, because we already hold the <genlock> mutex.
1126 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1127 	 * bit set here -- it seems that the chip can initiate MII
1128 	 * accesses internally, even with polling OFF.
1129 	 */
1130 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1131 	for (timeout = 100; ; ) {
1132 		if ((regval2 & MI_COMMS_START) == 0) {
1133 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1134 			break;
1135 		}
1136 		if (--timeout == 0)
1137 			break;
1138 		drv_usecwait(10);
1139 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1140 	}
1141 
1142 	if (timeout == 0)
1143 		return ((uint16_t)~0u);
1144 
1145 	if (timeout != 100)
1146 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1147 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1148 		    cmd, 10*(100-timeout), regval1, regval2));
1149 
1150 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1151 	for (timeout = 1000; ; ) {
1152 		if ((regval1 & MI_COMMS_START) == 0)
1153 			break;
1154 		if (--timeout == 0)
1155 			break;
1156 		drv_usecwait(10);
1157 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1158 	}
1159 
1160 	/*
1161 	 * Drop out early if the READ FAILED bit is set -- this chip
1162 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1163 	 */
1164 	if (regval2 & MI_COMMS_READ_FAILED)
1165 		return ((uint16_t)~0u);
1166 
1167 	if (timeout == 0)
1168 		return ((uint16_t)~0u);
1169 
1170 	/*
1171 	 * The PRM says to wait 5us after seeing the START bit clear
1172 	 * and then re-read the register to get the final value of the
1173 	 * data field, in order to avoid a race condition where the
1174 	 * START bit is clear but the data field isn't yet valid.
1175 	 *
1176 	 * Note: we don't actually seem to be encounter this race;
1177 	 * except when the START bit is seen set again (see below),
1178 	 * the data field doesn't change during this 5us interval.
1179 	 */
1180 	drv_usecwait(5);
1181 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1182 
1183 	/*
1184 	 * Unfortunately, when following the PRMs instructions above,
1185 	 * we have occasionally seen the START bit set again(!) in the
1186 	 * value read after the 5us delay. This seems to be due to the
1187 	 * chip autonomously starting another MII access internally.
1188 	 * In such cases, the command/data/etc fields relate to the
1189 	 * internal command, rather than the one that we thought had
1190 	 * just finished.  So in this case, we fall back to returning
1191 	 * the data from the original read that showed START clear.
1192 	 */
1193 	if (regval2 & MI_COMMS_START) {
1194 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1195 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1196 		    cmd, regval1, regval2));
1197 		regval2 = regval1;
1198 	}
1199 
1200 	if (regval2 & MI_COMMS_START)
1201 		return ((uint16_t)~0u);
1202 
1203 	if (regval2 & MI_COMMS_READ_FAILED)
1204 		return ((uint16_t)~0u);
1205 
1206 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1207 }
1208 
1209 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1210 #pragma	no_inline(bge_mii_get16)
1211 
1212 uint16_t
1213 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1214 {
1215 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1216 	    (void *)bgep, regno));
1217 
1218 	ASSERT(mutex_owned(bgep->genlock));
1219 
1220 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1221 	    (regno == MII_MSCONTROL)))
1222 		return (0);
1223 
1224 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1225 }
1226 
1227 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1228 #pragma	no_inline(bge_mii_put16)
1229 
1230 void
1231 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1232 {
1233 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1234 	    (void *)bgep, regno, data));
1235 
1236 	ASSERT(mutex_owned(bgep->genlock));
1237 
1238 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1239 	    (regno == MII_MSCONTROL)))
1240 		return;
1241 
1242 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1243 }
1244 
1245 #undef	BGE_DBG
1246 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1247 
1248 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1249 
1250 /*
1251  * Basic SEEPROM get/set access routine
1252  *
1253  * This uses the chip's SEEPROM auto-access method, controlled by the
1254  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1255  * doesn't have to fiddle with the individual bits.
1256  *
1257  * The caller should hold <genlock> and *also* have already acquired
1258  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1259  *
1260  * Return value:
1261  *	0 on success,
1262  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1263  *	EPROTO on other h/w or s/w errors.
1264  *
1265  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1266  * from a (successful) SEEPROM_ACCESS_READ.
1267  */
1268 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1269 				uint32_t *dp);
1270 #pragma	no_inline(bge_seeprom_access)
1271 
1272 static int
1273 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1274 {
1275 	uint32_t tries;
1276 	uint32_t regval;
1277 
1278 	ASSERT(mutex_owned(bgep->genlock));
1279 
1280 	/*
1281 	 * On the newer chips that support both SEEPROM & Flash, we need
1282 	 * to specifically enable SEEPROM access (Flash is the default).
1283 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1284 	 * and the NVM control registers don't exist ...
1285 	 */
1286 	switch (bgep->chipid.nvtype) {
1287 	case BGE_NVTYPE_NONE:
1288 	case BGE_NVTYPE_UNKNOWN:
1289 		_NOTE(NOTREACHED)
1290 	case BGE_NVTYPE_SEEPROM:
1291 		break;
1292 
1293 	case BGE_NVTYPE_LEGACY_SEEPROM:
1294 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1295 	case BGE_NVTYPE_BUFFERED_FLASH:
1296 	default:
1297 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1298 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1299 		break;
1300 	}
1301 
1302 	/*
1303 	 * Check there's no command in progress.
1304 	 *
1305 	 * Note: this *shouldn't* ever find that there is a command
1306 	 * in progress, because we already hold the <genlock> mutex.
1307 	 * Also, to ensure we don't have a conflict with the chip's
1308 	 * internal firmware or a process accessing the same (shared)
1309 	 * SEEPROM through the other port of a 5704, we've already
1310 	 * been through the "software arbitration" protocol.
1311 	 * So this is just a final consistency check: we shouldn't
1312 	 * see EITHER the START bit (command started but not complete)
1313 	 * OR the COMPLETE bit (command completed but not cleared).
1314 	 */
1315 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1316 	if (regval & SEEPROM_ACCESS_START)
1317 		return (EPROTO);
1318 	if (regval & SEEPROM_ACCESS_COMPLETE)
1319 		return (EPROTO);
1320 
1321 	/*
1322 	 * Assemble the command ...
1323 	 */
1324 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1325 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1326 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1327 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1328 	cmd |= SEEPROM_ACCESS_START;
1329 	cmd |= SEEPROM_ACCESS_COMPLETE;
1330 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1331 
1332 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1333 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1334 
1335 	/*
1336 	 * By observation, a successful access takes ~20us on a 5703/4,
1337 	 * but apparently much longer (up to 1000us) on the obsolescent
1338 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1339 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1340 	 * out interrupts for longer than necessary. So we'll allow up
1341 	 * to 1000us ...
1342 	 */
1343 	for (tries = 0; tries < 1000; ++tries) {
1344 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1345 		if (regval & SEEPROM_ACCESS_COMPLETE)
1346 			break;
1347 		drv_usecwait(1);
1348 	}
1349 
1350 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1351 		/*
1352 		 * All OK; read the SEEPROM data register, then write back
1353 		 * the value read from the address register in order to
1354 		 * clear the <complete> bit and leave the SEEPROM access
1355 		 * state machine idle, ready for the next access ...
1356 		 */
1357 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1358 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1359 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1360 		return (0);
1361 	}
1362 
1363 	/*
1364 	 * Hmm ... what happened here?
1365 	 *
1366 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1367 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1368 	 * and didn't respond to being addressed. Either way, it's left
1369 	 * the SEEPROM access state machine wedged. So we'll reset it
1370 	 * before we leave, so it's ready for next time ...
1371 	 */
1372 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1373 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1374 	return (ENODATA);
1375 }
1376 
1377 /*
1378  * Basic Flash get/set access routine
1379  *
1380  * These use the chip's Flash auto-access method, controlled by the
1381  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1382  * fiddle with the individual bits.
1383  *
1384  * The caller should hold <genlock> and *also* have already acquired
1385  * the right to access the Flash, via bge_nvmem_acquire() above.
1386  *
1387  * Return value:
1388  *	0 on success,
1389  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1390  *	ENODEV if the NVmem device is missing or otherwise unusable
1391  *
1392  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1393  * from a (successful) NVM_FLASH_CMD_RD.
1394  */
1395 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1396 				uint32_t *dp);
1397 #pragma	no_inline(bge_flash_access)
1398 
1399 static int
1400 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1401 {
1402 	uint32_t tries;
1403 	uint32_t regval;
1404 
1405 	ASSERT(mutex_owned(bgep->genlock));
1406 
1407 	/*
1408 	 * On the newer chips that support both SEEPROM & Flash, we need
1409 	 * to specifically disable SEEPROM access while accessing Flash.
1410 	 * The older chips don't support Flash, and the NVM registers don't
1411 	 * exist, so we shouldn't be here at all!
1412 	 */
1413 	switch (bgep->chipid.nvtype) {
1414 	case BGE_NVTYPE_NONE:
1415 	case BGE_NVTYPE_UNKNOWN:
1416 		_NOTE(NOTREACHED)
1417 	case BGE_NVTYPE_SEEPROM:
1418 		return (ENODEV);
1419 
1420 	case BGE_NVTYPE_LEGACY_SEEPROM:
1421 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1422 	case BGE_NVTYPE_BUFFERED_FLASH:
1423 	default:
1424 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1425 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1426 		break;
1427 	}
1428 
1429 	/*
1430 	 * Assemble the command ...
1431 	 */
1432 	addr &= NVM_FLASH_ADDR_MASK;
1433 	cmd |= NVM_FLASH_CMD_DOIT;
1434 	cmd |= NVM_FLASH_CMD_FIRST;
1435 	cmd |= NVM_FLASH_CMD_LAST;
1436 	cmd |= NVM_FLASH_CMD_DONE;
1437 
1438 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1439 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1440 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1441 
1442 	/*
1443 	 * Allow up to 1000ms ...
1444 	 */
1445 	for (tries = 0; tries < 1000; ++tries) {
1446 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1447 		if (regval & NVM_FLASH_CMD_DONE)
1448 			break;
1449 		drv_usecwait(1);
1450 	}
1451 
1452 	if (regval & NVM_FLASH_CMD_DONE) {
1453 		/*
1454 		 * All OK; read the data from the Flash read register
1455 		 */
1456 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1457 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1458 		return (0);
1459 	}
1460 
1461 	/*
1462 	 * Hmm ... what happened here?
1463 	 *
1464 	 * Most likely, the user addressed a non-existent Flash. Or
1465 	 * maybe the Flash was busy internally (e.g. processing a write)
1466 	 * and didn't respond to being addressed. Either way, there's
1467 	 * nothing we can here ...
1468 	 */
1469 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1470 	return (ENODATA);
1471 }
1472 
1473 /*
1474  * The next two functions regulate access to the NVram (if fitted).
1475  *
1476  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1477  * (SPI) interface, but they can be accessed through either port. These
1478  * are managed by different instance of this driver and have no software
1479  * state in common.
1480  *
1481  * In addition (and even on a single core chip) the chip's internal
1482  * firmware can access the SEEPROM/Flash, most notably after a RESET
1483  * when it may download code to run internally.
1484  *
1485  * So we need to arbitrate between these various software agents.  For
1486  * this purpose, the chip provides the Software Arbitration Register,
1487  * which implements hardware(!) arbitration.
1488  *
1489  * This functionality didn't exist on older (5700/5701) chips, so there's
1490  * nothing we can do by way of arbitration on those; also, if there's no
1491  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1492  * nothing to do.
1493  *
1494  * The internal firmware appears to use Request 0, which is the highest
1495  * priority.  So we'd like to use Request 2, leaving one higher and one
1496  * lower for any future developments ... but apparently this doesn't
1497  * always work.  So for now, the code uses Request 1 ;-(
1498  */
1499 
1500 #define	NVM_READ_REQ	NVM_READ_REQ1
1501 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1502 #define	NVM_SET_REQ	NVM_SET_REQ1
1503 
1504 static void bge_nvmem_relinquish(bge_t *bgep);
1505 #pragma	no_inline(bge_nvmem_relinquish)
1506 
1507 static void
1508 bge_nvmem_relinquish(bge_t *bgep)
1509 {
1510 	ASSERT(mutex_owned(bgep->genlock));
1511 
1512 	switch (bgep->chipid.nvtype) {
1513 	case BGE_NVTYPE_NONE:
1514 	case BGE_NVTYPE_UNKNOWN:
1515 		_NOTE(NOTREACHED)
1516 		return;
1517 
1518 	case BGE_NVTYPE_SEEPROM:
1519 		/*
1520 		 * No arbitration performed, no release needed
1521 		 */
1522 		return;
1523 
1524 	case BGE_NVTYPE_LEGACY_SEEPROM:
1525 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1526 	case BGE_NVTYPE_BUFFERED_FLASH:
1527 	default:
1528 		break;
1529 	}
1530 
1531 	/*
1532 	 * Our own request should be present (whether or not granted) ...
1533 	 */
1534 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1535 
1536 	/*
1537 	 * ... this will make it go away.
1538 	 */
1539 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1540 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1541 }
1542 
1543 /*
1544  * Arbitrate for access to the NVmem, if necessary
1545  *
1546  * Return value:
1547  *	0 on success
1548  *	EAGAIN if the device is in use (retryable)
1549  *	ENODEV if the NVmem device is missing or otherwise unusable
1550  */
1551 static int bge_nvmem_acquire(bge_t *bgep);
1552 #pragma	no_inline(bge_nvmem_acquire)
1553 
1554 static int
1555 bge_nvmem_acquire(bge_t *bgep)
1556 {
1557 	uint32_t regval;
1558 	uint32_t tries;
1559 
1560 	ASSERT(mutex_owned(bgep->genlock));
1561 
1562 	switch (bgep->chipid.nvtype) {
1563 	case BGE_NVTYPE_NONE:
1564 	case BGE_NVTYPE_UNKNOWN:
1565 		/*
1566 		 * Access denied: no (recognisable) device fitted
1567 		 */
1568 		return (ENODEV);
1569 
1570 	case BGE_NVTYPE_SEEPROM:
1571 		/*
1572 		 * Access granted: no arbitration needed (or possible)
1573 		 */
1574 		return (0);
1575 
1576 	case BGE_NVTYPE_LEGACY_SEEPROM:
1577 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1578 	case BGE_NVTYPE_BUFFERED_FLASH:
1579 	default:
1580 		/*
1581 		 * Access conditional: conduct arbitration protocol
1582 		 */
1583 		break;
1584 	}
1585 
1586 	/*
1587 	 * We're holding the per-port mutex <genlock>, so no-one other
1588 	 * thread can be attempting to access the NVmem through *this*
1589 	 * port. But it could be in use by the *other* port (of a 5704),
1590 	 * or by the chip's internal firmware, so we have to go through
1591 	 * the full (hardware) arbitration protocol ...
1592 	 *
1593 	 * Note that *because* we're holding <genlock>, the interrupt handler
1594 	 * won't be able to progress.  So we're only willing to spin for a
1595 	 * fairly short time.  Specifically:
1596 	 *
1597 	 *	We *must* wait long enough for the hardware to resolve all
1598 	 *	requests and determine the winner.  Fortunately, this is
1599 	 *	"almost instantaneous", even as observed by GHz CPUs.
1600 	 *
1601 	 *	A successful access by another Solaris thread (via either
1602 	 *	port) typically takes ~20us.  So waiting a bit longer than
1603 	 *	that will give a good chance of success, if the other user
1604 	 *	*is* another thread on the other port.
1605 	 *
1606 	 *	However, the internal firmware can hold on to the NVmem
1607 	 *	for *much* longer: at least 10 milliseconds just after a
1608 	 *	RESET, and maybe even longer if the NVmem actually contains
1609 	 *	code to download and run on the internal CPUs.
1610 	 *
1611 	 * So, we'll allow 50us; if that's not enough then it's up to the
1612 	 * caller to retry later (hence the choice of return code EAGAIN).
1613 	 */
1614 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1615 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1616 
1617 	for (tries = 0; tries < 50; ++tries) {
1618 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1619 		if (regval & NVM_WON_REQ1)
1620 			break;
1621 		drv_usecwait(1);
1622 	}
1623 
1624 	if (regval & NVM_WON_REQ1) {
1625 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1626 		return (0);
1627 	}
1628 
1629 	/*
1630 	 * Somebody else must be accessing the NVmem, so abandon our
1631 	 * attempt take control of it.  The caller can try again later ...
1632 	 */
1633 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1634 	bge_nvmem_relinquish(bgep);
1635 	return (EAGAIN);
1636 }
1637 
1638 /*
1639  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1640  * write protect line in such a way that the NVmem is protected when
1641  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1642  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1643  *
1644  * Note: there's only one set of GPIO pins on a 5704, even though they
1645  * can be accessed through either port.  So the chip has to resolve what
1646  * happens if the two ports program a single pin differently ... the rule
1647  * it uses is that if the ports disagree about the *direction* of a pin,
1648  * "output" wins over "input", but if they disagree about its *value* as
1649  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1650  * wins, and the external signal does whatever the external circuitry
1651  * defines as the default -- which we've assumed is the PROTECTED state.
1652  * So, we always change GPIO1 back to being an *input* whenever we're not
1653  * specifically using it to unprotect the NVmem. This allows either port
1654  * to update the NVmem, although obviously only one at a time!
1655  *
1656  * The caller should hold <genlock> and *also* have already acquired the
1657  * right to access the NVmem, via bge_nvmem_acquire() above.
1658  */
1659 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1660 #pragma	inline(bge_nvmem_protect)
1661 
1662 static void
1663 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1664 {
1665 	uint32_t regval;
1666 
1667 	ASSERT(mutex_owned(bgep->genlock));
1668 
1669 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1670 	if (protect) {
1671 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1672 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1673 	} else {
1674 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1675 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1676 	}
1677 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1678 }
1679 
1680 /*
1681  * Now put it all together ...
1682  *
1683  * Try to acquire control of the NVmem; if successful, then:
1684  *	unprotect it (if we want to write to it)
1685  *	perform the requested access
1686  *	reprotect it (after a write)
1687  *	relinquish control
1688  *
1689  * Return value:
1690  *	0 on success,
1691  *	EAGAIN if the device is in use (retryable)
1692  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1693  *	ENODEV if the NVmem device is missing or otherwise unusable
1694  *	EPROTO on other h/w or s/w errors.
1695  */
1696 static int
1697 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1698 {
1699 	int err;
1700 
1701 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1702 		switch (cmd) {
1703 		case BGE_SEE_READ:
1704 			err = bge_seeprom_access(bgep,
1705 			    SEEPROM_ACCESS_READ, addr, dp);
1706 			break;
1707 
1708 		case BGE_SEE_WRITE:
1709 			bge_nvmem_protect(bgep, B_FALSE);
1710 			err = bge_seeprom_access(bgep,
1711 			    SEEPROM_ACCESS_WRITE, addr, dp);
1712 			bge_nvmem_protect(bgep, B_TRUE);
1713 			break;
1714 
1715 		case BGE_FLASH_READ:
1716 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1717 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1718 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1719 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1720 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1721 				    NVM_ACCESS_ENABLE);
1722 			}
1723 			err = bge_flash_access(bgep,
1724 			    NVM_FLASH_CMD_RD, addr, dp);
1725 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1726 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1727 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1728 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1729 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1730 				    NVM_ACCESS_ENABLE);
1731 			}
1732 			break;
1733 
1734 		case BGE_FLASH_WRITE:
1735 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1736 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1737 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1738 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1739 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1740 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1741 			}
1742 			bge_nvmem_protect(bgep, B_FALSE);
1743 			err = bge_flash_access(bgep,
1744 			    NVM_FLASH_CMD_WR, addr, dp);
1745 			bge_nvmem_protect(bgep, B_TRUE);
1746 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1747 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1748 			    DEVICE_5717_SERIES_CHIPSETS(bgep) ||
1749 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1750 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1751 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1752 			}
1753 
1754 			break;
1755 
1756 		default:
1757 			_NOTE(NOTREACHED)
1758 			break;
1759 		}
1760 		bge_nvmem_relinquish(bgep);
1761 	}
1762 
1763 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1764 	return (err);
1765 }
1766 
1767 /*
1768  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1769  */
1770 static uint64_t bge_get_nvmac(bge_t *bgep);
1771 #pragma no_inline(bge_get_nvmac)
1772 
1773 static uint64_t
1774 bge_get_nvmac(bge_t *bgep)
1775 {
1776 	uint32_t mac_high;
1777 	uint32_t mac_low;
1778 	uint32_t addr;
1779 	uint32_t cmd;
1780 	uint64_t mac;
1781 
1782 	BGE_TRACE(("bge_get_nvmac($%p)",
1783 	    (void *)bgep));
1784 
1785 	switch (bgep->chipid.nvtype) {
1786 	case BGE_NVTYPE_NONE:
1787 	case BGE_NVTYPE_UNKNOWN:
1788 	default:
1789 		return (0ULL);
1790 
1791 	case BGE_NVTYPE_SEEPROM:
1792 	case BGE_NVTYPE_LEGACY_SEEPROM:
1793 		cmd = BGE_SEE_READ;
1794 		break;
1795 
1796 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1797 	case BGE_NVTYPE_BUFFERED_FLASH:
1798 		cmd = BGE_FLASH_READ;
1799 		break;
1800 	}
1801 
1802 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1803 		addr = NVMEM_DATA_MAC_ADDRESS_5906;
1804 	else
1805 		addr = NVMEM_DATA_MAC_ADDRESS;
1806 
1807 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1808 		return (0ULL);
1809 	addr += 4;
1810 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1811 		return (0ULL);
1812 
1813 	/*
1814 	 * The Broadcom chip is natively BIG-endian, so that's how the
1815 	 * MAC address is represented in NVmem.  We may need to swap it
1816 	 * around on a little-endian host ...
1817 	 */
1818 #ifdef	_BIG_ENDIAN
1819 	mac = mac_high;
1820 	mac = mac << 32;
1821 	mac |= mac_low;
1822 #else
1823 	mac = BGE_BSWAP_32(mac_high);
1824 	mac = mac << 32;
1825 	mac |= BGE_BSWAP_32(mac_low);
1826 #endif	/* _BIG_ENDIAN */
1827 
1828 	return (mac);
1829 }
1830 
1831 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1832 
1833 /*
1834  * Dummy version for when we're not supporting NVmem access
1835  */
1836 static uint64_t bge_get_nvmac(bge_t *bgep);
1837 #pragma inline(bge_get_nvmac)
1838 
1839 static uint64_t
1840 bge_get_nvmac(bge_t *bgep)
1841 {
1842 	_NOTE(ARGUNUSED(bgep))
1843 	return (0ULL);
1844 }
1845 
1846 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1847 
1848 /*
1849  * Determine the type of NVmem that is (or may be) attached to this chip,
1850  */
1851 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1852 #pragma no_inline(bge_nvmem_id)
1853 
1854 static enum bge_nvmem_type
1855 bge_nvmem_id(bge_t *bgep)
1856 {
1857 	enum bge_nvmem_type nvtype;
1858 	uint32_t config1;
1859 
1860 	BGE_TRACE(("bge_nvmem_id($%p)",
1861 	    (void *)bgep));
1862 
1863 	switch (bgep->chipid.device) {
1864 	default:
1865 		/*
1866 		 * We shouldn't get here; it means we don't recognise
1867 		 * the chip, which means we don't know how to determine
1868 		 * what sort of NVmem (if any) it has.  So we'll say
1869 		 * NONE, to disable the NVmem access code ...
1870 		 */
1871 		nvtype = BGE_NVTYPE_NONE;
1872 		break;
1873 
1874 	case DEVICE_ID_5700:
1875 	case DEVICE_ID_5700x:
1876 	case DEVICE_ID_5701:
1877 		/*
1878 		 * These devices support *only* SEEPROMs
1879 		 */
1880 		nvtype = BGE_NVTYPE_SEEPROM;
1881 		break;
1882 
1883 	case DEVICE_ID_5702:
1884 	case DEVICE_ID_5702fe:
1885 	case DEVICE_ID_5703C:
1886 	case DEVICE_ID_5703S:
1887 	case DEVICE_ID_5704C:
1888 	case DEVICE_ID_5704S:
1889 	case DEVICE_ID_5704:
1890 	case DEVICE_ID_5705M:
1891 	case DEVICE_ID_5705C:
1892 	case DEVICE_ID_5705_2:
1893 	case DEVICE_ID_5718:
1894 	case DEVICE_ID_5780:
1895 	case DEVICE_ID_5782:
1896 	case DEVICE_ID_5785:
1897 	case DEVICE_ID_5787:
1898 	case DEVICE_ID_5787M:
1899 	case DEVICE_ID_5788:
1900 	case DEVICE_ID_5789:
1901 	case DEVICE_ID_5751:
1902 	case DEVICE_ID_5751M:
1903 	case DEVICE_ID_5752:
1904 	case DEVICE_ID_5752M:
1905 	case DEVICE_ID_5754:
1906 	case DEVICE_ID_5755:
1907 	case DEVICE_ID_5755M:
1908 	case DEVICE_ID_5756M:
1909 	case DEVICE_ID_5721:
1910 	case DEVICE_ID_5722:
1911 	case DEVICE_ID_5723:
1912 	case DEVICE_ID_5761:
1913 	case DEVICE_ID_5761E:
1914 	case DEVICE_ID_5764:
1915 	case DEVICE_ID_5714C:
1916 	case DEVICE_ID_5714S:
1917 	case DEVICE_ID_5715C:
1918 	case DEVICE_ID_5715S:
1919 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1920 		if (config1 & NVM_CFG1_FLASH_MODE)
1921 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1922 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1923 			else
1924 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1925 		else
1926 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1927 		break;
1928 	case DEVICE_ID_5906:
1929 	case DEVICE_ID_5906M:
1930 		nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1931 		break;
1932 	}
1933 
1934 	return (nvtype);
1935 }
1936 
1937 #undef	BGE_DBG
1938 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1939 
1940 static void
1941 bge_init_recv_rule(bge_t *bgep)
1942 {
1943 	bge_recv_rule_t *rulep = bgep->recv_rules;
1944 	uint32_t i;
1945 
1946 	/*
1947 	 * Initialize receive rule registers.
1948 	 * Note that rules may persist across each bge_m_start/stop() call.
1949 	 */
1950 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1951 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1952 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1953 	}
1954 }
1955 
1956 /*
1957  * Using the values captured by bge_chip_cfg_init(), and additional probes
1958  * as required, characterise the chip fully: determine the label by which
1959  * to refer to this chip, the correct settings for various registers, and
1960  * of course whether the device and/or subsystem are supported!
1961  */
1962 int bge_chip_id_init(bge_t *bgep);
1963 #pragma	no_inline(bge_chip_id_init)
1964 
1965 int
1966 bge_chip_id_init(bge_t *bgep)
1967 {
1968 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1969 	boolean_t sys_ok;
1970 	boolean_t dev_ok;
1971 	chip_id_t *cidp;
1972 	uint32_t subid;
1973 	char *devname;
1974 	char *sysname;
1975 	int *ids;
1976 	int err;
1977 	uint_t i;
1978 
1979 	sys_ok = dev_ok = B_FALSE;
1980 	cidp = &bgep->chipid;
1981 
1982 	/*
1983 	 * Check the PCI device ID to determine the generic chip type and
1984 	 * select parameters that depend on this.
1985 	 *
1986 	 * Note: because the SPARC platforms in general don't fit the
1987 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1988 	 * as zero - which is why we use <asic_rev> rather than <revision>
1989 	 * below ...
1990 	 *
1991 	 * Note: in general we can't distinguish between the Copper/SerDes
1992 	 * versions by ID alone, as some Copper devices (e.g. some but not
1993 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1994 	 * treat them the same here, and the MII code works out the media
1995 	 * type later on ...
1996 	 */
1997 	cidp->mbuf_base = bge_mbuf_pool_base;
1998 	cidp->mbuf_length = bge_mbuf_pool_len;
1999 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
2000 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
2001 	cidp->pci_type = BGE_PCI_X;
2002 	cidp->statistic_type = BGE_STAT_BLK;
2003 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
2004 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
2005 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
2006 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
2007 	cidp->rx_count_norm = bge_rx_count_norm;
2008 	cidp->tx_ticks_norm = bge_tx_ticks_norm;
2009 	cidp->tx_count_norm = bge_tx_count_norm;
2010 	cidp->mask_pci_int = MHCR_MASK_PCI_INT_OUTPUT;
2011 
2012 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
2013 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
2014 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
2015 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
2016 
2017 	cidp->msi_enabled = B_FALSE;
2018 
2019 	switch (cidp->device) {
2020 	case DEVICE_ID_5718:
2021 		cidp->chip_label = 5718;
2022 		cidp->msi_enabled = bge_enable_msi;
2023 #ifdef __sparc
2024 		cidp->mask_pci_int = LE_32(MHCR_MASK_PCI_INT_OUTPUT);
2025 #endif
2026 		cidp->bge_dma_rwctrl = LE_32(PDRWCR_VAR_5717);
2027 		cidp->pci_type = BGE_PCI_E;
2028 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2029 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5717;
2030 		cidp->mbuf_hi_water = MBUF_HIWAT_5717;
2031 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2032 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2033 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2034 		cidp->bge_mlcr_default = MLCR_DEFAULT_5717;
2035 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2036 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2037 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2038 		cidp->statistic_type = BGE_STAT_REG;
2039 		dev_ok = B_TRUE;
2040 		break;
2041 
2042 	case DEVICE_ID_5700:
2043 	case DEVICE_ID_5700x:
2044 		cidp->chip_label = 5700;
2045 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2046 		break;
2047 
2048 	case DEVICE_ID_5701:
2049 		cidp->chip_label = 5701;
2050 		dev_ok = B_TRUE;
2051 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2052 		break;
2053 
2054 	case DEVICE_ID_5702:
2055 	case DEVICE_ID_5702fe:
2056 		cidp->chip_label = 5702;
2057 		dev_ok = B_TRUE;
2058 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2059 		cidp->pci_type = BGE_PCI;
2060 		break;
2061 
2062 	case DEVICE_ID_5703C:
2063 	case DEVICE_ID_5703S:
2064 	case DEVICE_ID_5703:
2065 		/*
2066 		 * Revision A0 of the 5703/5793 had various errata
2067 		 * that we can't or don't work around, so it's not
2068 		 * supported, but all later versions are
2069 		 */
2070 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2071 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2072 			dev_ok = B_TRUE;
2073 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2074 		break;
2075 
2076 	case DEVICE_ID_5704C:
2077 	case DEVICE_ID_5704S:
2078 	case DEVICE_ID_5704:
2079 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2080 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
2081 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
2082 		dev_ok = B_TRUE;
2083 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2084 		break;
2085 
2086 	case DEVICE_ID_5705C:
2087 	case DEVICE_ID_5705M:
2088 	case DEVICE_ID_5705MA3:
2089 	case DEVICE_ID_5705F:
2090 	case DEVICE_ID_5705_2:
2091 	case DEVICE_ID_5754:
2092 		if (cidp->device == DEVICE_ID_5754) {
2093 			cidp->chip_label = 5754;
2094 			cidp->pci_type = BGE_PCI_E;
2095 		} else {
2096 			cidp->chip_label = 5705;
2097 			cidp->pci_type = BGE_PCI;
2098 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2099 		}
2100 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2101 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2102 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2103 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2104 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2105 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2106 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2107 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2108 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2109 		cidp->statistic_type = BGE_STAT_REG;
2110 		dev_ok = B_TRUE;
2111 		break;
2112 
2113 	case DEVICE_ID_5906:
2114 	case DEVICE_ID_5906M:
2115 		cidp->chip_label = 5906;
2116 		cidp->pci_type = BGE_PCI_E;
2117 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2118 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2119 		cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2120 		cidp->mbuf_base = bge_mbuf_pool_base;
2121 		cidp->mbuf_length = bge_mbuf_pool_len;
2122 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2123 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2124 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2125 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2126 		cidp->statistic_type = BGE_STAT_REG;
2127 		dev_ok = B_TRUE;
2128 		break;
2129 
2130 	case DEVICE_ID_5753:
2131 		cidp->chip_label = 5753;
2132 		cidp->pci_type = BGE_PCI_E;
2133 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2134 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2135 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2136 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2137 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2138 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2139 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2140 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2141 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2142 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2143 		cidp->statistic_type = BGE_STAT_REG;
2144 		dev_ok = B_TRUE;
2145 		break;
2146 
2147 	case DEVICE_ID_5755:
2148 	case DEVICE_ID_5755M:
2149 		cidp->chip_label = 5755;
2150 		cidp->pci_type = BGE_PCI_E;
2151 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2152 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2153 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2154 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2155 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2156 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2157 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2158 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2159 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2160 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2161 		if (cidp->device == DEVICE_ID_5755M)
2162 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2163 		cidp->statistic_type = BGE_STAT_REG;
2164 		dev_ok = B_TRUE;
2165 		break;
2166 
2167 	case DEVICE_ID_5756M:
2168 		/*
2169 		 * This is nearly identical to the 5755M.
2170 		 * (Actually reports the 5755 chip ID.)
2171 		 */
2172 		cidp->chip_label = 5756;
2173 		cidp->pci_type = BGE_PCI_E;
2174 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2175 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2176 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2177 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2178 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2179 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2180 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2181 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2182 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2183 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2184 		cidp->statistic_type = BGE_STAT_REG;
2185 		dev_ok = B_TRUE;
2186 		break;
2187 
2188 	case DEVICE_ID_5787:
2189 	case DEVICE_ID_5787M:
2190 		cidp->chip_label = 5787;
2191 		cidp->pci_type = BGE_PCI_E;
2192 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2193 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2194 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2195 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2196 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2197 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2198 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2199 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2200 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2201 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2202 		cidp->statistic_type = BGE_STAT_REG;
2203 		dev_ok = B_TRUE;
2204 		break;
2205 
2206 	case DEVICE_ID_5723:
2207 	case DEVICE_ID_5761:
2208 	case DEVICE_ID_5761E:
2209 		cidp->msi_enabled = bge_enable_msi;
2210 		/*
2211 		 * We don't use MSI for BCM5764 and BCM5785, as the
2212 		 * status block may fail to update when the network
2213 		 * traffic is heavy.
2214 		 */
2215 		/* FALLTHRU */
2216 	case DEVICE_ID_5785:
2217 	case DEVICE_ID_5764:
2218 		if (cidp->device == DEVICE_ID_5723)
2219 			cidp->chip_label = 5723;
2220 		else if (cidp->device == DEVICE_ID_5764)
2221 			cidp->chip_label = 5764;
2222 		else if (cidp->device == DEVICE_ID_5785)
2223 			cidp->chip_label = 5785;
2224 		else
2225 			cidp->chip_label = 5761;
2226 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2227 		cidp->pci_type = BGE_PCI_E;
2228 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2229 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2230 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2231 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2232 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2233 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2234 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2235 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2236 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2237 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2238 		cidp->statistic_type = BGE_STAT_REG;
2239 		dev_ok = B_TRUE;
2240 		break;
2241 
2242 	/* PCI-X device, identical to 5714 */
2243 	case DEVICE_ID_5780:
2244 		cidp->chip_label = 5780;
2245 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2246 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2247 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2248 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2249 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2250 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2251 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2252 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2253 		cidp->statistic_type = BGE_STAT_REG;
2254 		dev_ok = B_TRUE;
2255 		break;
2256 
2257 	case DEVICE_ID_5782:
2258 		/*
2259 		 * Apart from the label, we treat this as a 5705(?)
2260 		 */
2261 		cidp->chip_label = 5782;
2262 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2263 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2264 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2265 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2266 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2267 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2268 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2269 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2270 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2271 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2272 		cidp->statistic_type = BGE_STAT_REG;
2273 		dev_ok = B_TRUE;
2274 		break;
2275 
2276 	case DEVICE_ID_5788:
2277 		/*
2278 		 * Apart from the label, we treat this as a 5705(?)
2279 		 */
2280 		cidp->chip_label = 5788;
2281 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2282 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2283 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2284 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2285 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2286 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2287 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2288 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2289 		cidp->statistic_type = BGE_STAT_REG;
2290 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2291 		dev_ok = B_TRUE;
2292 		break;
2293 
2294 	case DEVICE_ID_5714C:
2295 		if (cidp->revision >= REVISION_ID_5714_A2)
2296 			cidp->msi_enabled = bge_enable_msi;
2297 		/* FALLTHRU */
2298 	case DEVICE_ID_5714S:
2299 		cidp->chip_label = 5714;
2300 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2301 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2302 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2303 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2304 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2305 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2306 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2307 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2308 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2309 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2310 		cidp->pci_type = BGE_PCI_E;
2311 		cidp->statistic_type = BGE_STAT_REG;
2312 		dev_ok = B_TRUE;
2313 		break;
2314 
2315 	case DEVICE_ID_5715C:
2316 	case DEVICE_ID_5715S:
2317 		cidp->chip_label = 5715;
2318 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2319 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2320 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2321 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2322 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2323 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2324 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2325 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2326 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2327 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2328 		cidp->pci_type = BGE_PCI_E;
2329 		cidp->statistic_type = BGE_STAT_REG;
2330 		if (cidp->revision >= REVISION_ID_5715_A2)
2331 			cidp->msi_enabled = bge_enable_msi;
2332 		dev_ok = B_TRUE;
2333 		break;
2334 
2335 	case DEVICE_ID_5721:
2336 		cidp->chip_label = 5721;
2337 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2338 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2339 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2340 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2341 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2342 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2343 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2344 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2345 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2346 		cidp->pci_type = BGE_PCI_E;
2347 		cidp->statistic_type = BGE_STAT_REG;
2348 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2349 		dev_ok = B_TRUE;
2350 		break;
2351 
2352 	case DEVICE_ID_5722:
2353 		cidp->chip_label = 5722;
2354 		cidp->pci_type = BGE_PCI_E;
2355 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2356 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2357 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2358 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2359 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2360 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2361 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2362 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2363 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2364 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2365 		cidp->statistic_type = BGE_STAT_REG;
2366 		dev_ok = B_TRUE;
2367 		break;
2368 
2369 	case DEVICE_ID_5751:
2370 	case DEVICE_ID_5751M:
2371 		cidp->chip_label = 5751;
2372 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2373 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2374 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2375 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2376 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2377 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2378 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2379 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2380 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2381 		cidp->pci_type = BGE_PCI_E;
2382 		cidp->statistic_type = BGE_STAT_REG;
2383 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2384 		dev_ok = B_TRUE;
2385 		break;
2386 
2387 	case DEVICE_ID_5752:
2388 	case DEVICE_ID_5752M:
2389 		cidp->chip_label = 5752;
2390 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2391 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2392 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2393 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2394 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2395 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2396 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2397 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2398 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2399 		cidp->pci_type = BGE_PCI_E;
2400 		cidp->statistic_type = BGE_STAT_REG;
2401 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2402 		dev_ok = B_TRUE;
2403 		break;
2404 
2405 	case DEVICE_ID_5789:
2406 		cidp->chip_label = 5789;
2407 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2408 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2409 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2410 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2411 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2412 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2413 		cidp->pci_type = BGE_PCI_E;
2414 		cidp->statistic_type = BGE_STAT_REG;
2415 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2416 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2417 		cidp->msi_enabled = B_TRUE;
2418 		dev_ok = B_TRUE;
2419 		break;
2420 
2421 	}
2422 
2423 	/*
2424 	 * Setup the default jumbo parameter.
2425 	 */
2426 	cidp->ethmax_size = ETHERMAX;
2427 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2428 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2429 
2430 	/*
2431 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2432 	 * setup below jumbo specific parameters.
2433 	 *
2434 	 * For BCM5714/5715, there is only one standard receive ring. So the
2435 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2436 	 * feature is enabled.
2437 	 */
2438 	if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2439 	    (cidp->default_mtu > BGE_DEFAULT_MTU)) {
2440 		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2441 			cidp->mbuf_lo_water_rdma =
2442 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2443 			cidp->mbuf_lo_water_rmac =
2444 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2445 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2446 			cidp->jumbo_slots = 0;
2447 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2448 		} else {
2449 			cidp->mbuf_lo_water_rdma =
2450 			    RDMA_MBUF_LOWAT_JUMBO;
2451 			cidp->mbuf_lo_water_rmac =
2452 			    MAC_RX_MBUF_LOWAT_JUMBO;
2453 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2454 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2455 		}
2456 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2457 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2458 		cidp->ethmax_size = cidp->default_mtu +
2459 		    sizeof (struct ether_header);
2460 	}
2461 
2462 	/*
2463 	 * Identify the NV memory type: SEEPROM or Flash?
2464 	 */
2465 	cidp->nvtype = bge_nvmem_id(bgep);
2466 
2467 	/*
2468 	 * Now, we want to check whether this device is part of a
2469 	 * supported subsystem (e.g., on the motherboard of a Sun
2470 	 * branded platform).
2471 	 *
2472 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2473 	 */
2474 	if (cidp->subven == VENDOR_ID_SUN)
2475 		sys_ok = B_TRUE;
2476 
2477 	/*
2478 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2479 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2480 	 * doesn't enforce that.
2481 	 */
2482 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2483 	    DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2484 	if (err == DDI_PROP_SUCCESS) {
2485 		/*
2486 		 * Got the list; scan for a matching subsystem vendor/device
2487 		 */
2488 		subid = (cidp->subven << 16) | cidp->subdev;
2489 		while (i--)
2490 			if (ids[i] == subid)
2491 				sys_ok = B_TRUE;
2492 		ddi_prop_free(ids);
2493 	}
2494 
2495 	/*
2496 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2497 	 *
2498 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2499 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2500 	 * we have to check specially for the exact device paths to the
2501 	 * motherboard devices on those platforms ;-(
2502 	 *
2503 	 * Note: we can't just use the "supported-subsystems" mechanism
2504 	 * above, because the entry would have to be 0x14e41647 -- which
2505 	 * would then accept *any* plugin card that *didn't* contain a
2506 	 * (valid) SEEPROM ;-(
2507 	 */
2508 	sysname = ddi_node_name(ddi_root_node());
2509 	devname = ddi_pathname(bgep->devinfo, buf);
2510 	ASSERT(strlen(devname) > 0);
2511 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2512 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2513 			sys_ok = B_TRUE;
2514 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2515 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2516 			sys_ok = B_TRUE;
2517 
2518 	/*
2519 	 * Now check what we've discovered: is this truly a supported
2520 	 * chip on (the motherboard of) a supported platform?
2521 	 *
2522 	 * Possible problems here:
2523 	 * 1)	it's a completely unheard-of chip
2524 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2525 	 * 3)	it's a chip we would support if it were on the motherboard
2526 	 *	of a Sun platform, but this one isn't ;-(
2527 	 */
2528 	if (cidp->chip_label == 0)
2529 		bge_problem(bgep,
2530 		    "Device 'pci%04x,%04x' not recognized (%d?)",
2531 		    cidp->vendor, cidp->device, cidp->device);
2532 	else if (!dev_ok)
2533 		bge_problem(bgep,
2534 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
2535 		    cidp->vendor, cidp->device, cidp->chip_label,
2536 		    cidp->revision);
2537 #if	BGE_DEBUGGING
2538 	else if (!sys_ok)
2539 		bge_problem(bgep,
2540 		    "%d-based subsystem 'pci%04x,%04x' not validated",
2541 		    cidp->chip_label, cidp->subven, cidp->subdev);
2542 #endif
2543 	else
2544 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2545 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2546 		return (EIO);
2547 	return (0);
2548 }
2549 
2550 void
2551 bge_chip_msi_trig(bge_t *bgep)
2552 {
2553 	uint32_t	regval;
2554 
2555 	regval = bgep->param_msi_cnt<<4;
2556 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2557 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2558 }
2559 
2560 /*
2561  * Various registers that control the chip's internal engines (state
2562  * machines) have a <reset> and <enable> bits (fortunately, in the
2563  * same place in each such register :-).
2564  *
2565  * To reset the state machine, the <reset> bit must be written with 1;
2566  * it will then read back as 1 while the reset is in progress, but
2567  * self-clear to 0 when the reset completes.
2568  *
2569  * To enable a state machine, one must set the <enable> bit, which
2570  * will continue to read back as 0 until the state machine is running.
2571  *
2572  * To disable a state machine, the <enable> bit must be cleared, but
2573  * it will continue to read back as 1 until the state machine actually
2574  * stops.
2575  *
2576  * This routine implements polling for completion of a reset, enable
2577  * or disable operation, returning B_TRUE on success (bit reached the
2578  * required state) or B_FALSE on timeout (200*100us == 20ms).
2579  */
2580 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2581 					uint32_t mask, uint32_t val);
2582 #pragma	no_inline(bge_chip_poll_engine)
2583 
2584 static boolean_t
2585 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2586 	uint32_t mask, uint32_t val)
2587 {
2588 	uint32_t regval;
2589 	uint32_t n;
2590 
2591 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2592 	    (void *)bgep, regno, mask, val));
2593 
2594 	for (n = 200; n; --n) {
2595 		regval = bge_reg_get32(bgep, regno);
2596 		if ((regval & mask) == val)
2597 			return (B_TRUE);
2598 		drv_usecwait(100);
2599 	}
2600 
2601 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2602 	return (B_FALSE);
2603 }
2604 
2605 /*
2606  * Various registers that control the chip's internal engines (state
2607  * machines) have a <reset> bit (fortunately, in the same place in
2608  * each such register :-).  To reset the state machine, this bit must
2609  * be written with 1; it will then read back as 1 while the reset is
2610  * in progress, but self-clear to 0 when the reset completes.
2611  *
2612  * This code sets the bit, then polls for it to read back as zero.
2613  * The return value is B_TRUE on success (reset bit cleared itself),
2614  * or B_FALSE if the state machine didn't recover :(
2615  *
2616  * NOTE: the Core reset is similar to other resets, except that we
2617  * can't poll for completion, since the Core reset disables memory
2618  * access!  So we just have to assume that it will all complete in
2619  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2620  */
2621 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2622 #pragma	no_inline(bge_chip_reset_engine)
2623 
2624 static boolean_t
2625 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2626 {
2627 	uint32_t regval;
2628 	uint32_t val32;
2629 
2630 	regval = bge_reg_get32(bgep, regno);
2631 
2632 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2633 	    (void *)bgep, regno));
2634 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2635 	    regno, regval));
2636 
2637 	regval |= STATE_MACHINE_RESET_BIT;
2638 
2639 	switch (regno) {
2640 	case MISC_CONFIG_REG:
2641 		/*
2642 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2643 		 * resetting PCIE block and bringing PCIE link down, bit 29
2644 		 * in the register needs to be set first, and then set it again
2645 		 * while the reset bit is written.
2646 		 * See:P500 of 57xx-PG102-RDS.pdf.
2647 		 */
2648 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2649 		    DEVICE_5717_SERIES_CHIPSETS(bgep)||
2650 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2651 		    DEVICE_5723_SERIES_CHIPSETS(bgep)||
2652 		    DEVICE_5714_SERIES_CHIPSETS(bgep)||
2653 		    DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2654 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2655 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2656 				if (bgep->chipid.asic_rev ==
2657 				    MHCR_CHIP_REV_5751_A0 ||
2658 				    bgep->chipid.asic_rev ==
2659 				    MHCR_CHIP_REV_5721_A0 ||
2660 				    bgep->chipid.asic_rev ==
2661 				    MHCR_CHIP_REV_5755_A0) {
2662 					val32 = bge_reg_get32(bgep,
2663 					    PHY_TEST_CTRL_REG);
2664 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2665 					    PHY_PCIE_LTASS_MODE))
2666 						bge_reg_put32(bgep,
2667 						    PHY_TEST_CTRL_REG,
2668 						    PHY_PCIE_SCRAM_MODE);
2669 					val32 = pci_config_get32
2670 					    (bgep->cfg_handle,
2671 					    PCI_CONF_BGE_CLKCTL);
2672 					val32 |= CLKCTL_PCIE_A0_FIX;
2673 					pci_config_put32(bgep->cfg_handle,
2674 					    PCI_CONF_BGE_CLKCTL, val32);
2675 				}
2676 				bge_reg_set32(bgep, regno,
2677 				    MISC_CONFIG_GRC_RESET_DISABLE);
2678 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2679 			}
2680 		}
2681 
2682 		/*
2683 		 * Special case - causes Core reset
2684 		 *
2685 		 * On SPARC v9 we want to ensure that we don't start
2686 		 * timing until the I/O access has actually reached
2687 		 * the chip, otherwise we might make the next access
2688 		 * too early.  And we can't just force the write out
2689 		 * by following it with a read (even to config space)
2690 		 * because that would cause the fault we're trying
2691 		 * to avoid.  Hence the need for membar_sync() here.
2692 		 */
2693 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2694 #ifdef	__sparcv9
2695 		membar_sync();
2696 #endif	/* __sparcv9 */
2697 		/*
2698 		 * On some platforms,system need about 300us for
2699 		 * link setup.
2700 		 */
2701 		drv_usecwait(300);
2702 		if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2703 			bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
2704 			bge_reg_clr32(
2705 			    bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
2706 		}
2707 
2708 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2709 			/* PCI-E device need more reset time */
2710 			drv_usecwait(120000);
2711 
2712 			/* Set PCIE max payload size and clear error status. */
2713 			if ((bgep->chipid.chip_label == 5721) ||
2714 			    (bgep->chipid.chip_label == 5751) ||
2715 			    (bgep->chipid.chip_label == 5752) ||
2716 			    (bgep->chipid.chip_label == 5789) ||
2717 			    (bgep->chipid.chip_label == 5906)) {
2718 				pci_config_put16(bgep->cfg_handle,
2719 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2720 				pci_config_put16(bgep->cfg_handle,
2721 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2722 			}
2723 
2724 			if ((bgep->chipid.chip_label == 5723) ||
2725 			    (bgep->chipid.chip_label == 5761)) {
2726 				pci_config_put16(bgep->cfg_handle,
2727 				    PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
2728 				pci_config_put16(bgep->cfg_handle,
2729 				    PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
2730 			}
2731 		}
2732 
2733 		BGE_PCICHK(bgep);
2734 		return (B_TRUE);
2735 
2736 	default:
2737 		bge_reg_put32(bgep, regno, regval);
2738 		return (bge_chip_poll_engine(bgep, regno,
2739 		    STATE_MACHINE_RESET_BIT, 0));
2740 	}
2741 }
2742 
2743 /*
2744  * Various registers that control the chip's internal engines (state
2745  * machines) have an <enable> bit (fortunately, in the same place in
2746  * each such register :-).  To stop the state machine, this bit must
2747  * be written with 0, then polled to see when the state machine has
2748  * actually stopped.
2749  *
2750  * The return value is B_TRUE on success (enable bit cleared), or
2751  * B_FALSE if the state machine didn't stop :(
2752  */
2753 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2754 						uint32_t morebits);
2755 #pragma	no_inline(bge_chip_disable_engine)
2756 
2757 static boolean_t
2758 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2759 {
2760 	uint32_t regval;
2761 
2762 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2763 	    (void *)bgep, regno, morebits));
2764 
2765 	switch (regno) {
2766 	case FTQ_RESET_REG:
2767 		/*
2768 		 * For Schumacher's bugfix CR6490108
2769 		 */
2770 #ifdef BGE_IPMI_ASF
2771 #ifdef BGE_NETCONSOLE
2772 		if (bgep->asf_enabled)
2773 			return (B_TRUE);
2774 #endif
2775 #endif
2776 		/*
2777 		 * Not quite like the others; it doesn't
2778 		 * have an <enable> bit, but instead we
2779 		 * have to set and then clear all the bits
2780 		 */
2781 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2782 		drv_usecwait(100);
2783 		bge_reg_put32(bgep, regno, 0);
2784 		return (B_TRUE);
2785 
2786 	default:
2787 		regval = bge_reg_get32(bgep, regno);
2788 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2789 		regval &= ~morebits;
2790 		bge_reg_put32(bgep, regno, regval);
2791 		return (bge_chip_poll_engine(bgep, regno,
2792 		    STATE_MACHINE_ENABLE_BIT, 0));
2793 	}
2794 }
2795 
2796 /*
2797  * Various registers that control the chip's internal engines (state
2798  * machines) have an <enable> bit (fortunately, in the same place in
2799  * each such register :-).  To start the state machine, this bit must
2800  * be written with 1, then polled to see when the state machine has
2801  * actually started.
2802  *
2803  * The return value is B_TRUE on success (enable bit set), or
2804  * B_FALSE if the state machine didn't start :(
2805  */
2806 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2807 					uint32_t morebits);
2808 #pragma	no_inline(bge_chip_enable_engine)
2809 
2810 static boolean_t
2811 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2812 {
2813 	uint32_t regval;
2814 
2815 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2816 	    (void *)bgep, regno, morebits));
2817 
2818 	switch (regno) {
2819 	case FTQ_RESET_REG:
2820 #ifdef BGE_IPMI_ASF
2821 #ifdef BGE_NETCONSOLE
2822 		if (bgep->asf_enabled)
2823 			return (B_TRUE);
2824 #endif
2825 #endif
2826 		/*
2827 		 * Not quite like the others; it doesn't
2828 		 * have an <enable> bit, but instead we
2829 		 * have to set and then clear all the bits
2830 		 */
2831 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2832 		drv_usecwait(100);
2833 		bge_reg_put32(bgep, regno, 0);
2834 		return (B_TRUE);
2835 
2836 	default:
2837 		regval = bge_reg_get32(bgep, regno);
2838 		regval |= STATE_MACHINE_ENABLE_BIT;
2839 		regval |= morebits;
2840 		bge_reg_put32(bgep, regno, regval);
2841 		return (bge_chip_poll_engine(bgep, regno,
2842 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2843 	}
2844 }
2845 
2846 /*
2847  * Reprogram the Ethernet, Transmit, and Receive MAC
2848  * modes to match the param_* variables
2849  */
2850 void bge_sync_mac_modes(bge_t *bgep);
2851 #pragma	no_inline(bge_sync_mac_modes)
2852 
2853 void
2854 bge_sync_mac_modes(bge_t *bgep)
2855 {
2856 	uint32_t macmode;
2857 	uint32_t regval;
2858 
2859 	ASSERT(mutex_owned(bgep->genlock));
2860 
2861 	/*
2862 	 * Reprogram the Ethernet MAC mode ...
2863 	 */
2864 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2865 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2866 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2867 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2868 			macmode |= ETHERNET_MODE_LINK_POLARITY;
2869 		else
2870 			macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2871 	else
2872 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2873 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2874 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2875 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
2876 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2877 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
2878 		else
2879 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
2880 	} else if (bgep->param_link_speed == 10 ||
2881 	    bgep->param_link_speed == 100)
2882 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2883 	else
2884 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2885 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2886 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2887 	else
2888 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2889 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2890 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2891 	else
2892 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2893 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2894 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2895 	    (void *)bgep, regval, macmode));
2896 
2897 	/*
2898 	 * ... the Transmit MAC mode ...
2899 	 */
2900 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2901 	if (bgep->param_link_tx_pause)
2902 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2903 	else
2904 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2905 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2906 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2907 	    (void *)bgep, regval, macmode));
2908 
2909 	/*
2910 	 * ... and the Receive MAC mode
2911 	 */
2912 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2913 	if (bgep->param_link_rx_pause)
2914 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2915 	else
2916 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2917 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2918 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2919 	    (void *)bgep, regval, macmode));
2920 
2921 	/*
2922 	 * For BCM5785, we need to configure the link status in the MI Status
2923 	 * register with a write command when auto-polling is disabled.
2924 	 */
2925 	if (bgep->chipid.device == DEVICE_ID_5785)
2926 		if (bgep->param_link_speed == 10)
2927 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
2928 			    | MI_STATUS_10MBPS);
2929 		else
2930 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
2931 }
2932 
2933 /*
2934  * bge_chip_sync() -- program the chip with the unicast MAC address,
2935  * the multicast hash table, the required level of promiscuity, and
2936  * the current loopback mode ...
2937  */
2938 #ifdef BGE_IPMI_ASF
2939 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2940 #else
2941 int bge_chip_sync(bge_t *bgep);
2942 #endif
2943 #pragma	no_inline(bge_chip_sync)
2944 
2945 int
2946 #ifdef BGE_IPMI_ASF
2947 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2948 #else
2949 bge_chip_sync(bge_t *bgep)
2950 #endif
2951 {
2952 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2953 	boolean_t promisc;
2954 	uint64_t macaddr;
2955 	uint32_t fill = 0;
2956 	int i, j;
2957 	int retval = DDI_SUCCESS;
2958 
2959 	BGE_TRACE(("bge_chip_sync($%p)",
2960 	    (void *)bgep));
2961 
2962 	ASSERT(mutex_owned(bgep->genlock));
2963 
2964 	promisc = B_FALSE;
2965 	fill = ~(uint32_t)0;
2966 
2967 	if (bgep->promisc)
2968 		promisc = B_TRUE;
2969 	else
2970 		fill = (uint32_t)0;
2971 
2972 	/*
2973 	 * If the TX/RX MAC engines are already running, we should stop
2974 	 * them (and reset the RX engine) before changing the parameters.
2975 	 * If they're not running, this will have no effect ...
2976 	 *
2977 	 * NOTE: this is currently disabled by default because stopping
2978 	 * and restarting the Tx engine may cause an outgoing packet in
2979 	 * transit to be truncated.  Also, stopping and restarting the
2980 	 * Rx engine seems to not work correctly on the 5705.  Testing
2981 	 * has not (yet!) revealed any problems with NOT stopping and
2982 	 * restarting these engines (and Broadcom say their drivers don't
2983 	 * do this), but if it is found to cause problems, this variable
2984 	 * can be patched to re-enable the old behaviour ...
2985 	 */
2986 	if (bge_stop_start_on_sync) {
2987 #ifdef BGE_IPMI_ASF
2988 		if (!bgep->asf_enabled) {
2989 			if (!bge_chip_disable_engine(bgep,
2990 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2991 				retval = DDI_FAILURE;
2992 		} else {
2993 			if (!bge_chip_disable_engine(bgep,
2994 			    RECEIVE_MAC_MODE_REG, 0))
2995 				retval = DDI_FAILURE;
2996 		}
2997 #else
2998 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
2999 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3000 			retval = DDI_FAILURE;
3001 #endif
3002 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3003 			retval = DDI_FAILURE;
3004 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
3005 			retval = DDI_FAILURE;
3006 	}
3007 
3008 	/*
3009 	 * Reprogram the hashed multicast address table ...
3010 	 */
3011 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3012 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
3013 
3014 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
3015 		bge_reg_put32(bgep, MAC_HASH_REG(i),
3016 			bgep->mcast_hash[i] | fill);
3017 
3018 #ifdef BGE_IPMI_ASF
3019 	if (!bgep->asf_enabled || !asf_keeplive) {
3020 #endif
3021 		/*
3022 		 * Transform the MAC address(es) from host to chip format, then
3023 		 * reprogram the transmit random backoff seed and the unicast
3024 		 * MAC address(es) ...
3025 		 */
3026 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
3027 			for (i = 0, macaddr = 0ull;
3028 			    i < ETHERADDRL; ++i) {
3029 				macaddr <<= 8;
3030 				macaddr |= bgep->curr_addr[j].addr[i];
3031 			}
3032 			fill += (macaddr >> 16) + (macaddr & 0xffffffff);
3033 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
3034 
3035 			BGE_DEBUG(("bge_chip_sync($%p) "
3036 			    "setting MAC address %012llx",
3037 			    (void *)bgep, macaddr));
3038 		}
3039 #ifdef BGE_IPMI_ASF
3040 	}
3041 #endif
3042 	/*
3043 	 * Set random seed of backoff interval
3044 	 *   - Writing zero means no backoff interval
3045 	 */
3046 	fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
3047 	if (fill == 0)
3048 		fill = 1;
3049 	bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
3050 
3051 	/*
3052 	 * Set or clear the PROMISCUOUS mode bit
3053 	 */
3054 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
3055 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
3056 
3057 	/*
3058 	 * Sync the rest of the MAC modes too ...
3059 	 */
3060 	bge_sync_mac_modes(bgep);
3061 
3062 	/*
3063 	 * Restart RX/TX MAC engines if required ...
3064 	 */
3065 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3066 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3067 			retval = DDI_FAILURE;
3068 #ifdef BGE_IPMI_ASF
3069 		if (!bgep->asf_enabled) {
3070 			if (!bge_chip_enable_engine(bgep,
3071 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3072 				retval = DDI_FAILURE;
3073 		} else {
3074 			if (!bge_chip_enable_engine(bgep,
3075 			    RECEIVE_MAC_MODE_REG, 0))
3076 				retval = DDI_FAILURE;
3077 		}
3078 #else
3079 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3080 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3081 			retval = DDI_FAILURE;
3082 #endif
3083 	}
3084 	return (retval);
3085 }
3086 
3087 /*
3088  * This array defines the sequence of state machine control registers
3089  * in which the <enable> bit must be cleared to bring the chip to a
3090  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
3091  */
3092 static bge_regno_t shutdown_engine_regs[] = {
3093 	RECEIVE_MAC_MODE_REG,
3094 	RCV_BD_INITIATOR_MODE_REG,
3095 	RCV_LIST_PLACEMENT_MODE_REG,
3096 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
3097 	RCV_DATA_BD_INITIATOR_MODE_REG,
3098 	RCV_DATA_COMPLETION_MODE_REG,
3099 	RCV_BD_COMPLETION_MODE_REG,
3100 
3101 	SEND_BD_SELECTOR_MODE_REG,
3102 	SEND_BD_INITIATOR_MODE_REG,
3103 	SEND_DATA_INITIATOR_MODE_REG,
3104 	READ_DMA_MODE_REG,
3105 	SEND_DATA_COMPLETION_MODE_REG,
3106 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
3107 	SEND_BD_COMPLETION_MODE_REG,
3108 	TRANSMIT_MAC_MODE_REG,
3109 
3110 	HOST_COALESCE_MODE_REG,
3111 	WRITE_DMA_MODE_REG,
3112 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
3113 	FTQ_RESET_REG,		/* special - see code	*/
3114 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
3115 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
3116 	BGE_REGNO_NONE		/* terminator		*/
3117 };
3118 
3119 #ifndef __sparc
3120 static bge_regno_t quiesce_regs[] = {
3121 	READ_DMA_MODE_REG,
3122 	DMA_COMPLETION_MODE_REG,
3123 	WRITE_DMA_MODE_REG,
3124 	BGE_REGNO_NONE
3125 };
3126 
3127 void bge_chip_stop_nonblocking(bge_t *bgep);
3128 #pragma no_inline(bge_chip_stop_nonblocking)
3129 
3130 /*
3131  * This function is called by bge_quiesce(). We
3132  * turn off all the DMA engines here.
3133  */
3134 void
3135 bge_chip_stop_nonblocking(bge_t *bgep)
3136 {
3137 	bge_regno_t *rbp;
3138 
3139 	/*
3140 	 * Flag that no more activity may be initiated
3141 	 */
3142 	bgep->progress &= ~PROGRESS_READY;
3143 
3144 	rbp = quiesce_regs;
3145 	while (*rbp != BGE_REGNO_NONE) {
3146 		(void) bge_chip_disable_engine(bgep, *rbp, 0);
3147 		++rbp;
3148 	}
3149 
3150 	bgep->bge_chip_state = BGE_CHIP_STOPPED;
3151 }
3152 
3153 #endif
3154 
3155 /*
3156  * bge_chip_stop() -- stop all chip processing
3157  *
3158  * If the <fault> parameter is B_TRUE, we're stopping the chip because
3159  * we've detected a problem internally; otherwise, this is a normal
3160  * (clean) stop (at user request i.e. the last STREAM has been closed).
3161  */
3162 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3163 #pragma	no_inline(bge_chip_stop)
3164 
3165 void
3166 bge_chip_stop(bge_t *bgep, boolean_t fault)
3167 {
3168 	bge_regno_t regno;
3169 	bge_regno_t *rbp;
3170 	boolean_t ok;
3171 	uint_t asf_mode;
3172 
3173 	BGE_TRACE(("bge_chip_stop($%p)",
3174 	    (void *)bgep));
3175 
3176 	ASSERT(mutex_owned(bgep->genlock));
3177 
3178 	/*
3179 	 * In some case, some chips' internal engines may fail to reset,
3180 	 * so we call bge_chip_reset as a workaround.
3181 	 */
3182 	bgep->bge_chip_state = BGE_CHIP_RESET;
3183 #ifdef BGE_IPMI_ASF
3184 	asf_mode = bgep->asf_enabled? ASF_MODE_POST_INIT: ASF_MODE_NONE;
3185 	if (bge_chip_reset(bgep, B_TRUE, asf_mode) != DDI_SUCCESS)
3186 #else
3187 	if (bge_chip_reset(bgep, B_TRUE) != DDI_SUCCESS)
3188 #endif
3189 		ddi_fm_service_impact(bgep->devinfo,
3190 		    DDI_SERVICE_UNAFFECTED);
3191 
3192 	rbp = shutdown_engine_regs;
3193 	/*
3194 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
3195 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
3196 	 * -ory arbiter should not be disabled.
3197 	 */
3198 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
3199 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3200 				ok &= bge_chip_disable_engine(bgep, regno, 0);
3201 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
3202 			    (regno != DMA_COMPLETION_MODE_REG) &&
3203 			    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
3204 			    (regno != BUFFER_MANAGER_MODE_REG) &&
3205 			    (regno != MEMORY_ARBITER_MODE_REG))
3206 				ok &= bge_chip_disable_engine(bgep,
3207 				    regno, 0);
3208 	}
3209 
3210 	if (!ok && !fault)
3211 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3212 
3213 	/*
3214 	 * Finally, disable (all) MAC events & clear the MAC status
3215 	 */
3216 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3217 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3218 
3219 	/*
3220 	 * if we're stopping the chip because of a detected fault then do
3221 	 * appropriate actions
3222 	 */
3223 	if (fault) {
3224 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3225 			bgep->bge_chip_state = BGE_CHIP_FAULT;
3226 			if (!bgep->manual_reset)
3227 				ddi_fm_service_impact(bgep->devinfo,
3228 				    DDI_SERVICE_LOST);
3229 			if (bgep->bge_dma_error) {
3230 				/*
3231 				 * need to free buffers in case the fault was
3232 				 * due to a memory error in a buffer - got to
3233 				 * do a fair bit of tidying first
3234 				 */
3235 				if (bgep->progress & PROGRESS_KSTATS) {
3236 					bge_fini_kstats(bgep);
3237 					bgep->progress &= ~PROGRESS_KSTATS;
3238 				}
3239 				if (bgep->progress & PROGRESS_INTR) {
3240 					bge_intr_disable(bgep);
3241 					rw_enter(bgep->errlock, RW_WRITER);
3242 					bge_fini_rings(bgep);
3243 					rw_exit(bgep->errlock);
3244 					bgep->progress &= ~PROGRESS_INTR;
3245 				}
3246 				if (bgep->progress & PROGRESS_BUFS) {
3247 					bge_free_bufs(bgep);
3248 					bgep->progress &= ~PROGRESS_BUFS;
3249 				}
3250 				bgep->bge_dma_error = B_FALSE;
3251 			}
3252 		}
3253 	} else
3254 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
3255 }
3256 
3257 /*
3258  * Poll for completion of chip's ROM firmware; also, at least on the
3259  * first time through, find and return the hardware MAC address, if any.
3260  */
3261 static uint64_t bge_poll_firmware(bge_t *bgep);
3262 #pragma	no_inline(bge_poll_firmware)
3263 
3264 static uint64_t
3265 bge_poll_firmware(bge_t *bgep)
3266 {
3267 	uint64_t magic;
3268 	uint64_t mac;
3269 	uint32_t gen, val;
3270 	uint32_t i;
3271 
3272 	/*
3273 	 * Step 19: poll for firmware completion (GENCOMM port set
3274 	 * to the ones complement of T3_MAGIC_NUMBER).
3275 	 *
3276 	 * While we're at it, we also read the MAC address register;
3277 	 * at some stage the firmware will load this with the
3278 	 * factory-set value.
3279 	 *
3280 	 * When both the magic number and the MAC address are set,
3281 	 * we're done; but we impose a time limit of one second
3282 	 * (1000*1000us) in case the firmware fails in some fashion
3283 	 * or the SEEPROM that provides that MAC address isn't fitted.
3284 	 *
3285 	 * After the first time through (chip state != INITIAL), we
3286 	 * don't need the MAC address to be set (we've already got it
3287 	 * or not, from the first time), so we don't wait for it, but
3288 	 * we still have to wait for the T3_MAGIC_NUMBER.
3289 	 *
3290 	 * Note: the magic number is only a 32-bit quantity, but the NIC
3291 	 * memory is 64-bit (and big-endian) internally.  Addressing the
3292 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3293 	 * it work correctly on both big- and little-endian hosts.
3294 	 */
3295 	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3296 	    MHCR_CHIP_ASIC_REV_5906) {
3297 		for (i = 0; i < 1000; ++i) {
3298 			drv_usecwait(1000);
3299 			val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3300 			if (val & VCPU_INIT_DONE)
3301 				break;
3302 		}
3303 		BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3304 		    (void *)bgep, i));
3305 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3306 	} else {
3307 		for (i = 0; i < 1000; ++i) {
3308 			drv_usecwait(1000);
3309 			gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3310 			if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
3311 				drv_usecwait(100000);
3312 			mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3313 #ifdef BGE_IPMI_ASF
3314 			if (!bgep->asf_enabled) {
3315 #endif
3316 				if (gen != ~T3_MAGIC_NUMBER)
3317 					continue;
3318 #ifdef BGE_IPMI_ASF
3319 			}
3320 #endif
3321 			if (mac != 0ULL)
3322 				break;
3323 			if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3324 				break;
3325 		}
3326 	}
3327 
3328 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3329 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3330 	    (void *)bgep, gen, i));
3331 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3332 	    mac, magic));
3333 
3334 	return (mac);
3335 }
3336 
3337 /*
3338  * Maximum times of trying to get the NVRAM access lock
3339  * by calling bge_nvmem_acquire()
3340  */
3341 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3342 
3343 #ifdef BGE_IPMI_ASF
3344 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3345 #else
3346 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3347 #endif
3348 #pragma	no_inline(bge_chip_reset)
3349 
3350 int
3351 #ifdef BGE_IPMI_ASF
3352 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3353 #else
3354 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3355 #endif
3356 {
3357 	chip_id_t chipid;
3358 	uint64_t mac;
3359 	uint64_t magic;
3360 	uint32_t modeflags;
3361 	uint32_t mhcr;
3362 	uint32_t sx0;
3363 	uint32_t i, tries;
3364 #ifdef BGE_IPMI_ASF
3365 	uint32_t mailbox;
3366 #endif
3367 	int retval = DDI_SUCCESS;
3368 
3369 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3370 		(void *)bgep, enable_dma));
3371 
3372 	ASSERT(mutex_owned(bgep->genlock));
3373 
3374 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3375 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3376 
3377 	/*
3378 	 * Do we need to stop the chip cleanly before resetting?
3379 	 */
3380 	switch (bgep->bge_chip_state) {
3381 	default:
3382 		_NOTE(NOTREACHED)
3383 		return (DDI_FAILURE);
3384 
3385 	case BGE_CHIP_INITIAL:
3386 	case BGE_CHIP_STOPPED:
3387 	case BGE_CHIP_RESET:
3388 		break;
3389 
3390 	case BGE_CHIP_RUNNING:
3391 	case BGE_CHIP_ERROR:
3392 	case BGE_CHIP_FAULT:
3393 		bge_chip_stop(bgep, B_FALSE);
3394 		break;
3395 	}
3396 
3397 #ifdef BGE_IPMI_ASF
3398 	if (bgep->asf_enabled) {
3399 #ifdef __sparc
3400 		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3401 			MHCR_ENABLE_TAGGED_STATUS_MODE |
3402 			MHCR_MASK_INTERRUPT_MODE |
3403 			MHCR_MASK_PCI_INT_OUTPUT |
3404 			MHCR_CLEAR_INTERRUPT_INTA |
3405 			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3406 			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3407 		if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3408 			pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR,
3409 					0);
3410 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3411 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3412 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3413 			MEMORY_ARBITER_ENABLE);
3414 #endif
3415 		if (asf_mode == ASF_MODE_INIT) {
3416 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3417 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3418 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3419 		}
3420 	}
3421 #endif
3422 	/*
3423 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3424 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3425 	 *
3426 	 * Before reset Core clock,it is
3427 	 * also required to initialize the Memory Arbiter as specified in step9
3428 	 * and Misc Host Control Register as specified in step-13
3429 	 * Step 4-5: reset Core clock & wait for completion
3430 	 * Steps 6-8: are done by bge_chip_cfg_init()
3431 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3432 	 */
3433 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3434 		retval = DDI_FAILURE;
3435 
3436 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3437 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3438 	    MHCR_MASK_INTERRUPT_MODE |
3439 	    MHCR_MASK_PCI_INT_OUTPUT |
3440 	    MHCR_CLEAR_INTERRUPT_INTA;
3441 #ifdef  _BIG_ENDIAN
3442 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3443 #endif  /* _BIG_ENDIAN */
3444 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
3445 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, 0);
3446 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3447 #ifdef BGE_IPMI_ASF
3448 	if (bgep->asf_enabled)
3449 		bgep->asf_wordswapped = B_FALSE;
3450 #endif
3451 	/*
3452 	 * NVRAM Corruption Workaround
3453 	 */
3454 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3455 		if (bge_nvmem_acquire(bgep) != EAGAIN)
3456 			break;
3457 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3458 		BGE_DEBUG(("%s: fail to acquire nvram lock",
3459 			bgep->ifname));
3460 
3461 #ifdef BGE_IPMI_ASF
3462 	if (!bgep->asf_enabled) {
3463 #endif
3464 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3465 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3466 #ifdef BGE_IPMI_ASF
3467 	}
3468 #endif
3469 
3470 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3471 		retval = DDI_FAILURE;
3472 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3473 
3474 	/*
3475 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3476 	 * a bit set to avoid a fifo overflow/underflow bug.
3477 	 */
3478 	if ((bgep->chipid.chip_label == 5721) ||
3479 		(bgep->chipid.chip_label == 5751) ||
3480 		(bgep->chipid.chip_label == 5752) ||
3481 		(bgep->chipid.chip_label == 5755) ||
3482 		(bgep->chipid.chip_label == 5756) ||
3483 		(bgep->chipid.chip_label == 5789) ||
3484 		(bgep->chipid.chip_label == 5906))
3485 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3486 
3487 
3488 	/*
3489 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3490 	 * not be changed.
3491 	 */
3492 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3493 		retval = DDI_FAILURE;
3494 
3495 	/*
3496 	 * Steps 10-11: configure PIO endianness options and
3497 	 * enable indirect register access -- already done
3498 	 * Steps 12-13: enable writing to the PCI state & clock
3499 	 * control registers -- not required; we aren't going to
3500 	 * use those features.
3501 	 * Steps 14-15: Configure DMA endianness options.  See
3502 	 * the comments on the setting of the MHCR above.
3503 	 */
3504 #ifdef	_BIG_ENDIAN
3505 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3506 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3507 #else
3508 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3509 #endif	/* _BIG_ENDIAN */
3510 #ifdef BGE_IPMI_ASF
3511 	if (bgep->asf_enabled)
3512 		modeflags |= MODE_HOST_STACK_UP;
3513 #endif
3514 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3515 
3516 #ifdef BGE_IPMI_ASF
3517 	if (bgep->asf_enabled) {
3518 #ifdef __sparc
3519 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3520 			MEMORY_ARBITER_ENABLE |
3521 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3522 #endif
3523 
3524 #ifdef  BGE_NETCONSOLE
3525 		if (!bgep->asf_newhandshake) {
3526 			if ((asf_mode == ASF_MODE_INIT) ||
3527 			(asf_mode == ASF_MODE_POST_INIT)) {
3528 				bge_asf_post_reset_old_mode(bgep,
3529 					BGE_INIT_RESET);
3530 			} else {
3531 				bge_asf_post_reset_old_mode(bgep,
3532 					BGE_SHUTDOWN_RESET);
3533 			}
3534 		}
3535 #endif
3536 
3537 		/* Wait for NVRAM init */
3538 		i = 0;
3539 		drv_usecwait(5000);
3540 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3541 
3542 		while ((mailbox != (uint32_t)
3543 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3544 			(i < 10000)) {
3545 			drv_usecwait(100);
3546 			mailbox = bge_nic_get32(bgep,
3547 				BGE_FIRMWARE_MAILBOX);
3548 			i++;
3549 		}
3550 
3551 #ifndef BGE_NETCONSOLE
3552 		if (!bgep->asf_newhandshake) {
3553 			if ((asf_mode == ASF_MODE_INIT) ||
3554 				(asf_mode == ASF_MODE_POST_INIT)) {
3555 
3556 				bge_asf_post_reset_old_mode(bgep,
3557 					BGE_INIT_RESET);
3558 			} else {
3559 				bge_asf_post_reset_old_mode(bgep,
3560 					BGE_SHUTDOWN_RESET);
3561 			}
3562 		}
3563 #endif
3564 	}
3565 #endif
3566 	/*
3567 	 * Steps 16-17: poll for firmware completion
3568 	 */
3569 	mac = bge_poll_firmware(bgep);
3570 
3571 	/*
3572 	 * Step 18: enable external memory -- doesn't apply.
3573 	 *
3574 	 * However we take the opportunity to set the MLCR anyway, as
3575 	 * this register also controls the SEEPROM auto-access method
3576 	 * which we may want to use later ...
3577 	 *
3578 	 * The proper value here depends on the way the chip is wired
3579 	 * into the circuit board, as this register *also* controls which
3580 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3581 	 * values driven onto those pins!
3582 	 *
3583 	 * See also step 74 in the PRM ...
3584 	 */
3585 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3586 	    bgep->chipid.bge_mlcr_default);
3587 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3588 
3589 	/*
3590 	 * Step 20: clear the Ethernet MAC mode register
3591 	 */
3592 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3593 
3594 	/*
3595 	 * Step 21: restore cache-line-size, latency timer, and
3596 	 * subsystem ID registers to their original values (not
3597 	 * those read into the local structure <chipid>, 'cos
3598 	 * that was after they were cleared by the RESET).
3599 	 *
3600 	 * Note: the Subsystem Vendor/Device ID registers are not
3601 	 * directly writable in config space, so we use the shadow
3602 	 * copy in "Page Zero" of register space to restore them
3603 	 * both in one go ...
3604 	 */
3605 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3606 		bgep->chipid.clsize);
3607 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3608 		bgep->chipid.latency);
3609 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3610 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3611 
3612 	/*
3613 	 * The SEND INDEX registers should be reset to zero by the
3614 	 * global chip reset; if they're not, there'll be trouble
3615 	 * later on.
3616 	 */
3617 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3618 	if (sx0 != 0) {
3619 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3620 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3621 		retval = DDI_FAILURE;
3622 	}
3623 
3624 	/* Enable MSI code */
3625 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3626 		bge_reg_set32(bgep, MSI_MODE_REG,
3627 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3628 
3629 	/*
3630 	 * On the first time through, save the factory-set MAC address
3631 	 * (if any).  If bge_poll_firmware() above didn't return one
3632 	 * (from a chip register) consider looking in the attached NV
3633 	 * memory device, if any.  Once we have it, we save it in both
3634 	 * register-image (64-bit) and byte-array forms.  All-zero and
3635 	 * all-one addresses are not valid, and we refuse to stash those.
3636 	 */
3637 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3638 		if (mac == 0ULL)
3639 			mac = bge_get_nvmac(bgep);
3640 		if (mac != 0ULL && mac != ~0ULL) {
3641 			bgep->chipid.hw_mac_addr = mac;
3642 			for (i = ETHERADDRL; i-- != 0; ) {
3643 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3644 				mac >>= 8;
3645 			}
3646 			bgep->chipid.vendor_addr.set = B_TRUE;
3647 		}
3648 	}
3649 
3650 #ifdef BGE_IPMI_ASF
3651 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3652 		if (asf_mode != ASF_MODE_NONE) {
3653 			if ((asf_mode == ASF_MODE_INIT) ||
3654 				(asf_mode == ASF_MODE_POST_INIT)) {
3655 
3656 				bge_asf_post_reset_new_mode(bgep,
3657 					BGE_INIT_RESET);
3658 			} else {
3659 				bge_asf_post_reset_new_mode(bgep,
3660 					BGE_SHUTDOWN_RESET);
3661 			}
3662 		}
3663 	}
3664 #endif
3665 
3666 	/*
3667 	 * Record the new state
3668 	 */
3669 	bgep->chip_resets += 1;
3670 	bgep->bge_chip_state = BGE_CHIP_RESET;
3671 	return (retval);
3672 }
3673 
3674 /*
3675  * bge_chip_start() -- start the chip transmitting and/or receiving,
3676  * including enabling interrupts
3677  */
3678 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3679 #pragma	no_inline(bge_chip_start)
3680 
3681 void
3682 bge_chip_coalesce_update(bge_t *bgep)
3683 {
3684 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3685 	    bgep->chipid.tx_count_norm);
3686 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3687 	    bgep->chipid.tx_ticks_norm);
3688 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3689 	    bgep->chipid.rx_count_norm);
3690 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3691 	    bgep->chipid.rx_ticks_norm);
3692 }
3693 
3694 int
3695 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3696 {
3697 	uint32_t coalmode;
3698 	uint32_t ledctl;
3699 	uint32_t mtu;
3700 	uint32_t maxring;
3701 	uint32_t stats_mask;
3702 	uint32_t dma_wrprio;
3703 	uint64_t ring;
3704 	uint32_t regval;
3705 	int retval = DDI_SUCCESS;
3706 
3707 	BGE_TRACE(("bge_chip_start($%p)",
3708 	    (void *)bgep));
3709 
3710 	ASSERT(mutex_owned(bgep->genlock));
3711 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3712 
3713 	/*
3714 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3715 	 * The document specifies 95 separate steps to fully
3716 	 * initialise the chip!!!!
3717 	 *
3718 	 * The reset code above has already got us as far as step
3719 	 * 21, so we continue with ...
3720 	 *
3721 	 * Step 22: clear the MAC statistics block
3722 	 * (0x0300-0x0aff in NIC-local memory)
3723 	 */
3724 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3725 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3726 		    NIC_MEM_STATISTICS_SIZE);
3727 
3728 	/*
3729 	 * Step 23: clear the status block (in host memory)
3730 	 */
3731 	DMA_ZERO(bgep->status_block);
3732 
3733 	/*
3734 	 * Step 24: set DMA read/write control register
3735 	 */
3736 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3737 	    bgep->chipid.bge_dma_rwctrl);
3738 
3739 	/*
3740 	 * Step 25: Configure DMA endianness -- already done (16/17)
3741 	 * Step 26: Configure Host-Based Send Rings
3742 	 * Step 27: Indicate Host Stack Up
3743 	 */
3744 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3745 	    MODE_HOST_SEND_BDS |
3746 	    MODE_HOST_STACK_UP);
3747 
3748 	/*
3749 	 * Step 28: Configure checksum options:
3750 	 *	Solaris supports the hardware default checksum options.
3751 	 *
3752 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3753 	 */
3754 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3755 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3756 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3757 
3758 	/*
3759 	 * Step 29: configure Timer Prescaler.  The value is always the
3760 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3761 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3762 	 * for the whole chip!
3763 	 */
3764 	regval = bge_reg_get32(bgep, MISC_CONFIG_REG);
3765 	regval = (regval & 0xffffff00) | MISC_CONFIG_DEFAULT;
3766 	bge_reg_put32(bgep, MISC_CONFIG_REG, regval);
3767 
3768 	if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3769 		drv_usecwait(40);
3770 		/* put PHY into ready state */
3771 		bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
3772 		(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
3773 		drv_usecwait(40);
3774 	}
3775 
3776 	/*
3777 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3778 	 *
3779 	 * If the mbuf_length is specified as 0, we just leave these at
3780 	 * their hardware defaults, rather than explicitly setting them.
3781 	 * As the Broadcom HRM,driver better not change the parameters
3782 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3783 	 */
3784 	if ((bgep->chipid.mbuf_length != 0) &&
3785 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3786 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3787 			    bgep->chipid.mbuf_base);
3788 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3789 			    bgep->chipid.mbuf_length);
3790 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3791 			    DMAD_POOL_BASE_DEFAULT);
3792 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3793 			    DMAD_POOL_LENGTH_DEFAULT);
3794 	}
3795 
3796 	/*
3797 	 * Step 32: configure MAC memory pool watermarks
3798 	 */
3799 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3800 	    bgep->chipid.mbuf_lo_water_rdma);
3801 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3802 	    bgep->chipid.mbuf_lo_water_rmac);
3803 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3804 	    bgep->chipid.mbuf_hi_water);
3805 
3806 	/*
3807 	 * Step 33: configure DMA resource watermarks
3808 	 */
3809 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3810 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3811 		    bge_dmad_lo_water);
3812 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3813 		    bge_dmad_hi_water);
3814 	}
3815 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3816 
3817 	/*
3818 	 * Steps 34-36: enable buffer manager & internal h/w queues
3819 	 */
3820 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3821 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3822 		retval = DDI_FAILURE;
3823 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3824 		retval = DDI_FAILURE;
3825 
3826 	/*
3827 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3828 	 */
3829 	if (DEVICE_5717_SERIES_CHIPSETS(bgep)) {
3830 		buff_ring_t *brp = &bgep->buff[BGE_STD_BUFF_RING];
3831 		bge_reg_put64(bgep, STD_RCV_BD_RING_RCB_REG,
3832 		    brp->desc.cookie.dmac_laddress);
3833 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 8,
3834 		    (brp->desc.nslots) << 16 | brp->buf[0].size << 2);
3835 		bge_reg_put32(bgep, STD_RCV_BD_RING_RCB_REG + 0xc,
3836 		    NIC_MEM_SHADOW_BUFF_STD_5717);
3837 	} else
3838 		bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3839 		    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3840 
3841 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3842 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3843 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3844 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3845 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3846 	}
3847 
3848 	/*
3849 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3850 	 */
3851 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3852 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3853 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3854 		    bge_replenish_jumbo);
3855 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3856 		    bge_replenish_mini);
3857 	}
3858 
3859 	/*
3860 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3861 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3862 	 */
3863 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3864 		maxring = BGE_SEND_RINGS_MAX;
3865 	else
3866 		maxring = BGE_SEND_RINGS_MAX_5705;
3867 	for (ring = 0; ring < maxring; ++ring) {
3868 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3869 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3870 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3871 		    &bgep->send[ring].hw_rcb);
3872 	}
3873 
3874 	/*
3875 	 * Steps 44-45: initialise Receive Return Rings
3876 	 * (0x0200-0x02ff in NIC-local memory)
3877 	 */
3878 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3879 		maxring = BGE_RECV_RINGS_MAX;
3880 	else
3881 		maxring = BGE_RECV_RINGS_MAX_5705;
3882 	for (ring = 0; ring < maxring; ++ring)
3883 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3884 		    &bgep->recv[ring].hw_rcb);
3885 
3886 	/*
3887 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3888 	 */
3889 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3890 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3891 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3892 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3893 	}
3894 	/*
3895 	 * Step 47: configure the MAC unicast address
3896 	 * Step 48: configure the random backoff seed
3897 	 * Step 96: set up multicast filters
3898 	 */
3899 #ifdef BGE_IPMI_ASF
3900 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3901 #else
3902 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3903 #endif
3904 		retval = DDI_FAILURE;
3905 
3906 	/*
3907 	 * Step 49: configure the MTU
3908 	 */
3909 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3910 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3911 
3912 	/*
3913 	 * Step 50: configure the IPG et al
3914 	 */
3915 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3916 
3917 	/*
3918 	 * Step 51: configure the default Rx Return Ring
3919 	 */
3920 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3921 
3922 	/*
3923 	 * Steps 52-54: configure Receive List Placement,
3924 	 * and enable Receive List Placement Statistics
3925 	 */
3926 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3927 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
3928 	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3929 	case MHCR_CHIP_ASIC_REV_5700:
3930 	case MHCR_CHIP_ASIC_REV_5701:
3931 	case MHCR_CHIP_ASIC_REV_5703:
3932 	case MHCR_CHIP_ASIC_REV_5704:
3933 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3934 		break;
3935 	case MHCR_CHIP_ASIC_REV_5705:
3936 		break;
3937 	default:
3938 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3939 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3940 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3941 		break;
3942 	}
3943 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3944 
3945 	if (bgep->chipid.rx_rings > 1)
3946 		bge_init_recv_rule(bgep);
3947 
3948 	/*
3949 	 * Steps 55-56: enable Send Data Initiator Statistics
3950 	 */
3951 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3952 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3953 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3954 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3955 	} else {
3956 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3957 		    SEND_INIT_STATS_ENABLE);
3958 	}
3959 	/*
3960 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3961 	 */
3962 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3963 		retval = DDI_FAILURE;
3964 
3965 	/*
3966 	 * Steps 59-62: initialise Host Coalescing parameters
3967 	 */
3968 	bge_chip_coalesce_update(bgep);
3969 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3970 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3971 		    bge_tx_count_intr);
3972 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3973 		    bge_tx_ticks_intr);
3974 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3975 		    bge_rx_count_intr);
3976 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3977 		    bge_rx_ticks_intr);
3978 	}
3979 
3980 	/*
3981 	 * Steps 63-64: initialise status block & statistics
3982 	 * host memory addresses
3983 	 * The statistic block does not exist in some chipsets
3984 	 * Step 65: initialise Statistics Coalescing Tick Counter
3985 	 */
3986 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3987 	    bgep->status_block.cookie.dmac_laddress);
3988 
3989 	/*
3990 	 * Steps 66-67: initialise status block & statistics
3991 	 * NIC-local memory addresses
3992 	 */
3993 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3994 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3995 		    bgep->statistics.cookie.dmac_laddress);
3996 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3997 		    STATISTICS_TICKS_DEFAULT);
3998 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3999 		    NIC_MEM_STATUS_BLOCK);
4000 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
4001 		    NIC_MEM_STATISTICS);
4002 	}
4003 
4004 	/*
4005 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
4006 	 * Completion Engine, the Receive List Placement Engine, and the
4007 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
4008 	 * and BCM5715.
4009 	 */
4010 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
4011 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
4012 		coalmode = COALESCE_64_BYTE_STATUS;
4013 	else
4014 		coalmode = 0;
4015 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
4016 		coalmode = COALESCE_CLR_TICKS_RX;
4017 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
4018 		retval = DDI_FAILURE;
4019 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
4020 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4021 		retval = DDI_FAILURE;
4022 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
4023 		retval = DDI_FAILURE;
4024 
4025 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4026 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
4027 		    STATE_MACHINE_ATTN_ENABLE_BIT))
4028 			retval = DDI_FAILURE;
4029 
4030 	/*
4031 	 * Step 72: Enable MAC DMA engines
4032 	 * Step 73: Clear & enable MAC statistics
4033 	 */
4034 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4035 	    ETHERNET_MODE_ENABLE_FHDE |
4036 	    ETHERNET_MODE_ENABLE_RDE |
4037 	    ETHERNET_MODE_ENABLE_TDE);
4038 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
4039 	    ETHERNET_MODE_ENABLE_TX_STATS |
4040 	    ETHERNET_MODE_ENABLE_RX_STATS |
4041 	    ETHERNET_MODE_CLEAR_TX_STATS |
4042 	    ETHERNET_MODE_CLEAR_RX_STATS);
4043 
4044 	/*
4045 	 * Step 74: configure the MLCR (Miscellaneous Local Control
4046 	 * Register); not required, as we set up the MLCR in step 10
4047 	 * (part of the reset code) above.
4048 	 *
4049 	 * Step 75: clear Interrupt Mailbox 0
4050 	 */
4051 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
4052 
4053 	/*
4054 	 * Steps 76-87: Gentlemen, start your engines ...
4055 	 *
4056 	 * Enable the DMA Completion Engine, the Write DMA Engine,
4057 	 * the Read DMA Engine, Receive Data Completion Engine,
4058 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
4059 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
4060 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
4061 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
4062 	 *
4063 	 * Beware exhaust fumes?
4064 	 */
4065 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4066 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
4067 			retval = DDI_FAILURE;
4068 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
4069 	    ALL_DMA_ATTN_BITS;
4070 	if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4071 	    MHCR_CHIP_ASIC_REV_5755) ||
4072 	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4073 	    MHCR_CHIP_ASIC_REV_5723) ||
4074 	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
4075 	    MHCR_CHIP_ASIC_REV_5906)) {
4076 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
4077 	}
4078 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
4079 	    dma_wrprio))
4080 		retval = DDI_FAILURE;
4081 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) ||
4082 	    DEVICE_5717_SERIES_CHIPSETS(bgep))
4083 		bge_dma_rdprio = 0;
4084 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
4085 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
4086 		retval = DDI_FAILURE;
4087 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
4088 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4089 		retval = DDI_FAILURE;
4090 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4091 		if (!bge_chip_enable_engine(bgep,
4092 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
4093 			retval = DDI_FAILURE;
4094 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
4095 		retval = DDI_FAILURE;
4096 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
4097 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4098 		retval = DDI_FAILURE;
4099 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
4100 	    RCV_BD_DISABLED_RING_ATTN))
4101 		retval = DDI_FAILURE;
4102 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4103 	    RCV_DATA_BD_ILL_RING_ATTN))
4104 		retval = DDI_FAILURE;
4105 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4106 		retval = DDI_FAILURE;
4107 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4108 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4109 		retval = DDI_FAILURE;
4110 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4111 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4112 		retval = DDI_FAILURE;
4113 
4114 	/*
4115 	 * Step 88: download firmware -- doesn't apply
4116 	 * Steps 89-90: enable Transmit & Receive MAC Engines
4117 	 */
4118 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
4119 		retval = DDI_FAILURE;
4120 #ifdef BGE_IPMI_ASF
4121 	if (!bgep->asf_enabled) {
4122 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4123 		    RECEIVE_MODE_KEEP_VLAN_TAG))
4124 			retval = DDI_FAILURE;
4125 	} else {
4126 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4127 			retval = DDI_FAILURE;
4128 	}
4129 #else
4130 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4131 	    RECEIVE_MODE_KEEP_VLAN_TAG))
4132 		retval = DDI_FAILURE;
4133 #endif
4134 
4135 	/*
4136 	 * Step 91: disable auto-polling of PHY status
4137 	 */
4138 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4139 
4140 	/*
4141 	 * Step 92: configure D0 power state (not required)
4142 	 * Step 93: initialise LED control register ()
4143 	 */
4144 	ledctl = LED_CONTROL_DEFAULT;
4145 	switch (bgep->chipid.device) {
4146 	case DEVICE_ID_5700:
4147 	case DEVICE_ID_5700x:
4148 	case DEVICE_ID_5701:
4149 		/*
4150 		 * Switch to 5700 (MAC) mode on these older chips
4151 		 */
4152 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4153 		ledctl |= LED_CONTROL_LED_MODE_5700;
4154 		break;
4155 
4156 	default:
4157 		break;
4158 	}
4159 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4160 
4161 	/*
4162 	 * Step 94: activate link
4163 	 */
4164 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4165 
4166 	/*
4167 	 * Step 95: set up physical layer (PHY/SerDes)
4168 	 * restart autoneg (if required)
4169 	 */
4170 	if (reset_phys)
4171 		if (bge_phys_update(bgep) == DDI_FAILURE)
4172 			retval = DDI_FAILURE;
4173 
4174 	/*
4175 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
4176 	 */
4177 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4178 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4179 		    bgep->buff[ring].rf_next);
4180 
4181 	/*
4182 	 * MSI bits:The least significant MSI 16-bit word.
4183 	 * ISR will be triggered different.
4184 	 */
4185 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4186 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4187 
4188 	/*
4189 	 * Extra step (DSG): select which interrupts are enabled
4190 	 *
4191 	 * Program the Ethernet MAC engine to signal attention on
4192 	 * Link Change events, then enable interrupts on MAC, DMA,
4193 	 * and FLOW attention signals.
4194 	 */
4195 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4196 	    ETHERNET_EVENT_LINK_INT |
4197 	    ETHERNET_STATUS_PCS_ERROR_INT);
4198 #ifdef BGE_IPMI_ASF
4199 	if (bgep->asf_enabled) {
4200 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4201 		    MODE_INT_ON_FLOW_ATTN |
4202 		    MODE_INT_ON_DMA_ATTN |
4203 		    MODE_HOST_STACK_UP|
4204 		    MODE_INT_ON_MAC_ATTN);
4205 	} else {
4206 #endif
4207 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4208 		    MODE_INT_ON_FLOW_ATTN |
4209 		    MODE_INT_ON_DMA_ATTN |
4210 		    MODE_INT_ON_MAC_ATTN);
4211 #ifdef BGE_IPMI_ASF
4212 	}
4213 #endif
4214 
4215 	/*
4216 	 * Step 97: enable PCI interrupts!!!
4217 	 */
4218 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4219 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4220 		    bgep->chipid.mask_pci_int);
4221 
4222 	/*
4223 	 * All done!
4224 	 */
4225 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
4226 	return (retval);
4227 }
4228 
4229 
4230 /*
4231  * ========== Hardware interrupt handler ==========
4232  */
4233 
4234 #undef	BGE_DBG
4235 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
4236 
4237 /*
4238  * Sync the status block, then atomically clear the specified bits in
4239  * the <flags-and-tag> field of the status block.
4240  * the <flags> word of the status block, returning the value of the
4241  * <tag> and the <flags> before the bits were cleared.
4242  */
4243 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4244 #pragma	inline(bge_status_sync)
4245 
4246 static int
4247 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4248 {
4249 	bge_status_t *bsp;
4250 	int retval;
4251 
4252 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4253 	    (void *)bgep, bits));
4254 
4255 	ASSERT(bgep->bge_guard == BGE_GUARD);
4256 
4257 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4258 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4259 	if (retval != DDI_FM_OK)
4260 		return (retval);
4261 
4262 	bsp = DMA_VPTR(bgep->status_block);
4263 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4264 
4265 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4266 	    (void *)bgep, bits, *flags));
4267 
4268 	return (retval);
4269 }
4270 
4271 void bge_wake_factotum(bge_t *bgep);
4272 #pragma	inline(bge_wake_factotum)
4273 
4274 void
4275 bge_wake_factotum(bge_t *bgep)
4276 {
4277 	mutex_enter(bgep->softintrlock);
4278 	if (bgep->factotum_flag == 0) {
4279 		bgep->factotum_flag = 1;
4280 		ddi_trigger_softintr(bgep->factotum_id);
4281 	}
4282 	mutex_exit(bgep->softintrlock);
4283 }
4284 
4285 /*
4286  *	bge_intr() -- handle chip interrupts
4287  */
4288 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
4289 #pragma	no_inline(bge_intr)
4290 
4291 uint_t
4292 bge_intr(caddr_t arg1, caddr_t arg2)
4293 {
4294 	bge_t *bgep = (void *)arg1;		/* private device info	*/
4295 	bge_status_t *bsp;
4296 	uint64_t flags;
4297 	uint32_t regval;
4298 	uint_t result;
4299 	int retval, loop_cnt = 0;
4300 
4301 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
4302 
4303 	/*
4304 	 * GLD v2 checks that s/w setup is complete before passing
4305 	 * interrupts to this routine, thus eliminating the old
4306 	 * (and well-known) race condition around ddi_add_intr()
4307 	 */
4308 	ASSERT(bgep->progress & PROGRESS_HWINT);
4309 
4310 	result = DDI_INTR_UNCLAIMED;
4311 	mutex_enter(bgep->genlock);
4312 
4313 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4314 		/*
4315 		 * Check whether chip's says it's asserting #INTA;
4316 		 * if not, don't process or claim the interrupt.
4317 		 *
4318 		 * Note that the PCI signal is active low, so the
4319 		 * bit is *zero* when the interrupt is asserted.
4320 		 */
4321 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
4322 		if (!(DEVICE_5717_SERIES_CHIPSETS(bgep)) &&
4323 		    (regval & MLCR_INTA_STATE)) {
4324 			if (bge_check_acc_handle(bgep, bgep->io_handle)
4325 			    != DDI_FM_OK)
4326 				goto chip_stop;
4327 			mutex_exit(bgep->genlock);
4328 			return (result);
4329 		}
4330 
4331 		/*
4332 		 * Block further PCI interrupts ...
4333 		 */
4334 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4335 		    bgep->chipid.mask_pci_int);
4336 
4337 	} else {
4338 		/*
4339 		 * Check MSI status
4340 		 */
4341 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
4342 		if (regval & MSI_ERROR_ATTENTION) {
4343 			BGE_REPORT((bgep, "msi error attention,"
4344 			    " status=0x%x", regval));
4345 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4346 		}
4347 	}
4348 
4349 	result = DDI_INTR_CLAIMED;
4350 
4351 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
4352 
4353 	/*
4354 	 * Sync the status block and grab the flags-n-tag from it.
4355 	 * We count the number of interrupts where there doesn't
4356 	 * seem to have been a DMA update of the status block; if
4357 	 * it *has* been updated, the counter will be cleared in
4358 	 * the while() loop below ...
4359 	 */
4360 	bgep->missed_dmas += 1;
4361 	bsp = DMA_VPTR(bgep->status_block);
4362 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
4363 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
4364 			/*
4365 			 * bge_chip_stop() may have freed dma area etc
4366 			 * while we were in this interrupt handler -
4367 			 * better not call bge_status_sync()
4368 			 */
4369 			(void) bge_check_acc_handle(bgep,
4370 			    bgep->io_handle);
4371 			mutex_exit(bgep->genlock);
4372 			return (DDI_INTR_CLAIMED);
4373 		}
4374 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4375 		    &flags);
4376 		if (retval != DDI_FM_OK) {
4377 			bgep->bge_dma_error = B_TRUE;
4378 			goto chip_stop;
4379 		}
4380 
4381 		if (!(flags & STATUS_FLAG_UPDATED))
4382 			break;
4383 
4384 		/*
4385 		 * Tell the chip that we're processing the interrupt
4386 		 */
4387 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4388 		    INTERRUPT_MBOX_DISABLE(flags));
4389 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4390 		    DDI_FM_OK)
4391 			goto chip_stop;
4392 
4393 		/*
4394 		 * Drop the mutex while we:
4395 		 * 	Receive any newly-arrived packets
4396 		 *	Recycle any newly-finished send buffers
4397 		 */
4398 		bgep->bge_intr_running = B_TRUE;
4399 		mutex_exit(bgep->genlock);
4400 		bge_receive(bgep, bsp);
4401 		(void) bge_recycle(bgep, bsp);
4402 		mutex_enter(bgep->genlock);
4403 		bgep->bge_intr_running = B_FALSE;
4404 
4405 		/*
4406 		 * Tell the chip we've finished processing, and
4407 		 * give it the tag that we got from the status
4408 		 * block earlier, so that it knows just how far
4409 		 * we've gone.  If it's got more for us to do,
4410 		 * it will now update the status block and try
4411 		 * to assert an interrupt (but we've got the
4412 		 * #INTA blocked at present).  If we see the
4413 		 * update, we'll loop around to do some more.
4414 		 * Eventually we'll get out of here ...
4415 		 */
4416 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4417 		    INTERRUPT_MBOX_ENABLE(flags));
4418 		if (bgep->chipid.pci_type == BGE_PCI_E)
4419 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4420 		bgep->missed_dmas = 0;
4421 	}
4422 
4423 	/*
4424 	 * Check for exceptional conditions that we need to handle
4425 	 *
4426 	 * Link status changed
4427 	 * Status block not updated
4428 	 */
4429 	if (flags & STATUS_FLAG_LINK_CHANGED)
4430 		bge_wake_factotum(bgep);
4431 
4432 	if (bgep->missed_dmas) {
4433 		/*
4434 		 * Probably due to the internal status tag not
4435 		 * being reset.  Force a status block update now;
4436 		 * this should ensure that we get an update and
4437 		 * a new interrupt.  After that, we should be in
4438 		 * sync again ...
4439 		 */
4440 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4441 		    "not updated?", flags));
4442 		bgep->missed_updates++;
4443 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4444 		    COALESCE_NOW);
4445 
4446 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
4447 			/*
4448 			 * If this happens multiple times in a row,
4449 			 * it means DMA is just not working.  Maybe
4450 			 * the chip's failed, or maybe there's a
4451 			 * problem on the PCI bus or in the host-PCI
4452 			 * bridge (Tomatillo).
4453 			 *
4454 			 * At all events, we want to stop further
4455 			 * interrupts and let the recovery code take
4456 			 * over to see whether anything can be done
4457 			 * about it ...
4458 			 */
4459 			bge_fm_ereport(bgep,
4460 			    DDI_FM_DEVICE_BADINT_LIMIT);
4461 			goto chip_stop;
4462 		}
4463 	}
4464 
4465 	/*
4466 	 * Reenable assertion of #INTA, unless there's a DMA fault
4467 	 */
4468 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4469 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4470 		    bgep->chipid.mask_pci_int);
4471 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4472 		    DDI_FM_OK)
4473 			goto chip_stop;
4474 	}
4475 
4476 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4477 		goto chip_stop;
4478 
4479 	mutex_exit(bgep->genlock);
4480 	return (result);
4481 
4482 chip_stop:
4483 #ifdef BGE_IPMI_ASF
4484 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4485 		/*
4486 		 * We must stop ASF heart beat before
4487 		 * bge_chip_stop(), otherwise some
4488 		 * computers (ex. IBM HS20 blade
4489 		 * server) may crash.
4490 		 */
4491 		bge_asf_update_status(bgep);
4492 		bge_asf_stop_timer(bgep);
4493 		bgep->asf_status = ASF_STAT_STOP;
4494 
4495 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4496 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4497 	}
4498 #endif
4499 	bge_chip_stop(bgep, B_TRUE);
4500 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
4501 	mutex_exit(bgep->genlock);
4502 	return (result);
4503 }
4504 
4505 /*
4506  * ========== Factotum, implemented as a softint handler ==========
4507  */
4508 
4509 #undef	BGE_DBG
4510 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
4511 
4512 static void bge_factotum_error_handler(bge_t *bgep);
4513 #pragma	no_inline(bge_factotum_error_handler)
4514 
4515 static void
4516 bge_factotum_error_handler(bge_t *bgep)
4517 {
4518 	uint32_t flow;
4519 	uint32_t rdma;
4520 	uint32_t wdma;
4521 	uint32_t tmac;
4522 	uint32_t rmac;
4523 	uint32_t rxrs;
4524 	uint32_t txrs = 0;
4525 
4526 	ASSERT(mutex_owned(bgep->genlock));
4527 
4528 	/*
4529 	 * Read all the registers that show the possible
4530 	 * reasons for the ERROR bit to be asserted
4531 	 */
4532 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4533 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4534 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4535 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4536 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4537 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4538 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4539 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4540 
4541 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4542 	    (void *)bgep, flow, rdma, wdma));
4543 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4544 	    (void *)bgep, tmac, rmac, rxrs, txrs));
4545 
4546 	/*
4547 	 * For now, just clear all the errors ...
4548 	 */
4549 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4550 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4551 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4552 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4553 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4554 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4555 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4556 }
4557 
4558 /*
4559  * Handler for hardware link state change.
4560  *
4561  * When this routine is called, the hardware link state has changed
4562  * and the new state is reflected in the param_* variables.  Here
4563  * we must update the softstate and reprogram the MAC to match.
4564  */
4565 static void bge_factotum_link_handler(bge_t *bgep);
4566 #pragma	no_inline(bge_factotum_link_handler)
4567 
4568 static void
4569 bge_factotum_link_handler(bge_t *bgep)
4570 {
4571 	ASSERT(mutex_owned(bgep->genlock));
4572 
4573 	/*
4574 	 * Update the s/w link_state
4575 	 */
4576 	if (bgep->param_link_up)
4577 		bgep->link_state = LINK_STATE_UP;
4578 	else
4579 		bgep->link_state = LINK_STATE_DOWN;
4580 
4581 	/*
4582 	 * Reprogram the MAC modes to match
4583 	 */
4584 	bge_sync_mac_modes(bgep);
4585 }
4586 
4587 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4588 #pragma	no_inline(bge_factotum_link_check)
4589 
4590 static boolean_t
4591 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4592 {
4593 	boolean_t check;
4594 	uint64_t flags;
4595 	uint32_t tmac_status;
4596 
4597 	ASSERT(mutex_owned(bgep->genlock));
4598 
4599 	/*
4600 	 * Get & clear the writable status bits in the Tx status register
4601 	 * (some bits are write-1-to-clear, others are just readonly).
4602 	 */
4603 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4604 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4605 
4606 	/*
4607 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4608 	 */
4609 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4610 	    STATUS_FLAG_LINK_CHANGED, &flags);
4611 	if (*dma_state != DDI_FM_OK)
4612 		return (B_FALSE);
4613 
4614 	/*
4615 	 * Clear any errors flagged in the status block ...
4616 	 */
4617 	if (flags & STATUS_FLAG_ERROR)
4618 		bge_factotum_error_handler(bgep);
4619 
4620 	/*
4621 	 * We need to check the link status if:
4622 	 *	the status block says there's been a link change
4623 	 *	or there's any discrepancy between the various
4624 	 *	flags indicating the link state (link_state,
4625 	 *	param_link_up, and the LINK STATE bit in the
4626 	 *	Transmit MAC status register).
4627 	 */
4628 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4629 	switch (bgep->link_state) {
4630 	case LINK_STATE_UP:
4631 		check |= (bgep->param_link_up == B_FALSE);
4632 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4633 		break;
4634 
4635 	case LINK_STATE_DOWN:
4636 		check |= (bgep->param_link_up != B_FALSE);
4637 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4638 		break;
4639 
4640 	default:
4641 		check = B_TRUE;
4642 		break;
4643 	}
4644 
4645 	/*
4646 	 * If <check> is false, we're sure the link hasn't changed.
4647 	 * If true, however, it's not yet definitive; we have to call
4648 	 * bge_phys_check() to determine whether the link has settled
4649 	 * into a new state yet ... and if it has, then call the link
4650 	 * state change handler.But when the chip is 5700 in Dell 6650
4651 	 * ,even if check is false, the link may have changed.So we
4652 	 * have to call bge_phys_check() to determine the link state.
4653 	 */
4654 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4655 		check = bge_phys_check(bgep);
4656 		if (check)
4657 			bge_factotum_link_handler(bgep);
4658 	}
4659 
4660 	return (check);
4661 }
4662 
4663 /*
4664  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4665  */
4666 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4667 #pragma	no_inline(bge_factotum_stall_check)
4668 
4669 static boolean_t
4670 bge_factotum_stall_check(bge_t *bgep)
4671 {
4672 	uint32_t dogval;
4673 	bge_status_t *bsp;
4674 	uint64_t now = gethrtime();
4675 
4676 	if ((now - bgep->timestamp) < BGE_CYCLIC_PERIOD)
4677 		return (B_FALSE);
4678 
4679 	bgep->timestamp = now;
4680 
4681 	ASSERT(mutex_owned(bgep->genlock));
4682 
4683 	/*
4684 	 * Specific check for Tx stall ...
4685 	 *
4686 	 * The 'watchdog' counter is incremented whenever a packet
4687 	 * is queued, reset to 1 when some (but not all) buffers
4688 	 * are reclaimed, reset to 0 (disabled) when all buffers
4689 	 * are reclaimed, and shifted left here.  If it exceeds the
4690 	 * threshold value, the chip is assumed to have stalled and
4691 	 * is put into the ERROR state.  The factotum will then reset
4692 	 * it on the next pass.
4693 	 *
4694 	 * All of which should ensure that we don't get into a state
4695 	 * where packets are left pending indefinitely!
4696 	 */
4697 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4698 	bsp = DMA_VPTR(bgep->status_block);
4699 	if (dogval < bge_watchdog_count || bge_recycle(bgep, bsp))
4700 		return (B_FALSE);
4701 
4702 #if !defined(BGE_NETCONSOLE)
4703 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4704 #endif
4705 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4706 	return (B_TRUE);
4707 }
4708 
4709 /*
4710  * The factotum is woken up when there's something to do that we'd rather
4711  * not do from inside a hardware interrupt handler or high-level cyclic.
4712  * Its two main tasks are:
4713  *	reset & restart the chip after an error
4714  *	check the link status whenever necessary
4715  */
4716 uint_t bge_chip_factotum(caddr_t arg);
4717 #pragma	no_inline(bge_chip_factotum)
4718 
4719 uint_t
4720 bge_chip_factotum(caddr_t arg)
4721 {
4722 	bge_t *bgep;
4723 	uint_t result;
4724 	boolean_t error;
4725 	boolean_t linkchg;
4726 	int dma_state;
4727 
4728 	bgep = (void *)arg;
4729 
4730 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4731 
4732 	mutex_enter(bgep->softintrlock);
4733 	if (bgep->factotum_flag == 0) {
4734 		mutex_exit(bgep->softintrlock);
4735 		return (DDI_INTR_UNCLAIMED);
4736 	}
4737 	bgep->factotum_flag = 0;
4738 	mutex_exit(bgep->softintrlock);
4739 
4740 	result = DDI_INTR_CLAIMED;
4741 	error = B_FALSE;
4742 	linkchg = B_FALSE;
4743 
4744 	mutex_enter(bgep->genlock);
4745 	switch (bgep->bge_chip_state) {
4746 	default:
4747 		break;
4748 
4749 	case BGE_CHIP_RUNNING:
4750 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4751 		error = bge_factotum_stall_check(bgep);
4752 		if (dma_state != DDI_FM_OK) {
4753 			bgep->bge_dma_error = B_TRUE;
4754 			error = B_TRUE;
4755 		}
4756 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4757 			error = B_TRUE;
4758 		if (error)
4759 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4760 		break;
4761 
4762 	case BGE_CHIP_ERROR:
4763 		error = B_TRUE;
4764 		break;
4765 
4766 	case BGE_CHIP_FAULT:
4767 		/*
4768 		 * Fault detected, time to reset ...
4769 		 */
4770 		if (bge_autorecover) {
4771 			if (!(bgep->progress & PROGRESS_BUFS)) {
4772 				/*
4773 				 * if we can't allocate the ring buffers,
4774 				 * try later
4775 				 */
4776 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4777 					mutex_exit(bgep->genlock);
4778 					return (result);
4779 				}
4780 				bgep->progress |= PROGRESS_BUFS;
4781 			}
4782 			if (!(bgep->progress & PROGRESS_INTR)) {
4783 				bge_init_rings(bgep);
4784 				bge_intr_enable(bgep);
4785 				bgep->progress |= PROGRESS_INTR;
4786 			}
4787 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4788 				bge_init_kstats(bgep,
4789 				    ddi_get_instance(bgep->devinfo));
4790 				bgep->progress |= PROGRESS_KSTATS;
4791 			}
4792 
4793 			BGE_REPORT((bgep, "automatic recovery activated"));
4794 
4795 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4796 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4797 				error = B_TRUE;
4798 			}
4799 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4800 			    DDI_FM_OK) {
4801 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4802 				error = B_TRUE;
4803 			}
4804 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4805 			    DDI_FM_OK) {
4806 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4807 				error = B_TRUE;
4808 			}
4809 			if (error == B_FALSE) {
4810 #ifdef BGE_IPMI_ASF
4811 				if (bgep->asf_enabled &&
4812 				    bgep->asf_status != ASF_STAT_RUN) {
4813 					bgep->asf_timeout_id = timeout(
4814 					    bge_asf_heartbeat, (void *)bgep,
4815 					    drv_usectohz(
4816 					    BGE_ASF_HEARTBEAT_INTERVAL));
4817 					bgep->asf_status = ASF_STAT_RUN;
4818 				}
4819 #endif
4820 				if (!bgep->manual_reset) {
4821 					ddi_fm_service_impact(bgep->devinfo,
4822 					    DDI_SERVICE_RESTORED);
4823 				}
4824 			}
4825 		}
4826 		break;
4827 	}
4828 
4829 
4830 	/*
4831 	 * If an error is detected, stop the chip now, marking it as
4832 	 * faulty, so that it will be reset next time through ...
4833 	 *
4834 	 * Note that if intr_running is set, then bge_intr() has dropped
4835 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4836 	 * this point so have to wait until the next time the factotum runs.
4837 	 */
4838 	if (error && !bgep->bge_intr_running) {
4839 #ifdef BGE_IPMI_ASF
4840 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4841 			/*
4842 			 * We must stop ASF heart beat before bge_chip_stop(),
4843 			 * otherwise some computers (ex. IBM HS20 blade server)
4844 			 * may crash.
4845 			 */
4846 			bge_asf_update_status(bgep);
4847 			bge_asf_stop_timer(bgep);
4848 			bgep->asf_status = ASF_STAT_STOP;
4849 
4850 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4851 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4852 		}
4853 #endif
4854 		bge_chip_stop(bgep, B_TRUE);
4855 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4856 	}
4857 	mutex_exit(bgep->genlock);
4858 
4859 	/*
4860 	 * If the link state changed, tell the world about it.
4861 	 * Note: can't do this while still holding the mutex.
4862 	 */
4863 	if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4864 	    bgep->link_state != LINK_STATE_UNKNOWN)
4865 		linkchg = B_TRUE;
4866 	else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4867 	    bgep->link_state == LINK_STATE_DOWN)
4868 		linkchg = B_FALSE;
4869 
4870 	if (linkchg) {
4871 		mac_link_update(bgep->mh, bgep->link_state);
4872 		bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4873 	}
4874 	if (bgep->manual_reset) {
4875 		bgep->manual_reset = B_FALSE;
4876 	}
4877 
4878 	return (result);
4879 }
4880 
4881 /*
4882  * High-level cyclic handler
4883  *
4884  * This routine schedules a (low-level) softint callback to the
4885  * factotum, and prods the chip to update the status block (which
4886  * will cause a hardware interrupt when complete).
4887  */
4888 void bge_chip_cyclic(void *arg);
4889 #pragma	no_inline(bge_chip_cyclic)
4890 
4891 void
4892 bge_chip_cyclic(void *arg)
4893 {
4894 	bge_t *bgep;
4895 
4896 	bgep = arg;
4897 
4898 	switch (bgep->bge_chip_state) {
4899 	default:
4900 		return;
4901 
4902 	case BGE_CHIP_RUNNING:
4903 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4904 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4905 			ddi_fm_service_impact(bgep->devinfo,
4906 			    DDI_SERVICE_UNAFFECTED);
4907 
4908 		if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4909 			bgep->link_update_timer++;
4910 
4911 		break;
4912 
4913 	case BGE_CHIP_FAULT:
4914 	case BGE_CHIP_ERROR:
4915 		break;
4916 	}
4917 
4918 	bge_wake_factotum(bgep);
4919 }
4920 
4921 
4922 /*
4923  * ========== Ioctl subfunctions ==========
4924  */
4925 
4926 #undef	BGE_DBG
4927 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4928 
4929 #if	BGE_DEBUGGING || BGE_DO_PPIO
4930 
4931 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4932 #pragma	no_inline(bge_chip_peek_cfg)
4933 
4934 static void
4935 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4936 {
4937 	uint64_t regval;
4938 	uint64_t regno;
4939 
4940 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4941 	    (void *)bgep, (void *)ppd));
4942 
4943 	regno = ppd->pp_acc_offset;
4944 
4945 	switch (ppd->pp_acc_size) {
4946 	case 1:
4947 		regval = pci_config_get8(bgep->cfg_handle, regno);
4948 		break;
4949 
4950 	case 2:
4951 		regval = pci_config_get16(bgep->cfg_handle, regno);
4952 		break;
4953 
4954 	case 4:
4955 		regval = pci_config_get32(bgep->cfg_handle, regno);
4956 		break;
4957 
4958 	case 8:
4959 		regval = pci_config_get64(bgep->cfg_handle, regno);
4960 		break;
4961 	}
4962 
4963 	ppd->pp_acc_data = regval;
4964 }
4965 
4966 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4967 #pragma	no_inline(bge_chip_poke_cfg)
4968 
4969 static void
4970 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4971 {
4972 	uint64_t regval;
4973 	uint64_t regno;
4974 
4975 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4976 	    (void *)bgep, (void *)ppd));
4977 
4978 	regno = ppd->pp_acc_offset;
4979 	regval = ppd->pp_acc_data;
4980 
4981 	switch (ppd->pp_acc_size) {
4982 	case 1:
4983 		pci_config_put8(bgep->cfg_handle, regno, regval);
4984 		break;
4985 
4986 	case 2:
4987 		pci_config_put16(bgep->cfg_handle, regno, regval);
4988 		break;
4989 
4990 	case 4:
4991 		pci_config_put32(bgep->cfg_handle, regno, regval);
4992 		break;
4993 
4994 	case 8:
4995 		pci_config_put64(bgep->cfg_handle, regno, regval);
4996 		break;
4997 	}
4998 }
4999 
5000 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5001 #pragma	no_inline(bge_chip_peek_reg)
5002 
5003 static void
5004 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5005 {
5006 	uint64_t regval;
5007 	void *regaddr;
5008 
5009 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
5010 	    (void *)bgep, (void *)ppd));
5011 
5012 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5013 
5014 	switch (ppd->pp_acc_size) {
5015 	case 1:
5016 		regval = ddi_get8(bgep->io_handle, regaddr);
5017 		break;
5018 
5019 	case 2:
5020 		regval = ddi_get16(bgep->io_handle, regaddr);
5021 		break;
5022 
5023 	case 4:
5024 		regval = ddi_get32(bgep->io_handle, regaddr);
5025 		break;
5026 
5027 	case 8:
5028 		regval = ddi_get64(bgep->io_handle, regaddr);
5029 		break;
5030 	}
5031 
5032 	ppd->pp_acc_data = regval;
5033 }
5034 
5035 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
5036 #pragma	no_inline(bge_chip_peek_reg)
5037 
5038 static void
5039 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
5040 {
5041 	uint64_t regval;
5042 	void *regaddr;
5043 
5044 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
5045 	    (void *)bgep, (void *)ppd));
5046 
5047 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
5048 	regval = ppd->pp_acc_data;
5049 
5050 	switch (ppd->pp_acc_size) {
5051 	case 1:
5052 		ddi_put8(bgep->io_handle, regaddr, regval);
5053 		break;
5054 
5055 	case 2:
5056 		ddi_put16(bgep->io_handle, regaddr, regval);
5057 		break;
5058 
5059 	case 4:
5060 		ddi_put32(bgep->io_handle, regaddr, regval);
5061 		break;
5062 
5063 	case 8:
5064 		ddi_put64(bgep->io_handle, regaddr, regval);
5065 		break;
5066 	}
5067 	BGE_PCICHK(bgep);
5068 }
5069 
5070 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5071 #pragma	no_inline(bge_chip_peek_nic)
5072 
5073 static void
5074 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5075 {
5076 	uint64_t regoff;
5077 	uint64_t regval;
5078 	void *regaddr;
5079 
5080 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
5081 	    (void *)bgep, (void *)ppd));
5082 
5083 	regoff = ppd->pp_acc_offset;
5084 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5085 	regoff &= MWBAR_GRANULE_MASK;
5086 	regoff += NIC_MEM_WINDOW_OFFSET;
5087 	regaddr = PIO_ADDR(bgep, regoff);
5088 
5089 	switch (ppd->pp_acc_size) {
5090 	case 1:
5091 		regval = ddi_get8(bgep->io_handle, regaddr);
5092 		break;
5093 
5094 	case 2:
5095 		regval = ddi_get16(bgep->io_handle, regaddr);
5096 		break;
5097 
5098 	case 4:
5099 		regval = ddi_get32(bgep->io_handle, regaddr);
5100 		break;
5101 
5102 	case 8:
5103 		regval = ddi_get64(bgep->io_handle, regaddr);
5104 		break;
5105 	}
5106 
5107 	ppd->pp_acc_data = regval;
5108 }
5109 
5110 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5111 #pragma	no_inline(bge_chip_poke_nic)
5112 
5113 static void
5114 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5115 {
5116 	uint64_t regoff;
5117 	uint64_t regval;
5118 	void *regaddr;
5119 
5120 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5121 	    (void *)bgep, (void *)ppd));
5122 
5123 	regoff = ppd->pp_acc_offset;
5124 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5125 	regoff &= MWBAR_GRANULE_MASK;
5126 	regoff += NIC_MEM_WINDOW_OFFSET;
5127 	regaddr = PIO_ADDR(bgep, regoff);
5128 	regval = ppd->pp_acc_data;
5129 
5130 	switch (ppd->pp_acc_size) {
5131 	case 1:
5132 		ddi_put8(bgep->io_handle, regaddr, regval);
5133 		break;
5134 
5135 	case 2:
5136 		ddi_put16(bgep->io_handle, regaddr, regval);
5137 		break;
5138 
5139 	case 4:
5140 		ddi_put32(bgep->io_handle, regaddr, regval);
5141 		break;
5142 
5143 	case 8:
5144 		ddi_put64(bgep->io_handle, regaddr, regval);
5145 		break;
5146 	}
5147 	BGE_PCICHK(bgep);
5148 }
5149 
5150 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5151 #pragma	no_inline(bge_chip_peek_mii)
5152 
5153 static void
5154 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5155 {
5156 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5157 	    (void *)bgep, (void *)ppd));
5158 
5159 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5160 }
5161 
5162 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5163 #pragma	no_inline(bge_chip_poke_mii)
5164 
5165 static void
5166 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5167 {
5168 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5169 	    (void *)bgep, (void *)ppd));
5170 
5171 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5172 }
5173 
5174 #if	BGE_SEE_IO32
5175 
5176 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5177 #pragma	no_inline(bge_chip_peek_seeprom)
5178 
5179 static void
5180 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5181 {
5182 	uint32_t data;
5183 	int err;
5184 
5185 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5186 	    (void *)bgep, (void *)ppd));
5187 
5188 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5189 	ppd->pp_acc_data = err ? ~0ull : data;
5190 }
5191 
5192 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5193 #pragma	no_inline(bge_chip_poke_seeprom)
5194 
5195 static void
5196 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5197 {
5198 	uint32_t data;
5199 
5200 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5201 	    (void *)bgep, (void *)ppd));
5202 
5203 	data = ppd->pp_acc_data;
5204 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5205 }
5206 #endif	/* BGE_SEE_IO32 */
5207 
5208 #if	BGE_FLASH_IO32
5209 
5210 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5211 #pragma	no_inline(bge_chip_peek_flash)
5212 
5213 static void
5214 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5215 {
5216 	uint32_t data;
5217 	int err;
5218 
5219 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5220 	    (void *)bgep, (void *)ppd));
5221 
5222 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5223 	ppd->pp_acc_data = err ? ~0ull : data;
5224 }
5225 
5226 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5227 #pragma	no_inline(bge_chip_poke_flash)
5228 
5229 static void
5230 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5231 {
5232 	uint32_t data;
5233 
5234 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5235 	    (void *)bgep, (void *)ppd));
5236 
5237 	data = ppd->pp_acc_data;
5238 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5239 	    ppd->pp_acc_offset, &data);
5240 }
5241 #endif	/* BGE_FLASH_IO32 */
5242 
5243 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5244 #pragma	no_inline(bge_chip_peek_mem)
5245 
5246 static void
5247 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5248 {
5249 	uint64_t regval;
5250 	void *vaddr;
5251 
5252 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5253 	    (void *)bgep, (void *)ppd));
5254 
5255 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5256 
5257 	switch (ppd->pp_acc_size) {
5258 	case 1:
5259 		regval = *(uint8_t *)vaddr;
5260 		break;
5261 
5262 	case 2:
5263 		regval = *(uint16_t *)vaddr;
5264 		break;
5265 
5266 	case 4:
5267 		regval = *(uint32_t *)vaddr;
5268 		break;
5269 
5270 	case 8:
5271 		regval = *(uint64_t *)vaddr;
5272 		break;
5273 	}
5274 
5275 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5276 	    (void *)bgep, (void *)ppd, regval, vaddr));
5277 
5278 	ppd->pp_acc_data = regval;
5279 }
5280 
5281 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5282 #pragma	no_inline(bge_chip_poke_mem)
5283 
5284 static void
5285 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5286 {
5287 	uint64_t regval;
5288 	void *vaddr;
5289 
5290 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5291 	    (void *)bgep, (void *)ppd));
5292 
5293 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5294 	regval = ppd->pp_acc_data;
5295 
5296 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5297 	    (void *)bgep, (void *)ppd, regval, vaddr));
5298 
5299 	switch (ppd->pp_acc_size) {
5300 	case 1:
5301 		*(uint8_t *)vaddr = (uint8_t)regval;
5302 		break;
5303 
5304 	case 2:
5305 		*(uint16_t *)vaddr = (uint16_t)regval;
5306 		break;
5307 
5308 	case 4:
5309 		*(uint32_t *)vaddr = (uint32_t)regval;
5310 		break;
5311 
5312 	case 8:
5313 		*(uint64_t *)vaddr = (uint64_t)regval;
5314 		break;
5315 	}
5316 }
5317 
5318 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5319 					struct iocblk *iocp);
5320 #pragma	no_inline(bge_pp_ioctl)
5321 
5322 static enum ioc_reply
5323 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5324 {
5325 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5326 	bge_peekpoke_t *ppd;
5327 	dma_area_t *areap;
5328 	uint64_t sizemask;
5329 	uint64_t mem_va;
5330 	uint64_t maxoff;
5331 	boolean_t peek;
5332 
5333 	switch (cmd) {
5334 	default:
5335 		/* NOTREACHED */
5336 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5337 		return (IOC_INVAL);
5338 
5339 	case BGE_PEEK:
5340 		peek = B_TRUE;
5341 		break;
5342 
5343 	case BGE_POKE:
5344 		peek = B_FALSE;
5345 		break;
5346 	}
5347 
5348 	/*
5349 	 * Validate format of ioctl
5350 	 */
5351 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5352 		return (IOC_INVAL);
5353 	if (mp->b_cont == NULL)
5354 		return (IOC_INVAL);
5355 	ppd = (void *)mp->b_cont->b_rptr;
5356 
5357 	/*
5358 	 * Validate request parameters
5359 	 */
5360 	switch (ppd->pp_acc_space) {
5361 	default:
5362 		return (IOC_INVAL);
5363 
5364 	case BGE_PP_SPACE_CFG:
5365 		/*
5366 		 * Config space
5367 		 */
5368 		sizemask = 8|4|2|1;
5369 		mem_va = 0;
5370 		maxoff = PCI_CONF_HDR_SIZE;
5371 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5372 		break;
5373 
5374 	case BGE_PP_SPACE_REG:
5375 		/*
5376 		 * Memory-mapped I/O space
5377 		 */
5378 		sizemask = 8|4|2|1;
5379 		mem_va = 0;
5380 		maxoff = RIAAR_REGISTER_MAX;
5381 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5382 		break;
5383 
5384 	case BGE_PP_SPACE_NIC:
5385 		/*
5386 		 * NIC on-chip memory
5387 		 */
5388 		sizemask = 8|4|2|1;
5389 		mem_va = 0;
5390 		maxoff = MWBAR_ONCHIP_MAX;
5391 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5392 		break;
5393 
5394 	case BGE_PP_SPACE_MII:
5395 		/*
5396 		 * PHY's MII registers
5397 		 * NB: all PHY registers are two bytes, but the
5398 		 * addresses increment in ones (word addressing).
5399 		 * So we scale the address here, then undo the
5400 		 * transformation inside the peek/poke functions.
5401 		 */
5402 		ppd->pp_acc_offset *= 2;
5403 		sizemask = 2;
5404 		mem_va = 0;
5405 		maxoff = (MII_MAXREG+1)*2;
5406 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5407 		break;
5408 
5409 #if	BGE_SEE_IO32
5410 	case BGE_PP_SPACE_SEEPROM:
5411 		/*
5412 		 * Attached SEEPROM(s), if any.
5413 		 * NB: we use the high-order bits of the 'address' as
5414 		 * a device select to accommodate multiple SEEPROMS,
5415 		 * If each one is the maximum size (64kbytes), this
5416 		 * makes them appear contiguous.  Otherwise, there may
5417 		 * be holes in the mapping.  ENxS doesn't have any
5418 		 * SEEPROMs anyway ...
5419 		 */
5420 		sizemask = 4;
5421 		mem_va = 0;
5422 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5423 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5424 		break;
5425 #endif	/* BGE_SEE_IO32 */
5426 
5427 #if	BGE_FLASH_IO32
5428 	case BGE_PP_SPACE_FLASH:
5429 		/*
5430 		 * Attached Flash device (if any); a maximum of one device
5431 		 * is currently supported.  But it can be up to 1MB (unlike
5432 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
5433 		 */
5434 		sizemask = 4;
5435 		mem_va = 0;
5436 		maxoff = NVM_FLASH_ADDR_MASK;
5437 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5438 		break;
5439 #endif	/* BGE_FLASH_IO32 */
5440 
5441 	case BGE_PP_SPACE_BGE:
5442 		/*
5443 		 * BGE data structure!
5444 		 */
5445 		sizemask = 8|4|2|1;
5446 		mem_va = (uintptr_t)bgep;
5447 		maxoff = sizeof (*bgep);
5448 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5449 		break;
5450 
5451 	case BGE_PP_SPACE_STATUS:
5452 	case BGE_PP_SPACE_STATISTICS:
5453 	case BGE_PP_SPACE_TXDESC:
5454 	case BGE_PP_SPACE_TXBUFF:
5455 	case BGE_PP_SPACE_RXDESC:
5456 	case BGE_PP_SPACE_RXBUFF:
5457 		/*
5458 		 * Various DMA_AREAs
5459 		 */
5460 		switch (ppd->pp_acc_space) {
5461 		case BGE_PP_SPACE_TXDESC:
5462 			areap = &bgep->tx_desc;
5463 			break;
5464 		case BGE_PP_SPACE_TXBUFF:
5465 			areap = &bgep->tx_buff[0];
5466 			break;
5467 		case BGE_PP_SPACE_RXDESC:
5468 			areap = &bgep->rx_desc[0];
5469 			break;
5470 		case BGE_PP_SPACE_RXBUFF:
5471 			areap = &bgep->rx_buff[0];
5472 			break;
5473 		case BGE_PP_SPACE_STATUS:
5474 			areap = &bgep->status_block;
5475 			break;
5476 		case BGE_PP_SPACE_STATISTICS:
5477 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5478 				areap = &bgep->statistics;
5479 			break;
5480 		}
5481 
5482 		sizemask = 8|4|2|1;
5483 		mem_va = (uintptr_t)areap->mem_va;
5484 		maxoff = areap->alength;
5485 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5486 		break;
5487 	}
5488 
5489 	switch (ppd->pp_acc_size) {
5490 	default:
5491 		return (IOC_INVAL);
5492 
5493 	case 8:
5494 	case 4:
5495 	case 2:
5496 	case 1:
5497 		if ((ppd->pp_acc_size & sizemask) == 0)
5498 			return (IOC_INVAL);
5499 		break;
5500 	}
5501 
5502 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5503 		return (IOC_INVAL);
5504 
5505 	if (ppd->pp_acc_offset >= maxoff)
5506 		return (IOC_INVAL);
5507 
5508 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5509 		return (IOC_INVAL);
5510 
5511 	/*
5512 	 * All OK - go do it!
5513 	 */
5514 	ppd->pp_acc_offset += mem_va;
5515 	(*ppfn)(bgep, ppd);
5516 	return (peek ? IOC_REPLY : IOC_ACK);
5517 }
5518 
5519 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5520 					struct iocblk *iocp);
5521 #pragma	no_inline(bge_diag_ioctl)
5522 
5523 static enum ioc_reply
5524 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5525 {
5526 	ASSERT(mutex_owned(bgep->genlock));
5527 
5528 	switch (cmd) {
5529 	default:
5530 		/* NOTREACHED */
5531 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5532 		return (IOC_INVAL);
5533 
5534 	case BGE_DIAG:
5535 		/*
5536 		 * Currently a no-op
5537 		 */
5538 		return (IOC_ACK);
5539 
5540 	case BGE_PEEK:
5541 	case BGE_POKE:
5542 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5543 
5544 	case BGE_PHY_RESET:
5545 		return (IOC_RESTART_ACK);
5546 
5547 	case BGE_SOFT_RESET:
5548 	case BGE_HARD_RESET:
5549 		/*
5550 		 * Reset and reinitialise the 570x hardware
5551 		 */
5552 		bgep->bge_chip_state = BGE_CHIP_FAULT;
5553 		ddi_trigger_softintr(bgep->factotum_id);
5554 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5555 		return (IOC_ACK);
5556 	}
5557 
5558 	/* NOTREACHED */
5559 }
5560 
5561 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5562 
5563 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5564 				    struct iocblk *iocp);
5565 #pragma	no_inline(bge_mii_ioctl)
5566 
5567 static enum ioc_reply
5568 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5569 {
5570 	struct bge_mii_rw *miirwp;
5571 
5572 	/*
5573 	 * Validate format of ioctl
5574 	 */
5575 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5576 		return (IOC_INVAL);
5577 	if (mp->b_cont == NULL)
5578 		return (IOC_INVAL);
5579 	miirwp = (void *)mp->b_cont->b_rptr;
5580 
5581 	/*
5582 	 * Validate request parameters ...
5583 	 */
5584 	if (miirwp->mii_reg > MII_MAXREG)
5585 		return (IOC_INVAL);
5586 
5587 	switch (cmd) {
5588 	default:
5589 		/* NOTREACHED */
5590 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5591 		return (IOC_INVAL);
5592 
5593 	case BGE_MII_READ:
5594 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5595 		return (IOC_REPLY);
5596 
5597 	case BGE_MII_WRITE:
5598 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5599 		return (IOC_ACK);
5600 	}
5601 
5602 	/* NOTREACHED */
5603 }
5604 
5605 #if	BGE_SEE_IO32
5606 
5607 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5608 				    struct iocblk *iocp);
5609 #pragma	no_inline(bge_see_ioctl)
5610 
5611 static enum ioc_reply
5612 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5613 {
5614 	struct bge_see_rw *seerwp;
5615 
5616 	/*
5617 	 * Validate format of ioctl
5618 	 */
5619 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5620 		return (IOC_INVAL);
5621 	if (mp->b_cont == NULL)
5622 		return (IOC_INVAL);
5623 	seerwp = (void *)mp->b_cont->b_rptr;
5624 
5625 	/*
5626 	 * Validate request parameters ...
5627 	 */
5628 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5629 		return (IOC_INVAL);
5630 
5631 	switch (cmd) {
5632 	default:
5633 		/* NOTREACHED */
5634 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5635 		return (IOC_INVAL);
5636 
5637 	case BGE_SEE_READ:
5638 	case BGE_SEE_WRITE:
5639 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5640 		    seerwp->see_addr, &seerwp->see_data);
5641 		return (IOC_REPLY);
5642 	}
5643 
5644 	/* NOTREACHED */
5645 }
5646 
5647 #endif	/* BGE_SEE_IO32 */
5648 
5649 #if	BGE_FLASH_IO32
5650 
5651 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5652 				    struct iocblk *iocp);
5653 #pragma	no_inline(bge_flash_ioctl)
5654 
5655 static enum ioc_reply
5656 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5657 {
5658 	struct bge_flash_rw *flashrwp;
5659 
5660 	/*
5661 	 * Validate format of ioctl
5662 	 */
5663 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5664 		return (IOC_INVAL);
5665 	if (mp->b_cont == NULL)
5666 		return (IOC_INVAL);
5667 	flashrwp = (void *)mp->b_cont->b_rptr;
5668 
5669 	/*
5670 	 * Validate request parameters ...
5671 	 */
5672 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5673 		return (IOC_INVAL);
5674 
5675 	switch (cmd) {
5676 	default:
5677 		/* NOTREACHED */
5678 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5679 		return (IOC_INVAL);
5680 
5681 	case BGE_FLASH_READ:
5682 	case BGE_FLASH_WRITE:
5683 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5684 		    flashrwp->flash_addr, &flashrwp->flash_data);
5685 		return (IOC_REPLY);
5686 	}
5687 
5688 	/* NOTREACHED */
5689 }
5690 
5691 #endif	/* BGE_FLASH_IO32 */
5692 
5693 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5694 				struct iocblk *iocp);
5695 #pragma	no_inline(bge_chip_ioctl)
5696 
5697 enum ioc_reply
5698 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5699 {
5700 	int cmd;
5701 
5702 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5703 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5704 
5705 	ASSERT(mutex_owned(bgep->genlock));
5706 
5707 	cmd = iocp->ioc_cmd;
5708 	switch (cmd) {
5709 	default:
5710 		/* NOTREACHED */
5711 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5712 		return (IOC_INVAL);
5713 
5714 	case BGE_DIAG:
5715 	case BGE_PEEK:
5716 	case BGE_POKE:
5717 	case BGE_PHY_RESET:
5718 	case BGE_SOFT_RESET:
5719 	case BGE_HARD_RESET:
5720 #if	BGE_DEBUGGING || BGE_DO_PPIO
5721 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5722 #else
5723 		return (IOC_INVAL);
5724 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5725 
5726 	case BGE_MII_READ:
5727 	case BGE_MII_WRITE:
5728 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5729 
5730 #if	BGE_SEE_IO32
5731 	case BGE_SEE_READ:
5732 	case BGE_SEE_WRITE:
5733 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5734 #endif	/* BGE_SEE_IO32 */
5735 
5736 #if	BGE_FLASH_IO32
5737 	case BGE_FLASH_READ:
5738 	case BGE_FLASH_WRITE:
5739 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5740 #endif	/* BGE_FLASH_IO32 */
5741 	}
5742 
5743 	/* NOTREACHED */
5744 }
5745 
5746 /* ARGSUSED */
5747 void
5748 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
5749 {
5750 	recv_ring_t *rrp = arg;
5751 	bge_t *bgep = rrp->bgep;
5752 
5753 	mutex_enter(bgep->genlock);
5754 	rrp->poll_flag = flag;
5755 #ifdef NOT_YET
5756 	/*
5757 	 * XXX-Sunay: Since most broadcom cards support only one
5758 	 * interrupt but multiple rx rings, we can't disable the
5759 	 * physical interrupt. This need to be done via capability
5760 	 * negotiation depending on the NIC.
5761 	 */
5762 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5763 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5764 #endif
5765 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5766 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5767 	mutex_exit(bgep->genlock);
5768 }
5769 
5770 #ifdef BGE_IPMI_ASF
5771 
5772 uint32_t
5773 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5774 {
5775 	uint32_t data;
5776 
5777 #ifndef __sparc
5778 	if (!bgep->asf_wordswapped) {
5779 		/* a workaround word swap error */
5780 		if (addr & 4)
5781 			addr = addr - 4;
5782 		else
5783 			addr = addr + 4;
5784 	}
5785 #else
5786 	if (DEVICE_5717_SERIES_CHIPSETS(bgep))
5787 		addr = LE_32(addr);
5788 #endif
5789 
5790 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5791 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5792 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5793 
5794 	data = LE_32(data);
5795 
5796 	BGE_DEBUG(("bge_nic_read32($%p, 0x%x) => 0x%x",
5797 	    (void *)bgep, addr, data));
5798 
5799 	return (data);
5800 }
5801 
5802 void
5803 bge_asf_update_status(bge_t *bgep)
5804 {
5805 	uint32_t event;
5806 
5807 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5808 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5809 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5810 
5811 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5812 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5813 }
5814 
5815 
5816 /*
5817  * The driver is supposed to notify ASF that the OS is still running
5818  * every three seconds, otherwise the management server may attempt
5819  * to reboot the machine.  If it hasn't actually failed, this is
5820  * not a desirable result.  However, this isn't running as a real-time
5821  * thread, and even if it were, it might not be able to generate the
5822  * heartbeat in a timely manner due to system load.  As it isn't a
5823  * significant strain on the machine, we will set the interval to half
5824  * of the required value.
5825  */
5826 void
5827 bge_asf_heartbeat(void *arg)
5828 {
5829 	bge_t *bgep = (bge_t *)arg;
5830 
5831 	mutex_enter(bgep->genlock);
5832 	bge_asf_update_status((bge_t *)bgep);
5833 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5834 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5835 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5836 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5837 	mutex_exit(bgep->genlock);
5838 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5839 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5840 }
5841 
5842 
5843 void
5844 bge_asf_stop_timer(bge_t *bgep)
5845 {
5846 	timeout_id_t tmp_id = 0;
5847 
5848 	while ((bgep->asf_timeout_id != 0) &&
5849 	    (tmp_id != bgep->asf_timeout_id)) {
5850 		tmp_id = bgep->asf_timeout_id;
5851 		(void) untimeout(tmp_id);
5852 	}
5853 	bgep->asf_timeout_id = 0;
5854 }
5855 
5856 
5857 
5858 /*
5859  * This function should be placed at the earliest position of bge_attach().
5860  */
5861 void
5862 bge_asf_get_config(bge_t *bgep)
5863 {
5864 	uint32_t nicsig;
5865 	uint32_t niccfg;
5866 
5867 	bgep->asf_enabled = B_FALSE;
5868 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5869 	if (nicsig == BGE_NIC_DATA_SIG) {
5870 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5871 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5872 			/*
5873 			 * Here, we don't consider BAXTER, because BGE haven't
5874 			 * supported BAXTER (that is 5752). Also, as I know,
5875 			 * BAXTER doesn't support ASF feature.
5876 			 */
5877 			bgep->asf_enabled = B_TRUE;
5878 		else
5879 			bgep->asf_enabled = B_FALSE;
5880 	} else
5881 		bgep->asf_enabled = B_FALSE;
5882 }
5883 
5884 
5885 void
5886 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5887 {
5888 	uint32_t tries;
5889 	uint32_t event;
5890 
5891 	ASSERT(bgep->asf_enabled);
5892 
5893 	/* Issues "pause firmware" command and wait for ACK */
5894 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5895 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5896 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5897 
5898 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5899 	tries = 0;
5900 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5901 		drv_usecwait(1);
5902 		tries ++;
5903 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5904 	}
5905 
5906 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5907 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5908 
5909 	if (bgep->asf_newhandshake) {
5910 		switch (mode) {
5911 		case BGE_INIT_RESET:
5912 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5913 			    BGE_DRV_STATE_START);
5914 			break;
5915 		case BGE_SHUTDOWN_RESET:
5916 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5917 			    BGE_DRV_STATE_UNLOAD);
5918 			break;
5919 		case BGE_SUSPEND_RESET:
5920 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5921 			    BGE_DRV_STATE_SUSPEND);
5922 			break;
5923 		default:
5924 			break;
5925 		}
5926 	}
5927 }
5928 
5929 
5930 void
5931 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5932 {
5933 	switch (mode) {
5934 	case BGE_INIT_RESET:
5935 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5936 		    BGE_DRV_STATE_START);
5937 		break;
5938 	case BGE_SHUTDOWN_RESET:
5939 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5940 		    BGE_DRV_STATE_UNLOAD);
5941 		break;
5942 	case BGE_SUSPEND_RESET:
5943 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5944 		    BGE_DRV_STATE_SUSPEND);
5945 		break;
5946 	default:
5947 		break;
5948 	}
5949 }
5950 
5951 
5952 void
5953 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5954 {
5955 	switch (mode) {
5956 	case BGE_INIT_RESET:
5957 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5958 		    BGE_DRV_STATE_START_DONE);
5959 		break;
5960 	case BGE_SHUTDOWN_RESET:
5961 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5962 		    BGE_DRV_STATE_UNLOAD_DONE);
5963 		break;
5964 	default:
5965 		break;
5966 	}
5967 }
5968 
5969 #endif /* BGE_IPMI_ASF */
5970