1 /* 2 * intel_pt.c: Intel Processor Trace support 3 * Copyright (c) 2013-2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #include <inttypes.h> 17 #include <stdio.h> 18 #include <stdbool.h> 19 #include <errno.h> 20 #include <linux/kernel.h> 21 #include <linux/types.h> 22 23 #include "../perf.h" 24 #include "session.h" 25 #include "machine.h" 26 #include "memswap.h" 27 #include "sort.h" 28 #include "tool.h" 29 #include "event.h" 30 #include "evlist.h" 31 #include "evsel.h" 32 #include "map.h" 33 #include "color.h" 34 #include "util.h" 35 #include "thread.h" 36 #include "thread-stack.h" 37 #include "symbol.h" 38 #include "callchain.h" 39 #include "dso.h" 40 #include "debug.h" 41 #include "auxtrace.h" 42 #include "tsc.h" 43 #include "intel-pt.h" 44 #include "config.h" 45 46 #include "intel-pt-decoder/intel-pt-log.h" 47 #include "intel-pt-decoder/intel-pt-decoder.h" 48 #include "intel-pt-decoder/intel-pt-insn-decoder.h" 49 #include "intel-pt-decoder/intel-pt-pkt-decoder.h" 50 51 #define MAX_TIMESTAMP (~0ULL) 52 53 struct intel_pt { 54 struct auxtrace auxtrace; 55 struct auxtrace_queues queues; 56 struct auxtrace_heap heap; 57 u32 auxtrace_type; 58 struct perf_session *session; 59 struct machine *machine; 60 struct perf_evsel *switch_evsel; 61 struct thread *unknown_thread; 62 bool timeless_decoding; 63 bool sampling_mode; 64 bool snapshot_mode; 65 bool per_cpu_mmaps; 66 bool have_tsc; 67 bool data_queued; 68 bool est_tsc; 69 bool sync_switch; 70 bool mispred_all; 71 int have_sched_switch; 72 u32 pmu_type; 73 u64 kernel_start; 74 u64 switch_ip; 75 u64 ptss_ip; 76 77 struct perf_tsc_conversion tc; 78 bool cap_user_time_zero; 79 80 struct itrace_synth_opts synth_opts; 81 82 bool sample_instructions; 83 u64 instructions_sample_type; 84 u64 instructions_id; 85 86 bool sample_branches; 87 u32 branches_filter; 88 u64 branches_sample_type; 89 u64 branches_id; 90 91 bool sample_transactions; 92 u64 transactions_sample_type; 93 u64 transactions_id; 94 95 bool sample_ptwrites; 96 u64 ptwrites_sample_type; 97 u64 ptwrites_id; 98 99 bool sample_pwr_events; 100 u64 pwr_events_sample_type; 101 u64 mwait_id; 102 u64 pwre_id; 103 u64 exstop_id; 104 u64 pwrx_id; 105 u64 cbr_id; 106 107 u64 tsc_bit; 108 u64 mtc_bit; 109 u64 mtc_freq_bits; 110 u32 tsc_ctc_ratio_n; 111 u32 tsc_ctc_ratio_d; 112 u64 cyc_bit; 113 u64 noretcomp_bit; 114 unsigned max_non_turbo_ratio; 115 unsigned cbr2khz; 116 117 unsigned long num_events; 118 119 char *filter; 120 struct addr_filters filts; 121 }; 122 123 enum switch_state { 124 INTEL_PT_SS_NOT_TRACING, 125 INTEL_PT_SS_UNKNOWN, 126 INTEL_PT_SS_TRACING, 127 INTEL_PT_SS_EXPECTING_SWITCH_EVENT, 128 INTEL_PT_SS_EXPECTING_SWITCH_IP, 129 }; 130 131 struct intel_pt_queue { 132 struct intel_pt *pt; 133 unsigned int queue_nr; 134 struct auxtrace_buffer *buffer; 135 struct auxtrace_buffer *old_buffer; 136 void *decoder; 137 const struct intel_pt_state *state; 138 struct ip_callchain *chain; 139 struct branch_stack *last_branch; 140 struct branch_stack *last_branch_rb; 141 size_t last_branch_pos; 142 union perf_event *event_buf; 143 bool on_heap; 144 bool stop; 145 bool step_through_buffers; 146 bool use_buffer_pid_tid; 147 bool sync_switch; 148 pid_t pid, tid; 149 int cpu; 150 int switch_state; 151 pid_t next_tid; 152 struct thread *thread; 153 bool exclude_kernel; 154 bool have_sample; 155 u64 time; 156 u64 timestamp; 157 u32 flags; 158 u16 insn_len; 159 u64 last_insn_cnt; 160 char insn[INTEL_PT_INSN_BUF_SZ]; 161 }; 162 163 static void intel_pt_dump(struct intel_pt *pt __maybe_unused, 164 unsigned char *buf, size_t len) 165 { 166 struct intel_pt_pkt packet; 167 size_t pos = 0; 168 int ret, pkt_len, i; 169 char desc[INTEL_PT_PKT_DESC_MAX]; 170 const char *color = PERF_COLOR_BLUE; 171 172 color_fprintf(stdout, color, 173 ". ... Intel Processor Trace data: size %zu bytes\n", 174 len); 175 176 while (len) { 177 ret = intel_pt_get_packet(buf, len, &packet); 178 if (ret > 0) 179 pkt_len = ret; 180 else 181 pkt_len = 1; 182 printf("."); 183 color_fprintf(stdout, color, " %08x: ", pos); 184 for (i = 0; i < pkt_len; i++) 185 color_fprintf(stdout, color, " %02x", buf[i]); 186 for (; i < 16; i++) 187 color_fprintf(stdout, color, " "); 188 if (ret > 0) { 189 ret = intel_pt_pkt_desc(&packet, desc, 190 INTEL_PT_PKT_DESC_MAX); 191 if (ret > 0) 192 color_fprintf(stdout, color, " %s\n", desc); 193 } else { 194 color_fprintf(stdout, color, " Bad packet!\n"); 195 } 196 pos += pkt_len; 197 buf += pkt_len; 198 len -= pkt_len; 199 } 200 } 201 202 static void intel_pt_dump_event(struct intel_pt *pt, unsigned char *buf, 203 size_t len) 204 { 205 printf(".\n"); 206 intel_pt_dump(pt, buf, len); 207 } 208 209 static int intel_pt_do_fix_overlap(struct intel_pt *pt, struct auxtrace_buffer *a, 210 struct auxtrace_buffer *b) 211 { 212 bool consecutive = false; 213 void *start; 214 215 start = intel_pt_find_overlap(a->data, a->size, b->data, b->size, 216 pt->have_tsc, &consecutive); 217 if (!start) 218 return -EINVAL; 219 b->use_size = b->data + b->size - start; 220 b->use_data = start; 221 if (b->use_size && consecutive) 222 b->consecutive = true; 223 return 0; 224 } 225 226 /* This function assumes data is processed sequentially only */ 227 static int intel_pt_get_trace(struct intel_pt_buffer *b, void *data) 228 { 229 struct intel_pt_queue *ptq = data; 230 struct auxtrace_buffer *buffer = ptq->buffer; 231 struct auxtrace_buffer *old_buffer = ptq->old_buffer; 232 struct auxtrace_queue *queue; 233 bool might_overlap; 234 235 if (ptq->stop) { 236 b->len = 0; 237 return 0; 238 } 239 240 queue = &ptq->pt->queues.queue_array[ptq->queue_nr]; 241 242 buffer = auxtrace_buffer__next(queue, buffer); 243 if (!buffer) { 244 if (old_buffer) 245 auxtrace_buffer__drop_data(old_buffer); 246 b->len = 0; 247 return 0; 248 } 249 250 ptq->buffer = buffer; 251 252 if (!buffer->data) { 253 int fd = perf_data__fd(ptq->pt->session->data); 254 255 buffer->data = auxtrace_buffer__get_data(buffer, fd); 256 if (!buffer->data) 257 return -ENOMEM; 258 } 259 260 might_overlap = ptq->pt->snapshot_mode || ptq->pt->sampling_mode; 261 if (might_overlap && !buffer->consecutive && old_buffer && 262 intel_pt_do_fix_overlap(ptq->pt, old_buffer, buffer)) 263 return -ENOMEM; 264 265 if (buffer->use_data) { 266 b->len = buffer->use_size; 267 b->buf = buffer->use_data; 268 } else { 269 b->len = buffer->size; 270 b->buf = buffer->data; 271 } 272 b->ref_timestamp = buffer->reference; 273 274 if (!old_buffer || (might_overlap && !buffer->consecutive)) { 275 b->consecutive = false; 276 b->trace_nr = buffer->buffer_nr + 1; 277 } else { 278 b->consecutive = true; 279 } 280 281 if (ptq->step_through_buffers) 282 ptq->stop = true; 283 284 if (b->len) { 285 if (old_buffer) 286 auxtrace_buffer__drop_data(old_buffer); 287 ptq->old_buffer = buffer; 288 } else { 289 auxtrace_buffer__drop_data(buffer); 290 return intel_pt_get_trace(b, data); 291 } 292 293 return 0; 294 } 295 296 struct intel_pt_cache_entry { 297 struct auxtrace_cache_entry entry; 298 u64 insn_cnt; 299 u64 byte_cnt; 300 enum intel_pt_insn_op op; 301 enum intel_pt_insn_branch branch; 302 int length; 303 int32_t rel; 304 char insn[INTEL_PT_INSN_BUF_SZ]; 305 }; 306 307 static int intel_pt_config_div(const char *var, const char *value, void *data) 308 { 309 int *d = data; 310 long val; 311 312 if (!strcmp(var, "intel-pt.cache-divisor")) { 313 val = strtol(value, NULL, 0); 314 if (val > 0 && val <= INT_MAX) 315 *d = val; 316 } 317 318 return 0; 319 } 320 321 static int intel_pt_cache_divisor(void) 322 { 323 static int d; 324 325 if (d) 326 return d; 327 328 perf_config(intel_pt_config_div, &d); 329 330 if (!d) 331 d = 64; 332 333 return d; 334 } 335 336 static unsigned int intel_pt_cache_size(struct dso *dso, 337 struct machine *machine) 338 { 339 off_t size; 340 341 size = dso__data_size(dso, machine); 342 size /= intel_pt_cache_divisor(); 343 if (size < 1000) 344 return 10; 345 if (size > (1 << 21)) 346 return 21; 347 return 32 - __builtin_clz(size); 348 } 349 350 static struct auxtrace_cache *intel_pt_cache(struct dso *dso, 351 struct machine *machine) 352 { 353 struct auxtrace_cache *c; 354 unsigned int bits; 355 356 if (dso->auxtrace_cache) 357 return dso->auxtrace_cache; 358 359 bits = intel_pt_cache_size(dso, machine); 360 361 /* Ignoring cache creation failure */ 362 c = auxtrace_cache__new(bits, sizeof(struct intel_pt_cache_entry), 200); 363 364 dso->auxtrace_cache = c; 365 366 return c; 367 } 368 369 static int intel_pt_cache_add(struct dso *dso, struct machine *machine, 370 u64 offset, u64 insn_cnt, u64 byte_cnt, 371 struct intel_pt_insn *intel_pt_insn) 372 { 373 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 374 struct intel_pt_cache_entry *e; 375 int err; 376 377 if (!c) 378 return -ENOMEM; 379 380 e = auxtrace_cache__alloc_entry(c); 381 if (!e) 382 return -ENOMEM; 383 384 e->insn_cnt = insn_cnt; 385 e->byte_cnt = byte_cnt; 386 e->op = intel_pt_insn->op; 387 e->branch = intel_pt_insn->branch; 388 e->length = intel_pt_insn->length; 389 e->rel = intel_pt_insn->rel; 390 memcpy(e->insn, intel_pt_insn->buf, INTEL_PT_INSN_BUF_SZ); 391 392 err = auxtrace_cache__add(c, offset, &e->entry); 393 if (err) 394 auxtrace_cache__free_entry(c, e); 395 396 return err; 397 } 398 399 static struct intel_pt_cache_entry * 400 intel_pt_cache_lookup(struct dso *dso, struct machine *machine, u64 offset) 401 { 402 struct auxtrace_cache *c = intel_pt_cache(dso, machine); 403 404 if (!c) 405 return NULL; 406 407 return auxtrace_cache__lookup(dso->auxtrace_cache, offset); 408 } 409 410 static int intel_pt_walk_next_insn(struct intel_pt_insn *intel_pt_insn, 411 uint64_t *insn_cnt_ptr, uint64_t *ip, 412 uint64_t to_ip, uint64_t max_insn_cnt, 413 void *data) 414 { 415 struct intel_pt_queue *ptq = data; 416 struct machine *machine = ptq->pt->machine; 417 struct thread *thread; 418 struct addr_location al; 419 unsigned char buf[INTEL_PT_INSN_BUF_SZ]; 420 ssize_t len; 421 int x86_64; 422 u8 cpumode; 423 u64 offset, start_offset, start_ip; 424 u64 insn_cnt = 0; 425 bool one_map = true; 426 427 intel_pt_insn->length = 0; 428 429 if (to_ip && *ip == to_ip) 430 goto out_no_cache; 431 432 if (*ip >= ptq->pt->kernel_start) 433 cpumode = PERF_RECORD_MISC_KERNEL; 434 else 435 cpumode = PERF_RECORD_MISC_USER; 436 437 thread = ptq->thread; 438 if (!thread) { 439 if (cpumode != PERF_RECORD_MISC_KERNEL) 440 return -EINVAL; 441 thread = ptq->pt->unknown_thread; 442 } 443 444 while (1) { 445 if (!thread__find_map(thread, cpumode, *ip, &al) || !al.map->dso) 446 return -EINVAL; 447 448 if (al.map->dso->data.status == DSO_DATA_STATUS_ERROR && 449 dso__data_status_seen(al.map->dso, 450 DSO_DATA_STATUS_SEEN_ITRACE)) 451 return -ENOENT; 452 453 offset = al.map->map_ip(al.map, *ip); 454 455 if (!to_ip && one_map) { 456 struct intel_pt_cache_entry *e; 457 458 e = intel_pt_cache_lookup(al.map->dso, machine, offset); 459 if (e && 460 (!max_insn_cnt || e->insn_cnt <= max_insn_cnt)) { 461 *insn_cnt_ptr = e->insn_cnt; 462 *ip += e->byte_cnt; 463 intel_pt_insn->op = e->op; 464 intel_pt_insn->branch = e->branch; 465 intel_pt_insn->length = e->length; 466 intel_pt_insn->rel = e->rel; 467 memcpy(intel_pt_insn->buf, e->insn, 468 INTEL_PT_INSN_BUF_SZ); 469 intel_pt_log_insn_no_data(intel_pt_insn, *ip); 470 return 0; 471 } 472 } 473 474 start_offset = offset; 475 start_ip = *ip; 476 477 /* Load maps to ensure dso->is_64_bit has been updated */ 478 map__load(al.map); 479 480 x86_64 = al.map->dso->is_64_bit; 481 482 while (1) { 483 len = dso__data_read_offset(al.map->dso, machine, 484 offset, buf, 485 INTEL_PT_INSN_BUF_SZ); 486 if (len <= 0) 487 return -EINVAL; 488 489 if (intel_pt_get_insn(buf, len, x86_64, intel_pt_insn)) 490 return -EINVAL; 491 492 intel_pt_log_insn(intel_pt_insn, *ip); 493 494 insn_cnt += 1; 495 496 if (intel_pt_insn->branch != INTEL_PT_BR_NO_BRANCH) 497 goto out; 498 499 if (max_insn_cnt && insn_cnt >= max_insn_cnt) 500 goto out_no_cache; 501 502 *ip += intel_pt_insn->length; 503 504 if (to_ip && *ip == to_ip) 505 goto out_no_cache; 506 507 if (*ip >= al.map->end) 508 break; 509 510 offset += intel_pt_insn->length; 511 } 512 one_map = false; 513 } 514 out: 515 *insn_cnt_ptr = insn_cnt; 516 517 if (!one_map) 518 goto out_no_cache; 519 520 /* 521 * Didn't lookup in the 'to_ip' case, so do it now to prevent duplicate 522 * entries. 523 */ 524 if (to_ip) { 525 struct intel_pt_cache_entry *e; 526 527 e = intel_pt_cache_lookup(al.map->dso, machine, start_offset); 528 if (e) 529 return 0; 530 } 531 532 /* Ignore cache errors */ 533 intel_pt_cache_add(al.map->dso, machine, start_offset, insn_cnt, 534 *ip - start_ip, intel_pt_insn); 535 536 return 0; 537 538 out_no_cache: 539 *insn_cnt_ptr = insn_cnt; 540 return 0; 541 } 542 543 static bool intel_pt_match_pgd_ip(struct intel_pt *pt, uint64_t ip, 544 uint64_t offset, const char *filename) 545 { 546 struct addr_filter *filt; 547 bool have_filter = false; 548 bool hit_tracestop = false; 549 bool hit_filter = false; 550 551 list_for_each_entry(filt, &pt->filts.head, list) { 552 if (filt->start) 553 have_filter = true; 554 555 if ((filename && !filt->filename) || 556 (!filename && filt->filename) || 557 (filename && strcmp(filename, filt->filename))) 558 continue; 559 560 if (!(offset >= filt->addr && offset < filt->addr + filt->size)) 561 continue; 562 563 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s hit filter: %s offset %#"PRIx64" size %#"PRIx64"\n", 564 ip, offset, filename ? filename : "[kernel]", 565 filt->start ? "filter" : "stop", 566 filt->addr, filt->size); 567 568 if (filt->start) 569 hit_filter = true; 570 else 571 hit_tracestop = true; 572 } 573 574 if (!hit_tracestop && !hit_filter) 575 intel_pt_log("TIP.PGD ip %#"PRIx64" offset %#"PRIx64" in %s is not in a filter region\n", 576 ip, offset, filename ? filename : "[kernel]"); 577 578 return hit_tracestop || (have_filter && !hit_filter); 579 } 580 581 static int __intel_pt_pgd_ip(uint64_t ip, void *data) 582 { 583 struct intel_pt_queue *ptq = data; 584 struct thread *thread; 585 struct addr_location al; 586 u8 cpumode; 587 u64 offset; 588 589 if (ip >= ptq->pt->kernel_start) 590 return intel_pt_match_pgd_ip(ptq->pt, ip, ip, NULL); 591 592 cpumode = PERF_RECORD_MISC_USER; 593 594 thread = ptq->thread; 595 if (!thread) 596 return -EINVAL; 597 598 if (!thread__find_map(thread, cpumode, ip, &al) || !al.map->dso) 599 return -EINVAL; 600 601 offset = al.map->map_ip(al.map, ip); 602 603 return intel_pt_match_pgd_ip(ptq->pt, ip, offset, 604 al.map->dso->long_name); 605 } 606 607 static bool intel_pt_pgd_ip(uint64_t ip, void *data) 608 { 609 return __intel_pt_pgd_ip(ip, data) > 0; 610 } 611 612 static bool intel_pt_get_config(struct intel_pt *pt, 613 struct perf_event_attr *attr, u64 *config) 614 { 615 if (attr->type == pt->pmu_type) { 616 if (config) 617 *config = attr->config; 618 return true; 619 } 620 621 return false; 622 } 623 624 static bool intel_pt_exclude_kernel(struct intel_pt *pt) 625 { 626 struct perf_evsel *evsel; 627 628 evlist__for_each_entry(pt->session->evlist, evsel) { 629 if (intel_pt_get_config(pt, &evsel->attr, NULL) && 630 !evsel->attr.exclude_kernel) 631 return false; 632 } 633 return true; 634 } 635 636 static bool intel_pt_return_compression(struct intel_pt *pt) 637 { 638 struct perf_evsel *evsel; 639 u64 config; 640 641 if (!pt->noretcomp_bit) 642 return true; 643 644 evlist__for_each_entry(pt->session->evlist, evsel) { 645 if (intel_pt_get_config(pt, &evsel->attr, &config) && 646 (config & pt->noretcomp_bit)) 647 return false; 648 } 649 return true; 650 } 651 652 static bool intel_pt_branch_enable(struct intel_pt *pt) 653 { 654 struct perf_evsel *evsel; 655 u64 config; 656 657 evlist__for_each_entry(pt->session->evlist, evsel) { 658 if (intel_pt_get_config(pt, &evsel->attr, &config) && 659 (config & 1) && !(config & 0x2000)) 660 return false; 661 } 662 return true; 663 } 664 665 static unsigned int intel_pt_mtc_period(struct intel_pt *pt) 666 { 667 struct perf_evsel *evsel; 668 unsigned int shift; 669 u64 config; 670 671 if (!pt->mtc_freq_bits) 672 return 0; 673 674 for (shift = 0, config = pt->mtc_freq_bits; !(config & 1); shift++) 675 config >>= 1; 676 677 evlist__for_each_entry(pt->session->evlist, evsel) { 678 if (intel_pt_get_config(pt, &evsel->attr, &config)) 679 return (config & pt->mtc_freq_bits) >> shift; 680 } 681 return 0; 682 } 683 684 static bool intel_pt_timeless_decoding(struct intel_pt *pt) 685 { 686 struct perf_evsel *evsel; 687 bool timeless_decoding = true; 688 u64 config; 689 690 if (!pt->tsc_bit || !pt->cap_user_time_zero) 691 return true; 692 693 evlist__for_each_entry(pt->session->evlist, evsel) { 694 if (!(evsel->attr.sample_type & PERF_SAMPLE_TIME)) 695 return true; 696 if (intel_pt_get_config(pt, &evsel->attr, &config)) { 697 if (config & pt->tsc_bit) 698 timeless_decoding = false; 699 else 700 return true; 701 } 702 } 703 return timeless_decoding; 704 } 705 706 static bool intel_pt_tracing_kernel(struct intel_pt *pt) 707 { 708 struct perf_evsel *evsel; 709 710 evlist__for_each_entry(pt->session->evlist, evsel) { 711 if (intel_pt_get_config(pt, &evsel->attr, NULL) && 712 !evsel->attr.exclude_kernel) 713 return true; 714 } 715 return false; 716 } 717 718 static bool intel_pt_have_tsc(struct intel_pt *pt) 719 { 720 struct perf_evsel *evsel; 721 bool have_tsc = false; 722 u64 config; 723 724 if (!pt->tsc_bit) 725 return false; 726 727 evlist__for_each_entry(pt->session->evlist, evsel) { 728 if (intel_pt_get_config(pt, &evsel->attr, &config)) { 729 if (config & pt->tsc_bit) 730 have_tsc = true; 731 else 732 return false; 733 } 734 } 735 return have_tsc; 736 } 737 738 static u64 intel_pt_ns_to_ticks(const struct intel_pt *pt, u64 ns) 739 { 740 u64 quot, rem; 741 742 quot = ns / pt->tc.time_mult; 743 rem = ns % pt->tc.time_mult; 744 return (quot << pt->tc.time_shift) + (rem << pt->tc.time_shift) / 745 pt->tc.time_mult; 746 } 747 748 static struct intel_pt_queue *intel_pt_alloc_queue(struct intel_pt *pt, 749 unsigned int queue_nr) 750 { 751 struct intel_pt_params params = { .get_trace = 0, }; 752 struct intel_pt_queue *ptq; 753 754 ptq = zalloc(sizeof(struct intel_pt_queue)); 755 if (!ptq) 756 return NULL; 757 758 if (pt->synth_opts.callchain) { 759 size_t sz = sizeof(struct ip_callchain); 760 761 sz += pt->synth_opts.callchain_sz * sizeof(u64); 762 ptq->chain = zalloc(sz); 763 if (!ptq->chain) 764 goto out_free; 765 } 766 767 if (pt->synth_opts.last_branch) { 768 size_t sz = sizeof(struct branch_stack); 769 770 sz += pt->synth_opts.last_branch_sz * 771 sizeof(struct branch_entry); 772 ptq->last_branch = zalloc(sz); 773 if (!ptq->last_branch) 774 goto out_free; 775 ptq->last_branch_rb = zalloc(sz); 776 if (!ptq->last_branch_rb) 777 goto out_free; 778 } 779 780 ptq->event_buf = malloc(PERF_SAMPLE_MAX_SIZE); 781 if (!ptq->event_buf) 782 goto out_free; 783 784 ptq->pt = pt; 785 ptq->queue_nr = queue_nr; 786 ptq->exclude_kernel = intel_pt_exclude_kernel(pt); 787 ptq->pid = -1; 788 ptq->tid = -1; 789 ptq->cpu = -1; 790 ptq->next_tid = -1; 791 792 params.get_trace = intel_pt_get_trace; 793 params.walk_insn = intel_pt_walk_next_insn; 794 params.data = ptq; 795 params.return_compression = intel_pt_return_compression(pt); 796 params.branch_enable = intel_pt_branch_enable(pt); 797 params.max_non_turbo_ratio = pt->max_non_turbo_ratio; 798 params.mtc_period = intel_pt_mtc_period(pt); 799 params.tsc_ctc_ratio_n = pt->tsc_ctc_ratio_n; 800 params.tsc_ctc_ratio_d = pt->tsc_ctc_ratio_d; 801 802 if (pt->filts.cnt > 0) 803 params.pgd_ip = intel_pt_pgd_ip; 804 805 if (pt->synth_opts.instructions) { 806 if (pt->synth_opts.period) { 807 switch (pt->synth_opts.period_type) { 808 case PERF_ITRACE_PERIOD_INSTRUCTIONS: 809 params.period_type = 810 INTEL_PT_PERIOD_INSTRUCTIONS; 811 params.period = pt->synth_opts.period; 812 break; 813 case PERF_ITRACE_PERIOD_TICKS: 814 params.period_type = INTEL_PT_PERIOD_TICKS; 815 params.period = pt->synth_opts.period; 816 break; 817 case PERF_ITRACE_PERIOD_NANOSECS: 818 params.period_type = INTEL_PT_PERIOD_TICKS; 819 params.period = intel_pt_ns_to_ticks(pt, 820 pt->synth_opts.period); 821 break; 822 default: 823 break; 824 } 825 } 826 827 if (!params.period) { 828 params.period_type = INTEL_PT_PERIOD_INSTRUCTIONS; 829 params.period = 1; 830 } 831 } 832 833 ptq->decoder = intel_pt_decoder_new(¶ms); 834 if (!ptq->decoder) 835 goto out_free; 836 837 return ptq; 838 839 out_free: 840 zfree(&ptq->event_buf); 841 zfree(&ptq->last_branch); 842 zfree(&ptq->last_branch_rb); 843 zfree(&ptq->chain); 844 free(ptq); 845 return NULL; 846 } 847 848 static void intel_pt_free_queue(void *priv) 849 { 850 struct intel_pt_queue *ptq = priv; 851 852 if (!ptq) 853 return; 854 thread__zput(ptq->thread); 855 intel_pt_decoder_free(ptq->decoder); 856 zfree(&ptq->event_buf); 857 zfree(&ptq->last_branch); 858 zfree(&ptq->last_branch_rb); 859 zfree(&ptq->chain); 860 free(ptq); 861 } 862 863 static void intel_pt_set_pid_tid_cpu(struct intel_pt *pt, 864 struct auxtrace_queue *queue) 865 { 866 struct intel_pt_queue *ptq = queue->priv; 867 868 if (queue->tid == -1 || pt->have_sched_switch) { 869 ptq->tid = machine__get_current_tid(pt->machine, ptq->cpu); 870 thread__zput(ptq->thread); 871 } 872 873 if (!ptq->thread && ptq->tid != -1) 874 ptq->thread = machine__find_thread(pt->machine, -1, ptq->tid); 875 876 if (ptq->thread) { 877 ptq->pid = ptq->thread->pid_; 878 if (queue->cpu == -1) 879 ptq->cpu = ptq->thread->cpu; 880 } 881 } 882 883 static void intel_pt_sample_flags(struct intel_pt_queue *ptq) 884 { 885 if (ptq->state->flags & INTEL_PT_ABORT_TX) { 886 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_TX_ABORT; 887 } else if (ptq->state->flags & INTEL_PT_ASYNC) { 888 if (ptq->state->to_ip) 889 ptq->flags = PERF_IP_FLAG_BRANCH | PERF_IP_FLAG_CALL | 890 PERF_IP_FLAG_ASYNC | 891 PERF_IP_FLAG_INTERRUPT; 892 else 893 ptq->flags = PERF_IP_FLAG_BRANCH | 894 PERF_IP_FLAG_TRACE_END; 895 ptq->insn_len = 0; 896 } else { 897 if (ptq->state->from_ip) 898 ptq->flags = intel_pt_insn_type(ptq->state->insn_op); 899 else 900 ptq->flags = PERF_IP_FLAG_BRANCH | 901 PERF_IP_FLAG_TRACE_BEGIN; 902 if (ptq->state->flags & INTEL_PT_IN_TX) 903 ptq->flags |= PERF_IP_FLAG_IN_TX; 904 ptq->insn_len = ptq->state->insn_len; 905 memcpy(ptq->insn, ptq->state->insn, INTEL_PT_INSN_BUF_SZ); 906 } 907 } 908 909 static int intel_pt_setup_queue(struct intel_pt *pt, 910 struct auxtrace_queue *queue, 911 unsigned int queue_nr) 912 { 913 struct intel_pt_queue *ptq = queue->priv; 914 915 if (list_empty(&queue->head)) 916 return 0; 917 918 if (!ptq) { 919 ptq = intel_pt_alloc_queue(pt, queue_nr); 920 if (!ptq) 921 return -ENOMEM; 922 queue->priv = ptq; 923 924 if (queue->cpu != -1) 925 ptq->cpu = queue->cpu; 926 ptq->tid = queue->tid; 927 928 if (pt->sampling_mode && !pt->snapshot_mode && 929 pt->timeless_decoding) 930 ptq->step_through_buffers = true; 931 932 ptq->sync_switch = pt->sync_switch; 933 } 934 935 if (!ptq->on_heap && 936 (!ptq->sync_switch || 937 ptq->switch_state != INTEL_PT_SS_EXPECTING_SWITCH_EVENT)) { 938 const struct intel_pt_state *state; 939 int ret; 940 941 if (pt->timeless_decoding) 942 return 0; 943 944 intel_pt_log("queue %u getting timestamp\n", queue_nr); 945 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 946 queue_nr, ptq->cpu, ptq->pid, ptq->tid); 947 while (1) { 948 state = intel_pt_decode(ptq->decoder); 949 if (state->err) { 950 if (state->err == INTEL_PT_ERR_NODATA) { 951 intel_pt_log("queue %u has no timestamp\n", 952 queue_nr); 953 return 0; 954 } 955 continue; 956 } 957 if (state->timestamp) 958 break; 959 } 960 961 ptq->timestamp = state->timestamp; 962 intel_pt_log("queue %u timestamp 0x%" PRIx64 "\n", 963 queue_nr, ptq->timestamp); 964 ptq->state = state; 965 ptq->have_sample = true; 966 intel_pt_sample_flags(ptq); 967 ret = auxtrace_heap__add(&pt->heap, queue_nr, ptq->timestamp); 968 if (ret) 969 return ret; 970 ptq->on_heap = true; 971 } 972 973 return 0; 974 } 975 976 static int intel_pt_setup_queues(struct intel_pt *pt) 977 { 978 unsigned int i; 979 int ret; 980 981 for (i = 0; i < pt->queues.nr_queues; i++) { 982 ret = intel_pt_setup_queue(pt, &pt->queues.queue_array[i], i); 983 if (ret) 984 return ret; 985 } 986 return 0; 987 } 988 989 static inline void intel_pt_copy_last_branch_rb(struct intel_pt_queue *ptq) 990 { 991 struct branch_stack *bs_src = ptq->last_branch_rb; 992 struct branch_stack *bs_dst = ptq->last_branch; 993 size_t nr = 0; 994 995 bs_dst->nr = bs_src->nr; 996 997 if (!bs_src->nr) 998 return; 999 1000 nr = ptq->pt->synth_opts.last_branch_sz - ptq->last_branch_pos; 1001 memcpy(&bs_dst->entries[0], 1002 &bs_src->entries[ptq->last_branch_pos], 1003 sizeof(struct branch_entry) * nr); 1004 1005 if (bs_src->nr >= ptq->pt->synth_opts.last_branch_sz) { 1006 memcpy(&bs_dst->entries[nr], 1007 &bs_src->entries[0], 1008 sizeof(struct branch_entry) * ptq->last_branch_pos); 1009 } 1010 } 1011 1012 static inline void intel_pt_reset_last_branch_rb(struct intel_pt_queue *ptq) 1013 { 1014 ptq->last_branch_pos = 0; 1015 ptq->last_branch_rb->nr = 0; 1016 } 1017 1018 static void intel_pt_update_last_branch_rb(struct intel_pt_queue *ptq) 1019 { 1020 const struct intel_pt_state *state = ptq->state; 1021 struct branch_stack *bs = ptq->last_branch_rb; 1022 struct branch_entry *be; 1023 1024 if (!ptq->last_branch_pos) 1025 ptq->last_branch_pos = ptq->pt->synth_opts.last_branch_sz; 1026 1027 ptq->last_branch_pos -= 1; 1028 1029 be = &bs->entries[ptq->last_branch_pos]; 1030 be->from = state->from_ip; 1031 be->to = state->to_ip; 1032 be->flags.abort = !!(state->flags & INTEL_PT_ABORT_TX); 1033 be->flags.in_tx = !!(state->flags & INTEL_PT_IN_TX); 1034 /* No support for mispredict */ 1035 be->flags.mispred = ptq->pt->mispred_all; 1036 1037 if (bs->nr < ptq->pt->synth_opts.last_branch_sz) 1038 bs->nr += 1; 1039 } 1040 1041 static inline bool intel_pt_skip_event(struct intel_pt *pt) 1042 { 1043 return pt->synth_opts.initial_skip && 1044 pt->num_events++ < pt->synth_opts.initial_skip; 1045 } 1046 1047 static void intel_pt_prep_b_sample(struct intel_pt *pt, 1048 struct intel_pt_queue *ptq, 1049 union perf_event *event, 1050 struct perf_sample *sample) 1051 { 1052 event->sample.header.type = PERF_RECORD_SAMPLE; 1053 event->sample.header.misc = PERF_RECORD_MISC_USER; 1054 event->sample.header.size = sizeof(struct perf_event_header); 1055 1056 if (!pt->timeless_decoding) 1057 sample->time = tsc_to_perf_time(ptq->timestamp, &pt->tc); 1058 1059 sample->cpumode = PERF_RECORD_MISC_USER; 1060 sample->ip = ptq->state->from_ip; 1061 sample->pid = ptq->pid; 1062 sample->tid = ptq->tid; 1063 sample->addr = ptq->state->to_ip; 1064 sample->period = 1; 1065 sample->cpu = ptq->cpu; 1066 sample->flags = ptq->flags; 1067 sample->insn_len = ptq->insn_len; 1068 memcpy(sample->insn, ptq->insn, INTEL_PT_INSN_BUF_SZ); 1069 } 1070 1071 static int intel_pt_inject_event(union perf_event *event, 1072 struct perf_sample *sample, u64 type) 1073 { 1074 event->header.size = perf_event__sample_event_size(sample, type, 0); 1075 return perf_event__synthesize_sample(event, type, 0, sample); 1076 } 1077 1078 static inline int intel_pt_opt_inject(struct intel_pt *pt, 1079 union perf_event *event, 1080 struct perf_sample *sample, u64 type) 1081 { 1082 if (!pt->synth_opts.inject) 1083 return 0; 1084 1085 return intel_pt_inject_event(event, sample, type); 1086 } 1087 1088 static int intel_pt_deliver_synth_b_event(struct intel_pt *pt, 1089 union perf_event *event, 1090 struct perf_sample *sample, u64 type) 1091 { 1092 int ret; 1093 1094 ret = intel_pt_opt_inject(pt, event, sample, type); 1095 if (ret) 1096 return ret; 1097 1098 ret = perf_session__deliver_synth_event(pt->session, event, sample); 1099 if (ret) 1100 pr_err("Intel PT: failed to deliver event, error %d\n", ret); 1101 1102 return ret; 1103 } 1104 1105 static int intel_pt_synth_branch_sample(struct intel_pt_queue *ptq) 1106 { 1107 struct intel_pt *pt = ptq->pt; 1108 union perf_event *event = ptq->event_buf; 1109 struct perf_sample sample = { .ip = 0, }; 1110 struct dummy_branch_stack { 1111 u64 nr; 1112 struct branch_entry entries; 1113 } dummy_bs; 1114 1115 if (pt->branches_filter && !(pt->branches_filter & ptq->flags)) 1116 return 0; 1117 1118 if (intel_pt_skip_event(pt)) 1119 return 0; 1120 1121 intel_pt_prep_b_sample(pt, ptq, event, &sample); 1122 1123 sample.id = ptq->pt->branches_id; 1124 sample.stream_id = ptq->pt->branches_id; 1125 1126 /* 1127 * perf report cannot handle events without a branch stack when using 1128 * SORT_MODE__BRANCH so make a dummy one. 1129 */ 1130 if (pt->synth_opts.last_branch && sort__mode == SORT_MODE__BRANCH) { 1131 dummy_bs = (struct dummy_branch_stack){ 1132 .nr = 1, 1133 .entries = { 1134 .from = sample.ip, 1135 .to = sample.addr, 1136 }, 1137 }; 1138 sample.branch_stack = (struct branch_stack *)&dummy_bs; 1139 } 1140 1141 return intel_pt_deliver_synth_b_event(pt, event, &sample, 1142 pt->branches_sample_type); 1143 } 1144 1145 static void intel_pt_prep_sample(struct intel_pt *pt, 1146 struct intel_pt_queue *ptq, 1147 union perf_event *event, 1148 struct perf_sample *sample) 1149 { 1150 intel_pt_prep_b_sample(pt, ptq, event, sample); 1151 1152 if (pt->synth_opts.callchain) { 1153 thread_stack__sample(ptq->thread, ptq->chain, 1154 pt->synth_opts.callchain_sz, sample->ip); 1155 sample->callchain = ptq->chain; 1156 } 1157 1158 if (pt->synth_opts.last_branch) { 1159 intel_pt_copy_last_branch_rb(ptq); 1160 sample->branch_stack = ptq->last_branch; 1161 } 1162 } 1163 1164 static inline int intel_pt_deliver_synth_event(struct intel_pt *pt, 1165 struct intel_pt_queue *ptq, 1166 union perf_event *event, 1167 struct perf_sample *sample, 1168 u64 type) 1169 { 1170 int ret; 1171 1172 ret = intel_pt_deliver_synth_b_event(pt, event, sample, type); 1173 1174 if (pt->synth_opts.last_branch) 1175 intel_pt_reset_last_branch_rb(ptq); 1176 1177 return ret; 1178 } 1179 1180 static int intel_pt_synth_instruction_sample(struct intel_pt_queue *ptq) 1181 { 1182 struct intel_pt *pt = ptq->pt; 1183 union perf_event *event = ptq->event_buf; 1184 struct perf_sample sample = { .ip = 0, }; 1185 1186 if (intel_pt_skip_event(pt)) 1187 return 0; 1188 1189 intel_pt_prep_sample(pt, ptq, event, &sample); 1190 1191 sample.id = ptq->pt->instructions_id; 1192 sample.stream_id = ptq->pt->instructions_id; 1193 sample.period = ptq->state->tot_insn_cnt - ptq->last_insn_cnt; 1194 1195 ptq->last_insn_cnt = ptq->state->tot_insn_cnt; 1196 1197 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1198 pt->instructions_sample_type); 1199 } 1200 1201 static int intel_pt_synth_transaction_sample(struct intel_pt_queue *ptq) 1202 { 1203 struct intel_pt *pt = ptq->pt; 1204 union perf_event *event = ptq->event_buf; 1205 struct perf_sample sample = { .ip = 0, }; 1206 1207 if (intel_pt_skip_event(pt)) 1208 return 0; 1209 1210 intel_pt_prep_sample(pt, ptq, event, &sample); 1211 1212 sample.id = ptq->pt->transactions_id; 1213 sample.stream_id = ptq->pt->transactions_id; 1214 1215 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1216 pt->transactions_sample_type); 1217 } 1218 1219 static void intel_pt_prep_p_sample(struct intel_pt *pt, 1220 struct intel_pt_queue *ptq, 1221 union perf_event *event, 1222 struct perf_sample *sample) 1223 { 1224 intel_pt_prep_sample(pt, ptq, event, sample); 1225 1226 /* 1227 * Zero IP is used to mean "trace start" but that is not the case for 1228 * power or PTWRITE events with no IP, so clear the flags. 1229 */ 1230 if (!sample->ip) 1231 sample->flags = 0; 1232 } 1233 1234 static int intel_pt_synth_ptwrite_sample(struct intel_pt_queue *ptq) 1235 { 1236 struct intel_pt *pt = ptq->pt; 1237 union perf_event *event = ptq->event_buf; 1238 struct perf_sample sample = { .ip = 0, }; 1239 struct perf_synth_intel_ptwrite raw; 1240 1241 if (intel_pt_skip_event(pt)) 1242 return 0; 1243 1244 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1245 1246 sample.id = ptq->pt->ptwrites_id; 1247 sample.stream_id = ptq->pt->ptwrites_id; 1248 1249 raw.flags = 0; 1250 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1251 raw.payload = cpu_to_le64(ptq->state->ptw_payload); 1252 1253 sample.raw_size = perf_synth__raw_size(raw); 1254 sample.raw_data = perf_synth__raw_data(&raw); 1255 1256 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1257 pt->ptwrites_sample_type); 1258 } 1259 1260 static int intel_pt_synth_cbr_sample(struct intel_pt_queue *ptq) 1261 { 1262 struct intel_pt *pt = ptq->pt; 1263 union perf_event *event = ptq->event_buf; 1264 struct perf_sample sample = { .ip = 0, }; 1265 struct perf_synth_intel_cbr raw; 1266 u32 flags; 1267 1268 if (intel_pt_skip_event(pt)) 1269 return 0; 1270 1271 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1272 1273 sample.id = ptq->pt->cbr_id; 1274 sample.stream_id = ptq->pt->cbr_id; 1275 1276 flags = (u16)ptq->state->cbr_payload | (pt->max_non_turbo_ratio << 16); 1277 raw.flags = cpu_to_le32(flags); 1278 raw.freq = cpu_to_le32(raw.cbr * pt->cbr2khz); 1279 raw.reserved3 = 0; 1280 1281 sample.raw_size = perf_synth__raw_size(raw); 1282 sample.raw_data = perf_synth__raw_data(&raw); 1283 1284 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1285 pt->pwr_events_sample_type); 1286 } 1287 1288 static int intel_pt_synth_mwait_sample(struct intel_pt_queue *ptq) 1289 { 1290 struct intel_pt *pt = ptq->pt; 1291 union perf_event *event = ptq->event_buf; 1292 struct perf_sample sample = { .ip = 0, }; 1293 struct perf_synth_intel_mwait raw; 1294 1295 if (intel_pt_skip_event(pt)) 1296 return 0; 1297 1298 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1299 1300 sample.id = ptq->pt->mwait_id; 1301 sample.stream_id = ptq->pt->mwait_id; 1302 1303 raw.reserved = 0; 1304 raw.payload = cpu_to_le64(ptq->state->mwait_payload); 1305 1306 sample.raw_size = perf_synth__raw_size(raw); 1307 sample.raw_data = perf_synth__raw_data(&raw); 1308 1309 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1310 pt->pwr_events_sample_type); 1311 } 1312 1313 static int intel_pt_synth_pwre_sample(struct intel_pt_queue *ptq) 1314 { 1315 struct intel_pt *pt = ptq->pt; 1316 union perf_event *event = ptq->event_buf; 1317 struct perf_sample sample = { .ip = 0, }; 1318 struct perf_synth_intel_pwre raw; 1319 1320 if (intel_pt_skip_event(pt)) 1321 return 0; 1322 1323 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1324 1325 sample.id = ptq->pt->pwre_id; 1326 sample.stream_id = ptq->pt->pwre_id; 1327 1328 raw.reserved = 0; 1329 raw.payload = cpu_to_le64(ptq->state->pwre_payload); 1330 1331 sample.raw_size = perf_synth__raw_size(raw); 1332 sample.raw_data = perf_synth__raw_data(&raw); 1333 1334 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1335 pt->pwr_events_sample_type); 1336 } 1337 1338 static int intel_pt_synth_exstop_sample(struct intel_pt_queue *ptq) 1339 { 1340 struct intel_pt *pt = ptq->pt; 1341 union perf_event *event = ptq->event_buf; 1342 struct perf_sample sample = { .ip = 0, }; 1343 struct perf_synth_intel_exstop raw; 1344 1345 if (intel_pt_skip_event(pt)) 1346 return 0; 1347 1348 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1349 1350 sample.id = ptq->pt->exstop_id; 1351 sample.stream_id = ptq->pt->exstop_id; 1352 1353 raw.flags = 0; 1354 raw.ip = !!(ptq->state->flags & INTEL_PT_FUP_IP); 1355 1356 sample.raw_size = perf_synth__raw_size(raw); 1357 sample.raw_data = perf_synth__raw_data(&raw); 1358 1359 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1360 pt->pwr_events_sample_type); 1361 } 1362 1363 static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq) 1364 { 1365 struct intel_pt *pt = ptq->pt; 1366 union perf_event *event = ptq->event_buf; 1367 struct perf_sample sample = { .ip = 0, }; 1368 struct perf_synth_intel_pwrx raw; 1369 1370 if (intel_pt_skip_event(pt)) 1371 return 0; 1372 1373 intel_pt_prep_p_sample(pt, ptq, event, &sample); 1374 1375 sample.id = ptq->pt->pwrx_id; 1376 sample.stream_id = ptq->pt->pwrx_id; 1377 1378 raw.reserved = 0; 1379 raw.payload = cpu_to_le64(ptq->state->pwrx_payload); 1380 1381 sample.raw_size = perf_synth__raw_size(raw); 1382 sample.raw_data = perf_synth__raw_data(&raw); 1383 1384 return intel_pt_deliver_synth_event(pt, ptq, event, &sample, 1385 pt->pwr_events_sample_type); 1386 } 1387 1388 static int intel_pt_synth_error(struct intel_pt *pt, int code, int cpu, 1389 pid_t pid, pid_t tid, u64 ip) 1390 { 1391 union perf_event event; 1392 char msg[MAX_AUXTRACE_ERROR_MSG]; 1393 int err; 1394 1395 intel_pt__strerror(code, msg, MAX_AUXTRACE_ERROR_MSG); 1396 1397 auxtrace_synth_error(&event.auxtrace_error, PERF_AUXTRACE_ERROR_ITRACE, 1398 code, cpu, pid, tid, ip, msg); 1399 1400 err = perf_session__deliver_synth_event(pt->session, &event, NULL); 1401 if (err) 1402 pr_err("Intel Processor Trace: failed to deliver error event, error %d\n", 1403 err); 1404 1405 return err; 1406 } 1407 1408 static int intel_pt_next_tid(struct intel_pt *pt, struct intel_pt_queue *ptq) 1409 { 1410 struct auxtrace_queue *queue; 1411 pid_t tid = ptq->next_tid; 1412 int err; 1413 1414 if (tid == -1) 1415 return 0; 1416 1417 intel_pt_log("switch: cpu %d tid %d\n", ptq->cpu, tid); 1418 1419 err = machine__set_current_tid(pt->machine, ptq->cpu, -1, tid); 1420 1421 queue = &pt->queues.queue_array[ptq->queue_nr]; 1422 intel_pt_set_pid_tid_cpu(pt, queue); 1423 1424 ptq->next_tid = -1; 1425 1426 return err; 1427 } 1428 1429 static inline bool intel_pt_is_switch_ip(struct intel_pt_queue *ptq, u64 ip) 1430 { 1431 struct intel_pt *pt = ptq->pt; 1432 1433 return ip == pt->switch_ip && 1434 (ptq->flags & PERF_IP_FLAG_BRANCH) && 1435 !(ptq->flags & (PERF_IP_FLAG_CONDITIONAL | PERF_IP_FLAG_ASYNC | 1436 PERF_IP_FLAG_INTERRUPT | PERF_IP_FLAG_TX_ABORT)); 1437 } 1438 1439 #define INTEL_PT_PWR_EVT (INTEL_PT_MWAIT_OP | INTEL_PT_PWR_ENTRY | \ 1440 INTEL_PT_EX_STOP | INTEL_PT_PWR_EXIT | \ 1441 INTEL_PT_CBR_CHG) 1442 1443 static int intel_pt_sample(struct intel_pt_queue *ptq) 1444 { 1445 const struct intel_pt_state *state = ptq->state; 1446 struct intel_pt *pt = ptq->pt; 1447 int err; 1448 1449 if (!ptq->have_sample) 1450 return 0; 1451 1452 ptq->have_sample = false; 1453 1454 if (pt->sample_pwr_events && (state->type & INTEL_PT_PWR_EVT)) { 1455 if (state->type & INTEL_PT_CBR_CHG) { 1456 err = intel_pt_synth_cbr_sample(ptq); 1457 if (err) 1458 return err; 1459 } 1460 if (state->type & INTEL_PT_MWAIT_OP) { 1461 err = intel_pt_synth_mwait_sample(ptq); 1462 if (err) 1463 return err; 1464 } 1465 if (state->type & INTEL_PT_PWR_ENTRY) { 1466 err = intel_pt_synth_pwre_sample(ptq); 1467 if (err) 1468 return err; 1469 } 1470 if (state->type & INTEL_PT_EX_STOP) { 1471 err = intel_pt_synth_exstop_sample(ptq); 1472 if (err) 1473 return err; 1474 } 1475 if (state->type & INTEL_PT_PWR_EXIT) { 1476 err = intel_pt_synth_pwrx_sample(ptq); 1477 if (err) 1478 return err; 1479 } 1480 } 1481 1482 if (pt->sample_instructions && (state->type & INTEL_PT_INSTRUCTION)) { 1483 err = intel_pt_synth_instruction_sample(ptq); 1484 if (err) 1485 return err; 1486 } 1487 1488 if (pt->sample_transactions && (state->type & INTEL_PT_TRANSACTION)) { 1489 err = intel_pt_synth_transaction_sample(ptq); 1490 if (err) 1491 return err; 1492 } 1493 1494 if (pt->sample_ptwrites && (state->type & INTEL_PT_PTW)) { 1495 err = intel_pt_synth_ptwrite_sample(ptq); 1496 if (err) 1497 return err; 1498 } 1499 1500 if (!(state->type & INTEL_PT_BRANCH)) 1501 return 0; 1502 1503 if (pt->synth_opts.callchain || pt->synth_opts.thread_stack) 1504 thread_stack__event(ptq->thread, ptq->flags, state->from_ip, 1505 state->to_ip, ptq->insn_len, 1506 state->trace_nr); 1507 else 1508 thread_stack__set_trace_nr(ptq->thread, state->trace_nr); 1509 1510 if (pt->sample_branches) { 1511 err = intel_pt_synth_branch_sample(ptq); 1512 if (err) 1513 return err; 1514 } 1515 1516 if (pt->synth_opts.last_branch) 1517 intel_pt_update_last_branch_rb(ptq); 1518 1519 if (!ptq->sync_switch) 1520 return 0; 1521 1522 if (intel_pt_is_switch_ip(ptq, state->to_ip)) { 1523 switch (ptq->switch_state) { 1524 case INTEL_PT_SS_UNKNOWN: 1525 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 1526 err = intel_pt_next_tid(pt, ptq); 1527 if (err) 1528 return err; 1529 ptq->switch_state = INTEL_PT_SS_TRACING; 1530 break; 1531 default: 1532 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_EVENT; 1533 return 1; 1534 } 1535 } else if (!state->to_ip) { 1536 ptq->switch_state = INTEL_PT_SS_NOT_TRACING; 1537 } else if (ptq->switch_state == INTEL_PT_SS_NOT_TRACING) { 1538 ptq->switch_state = INTEL_PT_SS_UNKNOWN; 1539 } else if (ptq->switch_state == INTEL_PT_SS_UNKNOWN && 1540 state->to_ip == pt->ptss_ip && 1541 (ptq->flags & PERF_IP_FLAG_CALL)) { 1542 ptq->switch_state = INTEL_PT_SS_TRACING; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static u64 intel_pt_switch_ip(struct intel_pt *pt, u64 *ptss_ip) 1549 { 1550 struct machine *machine = pt->machine; 1551 struct map *map; 1552 struct symbol *sym, *start; 1553 u64 ip, switch_ip = 0; 1554 const char *ptss; 1555 1556 if (ptss_ip) 1557 *ptss_ip = 0; 1558 1559 map = machine__kernel_map(machine); 1560 if (!map) 1561 return 0; 1562 1563 if (map__load(map)) 1564 return 0; 1565 1566 start = dso__first_symbol(map->dso); 1567 1568 for (sym = start; sym; sym = dso__next_symbol(sym)) { 1569 if (sym->binding == STB_GLOBAL && 1570 !strcmp(sym->name, "__switch_to")) { 1571 ip = map->unmap_ip(map, sym->start); 1572 if (ip >= map->start && ip < map->end) { 1573 switch_ip = ip; 1574 break; 1575 } 1576 } 1577 } 1578 1579 if (!switch_ip || !ptss_ip) 1580 return 0; 1581 1582 if (pt->have_sched_switch == 1) 1583 ptss = "perf_trace_sched_switch"; 1584 else 1585 ptss = "__perf_event_task_sched_out"; 1586 1587 for (sym = start; sym; sym = dso__next_symbol(sym)) { 1588 if (!strcmp(sym->name, ptss)) { 1589 ip = map->unmap_ip(map, sym->start); 1590 if (ip >= map->start && ip < map->end) { 1591 *ptss_ip = ip; 1592 break; 1593 } 1594 } 1595 } 1596 1597 return switch_ip; 1598 } 1599 1600 static void intel_pt_enable_sync_switch(struct intel_pt *pt) 1601 { 1602 unsigned int i; 1603 1604 pt->sync_switch = true; 1605 1606 for (i = 0; i < pt->queues.nr_queues; i++) { 1607 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 1608 struct intel_pt_queue *ptq = queue->priv; 1609 1610 if (ptq) 1611 ptq->sync_switch = true; 1612 } 1613 } 1614 1615 static int intel_pt_run_decoder(struct intel_pt_queue *ptq, u64 *timestamp) 1616 { 1617 const struct intel_pt_state *state = ptq->state; 1618 struct intel_pt *pt = ptq->pt; 1619 int err; 1620 1621 if (!pt->kernel_start) { 1622 pt->kernel_start = machine__kernel_start(pt->machine); 1623 if (pt->per_cpu_mmaps && 1624 (pt->have_sched_switch == 1 || pt->have_sched_switch == 3) && 1625 !pt->timeless_decoding && intel_pt_tracing_kernel(pt) && 1626 !pt->sampling_mode) { 1627 pt->switch_ip = intel_pt_switch_ip(pt, &pt->ptss_ip); 1628 if (pt->switch_ip) { 1629 intel_pt_log("switch_ip: %"PRIx64" ptss_ip: %"PRIx64"\n", 1630 pt->switch_ip, pt->ptss_ip); 1631 intel_pt_enable_sync_switch(pt); 1632 } 1633 } 1634 } 1635 1636 intel_pt_log("queue %u decoding cpu %d pid %d tid %d\n", 1637 ptq->queue_nr, ptq->cpu, ptq->pid, ptq->tid); 1638 while (1) { 1639 err = intel_pt_sample(ptq); 1640 if (err) 1641 return err; 1642 1643 state = intel_pt_decode(ptq->decoder); 1644 if (state->err) { 1645 if (state->err == INTEL_PT_ERR_NODATA) 1646 return 1; 1647 if (ptq->sync_switch && 1648 state->from_ip >= pt->kernel_start) { 1649 ptq->sync_switch = false; 1650 intel_pt_next_tid(pt, ptq); 1651 } 1652 if (pt->synth_opts.errors) { 1653 err = intel_pt_synth_error(pt, state->err, 1654 ptq->cpu, ptq->pid, 1655 ptq->tid, 1656 state->from_ip); 1657 if (err) 1658 return err; 1659 } 1660 continue; 1661 } 1662 1663 ptq->state = state; 1664 ptq->have_sample = true; 1665 intel_pt_sample_flags(ptq); 1666 1667 /* Use estimated TSC upon return to user space */ 1668 if (pt->est_tsc && 1669 (state->from_ip >= pt->kernel_start || !state->from_ip) && 1670 state->to_ip && state->to_ip < pt->kernel_start) { 1671 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 1672 state->timestamp, state->est_timestamp); 1673 ptq->timestamp = state->est_timestamp; 1674 /* Use estimated TSC in unknown switch state */ 1675 } else if (ptq->sync_switch && 1676 ptq->switch_state == INTEL_PT_SS_UNKNOWN && 1677 intel_pt_is_switch_ip(ptq, state->to_ip) && 1678 ptq->next_tid == -1) { 1679 intel_pt_log("TSC %"PRIx64" est. TSC %"PRIx64"\n", 1680 state->timestamp, state->est_timestamp); 1681 ptq->timestamp = state->est_timestamp; 1682 } else if (state->timestamp > ptq->timestamp) { 1683 ptq->timestamp = state->timestamp; 1684 } 1685 1686 if (!pt->timeless_decoding && ptq->timestamp >= *timestamp) { 1687 *timestamp = ptq->timestamp; 1688 return 0; 1689 } 1690 } 1691 return 0; 1692 } 1693 1694 static inline int intel_pt_update_queues(struct intel_pt *pt) 1695 { 1696 if (pt->queues.new_data) { 1697 pt->queues.new_data = false; 1698 return intel_pt_setup_queues(pt); 1699 } 1700 return 0; 1701 } 1702 1703 static int intel_pt_process_queues(struct intel_pt *pt, u64 timestamp) 1704 { 1705 unsigned int queue_nr; 1706 u64 ts; 1707 int ret; 1708 1709 while (1) { 1710 struct auxtrace_queue *queue; 1711 struct intel_pt_queue *ptq; 1712 1713 if (!pt->heap.heap_cnt) 1714 return 0; 1715 1716 if (pt->heap.heap_array[0].ordinal >= timestamp) 1717 return 0; 1718 1719 queue_nr = pt->heap.heap_array[0].queue_nr; 1720 queue = &pt->queues.queue_array[queue_nr]; 1721 ptq = queue->priv; 1722 1723 intel_pt_log("queue %u processing 0x%" PRIx64 " to 0x%" PRIx64 "\n", 1724 queue_nr, pt->heap.heap_array[0].ordinal, 1725 timestamp); 1726 1727 auxtrace_heap__pop(&pt->heap); 1728 1729 if (pt->heap.heap_cnt) { 1730 ts = pt->heap.heap_array[0].ordinal + 1; 1731 if (ts > timestamp) 1732 ts = timestamp; 1733 } else { 1734 ts = timestamp; 1735 } 1736 1737 intel_pt_set_pid_tid_cpu(pt, queue); 1738 1739 ret = intel_pt_run_decoder(ptq, &ts); 1740 1741 if (ret < 0) { 1742 auxtrace_heap__add(&pt->heap, queue_nr, ts); 1743 return ret; 1744 } 1745 1746 if (!ret) { 1747 ret = auxtrace_heap__add(&pt->heap, queue_nr, ts); 1748 if (ret < 0) 1749 return ret; 1750 } else { 1751 ptq->on_heap = false; 1752 } 1753 } 1754 1755 return 0; 1756 } 1757 1758 static int intel_pt_process_timeless_queues(struct intel_pt *pt, pid_t tid, 1759 u64 time_) 1760 { 1761 struct auxtrace_queues *queues = &pt->queues; 1762 unsigned int i; 1763 u64 ts = 0; 1764 1765 for (i = 0; i < queues->nr_queues; i++) { 1766 struct auxtrace_queue *queue = &pt->queues.queue_array[i]; 1767 struct intel_pt_queue *ptq = queue->priv; 1768 1769 if (ptq && (tid == -1 || ptq->tid == tid)) { 1770 ptq->time = time_; 1771 intel_pt_set_pid_tid_cpu(pt, queue); 1772 intel_pt_run_decoder(ptq, &ts); 1773 } 1774 } 1775 return 0; 1776 } 1777 1778 static int intel_pt_lost(struct intel_pt *pt, struct perf_sample *sample) 1779 { 1780 return intel_pt_synth_error(pt, INTEL_PT_ERR_LOST, sample->cpu, 1781 sample->pid, sample->tid, 0); 1782 } 1783 1784 static struct intel_pt_queue *intel_pt_cpu_to_ptq(struct intel_pt *pt, int cpu) 1785 { 1786 unsigned i, j; 1787 1788 if (cpu < 0 || !pt->queues.nr_queues) 1789 return NULL; 1790 1791 if ((unsigned)cpu >= pt->queues.nr_queues) 1792 i = pt->queues.nr_queues - 1; 1793 else 1794 i = cpu; 1795 1796 if (pt->queues.queue_array[i].cpu == cpu) 1797 return pt->queues.queue_array[i].priv; 1798 1799 for (j = 0; i > 0; j++) { 1800 if (pt->queues.queue_array[--i].cpu == cpu) 1801 return pt->queues.queue_array[i].priv; 1802 } 1803 1804 for (; j < pt->queues.nr_queues; j++) { 1805 if (pt->queues.queue_array[j].cpu == cpu) 1806 return pt->queues.queue_array[j].priv; 1807 } 1808 1809 return NULL; 1810 } 1811 1812 static int intel_pt_sync_switch(struct intel_pt *pt, int cpu, pid_t tid, 1813 u64 timestamp) 1814 { 1815 struct intel_pt_queue *ptq; 1816 int err; 1817 1818 if (!pt->sync_switch) 1819 return 1; 1820 1821 ptq = intel_pt_cpu_to_ptq(pt, cpu); 1822 if (!ptq || !ptq->sync_switch) 1823 return 1; 1824 1825 switch (ptq->switch_state) { 1826 case INTEL_PT_SS_NOT_TRACING: 1827 ptq->next_tid = -1; 1828 break; 1829 case INTEL_PT_SS_UNKNOWN: 1830 case INTEL_PT_SS_TRACING: 1831 ptq->next_tid = tid; 1832 ptq->switch_state = INTEL_PT_SS_EXPECTING_SWITCH_IP; 1833 return 0; 1834 case INTEL_PT_SS_EXPECTING_SWITCH_EVENT: 1835 if (!ptq->on_heap) { 1836 ptq->timestamp = perf_time_to_tsc(timestamp, 1837 &pt->tc); 1838 err = auxtrace_heap__add(&pt->heap, ptq->queue_nr, 1839 ptq->timestamp); 1840 if (err) 1841 return err; 1842 ptq->on_heap = true; 1843 } 1844 ptq->switch_state = INTEL_PT_SS_TRACING; 1845 break; 1846 case INTEL_PT_SS_EXPECTING_SWITCH_IP: 1847 ptq->next_tid = tid; 1848 intel_pt_log("ERROR: cpu %d expecting switch ip\n", cpu); 1849 break; 1850 default: 1851 break; 1852 } 1853 1854 return 1; 1855 } 1856 1857 static int intel_pt_process_switch(struct intel_pt *pt, 1858 struct perf_sample *sample) 1859 { 1860 struct perf_evsel *evsel; 1861 pid_t tid; 1862 int cpu, ret; 1863 1864 evsel = perf_evlist__id2evsel(pt->session->evlist, sample->id); 1865 if (evsel != pt->switch_evsel) 1866 return 0; 1867 1868 tid = perf_evsel__intval(evsel, sample, "next_pid"); 1869 cpu = sample->cpu; 1870 1871 intel_pt_log("sched_switch: cpu %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 1872 cpu, tid, sample->time, perf_time_to_tsc(sample->time, 1873 &pt->tc)); 1874 1875 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 1876 if (ret <= 0) 1877 return ret; 1878 1879 return machine__set_current_tid(pt->machine, cpu, -1, tid); 1880 } 1881 1882 static int intel_pt_context_switch(struct intel_pt *pt, union perf_event *event, 1883 struct perf_sample *sample) 1884 { 1885 bool out = event->header.misc & PERF_RECORD_MISC_SWITCH_OUT; 1886 pid_t pid, tid; 1887 int cpu, ret; 1888 1889 cpu = sample->cpu; 1890 1891 if (pt->have_sched_switch == 3) { 1892 if (!out) 1893 return 0; 1894 if (event->header.type != PERF_RECORD_SWITCH_CPU_WIDE) { 1895 pr_err("Expecting CPU-wide context switch event\n"); 1896 return -EINVAL; 1897 } 1898 pid = event->context_switch.next_prev_pid; 1899 tid = event->context_switch.next_prev_tid; 1900 } else { 1901 if (out) 1902 return 0; 1903 pid = sample->pid; 1904 tid = sample->tid; 1905 } 1906 1907 if (tid == -1) { 1908 pr_err("context_switch event has no tid\n"); 1909 return -EINVAL; 1910 } 1911 1912 intel_pt_log("context_switch: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 1913 cpu, pid, tid, sample->time, perf_time_to_tsc(sample->time, 1914 &pt->tc)); 1915 1916 ret = intel_pt_sync_switch(pt, cpu, tid, sample->time); 1917 if (ret <= 0) 1918 return ret; 1919 1920 return machine__set_current_tid(pt->machine, cpu, pid, tid); 1921 } 1922 1923 static int intel_pt_process_itrace_start(struct intel_pt *pt, 1924 union perf_event *event, 1925 struct perf_sample *sample) 1926 { 1927 if (!pt->per_cpu_mmaps) 1928 return 0; 1929 1930 intel_pt_log("itrace_start: cpu %d pid %d tid %d time %"PRIu64" tsc %#"PRIx64"\n", 1931 sample->cpu, event->itrace_start.pid, 1932 event->itrace_start.tid, sample->time, 1933 perf_time_to_tsc(sample->time, &pt->tc)); 1934 1935 return machine__set_current_tid(pt->machine, sample->cpu, 1936 event->itrace_start.pid, 1937 event->itrace_start.tid); 1938 } 1939 1940 static int intel_pt_process_event(struct perf_session *session, 1941 union perf_event *event, 1942 struct perf_sample *sample, 1943 struct perf_tool *tool) 1944 { 1945 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 1946 auxtrace); 1947 u64 timestamp; 1948 int err = 0; 1949 1950 if (dump_trace) 1951 return 0; 1952 1953 if (!tool->ordered_events) { 1954 pr_err("Intel Processor Trace requires ordered events\n"); 1955 return -EINVAL; 1956 } 1957 1958 if (sample->time && sample->time != (u64)-1) 1959 timestamp = perf_time_to_tsc(sample->time, &pt->tc); 1960 else 1961 timestamp = 0; 1962 1963 if (timestamp || pt->timeless_decoding) { 1964 err = intel_pt_update_queues(pt); 1965 if (err) 1966 return err; 1967 } 1968 1969 if (pt->timeless_decoding) { 1970 if (event->header.type == PERF_RECORD_EXIT) { 1971 err = intel_pt_process_timeless_queues(pt, 1972 event->fork.tid, 1973 sample->time); 1974 } 1975 } else if (timestamp) { 1976 err = intel_pt_process_queues(pt, timestamp); 1977 } 1978 if (err) 1979 return err; 1980 1981 if (event->header.type == PERF_RECORD_AUX && 1982 (event->aux.flags & PERF_AUX_FLAG_TRUNCATED) && 1983 pt->synth_opts.errors) { 1984 err = intel_pt_lost(pt, sample); 1985 if (err) 1986 return err; 1987 } 1988 1989 if (pt->switch_evsel && event->header.type == PERF_RECORD_SAMPLE) 1990 err = intel_pt_process_switch(pt, sample); 1991 else if (event->header.type == PERF_RECORD_ITRACE_START) 1992 err = intel_pt_process_itrace_start(pt, event, sample); 1993 else if (event->header.type == PERF_RECORD_SWITCH || 1994 event->header.type == PERF_RECORD_SWITCH_CPU_WIDE) 1995 err = intel_pt_context_switch(pt, event, sample); 1996 1997 intel_pt_log("event %s (%u): cpu %d time %"PRIu64" tsc %#"PRIx64"\n", 1998 perf_event__name(event->header.type), event->header.type, 1999 sample->cpu, sample->time, timestamp); 2000 2001 return err; 2002 } 2003 2004 static int intel_pt_flush(struct perf_session *session, struct perf_tool *tool) 2005 { 2006 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2007 auxtrace); 2008 int ret; 2009 2010 if (dump_trace) 2011 return 0; 2012 2013 if (!tool->ordered_events) 2014 return -EINVAL; 2015 2016 ret = intel_pt_update_queues(pt); 2017 if (ret < 0) 2018 return ret; 2019 2020 if (pt->timeless_decoding) 2021 return intel_pt_process_timeless_queues(pt, -1, 2022 MAX_TIMESTAMP - 1); 2023 2024 return intel_pt_process_queues(pt, MAX_TIMESTAMP); 2025 } 2026 2027 static void intel_pt_free_events(struct perf_session *session) 2028 { 2029 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2030 auxtrace); 2031 struct auxtrace_queues *queues = &pt->queues; 2032 unsigned int i; 2033 2034 for (i = 0; i < queues->nr_queues; i++) { 2035 intel_pt_free_queue(queues->queue_array[i].priv); 2036 queues->queue_array[i].priv = NULL; 2037 } 2038 intel_pt_log_disable(); 2039 auxtrace_queues__free(queues); 2040 } 2041 2042 static void intel_pt_free(struct perf_session *session) 2043 { 2044 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2045 auxtrace); 2046 2047 auxtrace_heap__free(&pt->heap); 2048 intel_pt_free_events(session); 2049 session->auxtrace = NULL; 2050 thread__put(pt->unknown_thread); 2051 addr_filters__exit(&pt->filts); 2052 zfree(&pt->filter); 2053 free(pt); 2054 } 2055 2056 static int intel_pt_process_auxtrace_event(struct perf_session *session, 2057 union perf_event *event, 2058 struct perf_tool *tool __maybe_unused) 2059 { 2060 struct intel_pt *pt = container_of(session->auxtrace, struct intel_pt, 2061 auxtrace); 2062 2063 if (!pt->data_queued) { 2064 struct auxtrace_buffer *buffer; 2065 off_t data_offset; 2066 int fd = perf_data__fd(session->data); 2067 int err; 2068 2069 if (perf_data__is_pipe(session->data)) { 2070 data_offset = 0; 2071 } else { 2072 data_offset = lseek(fd, 0, SEEK_CUR); 2073 if (data_offset == -1) 2074 return -errno; 2075 } 2076 2077 err = auxtrace_queues__add_event(&pt->queues, session, event, 2078 data_offset, &buffer); 2079 if (err) 2080 return err; 2081 2082 /* Dump here now we have copied a piped trace out of the pipe */ 2083 if (dump_trace) { 2084 if (auxtrace_buffer__get_data(buffer, fd)) { 2085 intel_pt_dump_event(pt, buffer->data, 2086 buffer->size); 2087 auxtrace_buffer__put_data(buffer); 2088 } 2089 } 2090 } 2091 2092 return 0; 2093 } 2094 2095 struct intel_pt_synth { 2096 struct perf_tool dummy_tool; 2097 struct perf_session *session; 2098 }; 2099 2100 static int intel_pt_event_synth(struct perf_tool *tool, 2101 union perf_event *event, 2102 struct perf_sample *sample __maybe_unused, 2103 struct machine *machine __maybe_unused) 2104 { 2105 struct intel_pt_synth *intel_pt_synth = 2106 container_of(tool, struct intel_pt_synth, dummy_tool); 2107 2108 return perf_session__deliver_synth_event(intel_pt_synth->session, event, 2109 NULL); 2110 } 2111 2112 static int intel_pt_synth_event(struct perf_session *session, const char *name, 2113 struct perf_event_attr *attr, u64 id) 2114 { 2115 struct intel_pt_synth intel_pt_synth; 2116 int err; 2117 2118 pr_debug("Synthesizing '%s' event with id %" PRIu64 " sample type %#" PRIx64 "\n", 2119 name, id, (u64)attr->sample_type); 2120 2121 memset(&intel_pt_synth, 0, sizeof(struct intel_pt_synth)); 2122 intel_pt_synth.session = session; 2123 2124 err = perf_event__synthesize_attr(&intel_pt_synth.dummy_tool, attr, 1, 2125 &id, intel_pt_event_synth); 2126 if (err) 2127 pr_err("%s: failed to synthesize '%s' event type\n", 2128 __func__, name); 2129 2130 return err; 2131 } 2132 2133 static void intel_pt_set_event_name(struct perf_evlist *evlist, u64 id, 2134 const char *name) 2135 { 2136 struct perf_evsel *evsel; 2137 2138 evlist__for_each_entry(evlist, evsel) { 2139 if (evsel->id && evsel->id[0] == id) { 2140 if (evsel->name) 2141 zfree(&evsel->name); 2142 evsel->name = strdup(name); 2143 break; 2144 } 2145 } 2146 } 2147 2148 static struct perf_evsel *intel_pt_evsel(struct intel_pt *pt, 2149 struct perf_evlist *evlist) 2150 { 2151 struct perf_evsel *evsel; 2152 2153 evlist__for_each_entry(evlist, evsel) { 2154 if (evsel->attr.type == pt->pmu_type && evsel->ids) 2155 return evsel; 2156 } 2157 2158 return NULL; 2159 } 2160 2161 static int intel_pt_synth_events(struct intel_pt *pt, 2162 struct perf_session *session) 2163 { 2164 struct perf_evlist *evlist = session->evlist; 2165 struct perf_evsel *evsel = intel_pt_evsel(pt, evlist); 2166 struct perf_event_attr attr; 2167 u64 id; 2168 int err; 2169 2170 if (!evsel) { 2171 pr_debug("There are no selected events with Intel Processor Trace data\n"); 2172 return 0; 2173 } 2174 2175 memset(&attr, 0, sizeof(struct perf_event_attr)); 2176 attr.size = sizeof(struct perf_event_attr); 2177 attr.type = PERF_TYPE_HARDWARE; 2178 attr.sample_type = evsel->attr.sample_type & PERF_SAMPLE_MASK; 2179 attr.sample_type |= PERF_SAMPLE_IP | PERF_SAMPLE_TID | 2180 PERF_SAMPLE_PERIOD; 2181 if (pt->timeless_decoding) 2182 attr.sample_type &= ~(u64)PERF_SAMPLE_TIME; 2183 else 2184 attr.sample_type |= PERF_SAMPLE_TIME; 2185 if (!pt->per_cpu_mmaps) 2186 attr.sample_type &= ~(u64)PERF_SAMPLE_CPU; 2187 attr.exclude_user = evsel->attr.exclude_user; 2188 attr.exclude_kernel = evsel->attr.exclude_kernel; 2189 attr.exclude_hv = evsel->attr.exclude_hv; 2190 attr.exclude_host = evsel->attr.exclude_host; 2191 attr.exclude_guest = evsel->attr.exclude_guest; 2192 attr.sample_id_all = evsel->attr.sample_id_all; 2193 attr.read_format = evsel->attr.read_format; 2194 2195 id = evsel->id[0] + 1000000000; 2196 if (!id) 2197 id = 1; 2198 2199 if (pt->synth_opts.branches) { 2200 attr.config = PERF_COUNT_HW_BRANCH_INSTRUCTIONS; 2201 attr.sample_period = 1; 2202 attr.sample_type |= PERF_SAMPLE_ADDR; 2203 err = intel_pt_synth_event(session, "branches", &attr, id); 2204 if (err) 2205 return err; 2206 pt->sample_branches = true; 2207 pt->branches_sample_type = attr.sample_type; 2208 pt->branches_id = id; 2209 id += 1; 2210 attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR; 2211 } 2212 2213 if (pt->synth_opts.callchain) 2214 attr.sample_type |= PERF_SAMPLE_CALLCHAIN; 2215 if (pt->synth_opts.last_branch) 2216 attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; 2217 2218 if (pt->synth_opts.instructions) { 2219 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 2220 if (pt->synth_opts.period_type == PERF_ITRACE_PERIOD_NANOSECS) 2221 attr.sample_period = 2222 intel_pt_ns_to_ticks(pt, pt->synth_opts.period); 2223 else 2224 attr.sample_period = pt->synth_opts.period; 2225 err = intel_pt_synth_event(session, "instructions", &attr, id); 2226 if (err) 2227 return err; 2228 pt->sample_instructions = true; 2229 pt->instructions_sample_type = attr.sample_type; 2230 pt->instructions_id = id; 2231 id += 1; 2232 } 2233 2234 attr.sample_type &= ~(u64)PERF_SAMPLE_PERIOD; 2235 attr.sample_period = 1; 2236 2237 if (pt->synth_opts.transactions) { 2238 attr.config = PERF_COUNT_HW_INSTRUCTIONS; 2239 err = intel_pt_synth_event(session, "transactions", &attr, id); 2240 if (err) 2241 return err; 2242 pt->sample_transactions = true; 2243 pt->transactions_sample_type = attr.sample_type; 2244 pt->transactions_id = id; 2245 intel_pt_set_event_name(evlist, id, "transactions"); 2246 id += 1; 2247 } 2248 2249 attr.type = PERF_TYPE_SYNTH; 2250 attr.sample_type |= PERF_SAMPLE_RAW; 2251 2252 if (pt->synth_opts.ptwrites) { 2253 attr.config = PERF_SYNTH_INTEL_PTWRITE; 2254 err = intel_pt_synth_event(session, "ptwrite", &attr, id); 2255 if (err) 2256 return err; 2257 pt->sample_ptwrites = true; 2258 pt->ptwrites_sample_type = attr.sample_type; 2259 pt->ptwrites_id = id; 2260 intel_pt_set_event_name(evlist, id, "ptwrite"); 2261 id += 1; 2262 } 2263 2264 if (pt->synth_opts.pwr_events) { 2265 pt->sample_pwr_events = true; 2266 pt->pwr_events_sample_type = attr.sample_type; 2267 2268 attr.config = PERF_SYNTH_INTEL_CBR; 2269 err = intel_pt_synth_event(session, "cbr", &attr, id); 2270 if (err) 2271 return err; 2272 pt->cbr_id = id; 2273 intel_pt_set_event_name(evlist, id, "cbr"); 2274 id += 1; 2275 } 2276 2277 if (pt->synth_opts.pwr_events && (evsel->attr.config & 0x10)) { 2278 attr.config = PERF_SYNTH_INTEL_MWAIT; 2279 err = intel_pt_synth_event(session, "mwait", &attr, id); 2280 if (err) 2281 return err; 2282 pt->mwait_id = id; 2283 intel_pt_set_event_name(evlist, id, "mwait"); 2284 id += 1; 2285 2286 attr.config = PERF_SYNTH_INTEL_PWRE; 2287 err = intel_pt_synth_event(session, "pwre", &attr, id); 2288 if (err) 2289 return err; 2290 pt->pwre_id = id; 2291 intel_pt_set_event_name(evlist, id, "pwre"); 2292 id += 1; 2293 2294 attr.config = PERF_SYNTH_INTEL_EXSTOP; 2295 err = intel_pt_synth_event(session, "exstop", &attr, id); 2296 if (err) 2297 return err; 2298 pt->exstop_id = id; 2299 intel_pt_set_event_name(evlist, id, "exstop"); 2300 id += 1; 2301 2302 attr.config = PERF_SYNTH_INTEL_PWRX; 2303 err = intel_pt_synth_event(session, "pwrx", &attr, id); 2304 if (err) 2305 return err; 2306 pt->pwrx_id = id; 2307 intel_pt_set_event_name(evlist, id, "pwrx"); 2308 id += 1; 2309 } 2310 2311 return 0; 2312 } 2313 2314 static struct perf_evsel *intel_pt_find_sched_switch(struct perf_evlist *evlist) 2315 { 2316 struct perf_evsel *evsel; 2317 2318 evlist__for_each_entry_reverse(evlist, evsel) { 2319 const char *name = perf_evsel__name(evsel); 2320 2321 if (!strcmp(name, "sched:sched_switch")) 2322 return evsel; 2323 } 2324 2325 return NULL; 2326 } 2327 2328 static bool intel_pt_find_switch(struct perf_evlist *evlist) 2329 { 2330 struct perf_evsel *evsel; 2331 2332 evlist__for_each_entry(evlist, evsel) { 2333 if (evsel->attr.context_switch) 2334 return true; 2335 } 2336 2337 return false; 2338 } 2339 2340 static int intel_pt_perf_config(const char *var, const char *value, void *data) 2341 { 2342 struct intel_pt *pt = data; 2343 2344 if (!strcmp(var, "intel-pt.mispred-all")) 2345 pt->mispred_all = perf_config_bool(var, value); 2346 2347 return 0; 2348 } 2349 2350 static const char * const intel_pt_info_fmts[] = { 2351 [INTEL_PT_PMU_TYPE] = " PMU Type %"PRId64"\n", 2352 [INTEL_PT_TIME_SHIFT] = " Time Shift %"PRIu64"\n", 2353 [INTEL_PT_TIME_MULT] = " Time Muliplier %"PRIu64"\n", 2354 [INTEL_PT_TIME_ZERO] = " Time Zero %"PRIu64"\n", 2355 [INTEL_PT_CAP_USER_TIME_ZERO] = " Cap Time Zero %"PRId64"\n", 2356 [INTEL_PT_TSC_BIT] = " TSC bit %#"PRIx64"\n", 2357 [INTEL_PT_NORETCOMP_BIT] = " NoRETComp bit %#"PRIx64"\n", 2358 [INTEL_PT_HAVE_SCHED_SWITCH] = " Have sched_switch %"PRId64"\n", 2359 [INTEL_PT_SNAPSHOT_MODE] = " Snapshot mode %"PRId64"\n", 2360 [INTEL_PT_PER_CPU_MMAPS] = " Per-cpu maps %"PRId64"\n", 2361 [INTEL_PT_MTC_BIT] = " MTC bit %#"PRIx64"\n", 2362 [INTEL_PT_TSC_CTC_N] = " TSC:CTC numerator %"PRIu64"\n", 2363 [INTEL_PT_TSC_CTC_D] = " TSC:CTC denominator %"PRIu64"\n", 2364 [INTEL_PT_CYC_BIT] = " CYC bit %#"PRIx64"\n", 2365 [INTEL_PT_MAX_NONTURBO_RATIO] = " Max non-turbo ratio %"PRIu64"\n", 2366 [INTEL_PT_FILTER_STR_LEN] = " Filter string len. %"PRIu64"\n", 2367 }; 2368 2369 static void intel_pt_print_info(u64 *arr, int start, int finish) 2370 { 2371 int i; 2372 2373 if (!dump_trace) 2374 return; 2375 2376 for (i = start; i <= finish; i++) 2377 fprintf(stdout, intel_pt_info_fmts[i], arr[i]); 2378 } 2379 2380 static void intel_pt_print_info_str(const char *name, const char *str) 2381 { 2382 if (!dump_trace) 2383 return; 2384 2385 fprintf(stdout, " %-20s%s\n", name, str ? str : ""); 2386 } 2387 2388 static bool intel_pt_has(struct auxtrace_info_event *auxtrace_info, int pos) 2389 { 2390 return auxtrace_info->header.size >= 2391 sizeof(struct auxtrace_info_event) + (sizeof(u64) * (pos + 1)); 2392 } 2393 2394 int intel_pt_process_auxtrace_info(union perf_event *event, 2395 struct perf_session *session) 2396 { 2397 struct auxtrace_info_event *auxtrace_info = &event->auxtrace_info; 2398 size_t min_sz = sizeof(u64) * INTEL_PT_PER_CPU_MMAPS; 2399 struct intel_pt *pt; 2400 void *info_end; 2401 u64 *info; 2402 int err; 2403 2404 if (auxtrace_info->header.size < sizeof(struct auxtrace_info_event) + 2405 min_sz) 2406 return -EINVAL; 2407 2408 pt = zalloc(sizeof(struct intel_pt)); 2409 if (!pt) 2410 return -ENOMEM; 2411 2412 addr_filters__init(&pt->filts); 2413 2414 err = perf_config(intel_pt_perf_config, pt); 2415 if (err) 2416 goto err_free; 2417 2418 err = auxtrace_queues__init(&pt->queues); 2419 if (err) 2420 goto err_free; 2421 2422 intel_pt_log_set_name(INTEL_PT_PMU_NAME); 2423 2424 pt->session = session; 2425 pt->machine = &session->machines.host; /* No kvm support */ 2426 pt->auxtrace_type = auxtrace_info->type; 2427 pt->pmu_type = auxtrace_info->priv[INTEL_PT_PMU_TYPE]; 2428 pt->tc.time_shift = auxtrace_info->priv[INTEL_PT_TIME_SHIFT]; 2429 pt->tc.time_mult = auxtrace_info->priv[INTEL_PT_TIME_MULT]; 2430 pt->tc.time_zero = auxtrace_info->priv[INTEL_PT_TIME_ZERO]; 2431 pt->cap_user_time_zero = auxtrace_info->priv[INTEL_PT_CAP_USER_TIME_ZERO]; 2432 pt->tsc_bit = auxtrace_info->priv[INTEL_PT_TSC_BIT]; 2433 pt->noretcomp_bit = auxtrace_info->priv[INTEL_PT_NORETCOMP_BIT]; 2434 pt->have_sched_switch = auxtrace_info->priv[INTEL_PT_HAVE_SCHED_SWITCH]; 2435 pt->snapshot_mode = auxtrace_info->priv[INTEL_PT_SNAPSHOT_MODE]; 2436 pt->per_cpu_mmaps = auxtrace_info->priv[INTEL_PT_PER_CPU_MMAPS]; 2437 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_PMU_TYPE, 2438 INTEL_PT_PER_CPU_MMAPS); 2439 2440 if (intel_pt_has(auxtrace_info, INTEL_PT_CYC_BIT)) { 2441 pt->mtc_bit = auxtrace_info->priv[INTEL_PT_MTC_BIT]; 2442 pt->mtc_freq_bits = auxtrace_info->priv[INTEL_PT_MTC_FREQ_BITS]; 2443 pt->tsc_ctc_ratio_n = auxtrace_info->priv[INTEL_PT_TSC_CTC_N]; 2444 pt->tsc_ctc_ratio_d = auxtrace_info->priv[INTEL_PT_TSC_CTC_D]; 2445 pt->cyc_bit = auxtrace_info->priv[INTEL_PT_CYC_BIT]; 2446 intel_pt_print_info(&auxtrace_info->priv[0], INTEL_PT_MTC_BIT, 2447 INTEL_PT_CYC_BIT); 2448 } 2449 2450 if (intel_pt_has(auxtrace_info, INTEL_PT_MAX_NONTURBO_RATIO)) { 2451 pt->max_non_turbo_ratio = 2452 auxtrace_info->priv[INTEL_PT_MAX_NONTURBO_RATIO]; 2453 intel_pt_print_info(&auxtrace_info->priv[0], 2454 INTEL_PT_MAX_NONTURBO_RATIO, 2455 INTEL_PT_MAX_NONTURBO_RATIO); 2456 } 2457 2458 info = &auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN] + 1; 2459 info_end = (void *)info + auxtrace_info->header.size; 2460 2461 if (intel_pt_has(auxtrace_info, INTEL_PT_FILTER_STR_LEN)) { 2462 size_t len; 2463 2464 len = auxtrace_info->priv[INTEL_PT_FILTER_STR_LEN]; 2465 intel_pt_print_info(&auxtrace_info->priv[0], 2466 INTEL_PT_FILTER_STR_LEN, 2467 INTEL_PT_FILTER_STR_LEN); 2468 if (len) { 2469 const char *filter = (const char *)info; 2470 2471 len = roundup(len + 1, 8); 2472 info += len >> 3; 2473 if ((void *)info > info_end) { 2474 pr_err("%s: bad filter string length\n", __func__); 2475 err = -EINVAL; 2476 goto err_free_queues; 2477 } 2478 pt->filter = memdup(filter, len); 2479 if (!pt->filter) { 2480 err = -ENOMEM; 2481 goto err_free_queues; 2482 } 2483 if (session->header.needs_swap) 2484 mem_bswap_64(pt->filter, len); 2485 if (pt->filter[len - 1]) { 2486 pr_err("%s: filter string not null terminated\n", __func__); 2487 err = -EINVAL; 2488 goto err_free_queues; 2489 } 2490 err = addr_filters__parse_bare_filter(&pt->filts, 2491 filter); 2492 if (err) 2493 goto err_free_queues; 2494 } 2495 intel_pt_print_info_str("Filter string", pt->filter); 2496 } 2497 2498 pt->timeless_decoding = intel_pt_timeless_decoding(pt); 2499 pt->have_tsc = intel_pt_have_tsc(pt); 2500 pt->sampling_mode = false; 2501 pt->est_tsc = !pt->timeless_decoding; 2502 2503 pt->unknown_thread = thread__new(999999999, 999999999); 2504 if (!pt->unknown_thread) { 2505 err = -ENOMEM; 2506 goto err_free_queues; 2507 } 2508 2509 /* 2510 * Since this thread will not be kept in any rbtree not in a 2511 * list, initialize its list node so that at thread__put() the 2512 * current thread lifetime assuption is kept and we don't segfault 2513 * at list_del_init(). 2514 */ 2515 INIT_LIST_HEAD(&pt->unknown_thread->node); 2516 2517 err = thread__set_comm(pt->unknown_thread, "unknown", 0); 2518 if (err) 2519 goto err_delete_thread; 2520 if (thread__init_map_groups(pt->unknown_thread, pt->machine)) { 2521 err = -ENOMEM; 2522 goto err_delete_thread; 2523 } 2524 2525 pt->auxtrace.process_event = intel_pt_process_event; 2526 pt->auxtrace.process_auxtrace_event = intel_pt_process_auxtrace_event; 2527 pt->auxtrace.flush_events = intel_pt_flush; 2528 pt->auxtrace.free_events = intel_pt_free_events; 2529 pt->auxtrace.free = intel_pt_free; 2530 session->auxtrace = &pt->auxtrace; 2531 2532 if (dump_trace) 2533 return 0; 2534 2535 if (pt->have_sched_switch == 1) { 2536 pt->switch_evsel = intel_pt_find_sched_switch(session->evlist); 2537 if (!pt->switch_evsel) { 2538 pr_err("%s: missing sched_switch event\n", __func__); 2539 err = -EINVAL; 2540 goto err_delete_thread; 2541 } 2542 } else if (pt->have_sched_switch == 2 && 2543 !intel_pt_find_switch(session->evlist)) { 2544 pr_err("%s: missing context_switch attribute flag\n", __func__); 2545 err = -EINVAL; 2546 goto err_delete_thread; 2547 } 2548 2549 if (session->itrace_synth_opts && session->itrace_synth_opts->set) { 2550 pt->synth_opts = *session->itrace_synth_opts; 2551 } else { 2552 itrace_synth_opts__set_default(&pt->synth_opts); 2553 if (use_browser != -1) { 2554 pt->synth_opts.branches = false; 2555 pt->synth_opts.callchain = true; 2556 } 2557 if (session->itrace_synth_opts) 2558 pt->synth_opts.thread_stack = 2559 session->itrace_synth_opts->thread_stack; 2560 } 2561 2562 if (pt->synth_opts.log) 2563 intel_pt_log_enable(); 2564 2565 /* Maximum non-turbo ratio is TSC freq / 100 MHz */ 2566 if (pt->tc.time_mult) { 2567 u64 tsc_freq = intel_pt_ns_to_ticks(pt, 1000000000); 2568 2569 if (!pt->max_non_turbo_ratio) 2570 pt->max_non_turbo_ratio = 2571 (tsc_freq + 50000000) / 100000000; 2572 intel_pt_log("TSC frequency %"PRIu64"\n", tsc_freq); 2573 intel_pt_log("Maximum non-turbo ratio %u\n", 2574 pt->max_non_turbo_ratio); 2575 pt->cbr2khz = tsc_freq / pt->max_non_turbo_ratio / 1000; 2576 } 2577 2578 if (pt->synth_opts.calls) 2579 pt->branches_filter |= PERF_IP_FLAG_CALL | PERF_IP_FLAG_ASYNC | 2580 PERF_IP_FLAG_TRACE_END; 2581 if (pt->synth_opts.returns) 2582 pt->branches_filter |= PERF_IP_FLAG_RETURN | 2583 PERF_IP_FLAG_TRACE_BEGIN; 2584 2585 if (pt->synth_opts.callchain && !symbol_conf.use_callchain) { 2586 symbol_conf.use_callchain = true; 2587 if (callchain_register_param(&callchain_param) < 0) { 2588 symbol_conf.use_callchain = false; 2589 pt->synth_opts.callchain = false; 2590 } 2591 } 2592 2593 err = intel_pt_synth_events(pt, session); 2594 if (err) 2595 goto err_delete_thread; 2596 2597 err = auxtrace_queues__process_index(&pt->queues, session); 2598 if (err) 2599 goto err_delete_thread; 2600 2601 if (pt->queues.populated) 2602 pt->data_queued = true; 2603 2604 if (pt->timeless_decoding) 2605 pr_debug2("Intel PT decoding without timestamps\n"); 2606 2607 return 0; 2608 2609 err_delete_thread: 2610 thread__zput(pt->unknown_thread); 2611 err_free_queues: 2612 intel_pt_log_disable(); 2613 auxtrace_queues__free(&pt->queues); 2614 session->auxtrace = NULL; 2615 err_free: 2616 addr_filters__exit(&pt->filts); 2617 zfree(&pt->filter); 2618 free(pt); 2619 return err; 2620 } 2621