19146af44SZhengjun Xing[ 29146af44SZhengjun Xing { 39146af44SZhengjun Xing "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 4*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 59146af44SZhengjun Xing "EventCode": "0xe6", 69146af44SZhengjun Xing "EventName": "BACLEARS.ANY", 79146af44SZhengjun Xing "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", 89146af44SZhengjun Xing "SampleAfterValue": "200003", 99146af44SZhengjun Xing "UMask": "0x1" 109146af44SZhengjun Xing }, 119146af44SZhengjun Xing { 129146af44SZhengjun Xing "BriefDescription": "Counts the number of BACLEARS due to a conditional jump.", 13*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 149146af44SZhengjun Xing "EventCode": "0xe6", 159146af44SZhengjun Xing "EventName": "BACLEARS.COND", 169146af44SZhengjun Xing "SampleAfterValue": "200003", 179146af44SZhengjun Xing "UMask": "0x10" 189146af44SZhengjun Xing }, 199146af44SZhengjun Xing { 209146af44SZhengjun Xing "BriefDescription": "Counts the number of BACLEARS due to an indirect branch.", 21*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 229146af44SZhengjun Xing "EventCode": "0xe6", 239146af44SZhengjun Xing "EventName": "BACLEARS.INDIRECT", 249146af44SZhengjun Xing "SampleAfterValue": "200003", 259146af44SZhengjun Xing "UMask": "0x2" 269146af44SZhengjun Xing }, 279146af44SZhengjun Xing { 289146af44SZhengjun Xing "BriefDescription": "Counts the number of BACLEARS due to a return branch.", 29*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 309146af44SZhengjun Xing "EventCode": "0xe6", 319146af44SZhengjun Xing "EventName": "BACLEARS.RETURN", 329146af44SZhengjun Xing "SampleAfterValue": "200003", 339146af44SZhengjun Xing "UMask": "0x8" 349146af44SZhengjun Xing }, 359146af44SZhengjun Xing { 369146af44SZhengjun Xing "BriefDescription": "Counts the number of BACLEARS due to a direct, unconditional jump.", 37*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 389146af44SZhengjun Xing "EventCode": "0xe6", 399146af44SZhengjun Xing "EventName": "BACLEARS.UNCOND", 409146af44SZhengjun Xing "SampleAfterValue": "200003", 419146af44SZhengjun Xing "UMask": "0x4" 429146af44SZhengjun Xing }, 439146af44SZhengjun Xing { 449146af44SZhengjun Xing "BriefDescription": "Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction.", 45*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 469146af44SZhengjun Xing "EventCode": "0xe9", 479146af44SZhengjun Xing "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", 489146af44SZhengjun Xing "SampleAfterValue": "200003", 499146af44SZhengjun Xing "UMask": "0x1" 509146af44SZhengjun Xing }, 519146af44SZhengjun Xing { 529146af44SZhengjun Xing "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", 53*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 549146af44SZhengjun Xing "EventCode": "0x80", 559146af44SZhengjun Xing "EventName": "ICACHE.ACCESSES", 569146af44SZhengjun Xing "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", 579146af44SZhengjun Xing "SampleAfterValue": "200003", 589146af44SZhengjun Xing "UMask": "0x3" 599146af44SZhengjun Xing }, 609146af44SZhengjun Xing { 619146af44SZhengjun Xing "BriefDescription": "Counts the number of instruction cache hits.", 62*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 639146af44SZhengjun Xing "EventCode": "0x80", 649146af44SZhengjun Xing "EventName": "ICACHE.HIT", 659146af44SZhengjun Xing "PublicDescription": "Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", 669146af44SZhengjun Xing "SampleAfterValue": "200003", 679146af44SZhengjun Xing "UMask": "0x1" 689146af44SZhengjun Xing }, 699146af44SZhengjun Xing { 709146af44SZhengjun Xing "BriefDescription": "Counts the number of instruction cache misses.", 71*7c79eb5cSIan Rogers "Counter": "0,1,2,3", 729146af44SZhengjun Xing "EventCode": "0x80", 739146af44SZhengjun Xing "EventName": "ICACHE.MISSES", 749146af44SZhengjun Xing "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", 759146af44SZhengjun Xing "SampleAfterValue": "200003", 769146af44SZhengjun Xing "UMask": "0x2" 779146af44SZhengjun Xing } 789146af44SZhengjun Xing] 79