1[ 2 { 3 "BriefDescription": "Cycles when floating-point divide unit is busy executing divide or square root operations.", 4 "Counter": "0,1,2,3,4,5,6,7,8,9", 5 "CounterMask": "1", 6 "EventCode": "0xb0", 7 "EventName": "ARITH.FPDIV_ACTIVE", 8 "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only.", 9 "SampleAfterValue": "1000003", 10 "UMask": "0x1", 11 "Unit": "cpu_core" 12 }, 13 { 14 "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", 15 "Counter": "0,1,2,3,4,5,6,7", 16 "CounterMask": "1", 17 "EventCode": "0xcd", 18 "EventName": "ARITH.FPDIV_ACTIVE", 19 "SampleAfterValue": "1000003", 20 "UMask": "0x2", 21 "Unit": "cpu_lowpower" 22 }, 23 { 24 "BriefDescription": "Counts all microcode FP assists.", 25 "Counter": "0,1,2,3,4,5,6,7,8,9", 26 "EventCode": "0xc1", 27 "EventName": "ASSISTS.FP", 28 "PublicDescription": "Counts all microcode Floating Point assists.", 29 "SampleAfterValue": "100003", 30 "UMask": "0x2", 31 "Unit": "cpu_core" 32 }, 33 { 34 "BriefDescription": "ASSISTS.SSE_AVX_MIX", 35 "Counter": "0,1,2,3,4,5,6,7,8,9", 36 "EventCode": "0xc1", 37 "EventName": "ASSISTS.SSE_AVX_MIX", 38 "SampleAfterValue": "1000003", 39 "UMask": "0x10", 40 "Unit": "cpu_core" 41 }, 42 { 43 "BriefDescription": "Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD* / SUB* / MUL / FMA* / DPP.", 44 "Counter": "0,1,2,3,4,5,6,7,8,9", 45 "EventCode": "0xb3", 46 "EventName": "FP_ARITH_DISPATCHED.V0", 47 "SampleAfterValue": "2000003", 48 "UMask": "0x1", 49 "Unit": "cpu_core" 50 }, 51 { 52 "BriefDescription": "Number of FP-arith-uops dispatched on 2nd VEC port (port 1)", 53 "Counter": "0,1,2,3,4,5,6,7,8,9", 54 "EventCode": "0xb3", 55 "EventName": "FP_ARITH_DISPATCHED.V1", 56 "SampleAfterValue": "2000003", 57 "UMask": "0x2", 58 "Unit": "cpu_core" 59 }, 60 { 61 "BriefDescription": "Number of FP-arith-uops dispatched on 3rd VEC port (port 5)", 62 "Counter": "0,1,2,3,4,5,6,7,8,9", 63 "EventCode": "0xb3", 64 "EventName": "FP_ARITH_DISPATCHED.V2", 65 "SampleAfterValue": "2000003", 66 "UMask": "0x4", 67 "Unit": "cpu_core" 68 }, 69 { 70 "BriefDescription": "Number of FP-arith-uops dispatched on 4th VEC port", 71 "Counter": "0,1,2,3,4,5,6,7,8,9", 72 "EventCode": "0xb3", 73 "EventName": "FP_ARITH_DISPATCHED.V3", 74 "SampleAfterValue": "2000003", 75 "UMask": "0x8", 76 "Unit": "cpu_core" 77 }, 78 { 79 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", 80 "Counter": "0,1,2,3,4,5,6,7,8,9", 81 "Deprecated": "1", 82 "EventCode": "0xc7", 83 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", 84 "SampleAfterValue": "100003", 85 "UMask": "0x4", 86 "Unit": "cpu_core" 87 }, 88 { 89 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", 90 "Counter": "0,1,2,3,4,5,6,7,8,9", 91 "Deprecated": "1", 92 "EventCode": "0xc7", 93 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", 94 "SampleAfterValue": "100003", 95 "UMask": "0x8", 96 "Unit": "cpu_core" 97 }, 98 { 99 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", 100 "Counter": "0,1,2,3,4,5,6,7,8,9", 101 "Deprecated": "1", 102 "EventCode": "0xc7", 103 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", 104 "SampleAfterValue": "100003", 105 "UMask": "0x10", 106 "Unit": "cpu_core" 107 }, 108 { 109 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", 110 "Counter": "0,1,2,3,4,5,6,7,8,9", 111 "Deprecated": "1", 112 "EventCode": "0xc7", 113 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", 114 "SampleAfterValue": "100003", 115 "UMask": "0x20", 116 "Unit": "cpu_core" 117 }, 118 { 119 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS", 120 "Counter": "0,1,2,3,4,5,6,7,8,9", 121 "Deprecated": "1", 122 "EventCode": "0xc7", 123 "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", 124 "SampleAfterValue": "100003", 125 "UMask": "0x18", 126 "Unit": "cpu_core" 127 }, 128 { 129 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR", 130 "Counter": "0,1,2,3,4,5,6,7,8,9", 131 "Deprecated": "1", 132 "EventCode": "0xc7", 133 "EventName": "FP_ARITH_INST_RETIRED.SCALAR", 134 "SampleAfterValue": "1000003", 135 "UMask": "0x3", 136 "Unit": "cpu_core" 137 }, 138 { 139 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", 140 "Counter": "0,1,2,3,4,5,6,7,8,9", 141 "Deprecated": "1", 142 "EventCode": "0xc7", 143 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", 144 "SampleAfterValue": "100003", 145 "UMask": "0x1", 146 "Unit": "cpu_core" 147 }, 148 { 149 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", 150 "Counter": "0,1,2,3,4,5,6,7,8,9", 151 "Deprecated": "1", 152 "EventCode": "0xc7", 153 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", 154 "SampleAfterValue": "100003", 155 "UMask": "0x2", 156 "Unit": "cpu_core" 157 }, 158 { 159 "BriefDescription": "This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR", 160 "Counter": "0,1,2,3,4,5,6,7,8,9", 161 "Deprecated": "1", 162 "EventCode": "0xc7", 163 "EventName": "FP_ARITH_INST_RETIRED.VECTOR", 164 "SampleAfterValue": "1000003", 165 "UMask": "0x3c", 166 "Unit": "cpu_core" 167 }, 168 { 169 "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_128B]", 170 "Counter": "0,1,2,3,4,5,6,7,8,9", 171 "EventCode": "0xc7", 172 "EventName": "FP_ARITH_INST_RETIRED.VECTOR_128B", 173 "SampleAfterValue": "100003", 174 "UMask": "0xc", 175 "Unit": "cpu_core" 176 }, 177 { 178 "BriefDescription": "FP_ARITH_INST_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_OPS_RETIRED.VECTOR_256B]", 179 "Counter": "0,1,2,3,4,5,6,7,8,9", 180 "EventCode": "0xc7", 181 "EventName": "FP_ARITH_INST_RETIRED.VECTOR_256B", 182 "SampleAfterValue": "100003", 183 "UMask": "0x30", 184 "Unit": "cpu_core" 185 }, 186 { 187 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 188 "Counter": "0,1,2,3,4,5,6,7,8,9", 189 "EventCode": "0xc7", 190 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE", 191 "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 192 "SampleAfterValue": "100003", 193 "UMask": "0x4", 194 "Unit": "cpu_core" 195 }, 196 { 197 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 198 "Counter": "0,1,2,3,4,5,6,7,8,9", 199 "EventCode": "0xc7", 200 "EventName": "FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE", 201 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 202 "SampleAfterValue": "100003", 203 "UMask": "0x8", 204 "Unit": "cpu_core" 205 }, 206 { 207 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 208 "Counter": "0,1,2,3,4,5,6,7,8,9", 209 "EventCode": "0xc7", 210 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE", 211 "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 212 "SampleAfterValue": "100003", 213 "UMask": "0x10", 214 "Unit": "cpu_core" 215 }, 216 { 217 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 218 "Counter": "0,1,2,3,4,5,6,7,8,9", 219 "EventCode": "0xc7", 220 "EventName": "FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE", 221 "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 222 "SampleAfterValue": "100003", 223 "UMask": "0x20", 224 "Unit": "cpu_core" 225 }, 226 { 227 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", 228 "Counter": "0,1,2,3,4,5,6,7,8,9", 229 "EventCode": "0xc7", 230 "EventName": "FP_ARITH_OPS_RETIRED.4_FLOPS", 231 "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 232 "SampleAfterValue": "100003", 233 "UMask": "0x18", 234 "Unit": "cpu_core" 235 }, 236 { 237 "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", 238 "Counter": "0,1,2,3,4,5,6,7,8,9", 239 "EventCode": "0xc7", 240 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR", 241 "PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 242 "SampleAfterValue": "1000003", 243 "UMask": "0x3", 244 "Unit": "cpu_core" 245 }, 246 { 247 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 248 "Counter": "0,1,2,3,4,5,6,7,8,9", 249 "EventCode": "0xc7", 250 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE", 251 "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 252 "SampleAfterValue": "100003", 253 "UMask": "0x1", 254 "Unit": "cpu_core" 255 }, 256 { 257 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", 258 "Counter": "0,1,2,3,4,5,6,7,8,9", 259 "EventCode": "0xc7", 260 "EventName": "FP_ARITH_OPS_RETIRED.SCALAR_SINGLE", 261 "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 262 "SampleAfterValue": "100003", 263 "UMask": "0x2", 264 "Unit": "cpu_core" 265 }, 266 { 267 "BriefDescription": "Number of any Vector retired FP arithmetic instructions", 268 "Counter": "0,1,2,3,4,5,6,7,8,9", 269 "EventCode": "0xc7", 270 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR", 271 "PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.", 272 "SampleAfterValue": "1000003", 273 "UMask": "0x3c", 274 "Unit": "cpu_core" 275 }, 276 { 277 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_128B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_128B]", 278 "Counter": "0,1,2,3,4,5,6,7,8,9", 279 "EventCode": "0xc7", 280 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_128B", 281 "SampleAfterValue": "100003", 282 "UMask": "0xc", 283 "Unit": "cpu_core" 284 }, 285 { 286 "BriefDescription": "FP_ARITH_OPS_RETIRED.VECTOR_256B [This event is alias to FP_ARITH_INST_RETIRED.VECTOR_256B]", 287 "Counter": "0,1,2,3,4,5,6,7,8,9", 288 "EventCode": "0xc7", 289 "EventName": "FP_ARITH_OPS_RETIRED.VECTOR_256B", 290 "SampleAfterValue": "100003", 291 "UMask": "0x30", 292 "Unit": "cpu_core" 293 }, 294 { 295 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", 296 "Counter": "0,1,2,3,4,5,6,7", 297 "EventCode": "0xc8", 298 "EventName": "FP_FLOPS_RETIRED.ALL", 299 "SampleAfterValue": "1000003", 300 "UMask": "0x3", 301 "Unit": "cpu_atom" 302 }, 303 { 304 "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", 305 "Counter": "0,1,2,3,4,5,6,7", 306 "EventCode": "0xc8", 307 "EventName": "FP_FLOPS_RETIRED.ALL", 308 "SampleAfterValue": "1000003", 309 "UMask": "0x3", 310 "Unit": "cpu_lowpower" 311 }, 312 { 313 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]", 314 "Counter": "0,1,2,3,4,5,6,7", 315 "Deprecated": "1", 316 "EventCode": "0xc8", 317 "EventName": "FP_FLOPS_RETIRED.DP", 318 "SampleAfterValue": "1000003", 319 "UMask": "0x1", 320 "Unit": "cpu_lowpower" 321 }, 322 { 323 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results", 324 "Counter": "0,1,2,3,4,5,6,7", 325 "EventCode": "0xc8", 326 "EventName": "FP_FLOPS_RETIRED.FP32", 327 "SampleAfterValue": "1000003", 328 "UMask": "0x2", 329 "Unit": "cpu_atom" 330 }, 331 { 332 "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]", 333 "Counter": "0,1,2,3,4,5,6,7", 334 "EventCode": "0xc8", 335 "EventName": "FP_FLOPS_RETIRED.FP32", 336 "SampleAfterValue": "1000003", 337 "UMask": "0x2", 338 "Unit": "cpu_lowpower" 339 }, 340 { 341 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results", 342 "Counter": "0,1,2,3,4,5,6,7", 343 "EventCode": "0xc8", 344 "EventName": "FP_FLOPS_RETIRED.FP64", 345 "SampleAfterValue": "1000003", 346 "UMask": "0x1", 347 "Unit": "cpu_atom" 348 }, 349 { 350 "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]", 351 "Counter": "0,1,2,3,4,5,6,7", 352 "EventCode": "0xc8", 353 "EventName": "FP_FLOPS_RETIRED.FP64", 354 "SampleAfterValue": "1000003", 355 "UMask": "0x1", 356 "Unit": "cpu_lowpower" 357 }, 358 { 359 "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]", 360 "Counter": "0,1,2,3,4,5,6,7", 361 "Deprecated": "1", 362 "EventCode": "0xc8", 363 "EventName": "FP_FLOPS_RETIRED.SP", 364 "SampleAfterValue": "1000003", 365 "UMask": "0x2", 366 "Unit": "cpu_lowpower" 367 }, 368 { 369 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations.", 370 "Counter": "0,1,2,3,4,5,6,7", 371 "EventCode": "0xc7", 372 "EventName": "FP_INST_RETIRED.128B_DP", 373 "SampleAfterValue": "1000003", 374 "UMask": "0x8", 375 "Unit": "cpu_atom" 376 }, 377 { 378 "BriefDescription": "Counts the total number of floating point retired instructions.", 379 "Counter": "0,1,2,3,4,5,6,7", 380 "EventCode": "0xc7", 381 "EventName": "FP_INST_RETIRED.128B_DP", 382 "SampleAfterValue": "1000003", 383 "UMask": "0x8", 384 "Unit": "cpu_lowpower" 385 }, 386 { 387 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", 388 "Counter": "0,1,2,3,4,5,6,7", 389 "EventCode": "0xc7", 390 "EventName": "FP_INST_RETIRED.128B_SP", 391 "SampleAfterValue": "1000003", 392 "UMask": "0x4", 393 "Unit": "cpu_atom" 394 }, 395 { 396 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", 397 "Counter": "0,1,2,3,4,5,6,7", 398 "EventCode": "0xc7", 399 "EventName": "FP_INST_RETIRED.128B_SP", 400 "SampleAfterValue": "1000003", 401 "UMask": "0x4", 402 "Unit": "cpu_lowpower" 403 }, 404 { 405 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", 406 "Counter": "0,1,2,3,4,5,6,7", 407 "EventCode": "0xc7", 408 "EventName": "FP_INST_RETIRED.256B_DP", 409 "SampleAfterValue": "1000003", 410 "UMask": "0x20", 411 "Unit": "cpu_atom" 412 }, 413 { 414 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", 415 "Counter": "0,1,2,3,4,5,6,7", 416 "EventCode": "0xc7", 417 "EventName": "FP_INST_RETIRED.256B_DP", 418 "SampleAfterValue": "1000003", 419 "UMask": "0x20", 420 "Unit": "cpu_lowpower" 421 }, 422 { 423 "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point.", 424 "Counter": "0,1,2,3,4,5,6,7", 425 "EventCode": "0xc7", 426 "EventName": "FP_INST_RETIRED.256B_SP", 427 "SampleAfterValue": "1000003", 428 "UMask": "0x10", 429 "Unit": "cpu_atom" 430 }, 431 { 432 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point", 433 "Counter": "0,1,2,3,4,5,6,7", 434 "EventCode": "0xc7", 435 "EventName": "FP_INST_RETIRED.32B_SP", 436 "SampleAfterValue": "1000003", 437 "UMask": "0x1", 438 "Unit": "cpu_atom" 439 }, 440 { 441 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", 442 "Counter": "0,1,2,3,4,5,6,7", 443 "EventCode": "0xc7", 444 "EventName": "FP_INST_RETIRED.32B_SP", 445 "SampleAfterValue": "1000003", 446 "UMask": "0x1", 447 "Unit": "cpu_lowpower" 448 }, 449 { 450 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point", 451 "Counter": "0,1,2,3,4,5,6,7", 452 "EventCode": "0xc7", 453 "EventName": "FP_INST_RETIRED.64B_DP", 454 "SampleAfterValue": "1000003", 455 "UMask": "0x2", 456 "Unit": "cpu_atom" 457 }, 458 { 459 "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", 460 "Counter": "0,1,2,3,4,5,6,7", 461 "EventCode": "0xc7", 462 "EventName": "FP_INST_RETIRED.64B_DP", 463 "SampleAfterValue": "1000003", 464 "UMask": "0x2", 465 "Unit": "cpu_lowpower" 466 }, 467 { 468 "BriefDescription": "Counts the total number of floating point retired instructions.", 469 "Counter": "0,1,2,3,4,5,6,7", 470 "EventCode": "0xc7", 471 "EventName": "FP_INST_RETIRED.ALL", 472 "SampleAfterValue": "1000003", 473 "UMask": "0x3f", 474 "Unit": "cpu_atom" 475 }, 476 { 477 "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.", 478 "Counter": "0,1,2,3,4,5,6,7", 479 "EventCode": "0xb2", 480 "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY", 481 "SampleAfterValue": "1000003", 482 "UMask": "0x1e", 483 "Unit": "cpu_atom" 484 }, 485 { 486 "BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.", 487 "Counter": "0,1,2,3,4,5,6,7", 488 "EventCode": "0xb2", 489 "EventName": "FP_VINT_UOPS_EXECUTED.STD", 490 "SampleAfterValue": "1000003", 491 "UMask": "0x1", 492 "Unit": "cpu_atom" 493 }, 494 { 495 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 496 "Counter": "0,1,2,3,4,5,6,7", 497 "EventCode": "0xc3", 498 "EventName": "MACHINE_CLEARS.FP_ASSIST", 499 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 500 "SampleAfterValue": "20003", 501 "UMask": "0x4", 502 "Unit": "cpu_atom" 503 }, 504 { 505 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", 506 "Counter": "0,1,2,3,4,5,6,7", 507 "EventCode": "0xc3", 508 "EventName": "MACHINE_CLEARS.FP_ASSIST", 509 "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", 510 "SampleAfterValue": "20003", 511 "UMask": "0x4", 512 "Unit": "cpu_lowpower" 513 }, 514 { 515 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt)", 516 "Counter": "0,1,2,3,4,5,6,7", 517 "EventCode": "0xc2", 518 "EventName": "UOPS_RETIRED.FPDIV", 519 "SampleAfterValue": "2000003", 520 "UMask": "0x8", 521 "Unit": "cpu_atom" 522 }, 523 { 524 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", 525 "Counter": "0,1,2,3,4,5,6,7", 526 "EventCode": "0xc2", 527 "EventName": "UOPS_RETIRED.FPDIV", 528 "SampleAfterValue": "2000003", 529 "UMask": "0x8", 530 "Unit": "cpu_lowpower" 531 } 532] 533