1 /* 2 * Driver for CS4231 sound chips found on Sparcs. 3 * Copyright (C) 2002 David S. Miller <davem@redhat.com> 4 * 5 * Based entirely upon drivers/sbus/audio/cs4231.c which is: 6 * Copyright (C) 1996, 1997, 1998, 1998 Derrick J Brashear (shadow@andrew.cmu.edu) 7 * and also sound/isa/cs423x/cs4231_lib.c which is: 8 * Copyright (c) by Jaroslav Kysela <perex@suse.cz> 9 */ 10 11 #include <linux/config.h> 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/moduleparam.h> 19 20 #include <sound/driver.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/info.h> 24 #include <sound/control.h> 25 #include <sound/timer.h> 26 #include <sound/initval.h> 27 #include <sound/pcm_params.h> 28 29 #include <asm/io.h> 30 #include <asm/irq.h> 31 32 #ifdef CONFIG_SBUS 33 #define SBUS_SUPPORT 34 #endif 35 36 #ifdef SBUS_SUPPORT 37 #include <asm/sbus.h> 38 #endif 39 40 #if defined(CONFIG_PCI) && defined(CONFIG_SPARC64) 41 #define EBUS_SUPPORT 42 #endif 43 44 #ifdef EBUS_SUPPORT 45 #include <linux/pci.h> 46 #include <asm/ebus.h> 47 #endif 48 49 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 50 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 52 53 module_param_array(index, int, NULL, 0444); 54 MODULE_PARM_DESC(index, "Index value for Sun CS4231 soundcard."); 55 module_param_array(id, charp, NULL, 0444); 56 MODULE_PARM_DESC(id, "ID string for Sun CS4231 soundcard."); 57 module_param_array(enable, bool, NULL, 0444); 58 MODULE_PARM_DESC(enable, "Enable Sun CS4231 soundcard."); 59 MODULE_AUTHOR("Jaroslav Kysela, Derrick J. Brashear and David S. Miller"); 60 MODULE_DESCRIPTION("Sun CS4231"); 61 MODULE_LICENSE("GPL"); 62 MODULE_SUPPORTED_DEVICE("{{Sun,CS4231}}"); 63 64 #ifdef SBUS_SUPPORT 65 typedef struct sbus_dma_info { 66 spinlock_t lock; 67 int dir; 68 void __iomem *regs; 69 } sbus_dma_info_t; 70 #endif 71 72 typedef struct snd_cs4231 cs4231_t; 73 74 typedef struct cs4231_dma_control { 75 void (*prepare)(struct cs4231_dma_control *dma_cont, int dir); 76 void (*enable)(struct cs4231_dma_control *dma_cont, int on); 77 int (*request)(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len); 78 unsigned int (*address)(struct cs4231_dma_control *dma_cont); 79 void (*reset)(cs4231_t *chip); 80 void (*preallocate)(cs4231_t *chip, snd_pcm_t *pcm); 81 #ifdef EBUS_SUPPORT 82 struct ebus_dma_info ebus_info; 83 #endif 84 #ifdef SBUS_SUPPORT 85 struct sbus_dma_info sbus_info; 86 #endif 87 } cs4231_dma_control_t; 88 89 struct snd_cs4231 { 90 spinlock_t lock; 91 void __iomem *port; 92 93 cs4231_dma_control_t p_dma; 94 cs4231_dma_control_t c_dma; 95 96 u32 flags; 97 #define CS4231_FLAG_EBUS 0x00000001 98 #define CS4231_FLAG_PLAYBACK 0x00000002 99 #define CS4231_FLAG_CAPTURE 0x00000004 100 101 snd_card_t *card; 102 snd_pcm_t *pcm; 103 snd_pcm_substream_t *playback_substream; 104 unsigned int p_periods_sent; 105 snd_pcm_substream_t *capture_substream; 106 unsigned int c_periods_sent; 107 snd_timer_t *timer; 108 109 unsigned short mode; 110 #define CS4231_MODE_NONE 0x0000 111 #define CS4231_MODE_PLAY 0x0001 112 #define CS4231_MODE_RECORD 0x0002 113 #define CS4231_MODE_TIMER 0x0004 114 #define CS4231_MODE_OPEN (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER) 115 116 unsigned char image[32]; /* registers image */ 117 int mce_bit; 118 int calibrate_mute; 119 struct semaphore mce_mutex; 120 struct semaphore open_mutex; 121 122 union { 123 #ifdef SBUS_SUPPORT 124 struct sbus_dev *sdev; 125 #endif 126 #ifdef EBUS_SUPPORT 127 struct pci_dev *pdev; 128 #endif 129 } dev_u; 130 unsigned int irq[2]; 131 unsigned int regs_size; 132 struct snd_cs4231 *next; 133 }; 134 135 static cs4231_t *cs4231_list; 136 137 /* Eventually we can use sound/isa/cs423x/cs4231_lib.c directly, but for 138 * now.... -DaveM 139 */ 140 141 /* IO ports */ 142 143 #define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x) 144 145 /* XXX offsets are different than PC ISA chips... */ 146 #define c_d_c_CS4231REGSEL 0x0 147 #define c_d_c_CS4231REG 0x4 148 #define c_d_c_CS4231STATUS 0x8 149 #define c_d_c_CS4231PIO 0xc 150 151 /* codec registers */ 152 153 #define CS4231_LEFT_INPUT 0x00 /* left input control */ 154 #define CS4231_RIGHT_INPUT 0x01 /* right input control */ 155 #define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 156 #define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 157 #define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 158 #define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 159 #define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 160 #define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 161 #define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 162 #define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 163 #define CS4231_PIN_CTRL 0x0a /* pin control */ 164 #define CS4231_TEST_INIT 0x0b /* test and initialization */ 165 #define CS4231_MISC_INFO 0x0c /* miscellaneaous information */ 166 #define CS4231_LOOPBACK 0x0d /* loopback control */ 167 #define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 168 #define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 169 #define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 170 #define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 171 #define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 172 #define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 173 #define CS4231_TIMER_LOW 0x14 /* timer low byte */ 174 #define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 175 #define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 176 #define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 177 #define CS4236_EXT_REG 0x17 /* extended register access */ 178 #define CS4231_IRQ_STATUS 0x18 /* irq status register */ 179 #define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 180 #define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 181 #define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 182 #define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 183 #define CS4235_LEFT_MASTER 0x1b /* left master output control */ 184 #define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 185 #define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */ 186 #define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 187 #define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 188 #define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 189 190 /* definitions for codec register select port - CODECP( REGSEL ) */ 191 192 #define CS4231_INIT 0x80 /* CODEC is initializing */ 193 #define CS4231_MCE 0x40 /* mode change enable */ 194 #define CS4231_TRD 0x20 /* transfer request disable */ 195 196 /* definitions for codec status register - CODECP( STATUS ) */ 197 198 #define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 199 200 /* definitions for codec irq status - CS4231_IRQ_STATUS */ 201 202 #define CS4231_PLAYBACK_IRQ 0x10 203 #define CS4231_RECORD_IRQ 0x20 204 #define CS4231_TIMER_IRQ 0x40 205 #define CS4231_ALL_IRQS 0x70 206 #define CS4231_REC_UNDERRUN 0x08 207 #define CS4231_REC_OVERRUN 0x04 208 #define CS4231_PLY_OVERRUN 0x02 209 #define CS4231_PLY_UNDERRUN 0x01 210 211 /* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 212 213 #define CS4231_ENABLE_MIC_GAIN 0x20 214 215 #define CS4231_MIXS_LINE 0x00 216 #define CS4231_MIXS_AUX1 0x40 217 #define CS4231_MIXS_MIC 0x80 218 #define CS4231_MIXS_ALL 0xc0 219 220 /* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 221 222 #define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 223 #define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 224 #define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 225 #define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 226 #define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 227 #define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 228 #define CS4231_STEREO 0x10 /* stereo mode */ 229 /* bits 3-1 define frequency divisor */ 230 #define CS4231_XTAL1 0x00 /* 24.576 crystal */ 231 #define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 232 233 /* definitions for interface control register - CS4231_IFACE_CTRL */ 234 235 #define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 236 #define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 237 #define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 238 #define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 239 #define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 240 #define CS4231_RECORD_ENABLE 0x02 /* record enable */ 241 #define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 242 243 /* definitions for pin control register - CS4231_PIN_CTRL */ 244 245 #define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 246 #define CS4231_XCTL1 0x40 /* external control #1 */ 247 #define CS4231_XCTL0 0x80 /* external control #0 */ 248 249 /* definitions for test and init register - CS4231_TEST_INIT */ 250 251 #define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 252 #define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 253 254 /* definitions for misc control register - CS4231_MISC_INFO */ 255 256 #define CS4231_MODE2 0x40 /* MODE 2 */ 257 #define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 258 #define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 259 260 /* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 261 262 #define CS4231_DACZ 0x01 /* zero DAC when underrun */ 263 #define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 264 #define CS4231_OLB 0x80 /* output level bit */ 265 266 /* SBUS DMA register defines. */ 267 268 #define APCCSR 0x10UL /* APC DMA CSR */ 269 #define APCCVA 0x20UL /* APC Capture DMA Address */ 270 #define APCCC 0x24UL /* APC Capture Count */ 271 #define APCCNVA 0x28UL /* APC Capture DMA Next Address */ 272 #define APCCNC 0x2cUL /* APC Capture Next Count */ 273 #define APCPVA 0x30UL /* APC Play DMA Address */ 274 #define APCPC 0x34UL /* APC Play Count */ 275 #define APCPNVA 0x38UL /* APC Play DMA Next Address */ 276 #define APCPNC 0x3cUL /* APC Play Next Count */ 277 278 /* Defines for SBUS DMA-routines */ 279 280 #define APCVA 0x0UL /* APC DMA Address */ 281 #define APCC 0x4UL /* APC Count */ 282 #define APCNVA 0x8UL /* APC DMA Next Address */ 283 #define APCNC 0xcUL /* APC Next Count */ 284 #define APC_PLAY 0x30UL /* Play registers start at 0x30 */ 285 #define APC_RECORD 0x20UL /* Record registers start at 0x20 */ 286 287 /* APCCSR bits */ 288 289 #define APC_INT_PENDING 0x800000 /* Interrupt Pending */ 290 #define APC_PLAY_INT 0x400000 /* Playback interrupt */ 291 #define APC_CAPT_INT 0x200000 /* Capture interrupt */ 292 #define APC_GENL_INT 0x100000 /* General interrupt */ 293 #define APC_XINT_ENA 0x80000 /* General ext int. enable */ 294 #define APC_XINT_PLAY 0x40000 /* Playback ext intr */ 295 #define APC_XINT_CAPT 0x20000 /* Capture ext intr */ 296 #define APC_XINT_GENL 0x10000 /* Error ext intr */ 297 #define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */ 298 #define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */ 299 #define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */ 300 #define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */ 301 #define APC_XINT_COVF 0x800 /* Cap data dropped on floor */ 302 #define APC_XINT_CNVA 0x400 /* Capture NVA dirty */ 303 #define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */ 304 #define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */ 305 #define APC_PPAUSE 0x80 /* Pause the play DMA */ 306 #define APC_CPAUSE 0x40 /* Pause the capture DMA */ 307 #define APC_CDC_RESET 0x20 /* CODEC RESET */ 308 #define APC_PDMA_READY 0x08 /* Play DMA Go */ 309 #define APC_CDMA_READY 0x04 /* Capture DMA Go */ 310 #define APC_CHIP_RESET 0x01 /* Reset the chip */ 311 312 /* EBUS DMA register offsets */ 313 314 #define EBDMA_CSR 0x00UL /* Control/Status */ 315 #define EBDMA_ADDR 0x04UL /* DMA Address */ 316 #define EBDMA_COUNT 0x08UL /* DMA Count */ 317 318 /* 319 * Some variables 320 */ 321 322 static unsigned char freq_bits[14] = { 323 /* 5510 */ 0x00 | CS4231_XTAL2, 324 /* 6620 */ 0x0E | CS4231_XTAL2, 325 /* 8000 */ 0x00 | CS4231_XTAL1, 326 /* 9600 */ 0x0E | CS4231_XTAL1, 327 /* 11025 */ 0x02 | CS4231_XTAL2, 328 /* 16000 */ 0x02 | CS4231_XTAL1, 329 /* 18900 */ 0x04 | CS4231_XTAL2, 330 /* 22050 */ 0x06 | CS4231_XTAL2, 331 /* 27042 */ 0x04 | CS4231_XTAL1, 332 /* 32000 */ 0x06 | CS4231_XTAL1, 333 /* 33075 */ 0x0C | CS4231_XTAL2, 334 /* 37800 */ 0x08 | CS4231_XTAL2, 335 /* 44100 */ 0x0A | CS4231_XTAL2, 336 /* 48000 */ 0x0C | CS4231_XTAL1 337 }; 338 339 static unsigned int rates[14] = { 340 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050, 341 27042, 32000, 33075, 37800, 44100, 48000 342 }; 343 344 static snd_pcm_hw_constraint_list_t hw_constraints_rates = { 345 .count = 14, 346 .list = rates, 347 }; 348 349 static int snd_cs4231_xrate(snd_pcm_runtime_t *runtime) 350 { 351 return snd_pcm_hw_constraint_list(runtime, 0, 352 SNDRV_PCM_HW_PARAM_RATE, 353 &hw_constraints_rates); 354 } 355 356 static unsigned char snd_cs4231_original_image[32] = 357 { 358 0x00, /* 00/00 - lic */ 359 0x00, /* 01/01 - ric */ 360 0x9f, /* 02/02 - la1ic */ 361 0x9f, /* 03/03 - ra1ic */ 362 0x9f, /* 04/04 - la2ic */ 363 0x9f, /* 05/05 - ra2ic */ 364 0xbf, /* 06/06 - loc */ 365 0xbf, /* 07/07 - roc */ 366 0x20, /* 08/08 - pdfr */ 367 CS4231_AUTOCALIB, /* 09/09 - ic */ 368 0x00, /* 0a/10 - pc */ 369 0x00, /* 0b/11 - ti */ 370 CS4231_MODE2, /* 0c/12 - mi */ 371 0x00, /* 0d/13 - lbc */ 372 0x00, /* 0e/14 - pbru */ 373 0x00, /* 0f/15 - pbrl */ 374 0x80, /* 10/16 - afei */ 375 0x01, /* 11/17 - afeii */ 376 0x9f, /* 12/18 - llic */ 377 0x9f, /* 13/19 - rlic */ 378 0x00, /* 14/20 - tlb */ 379 0x00, /* 15/21 - thb */ 380 0x00, /* 16/22 - la3mic/reserved */ 381 0x00, /* 17/23 - ra3mic/reserved */ 382 0x00, /* 18/24 - afs */ 383 0x00, /* 19/25 - lamoc/version */ 384 0x00, /* 1a/26 - mioc */ 385 0x00, /* 1b/27 - ramoc/reserved */ 386 0x20, /* 1c/28 - cdfr */ 387 0x00, /* 1d/29 - res4 */ 388 0x00, /* 1e/30 - cbru */ 389 0x00, /* 1f/31 - cbrl */ 390 }; 391 392 static u8 __cs4231_readb(cs4231_t *cp, void __iomem *reg_addr) 393 { 394 #ifdef EBUS_SUPPORT 395 if (cp->flags & CS4231_FLAG_EBUS) { 396 return readb(reg_addr); 397 } else { 398 #endif 399 #ifdef SBUS_SUPPORT 400 return sbus_readb(reg_addr); 401 #endif 402 #ifdef EBUS_SUPPORT 403 } 404 #endif 405 } 406 407 static void __cs4231_writeb(cs4231_t *cp, u8 val, void __iomem *reg_addr) 408 { 409 #ifdef EBUS_SUPPORT 410 if (cp->flags & CS4231_FLAG_EBUS) { 411 return writeb(val, reg_addr); 412 } else { 413 #endif 414 #ifdef SBUS_SUPPORT 415 return sbus_writeb(val, reg_addr); 416 #endif 417 #ifdef EBUS_SUPPORT 418 } 419 #endif 420 } 421 422 /* 423 * Basic I/O functions 424 */ 425 426 static void snd_cs4231_outm(cs4231_t *chip, unsigned char reg, 427 unsigned char mask, unsigned char value) 428 { 429 int timeout; 430 unsigned char tmp; 431 432 for (timeout = 250; 433 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 434 timeout--) 435 udelay(100); 436 #ifdef CONFIG_SND_DEBUG 437 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 438 snd_printdd("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 439 #endif 440 if (chip->calibrate_mute) { 441 chip->image[reg] &= mask; 442 chip->image[reg] |= value; 443 } else { 444 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 445 mb(); 446 tmp = (chip->image[reg] & mask) | value; 447 __cs4231_writeb(chip, tmp, CS4231P(chip, REG)); 448 chip->image[reg] = tmp; 449 mb(); 450 } 451 } 452 453 static void snd_cs4231_dout(cs4231_t *chip, unsigned char reg, unsigned char value) 454 { 455 int timeout; 456 457 for (timeout = 250; 458 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 459 timeout--) 460 udelay(100); 461 #ifdef CONFIG_SND_DEBUG 462 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 463 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 464 #endif 465 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 466 __cs4231_writeb(chip, value, CS4231P(chip, REG)); 467 mb(); 468 } 469 470 static void snd_cs4231_out(cs4231_t *chip, unsigned char reg, unsigned char value) 471 { 472 int timeout; 473 474 for (timeout = 250; 475 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 476 timeout--) 477 udelay(100); 478 #ifdef CONFIG_SND_DEBUG 479 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 480 snd_printdd("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value); 481 #endif 482 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 483 __cs4231_writeb(chip, value, CS4231P(chip, REG)); 484 chip->image[reg] = value; 485 mb(); 486 } 487 488 static unsigned char snd_cs4231_in(cs4231_t *chip, unsigned char reg) 489 { 490 int timeout; 491 unsigned char ret; 492 493 for (timeout = 250; 494 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 495 timeout--) 496 udelay(100); 497 #ifdef CONFIG_SND_DEBUG 498 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 499 snd_printdd("in: auto calibration time out - reg = 0x%x\n", reg); 500 #endif 501 __cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL)); 502 mb(); 503 ret = __cs4231_readb(chip, CS4231P(chip, REG)); 504 return ret; 505 } 506 507 /* 508 * CS4231 detection / MCE routines 509 */ 510 511 static void snd_cs4231_busy_wait(cs4231_t *chip) 512 { 513 int timeout; 514 515 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */ 516 for (timeout = 5; timeout > 0; timeout--) 517 __cs4231_readb(chip, CS4231P(chip, REGSEL)); 518 519 /* end of cleanup sequence */ 520 for (timeout = 500; 521 timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); 522 timeout--) 523 udelay(1000); 524 } 525 526 static void snd_cs4231_mce_up(cs4231_t *chip) 527 { 528 unsigned long flags; 529 int timeout; 530 531 spin_lock_irqsave(&chip->lock, flags); 532 for (timeout = 250; timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT); timeout--) 533 udelay(100); 534 #ifdef CONFIG_SND_DEBUG 535 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 536 snd_printdd("mce_up - auto calibration time out (0)\n"); 537 #endif 538 chip->mce_bit |= CS4231_MCE; 539 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); 540 if (timeout == 0x80) 541 snd_printdd("mce_up [%p]: serious init problem - codec still busy\n", chip->port); 542 if (!(timeout & CS4231_MCE)) 543 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); 544 spin_unlock_irqrestore(&chip->lock, flags); 545 } 546 547 static void snd_cs4231_mce_down(cs4231_t *chip) 548 { 549 unsigned long flags; 550 int timeout; 551 552 spin_lock_irqsave(&chip->lock, flags); 553 snd_cs4231_busy_wait(chip); 554 #ifdef CONFIG_SND_DEBUG 555 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 556 snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL)); 557 #endif 558 chip->mce_bit &= ~CS4231_MCE; 559 timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL)); 560 __cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL)); 561 if (timeout == 0x80) 562 snd_printdd("mce_down [%p]: serious init problem - codec still busy\n", chip->port); 563 if ((timeout & CS4231_MCE) == 0) { 564 spin_unlock_irqrestore(&chip->lock, flags); 565 return; 566 } 567 snd_cs4231_busy_wait(chip); 568 569 /* calibration process */ 570 571 for (timeout = 500; timeout > 0 && (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0; timeout--) 572 udelay(100); 573 if ((snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) == 0) { 574 snd_printd("cs4231_mce_down - auto calibration time out (1)\n"); 575 spin_unlock_irqrestore(&chip->lock, flags); 576 return; 577 } 578 579 /* in 10ms increments, check condition, up to 250ms */ 580 timeout = 25; 581 while (snd_cs4231_in(chip, CS4231_TEST_INIT) & CS4231_CALIB_IN_PROGRESS) { 582 spin_unlock_irqrestore(&chip->lock, flags); 583 if (--timeout < 0) { 584 snd_printk("mce_down - auto calibration time out (2)\n"); 585 return; 586 } 587 msleep(10); 588 spin_lock_irqsave(&chip->lock, flags); 589 } 590 591 /* in 10ms increments, check condition, up to 100ms */ 592 timeout = 10; 593 while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) { 594 spin_unlock_irqrestore(&chip->lock, flags); 595 if (--timeout < 0) { 596 snd_printk("mce_down - auto calibration time out (3)\n"); 597 return; 598 } 599 msleep(10); 600 spin_lock_irqsave(&chip->lock, flags); 601 } 602 spin_unlock_irqrestore(&chip->lock, flags); 603 } 604 605 static void snd_cs4231_advance_dma(struct cs4231_dma_control *dma_cont, snd_pcm_substream_t *substream, unsigned int *periods_sent) 606 { 607 snd_pcm_runtime_t *runtime = substream->runtime; 608 609 while (1) { 610 unsigned int period_size = snd_pcm_lib_period_bytes(substream); 611 unsigned int offset = period_size * (*periods_sent); 612 613 if (period_size >= (1 << 24)) 614 BUG(); 615 616 if (dma_cont->request(dma_cont, runtime->dma_addr + offset, period_size)) 617 return; 618 (*periods_sent) = ((*periods_sent) + 1) % runtime->periods; 619 } 620 } 621 622 static void cs4231_dma_trigger(snd_pcm_substream_t *substream, unsigned int what, int on) 623 { 624 cs4231_t *chip = snd_pcm_substream_chip(substream); 625 cs4231_dma_control_t *dma_cont; 626 627 if (what & CS4231_PLAYBACK_ENABLE) { 628 dma_cont = &chip->p_dma; 629 if (on) { 630 dma_cont->prepare(dma_cont, 0); 631 dma_cont->enable(dma_cont, 1); 632 snd_cs4231_advance_dma(dma_cont, 633 chip->playback_substream, 634 &chip->p_periods_sent); 635 } else { 636 dma_cont->enable(dma_cont, 0); 637 } 638 } 639 if (what & CS4231_RECORD_ENABLE) { 640 dma_cont = &chip->c_dma; 641 if (on) { 642 dma_cont->prepare(dma_cont, 1); 643 dma_cont->enable(dma_cont, 1); 644 snd_cs4231_advance_dma(dma_cont, 645 chip->capture_substream, 646 &chip->c_periods_sent); 647 } else { 648 dma_cont->enable(dma_cont, 0); 649 } 650 } 651 } 652 653 static int snd_cs4231_trigger(snd_pcm_substream_t *substream, int cmd) 654 { 655 cs4231_t *chip = snd_pcm_substream_chip(substream); 656 int result = 0; 657 658 switch (cmd) { 659 case SNDRV_PCM_TRIGGER_START: 660 case SNDRV_PCM_TRIGGER_STOP: 661 { 662 unsigned int what = 0; 663 snd_pcm_substream_t *s; 664 struct list_head *pos; 665 unsigned long flags; 666 667 snd_pcm_group_for_each(pos, substream) { 668 s = snd_pcm_group_substream_entry(pos); 669 if (s == chip->playback_substream) { 670 what |= CS4231_PLAYBACK_ENABLE; 671 snd_pcm_trigger_done(s, substream); 672 } else if (s == chip->capture_substream) { 673 what |= CS4231_RECORD_ENABLE; 674 snd_pcm_trigger_done(s, substream); 675 } 676 } 677 678 spin_lock_irqsave(&chip->lock, flags); 679 if (cmd == SNDRV_PCM_TRIGGER_START) { 680 cs4231_dma_trigger(substream, what, 1); 681 chip->image[CS4231_IFACE_CTRL] |= what; 682 } else { 683 cs4231_dma_trigger(substream, what, 0); 684 chip->image[CS4231_IFACE_CTRL] &= ~what; 685 } 686 snd_cs4231_out(chip, CS4231_IFACE_CTRL, 687 chip->image[CS4231_IFACE_CTRL]); 688 spin_unlock_irqrestore(&chip->lock, flags); 689 break; 690 } 691 default: 692 result = -EINVAL; 693 break; 694 } 695 696 return result; 697 } 698 699 /* 700 * CODEC I/O 701 */ 702 703 static unsigned char snd_cs4231_get_rate(unsigned int rate) 704 { 705 int i; 706 707 for (i = 0; i < 14; i++) 708 if (rate == rates[i]) 709 return freq_bits[i]; 710 // snd_BUG(); 711 return freq_bits[13]; 712 } 713 714 static unsigned char snd_cs4231_get_format(cs4231_t *chip, int format, int channels) 715 { 716 unsigned char rformat; 717 718 rformat = CS4231_LINEAR_8; 719 switch (format) { 720 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break; 721 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break; 722 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break; 723 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break; 724 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break; 725 } 726 if (channels > 1) 727 rformat |= CS4231_STEREO; 728 return rformat; 729 } 730 731 static void snd_cs4231_calibrate_mute(cs4231_t *chip, int mute) 732 { 733 unsigned long flags; 734 735 mute = mute ? 1 : 0; 736 spin_lock_irqsave(&chip->lock, flags); 737 if (chip->calibrate_mute == mute) { 738 spin_unlock_irqrestore(&chip->lock, flags); 739 return; 740 } 741 if (!mute) { 742 snd_cs4231_dout(chip, CS4231_LEFT_INPUT, 743 chip->image[CS4231_LEFT_INPUT]); 744 snd_cs4231_dout(chip, CS4231_RIGHT_INPUT, 745 chip->image[CS4231_RIGHT_INPUT]); 746 snd_cs4231_dout(chip, CS4231_LOOPBACK, 747 chip->image[CS4231_LOOPBACK]); 748 } 749 snd_cs4231_dout(chip, CS4231_AUX1_LEFT_INPUT, 750 mute ? 0x80 : chip->image[CS4231_AUX1_LEFT_INPUT]); 751 snd_cs4231_dout(chip, CS4231_AUX1_RIGHT_INPUT, 752 mute ? 0x80 : chip->image[CS4231_AUX1_RIGHT_INPUT]); 753 snd_cs4231_dout(chip, CS4231_AUX2_LEFT_INPUT, 754 mute ? 0x80 : chip->image[CS4231_AUX2_LEFT_INPUT]); 755 snd_cs4231_dout(chip, CS4231_AUX2_RIGHT_INPUT, 756 mute ? 0x80 : chip->image[CS4231_AUX2_RIGHT_INPUT]); 757 snd_cs4231_dout(chip, CS4231_LEFT_OUTPUT, 758 mute ? 0x80 : chip->image[CS4231_LEFT_OUTPUT]); 759 snd_cs4231_dout(chip, CS4231_RIGHT_OUTPUT, 760 mute ? 0x80 : chip->image[CS4231_RIGHT_OUTPUT]); 761 snd_cs4231_dout(chip, CS4231_LEFT_LINE_IN, 762 mute ? 0x80 : chip->image[CS4231_LEFT_LINE_IN]); 763 snd_cs4231_dout(chip, CS4231_RIGHT_LINE_IN, 764 mute ? 0x80 : chip->image[CS4231_RIGHT_LINE_IN]); 765 snd_cs4231_dout(chip, CS4231_MONO_CTRL, 766 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]); 767 chip->calibrate_mute = mute; 768 spin_unlock_irqrestore(&chip->lock, flags); 769 } 770 771 static void snd_cs4231_playback_format(cs4231_t *chip, snd_pcm_hw_params_t *params, 772 unsigned char pdfr) 773 { 774 unsigned long flags; 775 776 down(&chip->mce_mutex); 777 snd_cs4231_calibrate_mute(chip, 1); 778 779 snd_cs4231_mce_up(chip); 780 781 spin_lock_irqsave(&chip->lock, flags); 782 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 783 (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) ? 784 (pdfr & 0xf0) | (chip->image[CS4231_REC_FORMAT] & 0x0f) : 785 pdfr); 786 spin_unlock_irqrestore(&chip->lock, flags); 787 788 snd_cs4231_mce_down(chip); 789 790 snd_cs4231_calibrate_mute(chip, 0); 791 up(&chip->mce_mutex); 792 } 793 794 static void snd_cs4231_capture_format(cs4231_t *chip, snd_pcm_hw_params_t *params, 795 unsigned char cdfr) 796 { 797 unsigned long flags; 798 799 down(&chip->mce_mutex); 800 snd_cs4231_calibrate_mute(chip, 1); 801 802 snd_cs4231_mce_up(chip); 803 804 spin_lock_irqsave(&chip->lock, flags); 805 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) { 806 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, 807 ((chip->image[CS4231_PLAYBK_FORMAT]) & 0xf0) | 808 (cdfr & 0x0f)); 809 spin_unlock_irqrestore(&chip->lock, flags); 810 snd_cs4231_mce_down(chip); 811 snd_cs4231_mce_up(chip); 812 spin_lock_irqsave(&chip->lock, flags); 813 } 814 snd_cs4231_out(chip, CS4231_REC_FORMAT, cdfr); 815 spin_unlock_irqrestore(&chip->lock, flags); 816 817 snd_cs4231_mce_down(chip); 818 819 snd_cs4231_calibrate_mute(chip, 0); 820 up(&chip->mce_mutex); 821 } 822 823 /* 824 * Timer interface 825 */ 826 827 static unsigned long snd_cs4231_timer_resolution(snd_timer_t *timer) 828 { 829 cs4231_t *chip = snd_timer_chip(timer); 830 831 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920; 832 } 833 834 static int snd_cs4231_timer_start(snd_timer_t *timer) 835 { 836 unsigned long flags; 837 unsigned int ticks; 838 cs4231_t *chip = snd_timer_chip(timer); 839 840 spin_lock_irqsave(&chip->lock, flags); 841 ticks = timer->sticks; 842 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 || 843 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] || 844 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) { 845 snd_cs4231_out(chip, CS4231_TIMER_HIGH, 846 chip->image[CS4231_TIMER_HIGH] = 847 (unsigned char) (ticks >> 8)); 848 snd_cs4231_out(chip, CS4231_TIMER_LOW, 849 chip->image[CS4231_TIMER_LOW] = 850 (unsigned char) ticks); 851 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 852 chip->image[CS4231_ALT_FEATURE_1] | CS4231_TIMER_ENABLE); 853 } 854 spin_unlock_irqrestore(&chip->lock, flags); 855 856 return 0; 857 } 858 859 static int snd_cs4231_timer_stop(snd_timer_t *timer) 860 { 861 unsigned long flags; 862 cs4231_t *chip = snd_timer_chip(timer); 863 864 spin_lock_irqsave(&chip->lock, flags); 865 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, 866 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE); 867 spin_unlock_irqrestore(&chip->lock, flags); 868 869 return 0; 870 } 871 872 static void snd_cs4231_init(cs4231_t *chip) 873 { 874 unsigned long flags; 875 876 snd_cs4231_mce_down(chip); 877 878 #ifdef SNDRV_DEBUG_MCE 879 snd_printdd("init: (1)\n"); 880 #endif 881 snd_cs4231_mce_up(chip); 882 spin_lock_irqsave(&chip->lock, flags); 883 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 884 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO | 885 CS4231_CALIB_MODE); 886 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB; 887 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 888 spin_unlock_irqrestore(&chip->lock, flags); 889 snd_cs4231_mce_down(chip); 890 891 #ifdef SNDRV_DEBUG_MCE 892 snd_printdd("init: (2)\n"); 893 #endif 894 895 snd_cs4231_mce_up(chip); 896 spin_lock_irqsave(&chip->lock, flags); 897 snd_cs4231_out(chip, CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]); 898 spin_unlock_irqrestore(&chip->lock, flags); 899 snd_cs4231_mce_down(chip); 900 901 #ifdef SNDRV_DEBUG_MCE 902 snd_printdd("init: (3) - afei = 0x%x\n", chip->image[CS4231_ALT_FEATURE_1]); 903 #endif 904 905 spin_lock_irqsave(&chip->lock, flags); 906 snd_cs4231_out(chip, CS4231_ALT_FEATURE_2, chip->image[CS4231_ALT_FEATURE_2]); 907 spin_unlock_irqrestore(&chip->lock, flags); 908 909 snd_cs4231_mce_up(chip); 910 spin_lock_irqsave(&chip->lock, flags); 911 snd_cs4231_out(chip, CS4231_PLAYBK_FORMAT, chip->image[CS4231_PLAYBK_FORMAT]); 912 spin_unlock_irqrestore(&chip->lock, flags); 913 snd_cs4231_mce_down(chip); 914 915 #ifdef SNDRV_DEBUG_MCE 916 snd_printdd("init: (4)\n"); 917 #endif 918 919 snd_cs4231_mce_up(chip); 920 spin_lock_irqsave(&chip->lock, flags); 921 snd_cs4231_out(chip, CS4231_REC_FORMAT, chip->image[CS4231_REC_FORMAT]); 922 spin_unlock_irqrestore(&chip->lock, flags); 923 snd_cs4231_mce_down(chip); 924 925 #ifdef SNDRV_DEBUG_MCE 926 snd_printdd("init: (5)\n"); 927 #endif 928 } 929 930 static int snd_cs4231_open(cs4231_t *chip, unsigned int mode) 931 { 932 unsigned long flags; 933 934 down(&chip->open_mutex); 935 if ((chip->mode & mode)) { 936 up(&chip->open_mutex); 937 return -EAGAIN; 938 } 939 if (chip->mode & CS4231_MODE_OPEN) { 940 chip->mode |= mode; 941 up(&chip->open_mutex); 942 return 0; 943 } 944 /* ok. now enable and ack CODEC IRQ */ 945 spin_lock_irqsave(&chip->lock, flags); 946 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 947 CS4231_RECORD_IRQ | 948 CS4231_TIMER_IRQ); 949 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 950 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 951 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 952 953 snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ | 954 CS4231_RECORD_IRQ | 955 CS4231_TIMER_IRQ); 956 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 957 958 spin_unlock_irqrestore(&chip->lock, flags); 959 960 chip->mode = mode; 961 up(&chip->open_mutex); 962 return 0; 963 } 964 965 static void snd_cs4231_close(cs4231_t *chip, unsigned int mode) 966 { 967 unsigned long flags; 968 969 down(&chip->open_mutex); 970 chip->mode &= ~mode; 971 if (chip->mode & CS4231_MODE_OPEN) { 972 up(&chip->open_mutex); 973 return; 974 } 975 snd_cs4231_calibrate_mute(chip, 1); 976 977 /* disable IRQ */ 978 spin_lock_irqsave(&chip->lock, flags); 979 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 980 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 981 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 982 983 /* now disable record & playback */ 984 985 if (chip->image[CS4231_IFACE_CTRL] & 986 (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 987 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) { 988 spin_unlock_irqrestore(&chip->lock, flags); 989 snd_cs4231_mce_up(chip); 990 spin_lock_irqsave(&chip->lock, flags); 991 chip->image[CS4231_IFACE_CTRL] &= 992 ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO | 993 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO); 994 snd_cs4231_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]); 995 spin_unlock_irqrestore(&chip->lock, flags); 996 snd_cs4231_mce_down(chip); 997 spin_lock_irqsave(&chip->lock, flags); 998 } 999 1000 /* clear IRQ again */ 1001 snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0); 1002 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 1003 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */ 1004 spin_unlock_irqrestore(&chip->lock, flags); 1005 1006 snd_cs4231_calibrate_mute(chip, 0); 1007 1008 chip->mode = 0; 1009 up(&chip->open_mutex); 1010 } 1011 1012 /* 1013 * timer open/close 1014 */ 1015 1016 static int snd_cs4231_timer_open(snd_timer_t *timer) 1017 { 1018 cs4231_t *chip = snd_timer_chip(timer); 1019 snd_cs4231_open(chip, CS4231_MODE_TIMER); 1020 return 0; 1021 } 1022 1023 static int snd_cs4231_timer_close(snd_timer_t * timer) 1024 { 1025 cs4231_t *chip = snd_timer_chip(timer); 1026 snd_cs4231_close(chip, CS4231_MODE_TIMER); 1027 return 0; 1028 } 1029 1030 static struct _snd_timer_hardware snd_cs4231_timer_table = 1031 { 1032 .flags = SNDRV_TIMER_HW_AUTO, 1033 .resolution = 9945, 1034 .ticks = 65535, 1035 .open = snd_cs4231_timer_open, 1036 .close = snd_cs4231_timer_close, 1037 .c_resolution = snd_cs4231_timer_resolution, 1038 .start = snd_cs4231_timer_start, 1039 .stop = snd_cs4231_timer_stop, 1040 }; 1041 1042 /* 1043 * ok.. exported functions.. 1044 */ 1045 1046 static int snd_cs4231_playback_hw_params(snd_pcm_substream_t *substream, 1047 snd_pcm_hw_params_t *hw_params) 1048 { 1049 cs4231_t *chip = snd_pcm_substream_chip(substream); 1050 unsigned char new_pdfr; 1051 int err; 1052 1053 if ((err = snd_pcm_lib_malloc_pages(substream, 1054 params_buffer_bytes(hw_params))) < 0) 1055 return err; 1056 new_pdfr = snd_cs4231_get_format(chip, params_format(hw_params), 1057 params_channels(hw_params)) | 1058 snd_cs4231_get_rate(params_rate(hw_params)); 1059 snd_cs4231_playback_format(chip, hw_params, new_pdfr); 1060 1061 return 0; 1062 } 1063 1064 static int snd_cs4231_playback_hw_free(snd_pcm_substream_t *substream) 1065 { 1066 return snd_pcm_lib_free_pages(substream); 1067 } 1068 1069 static int snd_cs4231_playback_prepare(snd_pcm_substream_t *substream) 1070 { 1071 cs4231_t *chip = snd_pcm_substream_chip(substream); 1072 snd_pcm_runtime_t *runtime = substream->runtime; 1073 unsigned long flags; 1074 1075 spin_lock_irqsave(&chip->lock, flags); 1076 1077 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | 1078 CS4231_PLAYBACK_PIO); 1079 1080 if (runtime->period_size > 0xffff + 1) 1081 BUG(); 1082 1083 chip->p_periods_sent = 0; 1084 spin_unlock_irqrestore(&chip->lock, flags); 1085 1086 return 0; 1087 } 1088 1089 static int snd_cs4231_capture_hw_params(snd_pcm_substream_t *substream, 1090 snd_pcm_hw_params_t *hw_params) 1091 { 1092 cs4231_t *chip = snd_pcm_substream_chip(substream); 1093 unsigned char new_cdfr; 1094 int err; 1095 1096 if ((err = snd_pcm_lib_malloc_pages(substream, 1097 params_buffer_bytes(hw_params))) < 0) 1098 return err; 1099 new_cdfr = snd_cs4231_get_format(chip, params_format(hw_params), 1100 params_channels(hw_params)) | 1101 snd_cs4231_get_rate(params_rate(hw_params)); 1102 snd_cs4231_capture_format(chip, hw_params, new_cdfr); 1103 1104 return 0; 1105 } 1106 1107 static int snd_cs4231_capture_hw_free(snd_pcm_substream_t *substream) 1108 { 1109 return snd_pcm_lib_free_pages(substream); 1110 } 1111 1112 static int snd_cs4231_capture_prepare(snd_pcm_substream_t *substream) 1113 { 1114 cs4231_t *chip = snd_pcm_substream_chip(substream); 1115 unsigned long flags; 1116 1117 spin_lock_irqsave(&chip->lock, flags); 1118 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | 1119 CS4231_RECORD_PIO); 1120 1121 1122 chip->c_periods_sent = 0; 1123 spin_unlock_irqrestore(&chip->lock, flags); 1124 1125 return 0; 1126 } 1127 1128 static void snd_cs4231_overrange(cs4231_t *chip) 1129 { 1130 unsigned long flags; 1131 unsigned char res; 1132 1133 spin_lock_irqsave(&chip->lock, flags); 1134 res = snd_cs4231_in(chip, CS4231_TEST_INIT); 1135 spin_unlock_irqrestore(&chip->lock, flags); 1136 1137 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */ 1138 chip->capture_substream->runtime->overrange++; 1139 } 1140 1141 static void snd_cs4231_play_callback(cs4231_t *cookie) 1142 { 1143 cs4231_t *chip = cookie; 1144 1145 if (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE) { 1146 snd_pcm_period_elapsed(chip->playback_substream); 1147 snd_cs4231_advance_dma(&chip->p_dma, chip->playback_substream, 1148 &chip->p_periods_sent); 1149 } 1150 } 1151 1152 static void snd_cs4231_capture_callback(cs4231_t *cookie) 1153 { 1154 cs4231_t *chip = cookie; 1155 1156 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE) { 1157 snd_pcm_period_elapsed(chip->capture_substream); 1158 snd_cs4231_advance_dma(&chip->c_dma, chip->capture_substream, 1159 &chip->c_periods_sent); 1160 } 1161 } 1162 1163 static snd_pcm_uframes_t snd_cs4231_playback_pointer(snd_pcm_substream_t *substream) 1164 { 1165 cs4231_t *chip = snd_pcm_substream_chip(substream); 1166 cs4231_dma_control_t *dma_cont = &chip->p_dma; 1167 size_t ptr; 1168 1169 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) 1170 return 0; 1171 ptr = dma_cont->address(dma_cont); 1172 if (ptr != 0) 1173 ptr -= substream->runtime->dma_addr; 1174 1175 return bytes_to_frames(substream->runtime, ptr); 1176 } 1177 1178 static snd_pcm_uframes_t snd_cs4231_capture_pointer(snd_pcm_substream_t * substream) 1179 { 1180 cs4231_t *chip = snd_pcm_substream_chip(substream); 1181 cs4231_dma_control_t *dma_cont = &chip->c_dma; 1182 size_t ptr; 1183 1184 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)) 1185 return 0; 1186 ptr = dma_cont->address(dma_cont); 1187 if (ptr != 0) 1188 ptr -= substream->runtime->dma_addr; 1189 1190 return bytes_to_frames(substream->runtime, ptr); 1191 } 1192 1193 /* 1194 1195 */ 1196 1197 static int snd_cs4231_probe(cs4231_t *chip) 1198 { 1199 unsigned long flags; 1200 int i, id, vers; 1201 unsigned char *ptr; 1202 1203 id = vers = 0; 1204 for (i = 0; i < 50; i++) { 1205 mb(); 1206 if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) 1207 udelay(2000); 1208 else { 1209 spin_lock_irqsave(&chip->lock, flags); 1210 snd_cs4231_out(chip, CS4231_MISC_INFO, CS4231_MODE2); 1211 id = snd_cs4231_in(chip, CS4231_MISC_INFO) & 0x0f; 1212 vers = snd_cs4231_in(chip, CS4231_VERSION); 1213 spin_unlock_irqrestore(&chip->lock, flags); 1214 if (id == 0x0a) 1215 break; /* this is valid value */ 1216 } 1217 } 1218 snd_printdd("cs4231: port = %p, id = 0x%x\n", chip->port, id); 1219 if (id != 0x0a) 1220 return -ENODEV; /* no valid device found */ 1221 1222 spin_lock_irqsave(&chip->lock, flags); 1223 1224 1225 /* Reset DMA engine (sbus only). */ 1226 chip->p_dma.reset(chip); 1227 1228 __cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */ 1229 __cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); 1230 mb(); 1231 1232 spin_unlock_irqrestore(&chip->lock, flags); 1233 1234 chip->image[CS4231_MISC_INFO] = CS4231_MODE2; 1235 chip->image[CS4231_IFACE_CTRL] = 1236 chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA; 1237 chip->image[CS4231_ALT_FEATURE_1] = 0x80; 1238 chip->image[CS4231_ALT_FEATURE_2] = 0x01; 1239 if (vers & 0x20) 1240 chip->image[CS4231_ALT_FEATURE_2] |= 0x02; 1241 1242 ptr = (unsigned char *) &chip->image; 1243 1244 snd_cs4231_mce_down(chip); 1245 1246 spin_lock_irqsave(&chip->lock, flags); 1247 1248 for (i = 0; i < 32; i++) /* ok.. fill all CS4231 registers */ 1249 snd_cs4231_out(chip, i, *ptr++); 1250 1251 spin_unlock_irqrestore(&chip->lock, flags); 1252 1253 snd_cs4231_mce_up(chip); 1254 1255 snd_cs4231_mce_down(chip); 1256 1257 mdelay(2); 1258 1259 return 0; /* all things are ok.. */ 1260 } 1261 1262 static snd_pcm_hardware_t snd_cs4231_playback = 1263 { 1264 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1265 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1266 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | 1267 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1268 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | 1269 SNDRV_PCM_FMTBIT_S16_BE), 1270 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1271 .rate_min = 5510, 1272 .rate_max = 48000, 1273 .channels_min = 1, 1274 .channels_max = 2, 1275 .buffer_bytes_max = (32*1024), 1276 .period_bytes_min = 4096, 1277 .period_bytes_max = (32*1024), 1278 .periods_min = 1, 1279 .periods_max = 1024, 1280 }; 1281 1282 static snd_pcm_hardware_t snd_cs4231_capture = 1283 { 1284 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1285 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START), 1286 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | 1287 SNDRV_PCM_FMTBIT_IMA_ADPCM | 1288 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | 1289 SNDRV_PCM_FMTBIT_S16_BE), 1290 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000, 1291 .rate_min = 5510, 1292 .rate_max = 48000, 1293 .channels_min = 1, 1294 .channels_max = 2, 1295 .buffer_bytes_max = (32*1024), 1296 .period_bytes_min = 4096, 1297 .period_bytes_max = (32*1024), 1298 .periods_min = 1, 1299 .periods_max = 1024, 1300 }; 1301 1302 static int snd_cs4231_playback_open(snd_pcm_substream_t *substream) 1303 { 1304 cs4231_t *chip = snd_pcm_substream_chip(substream); 1305 snd_pcm_runtime_t *runtime = substream->runtime; 1306 int err; 1307 1308 runtime->hw = snd_cs4231_playback; 1309 1310 if ((err = snd_cs4231_open(chip, CS4231_MODE_PLAY)) < 0) { 1311 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1312 return err; 1313 } 1314 chip->playback_substream = substream; 1315 chip->p_periods_sent = 0; 1316 snd_pcm_set_sync(substream); 1317 snd_cs4231_xrate(runtime); 1318 1319 return 0; 1320 } 1321 1322 static int snd_cs4231_capture_open(snd_pcm_substream_t *substream) 1323 { 1324 cs4231_t *chip = snd_pcm_substream_chip(substream); 1325 snd_pcm_runtime_t *runtime = substream->runtime; 1326 int err; 1327 1328 runtime->hw = snd_cs4231_capture; 1329 1330 if ((err = snd_cs4231_open(chip, CS4231_MODE_RECORD)) < 0) { 1331 snd_free_pages(runtime->dma_area, runtime->dma_bytes); 1332 return err; 1333 } 1334 chip->capture_substream = substream; 1335 chip->c_periods_sent = 0; 1336 snd_pcm_set_sync(substream); 1337 snd_cs4231_xrate(runtime); 1338 1339 return 0; 1340 } 1341 1342 static int snd_cs4231_playback_close(snd_pcm_substream_t *substream) 1343 { 1344 cs4231_t *chip = snd_pcm_substream_chip(substream); 1345 1346 snd_cs4231_close(chip, CS4231_MODE_PLAY); 1347 chip->playback_substream = NULL; 1348 1349 return 0; 1350 } 1351 1352 static int snd_cs4231_capture_close(snd_pcm_substream_t *substream) 1353 { 1354 cs4231_t *chip = snd_pcm_substream_chip(substream); 1355 1356 snd_cs4231_close(chip, CS4231_MODE_RECORD); 1357 chip->capture_substream = NULL; 1358 1359 return 0; 1360 } 1361 1362 /* XXX We can do some power-management, in particular on EBUS using 1363 * XXX the audio AUXIO register... 1364 */ 1365 1366 static snd_pcm_ops_t snd_cs4231_playback_ops = { 1367 .open = snd_cs4231_playback_open, 1368 .close = snd_cs4231_playback_close, 1369 .ioctl = snd_pcm_lib_ioctl, 1370 .hw_params = snd_cs4231_playback_hw_params, 1371 .hw_free = snd_cs4231_playback_hw_free, 1372 .prepare = snd_cs4231_playback_prepare, 1373 .trigger = snd_cs4231_trigger, 1374 .pointer = snd_cs4231_playback_pointer, 1375 }; 1376 1377 static snd_pcm_ops_t snd_cs4231_capture_ops = { 1378 .open = snd_cs4231_capture_open, 1379 .close = snd_cs4231_capture_close, 1380 .ioctl = snd_pcm_lib_ioctl, 1381 .hw_params = snd_cs4231_capture_hw_params, 1382 .hw_free = snd_cs4231_capture_hw_free, 1383 .prepare = snd_cs4231_capture_prepare, 1384 .trigger = snd_cs4231_trigger, 1385 .pointer = snd_cs4231_capture_pointer, 1386 }; 1387 1388 static void snd_cs4231_pcm_free(snd_pcm_t *pcm) 1389 { 1390 cs4231_t *chip = pcm->private_data; 1391 chip->pcm = NULL; 1392 snd_pcm_lib_preallocate_free_for_all(pcm); 1393 } 1394 1395 int snd_cs4231_pcm(cs4231_t *chip) 1396 { 1397 snd_pcm_t *pcm; 1398 int err; 1399 1400 if ((err = snd_pcm_new(chip->card, "CS4231", 0, 1, 1, &pcm)) < 0) 1401 return err; 1402 1403 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs4231_playback_ops); 1404 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs4231_capture_ops); 1405 1406 /* global setup */ 1407 pcm->private_data = chip; 1408 pcm->private_free = snd_cs4231_pcm_free; 1409 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1410 strcpy(pcm->name, "CS4231"); 1411 1412 chip->p_dma.preallocate(chip, pcm); 1413 1414 chip->pcm = pcm; 1415 1416 return 0; 1417 } 1418 1419 static void snd_cs4231_timer_free(snd_timer_t *timer) 1420 { 1421 cs4231_t *chip = timer->private_data; 1422 chip->timer = NULL; 1423 } 1424 1425 int snd_cs4231_timer(cs4231_t *chip) 1426 { 1427 snd_timer_t *timer; 1428 snd_timer_id_t tid; 1429 int err; 1430 1431 /* Timer initialization */ 1432 tid.dev_class = SNDRV_TIMER_CLASS_CARD; 1433 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE; 1434 tid.card = chip->card->number; 1435 tid.device = 0; 1436 tid.subdevice = 0; 1437 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0) 1438 return err; 1439 strcpy(timer->name, "CS4231"); 1440 timer->private_data = chip; 1441 timer->private_free = snd_cs4231_timer_free; 1442 timer->hw = snd_cs4231_timer_table; 1443 chip->timer = timer; 1444 1445 return 0; 1446 } 1447 1448 /* 1449 * MIXER part 1450 */ 1451 1452 static int snd_cs4231_info_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1453 { 1454 static char *texts[4] = { 1455 "Line", "CD", "Mic", "Mix" 1456 }; 1457 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1458 1459 snd_assert(chip->card != NULL, return -EINVAL); 1460 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1461 uinfo->count = 2; 1462 uinfo->value.enumerated.items = 4; 1463 if (uinfo->value.enumerated.item > 3) 1464 uinfo->value.enumerated.item = 3; 1465 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1466 1467 return 0; 1468 } 1469 1470 static int snd_cs4231_get_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1471 { 1472 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1473 unsigned long flags; 1474 1475 spin_lock_irqsave(&chip->lock, flags); 1476 ucontrol->value.enumerated.item[0] = 1477 (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6; 1478 ucontrol->value.enumerated.item[1] = 1479 (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6; 1480 spin_unlock_irqrestore(&chip->lock, flags); 1481 1482 return 0; 1483 } 1484 1485 static int snd_cs4231_put_mux(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1486 { 1487 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1488 unsigned long flags; 1489 unsigned short left, right; 1490 int change; 1491 1492 if (ucontrol->value.enumerated.item[0] > 3 || 1493 ucontrol->value.enumerated.item[1] > 3) 1494 return -EINVAL; 1495 left = ucontrol->value.enumerated.item[0] << 6; 1496 right = ucontrol->value.enumerated.item[1] << 6; 1497 1498 spin_lock_irqsave(&chip->lock, flags); 1499 1500 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left; 1501 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right; 1502 change = left != chip->image[CS4231_LEFT_INPUT] || 1503 right != chip->image[CS4231_RIGHT_INPUT]; 1504 snd_cs4231_out(chip, CS4231_LEFT_INPUT, left); 1505 snd_cs4231_out(chip, CS4231_RIGHT_INPUT, right); 1506 1507 spin_unlock_irqrestore(&chip->lock, flags); 1508 1509 return change; 1510 } 1511 1512 int snd_cs4231_info_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1513 { 1514 int mask = (kcontrol->private_value >> 16) & 0xff; 1515 1516 uinfo->type = (mask == 1) ? 1517 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1518 uinfo->count = 1; 1519 uinfo->value.integer.min = 0; 1520 uinfo->value.integer.max = mask; 1521 1522 return 0; 1523 } 1524 1525 int snd_cs4231_get_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1526 { 1527 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1528 unsigned long flags; 1529 int reg = kcontrol->private_value & 0xff; 1530 int shift = (kcontrol->private_value >> 8) & 0xff; 1531 int mask = (kcontrol->private_value >> 16) & 0xff; 1532 int invert = (kcontrol->private_value >> 24) & 0xff; 1533 1534 spin_lock_irqsave(&chip->lock, flags); 1535 1536 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask; 1537 1538 spin_unlock_irqrestore(&chip->lock, flags); 1539 1540 if (invert) 1541 ucontrol->value.integer.value[0] = 1542 (mask - ucontrol->value.integer.value[0]); 1543 1544 return 0; 1545 } 1546 1547 int snd_cs4231_put_single(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1548 { 1549 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1550 unsigned long flags; 1551 int reg = kcontrol->private_value & 0xff; 1552 int shift = (kcontrol->private_value >> 8) & 0xff; 1553 int mask = (kcontrol->private_value >> 16) & 0xff; 1554 int invert = (kcontrol->private_value >> 24) & 0xff; 1555 int change; 1556 unsigned short val; 1557 1558 val = (ucontrol->value.integer.value[0] & mask); 1559 if (invert) 1560 val = mask - val; 1561 val <<= shift; 1562 1563 spin_lock_irqsave(&chip->lock, flags); 1564 1565 val = (chip->image[reg] & ~(mask << shift)) | val; 1566 change = val != chip->image[reg]; 1567 snd_cs4231_out(chip, reg, val); 1568 1569 spin_unlock_irqrestore(&chip->lock, flags); 1570 1571 return change; 1572 } 1573 1574 int snd_cs4231_info_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_info_t *uinfo) 1575 { 1576 int mask = (kcontrol->private_value >> 24) & 0xff; 1577 1578 uinfo->type = mask == 1 ? 1579 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER; 1580 uinfo->count = 2; 1581 uinfo->value.integer.min = 0; 1582 uinfo->value.integer.max = mask; 1583 1584 return 0; 1585 } 1586 1587 int snd_cs4231_get_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1588 { 1589 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1590 unsigned long flags; 1591 int left_reg = kcontrol->private_value & 0xff; 1592 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1593 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1594 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1595 int mask = (kcontrol->private_value >> 24) & 0xff; 1596 int invert = (kcontrol->private_value >> 22) & 1; 1597 1598 spin_lock_irqsave(&chip->lock, flags); 1599 1600 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask; 1601 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask; 1602 1603 spin_unlock_irqrestore(&chip->lock, flags); 1604 1605 if (invert) { 1606 ucontrol->value.integer.value[0] = 1607 (mask - ucontrol->value.integer.value[0]); 1608 ucontrol->value.integer.value[1] = 1609 (mask - ucontrol->value.integer.value[1]); 1610 } 1611 1612 return 0; 1613 } 1614 1615 int snd_cs4231_put_double(snd_kcontrol_t *kcontrol, snd_ctl_elem_value_t *ucontrol) 1616 { 1617 cs4231_t *chip = snd_kcontrol_chip(kcontrol); 1618 unsigned long flags; 1619 int left_reg = kcontrol->private_value & 0xff; 1620 int right_reg = (kcontrol->private_value >> 8) & 0xff; 1621 int shift_left = (kcontrol->private_value >> 16) & 0x07; 1622 int shift_right = (kcontrol->private_value >> 19) & 0x07; 1623 int mask = (kcontrol->private_value >> 24) & 0xff; 1624 int invert = (kcontrol->private_value >> 22) & 1; 1625 int change; 1626 unsigned short val1, val2; 1627 1628 val1 = ucontrol->value.integer.value[0] & mask; 1629 val2 = ucontrol->value.integer.value[1] & mask; 1630 if (invert) { 1631 val1 = mask - val1; 1632 val2 = mask - val2; 1633 } 1634 val1 <<= shift_left; 1635 val2 <<= shift_right; 1636 1637 spin_lock_irqsave(&chip->lock, flags); 1638 1639 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1; 1640 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2; 1641 change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg]; 1642 snd_cs4231_out(chip, left_reg, val1); 1643 snd_cs4231_out(chip, right_reg, val2); 1644 1645 spin_unlock_irqrestore(&chip->lock, flags); 1646 1647 return change; 1648 } 1649 1650 #define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \ 1651 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1652 .info = snd_cs4231_info_single, \ 1653 .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \ 1654 .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } 1655 1656 #define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ 1657 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1658 .info = snd_cs4231_info_double, \ 1659 .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \ 1660 .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) } 1661 1662 static snd_kcontrol_new_t snd_cs4231_controls[] = { 1663 CS4231_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1), 1664 CS4231_DOUBLE("PCM Playback Volume", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1), 1665 CS4231_DOUBLE("Line Playback Switch", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1), 1666 CS4231_DOUBLE("Line Playback Volume", 0, CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1), 1667 CS4231_DOUBLE("Aux Playback Switch", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1), 1668 CS4231_DOUBLE("Aux Playback Volume", 0, CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1), 1669 CS4231_DOUBLE("Aux Playback Switch", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1), 1670 CS4231_DOUBLE("Aux Playback Volume", 1, CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1), 1671 CS4231_SINGLE("Mono Playback Switch", 0, CS4231_MONO_CTRL, 7, 1, 1), 1672 CS4231_SINGLE("Mono Playback Volume", 0, CS4231_MONO_CTRL, 0, 15, 1), 1673 CS4231_SINGLE("Mono Output Playback Switch", 0, CS4231_MONO_CTRL, 6, 1, 1), 1674 CS4231_SINGLE("Mono Output Playback Bypass", 0, CS4231_MONO_CTRL, 5, 1, 0), 1675 CS4231_DOUBLE("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0), 1676 { 1677 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1678 .name = "Capture Source", 1679 .info = snd_cs4231_info_mux, 1680 .get = snd_cs4231_get_mux, 1681 .put = snd_cs4231_put_mux, 1682 }, 1683 CS4231_DOUBLE("Mic Boost", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0), 1684 CS4231_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0), 1685 CS4231_SINGLE("Loopback Capture Volume", 0, CS4231_LOOPBACK, 2, 63, 1), 1686 /* SPARC specific uses of XCTL{0,1} general purpose outputs. */ 1687 CS4231_SINGLE("Line Out Switch", 0, CS4231_PIN_CTRL, 6, 1, 1), 1688 CS4231_SINGLE("Headphone Out Switch", 0, CS4231_PIN_CTRL, 7, 1, 1) 1689 }; 1690 1691 int snd_cs4231_mixer(cs4231_t *chip) 1692 { 1693 snd_card_t *card; 1694 int err, idx; 1695 1696 snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL); 1697 1698 card = chip->card; 1699 1700 strcpy(card->mixername, chip->pcm->name); 1701 1702 for (idx = 0; idx < ARRAY_SIZE(snd_cs4231_controls); idx++) { 1703 if ((err = snd_ctl_add(card, 1704 snd_ctl_new1(&snd_cs4231_controls[idx], 1705 chip))) < 0) 1706 return err; 1707 } 1708 return 0; 1709 } 1710 1711 static int dev; 1712 1713 static int cs4231_attach_begin(snd_card_t **rcard) 1714 { 1715 snd_card_t *card; 1716 1717 *rcard = NULL; 1718 1719 if (dev >= SNDRV_CARDS) 1720 return -ENODEV; 1721 1722 if (!enable[dev]) { 1723 dev++; 1724 return -ENOENT; 1725 } 1726 1727 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 1728 if (card == NULL) 1729 return -ENOMEM; 1730 1731 strcpy(card->driver, "CS4231"); 1732 strcpy(card->shortname, "Sun CS4231"); 1733 1734 *rcard = card; 1735 return 0; 1736 } 1737 1738 static int cs4231_attach_finish(snd_card_t *card, cs4231_t *chip) 1739 { 1740 int err; 1741 1742 if ((err = snd_cs4231_pcm(chip)) < 0) 1743 goto out_err; 1744 1745 if ((err = snd_cs4231_mixer(chip)) < 0) 1746 goto out_err; 1747 1748 if ((err = snd_cs4231_timer(chip)) < 0) 1749 goto out_err; 1750 1751 if ((err = snd_card_set_generic_dev(card)) < 0) 1752 goto out_err; 1753 1754 if ((err = snd_card_register(card)) < 0) 1755 goto out_err; 1756 1757 chip->next = cs4231_list; 1758 cs4231_list = chip; 1759 1760 dev++; 1761 return 0; 1762 1763 out_err: 1764 snd_card_free(card); 1765 return err; 1766 } 1767 1768 #ifdef SBUS_SUPPORT 1769 1770 static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id, struct pt_regs *regs) 1771 { 1772 unsigned long flags; 1773 unsigned char status; 1774 u32 csr; 1775 cs4231_t *chip = dev_id; 1776 1777 /*This is IRQ is not raised by the cs4231*/ 1778 if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ)) 1779 return IRQ_NONE; 1780 1781 /* ACK the APC interrupt. */ 1782 csr = sbus_readl(chip->port + APCCSR); 1783 1784 sbus_writel(csr, chip->port + APCCSR); 1785 1786 if ((csr & APC_PDMA_READY) && 1787 (csr & APC_PLAY_INT) && 1788 (csr & APC_XINT_PNVA) && 1789 !(csr & APC_XINT_EMPT)) 1790 snd_cs4231_play_callback(chip); 1791 1792 if ((csr & APC_CDMA_READY) && 1793 (csr & APC_CAPT_INT) && 1794 (csr & APC_XINT_CNVA) && 1795 !(csr & APC_XINT_EMPT)) 1796 snd_cs4231_capture_callback(chip); 1797 1798 status = snd_cs4231_in(chip, CS4231_IRQ_STATUS); 1799 1800 if (status & CS4231_TIMER_IRQ) { 1801 if (chip->timer) 1802 snd_timer_interrupt(chip->timer, chip->timer->sticks); 1803 } 1804 1805 if ((status & CS4231_RECORD_IRQ) && (csr & APC_CDMA_READY)) 1806 snd_cs4231_overrange(chip); 1807 1808 /* ACK the CS4231 interrupt. */ 1809 spin_lock_irqsave(&chip->lock, flags); 1810 snd_cs4231_outm(chip, CS4231_IRQ_STATUS, ~CS4231_ALL_IRQS | ~status, 0); 1811 spin_unlock_irqrestore(&chip->lock, flags); 1812 1813 return 0; 1814 } 1815 1816 /* 1817 * SBUS DMA routines 1818 */ 1819 1820 int sbus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) 1821 { 1822 unsigned long flags; 1823 u32 test, csr; 1824 int err; 1825 sbus_dma_info_t *base = &dma_cont->sbus_info; 1826 1827 if (len >= (1 << 24)) 1828 return -EINVAL; 1829 spin_lock_irqsave(&base->lock, flags); 1830 csr = sbus_readl(base->regs + APCCSR); 1831 err = -EINVAL; 1832 test = APC_CDMA_READY; 1833 if ( base->dir == APC_PLAY ) 1834 test = APC_PDMA_READY; 1835 if (!(csr & test)) 1836 goto out; 1837 err = -EBUSY; 1838 csr = sbus_readl(base->regs + APCCSR); 1839 test = APC_XINT_CNVA; 1840 if ( base->dir == APC_PLAY ) 1841 test = APC_XINT_PNVA; 1842 if (!(csr & test)) 1843 goto out; 1844 err = 0; 1845 sbus_writel(bus_addr, base->regs + base->dir + APCNVA); 1846 sbus_writel(len, base->regs + base->dir + APCNC); 1847 out: 1848 spin_unlock_irqrestore(&base->lock, flags); 1849 return err; 1850 } 1851 1852 void sbus_dma_prepare(struct cs4231_dma_control *dma_cont, int d) 1853 { 1854 unsigned long flags; 1855 u32 csr, test; 1856 sbus_dma_info_t *base = &dma_cont->sbus_info; 1857 1858 spin_lock_irqsave(&base->lock, flags); 1859 csr = sbus_readl(base->regs + APCCSR); 1860 test = APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | 1861 APC_XINT_PLAY | APC_XINT_PEMP | APC_XINT_GENL | 1862 APC_XINT_PENA; 1863 if ( base->dir == APC_RECORD ) 1864 test = APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | 1865 APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL; 1866 csr |= test; 1867 sbus_writel(csr, base->regs + APCCSR); 1868 spin_unlock_irqrestore(&base->lock, flags); 1869 } 1870 1871 void sbus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 1872 { 1873 unsigned long flags; 1874 u32 csr, shift; 1875 sbus_dma_info_t *base = &dma_cont->sbus_info; 1876 1877 spin_lock_irqsave(&base->lock, flags); 1878 if (!on) { 1879 if (base->dir == APC_PLAY) { 1880 sbus_writel(0, base->regs + base->dir + APCNVA); 1881 sbus_writel(1, base->regs + base->dir + APCC); 1882 } 1883 else 1884 { 1885 sbus_writel(0, base->regs + base->dir + APCNC); 1886 sbus_writel(0, base->regs + base->dir + APCVA); 1887 } 1888 } 1889 udelay(600); 1890 csr = sbus_readl(base->regs + APCCSR); 1891 shift = 0; 1892 if ( base->dir == APC_PLAY ) 1893 shift = 1; 1894 if (on) 1895 csr &= ~(APC_CPAUSE << shift); 1896 else 1897 csr |= (APC_CPAUSE << shift); 1898 sbus_writel(csr, base->regs + APCCSR); 1899 if (on) 1900 csr |= (APC_CDMA_READY << shift); 1901 else 1902 csr &= ~(APC_CDMA_READY << shift); 1903 sbus_writel(csr, base->regs + APCCSR); 1904 1905 spin_unlock_irqrestore(&base->lock, flags); 1906 } 1907 1908 unsigned int sbus_dma_addr(struct cs4231_dma_control *dma_cont) 1909 { 1910 sbus_dma_info_t *base = &dma_cont->sbus_info; 1911 1912 return sbus_readl(base->regs + base->dir + APCVA); 1913 } 1914 1915 void sbus_dma_reset(cs4231_t *chip) 1916 { 1917 sbus_writel(APC_CHIP_RESET, chip->port + APCCSR); 1918 sbus_writel(0x00, chip->port + APCCSR); 1919 sbus_writel(sbus_readl(chip->port + APCCSR) | APC_CDC_RESET, 1920 chip->port + APCCSR); 1921 1922 udelay(20); 1923 1924 sbus_writel(sbus_readl(chip->port + APCCSR) & ~APC_CDC_RESET, 1925 chip->port + APCCSR); 1926 sbus_writel(sbus_readl(chip->port + APCCSR) | (APC_XINT_ENA | 1927 APC_XINT_PENA | 1928 APC_XINT_CENA), 1929 chip->port + APCCSR); 1930 } 1931 1932 void sbus_dma_preallocate(cs4231_t *chip, snd_pcm_t *pcm) 1933 { 1934 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_SBUS, 1935 snd_dma_sbus_data(chip->dev_u.sdev), 1936 64*1024, 128*1024); 1937 } 1938 1939 /* 1940 * Init and exit routines 1941 */ 1942 1943 static int snd_cs4231_sbus_free(cs4231_t *chip) 1944 { 1945 if (chip->irq[0]) 1946 free_irq(chip->irq[0], chip); 1947 1948 if (chip->port) 1949 sbus_iounmap(chip->port, chip->regs_size); 1950 1951 if (chip->timer) 1952 snd_device_free(chip->card, chip->timer); 1953 1954 kfree(chip); 1955 1956 return 0; 1957 } 1958 1959 static int snd_cs4231_sbus_dev_free(snd_device_t *device) 1960 { 1961 cs4231_t *cp = device->device_data; 1962 1963 return snd_cs4231_sbus_free(cp); 1964 } 1965 1966 static snd_device_ops_t snd_cs4231_sbus_dev_ops = { 1967 .dev_free = snd_cs4231_sbus_dev_free, 1968 }; 1969 1970 static int __init snd_cs4231_sbus_create(snd_card_t *card, 1971 struct sbus_dev *sdev, 1972 int dev, 1973 cs4231_t **rchip) 1974 { 1975 cs4231_t *chip; 1976 int err; 1977 1978 *rchip = NULL; 1979 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1980 if (chip == NULL) 1981 return -ENOMEM; 1982 1983 spin_lock_init(&chip->lock); 1984 spin_lock_init(&chip->c_dma.sbus_info.lock); 1985 spin_lock_init(&chip->p_dma.sbus_info.lock); 1986 init_MUTEX(&chip->mce_mutex); 1987 init_MUTEX(&chip->open_mutex); 1988 chip->card = card; 1989 chip->dev_u.sdev = sdev; 1990 chip->regs_size = sdev->reg_addrs[0].reg_size; 1991 memcpy(&chip->image, &snd_cs4231_original_image, 1992 sizeof(snd_cs4231_original_image)); 1993 1994 chip->port = sbus_ioremap(&sdev->resource[0], 0, 1995 chip->regs_size, "cs4231"); 1996 if (!chip->port) { 1997 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 1998 return -EIO; 1999 } 2000 2001 chip->c_dma.sbus_info.regs = chip->port; 2002 chip->p_dma.sbus_info.regs = chip->port; 2003 chip->c_dma.sbus_info.dir = APC_RECORD; 2004 chip->p_dma.sbus_info.dir = APC_PLAY; 2005 2006 chip->p_dma.prepare = sbus_dma_prepare; 2007 chip->p_dma.enable = sbus_dma_enable; 2008 chip->p_dma.request = sbus_dma_request; 2009 chip->p_dma.address = sbus_dma_addr; 2010 chip->p_dma.reset = sbus_dma_reset; 2011 chip->p_dma.preallocate = sbus_dma_preallocate; 2012 2013 chip->c_dma.prepare = sbus_dma_prepare; 2014 chip->c_dma.enable = sbus_dma_enable; 2015 chip->c_dma.request = sbus_dma_request; 2016 chip->c_dma.address = sbus_dma_addr; 2017 chip->c_dma.reset = sbus_dma_reset; 2018 chip->c_dma.preallocate = sbus_dma_preallocate; 2019 2020 if (request_irq(sdev->irqs[0], snd_cs4231_sbus_interrupt, 2021 SA_SHIRQ, "cs4231", chip)) { 2022 snd_printdd("cs4231-%d: Unable to grab SBUS IRQ %s\n", 2023 dev, 2024 __irq_itoa(sdev->irqs[0])); 2025 snd_cs4231_sbus_free(chip); 2026 return -EBUSY; 2027 } 2028 chip->irq[0] = sdev->irqs[0]; 2029 2030 if (snd_cs4231_probe(chip) < 0) { 2031 snd_cs4231_sbus_free(chip); 2032 return -ENODEV; 2033 } 2034 snd_cs4231_init(chip); 2035 2036 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 2037 chip, &snd_cs4231_sbus_dev_ops)) < 0) { 2038 snd_cs4231_sbus_free(chip); 2039 return err; 2040 } 2041 2042 *rchip = chip; 2043 return 0; 2044 } 2045 2046 static int cs4231_sbus_attach(struct sbus_dev *sdev) 2047 { 2048 struct resource *rp = &sdev->resource[0]; 2049 cs4231_t *cp; 2050 snd_card_t *card; 2051 int err; 2052 2053 err = cs4231_attach_begin(&card); 2054 if (err) 2055 return err; 2056 2057 sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %s", 2058 card->shortname, 2059 rp->flags & 0xffL, 2060 rp->start, 2061 __irq_itoa(sdev->irqs[0])); 2062 2063 if ((err = snd_cs4231_sbus_create(card, sdev, dev, &cp)) < 0) { 2064 snd_card_free(card); 2065 return err; 2066 } 2067 2068 return cs4231_attach_finish(card, cp); 2069 } 2070 #endif 2071 2072 #ifdef EBUS_SUPPORT 2073 2074 static void snd_cs4231_ebus_play_callback(struct ebus_dma_info *p, int event, void *cookie) 2075 { 2076 cs4231_t *chip = cookie; 2077 2078 snd_cs4231_play_callback(chip); 2079 } 2080 2081 static void snd_cs4231_ebus_capture_callback(struct ebus_dma_info *p, int event, void *cookie) 2082 { 2083 cs4231_t *chip = cookie; 2084 2085 snd_cs4231_capture_callback(chip); 2086 } 2087 2088 /* 2089 * EBUS DMA wrappers 2090 */ 2091 2092 int _ebus_dma_request(struct cs4231_dma_control *dma_cont, dma_addr_t bus_addr, size_t len) 2093 { 2094 return ebus_dma_request(&dma_cont->ebus_info, bus_addr, len); 2095 } 2096 2097 void _ebus_dma_enable(struct cs4231_dma_control *dma_cont, int on) 2098 { 2099 ebus_dma_enable(&dma_cont->ebus_info, on); 2100 } 2101 2102 void _ebus_dma_prepare(struct cs4231_dma_control *dma_cont, int dir) 2103 { 2104 ebus_dma_prepare(&dma_cont->ebus_info, dir); 2105 } 2106 2107 unsigned int _ebus_dma_addr(struct cs4231_dma_control *dma_cont) 2108 { 2109 return ebus_dma_addr(&dma_cont->ebus_info); 2110 } 2111 2112 void _ebus_dma_reset(cs4231_t *chip) 2113 { 2114 return; 2115 } 2116 2117 void _ebus_dma_preallocate(cs4231_t *chip, snd_pcm_t *pcm) 2118 { 2119 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 2120 snd_dma_pci_data(chip->dev_u.pdev), 2121 64*1024, 128*1024); 2122 } 2123 2124 /* 2125 * Init and exit routines 2126 */ 2127 2128 static int snd_cs4231_ebus_free(cs4231_t *chip) 2129 { 2130 if (chip->c_dma.ebus_info.regs) { 2131 ebus_dma_unregister(&chip->c_dma.ebus_info); 2132 iounmap(chip->c_dma.ebus_info.regs); 2133 } 2134 if (chip->p_dma.ebus_info.regs) { 2135 ebus_dma_unregister(&chip->p_dma.ebus_info); 2136 iounmap(chip->p_dma.ebus_info.regs); 2137 } 2138 2139 if (chip->port) 2140 iounmap(chip->port); 2141 if (chip->timer) 2142 snd_device_free(chip->card, chip->timer); 2143 2144 kfree(chip); 2145 2146 return 0; 2147 } 2148 2149 static int snd_cs4231_ebus_dev_free(snd_device_t *device) 2150 { 2151 cs4231_t *cp = device->device_data; 2152 2153 return snd_cs4231_ebus_free(cp); 2154 } 2155 2156 static snd_device_ops_t snd_cs4231_ebus_dev_ops = { 2157 .dev_free = snd_cs4231_ebus_dev_free, 2158 }; 2159 2160 static int __init snd_cs4231_ebus_create(snd_card_t *card, 2161 struct linux_ebus_device *edev, 2162 int dev, 2163 cs4231_t **rchip) 2164 { 2165 cs4231_t *chip; 2166 int err; 2167 2168 *rchip = NULL; 2169 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2170 if (chip == NULL) 2171 return -ENOMEM; 2172 2173 spin_lock_init(&chip->lock); 2174 spin_lock_init(&chip->c_dma.ebus_info.lock); 2175 spin_lock_init(&chip->p_dma.ebus_info.lock); 2176 init_MUTEX(&chip->mce_mutex); 2177 init_MUTEX(&chip->open_mutex); 2178 chip->flags |= CS4231_FLAG_EBUS; 2179 chip->card = card; 2180 chip->dev_u.pdev = edev->bus->self; 2181 memcpy(&chip->image, &snd_cs4231_original_image, 2182 sizeof(snd_cs4231_original_image)); 2183 strcpy(chip->c_dma.ebus_info.name, "cs4231(capture)"); 2184 chip->c_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 2185 chip->c_dma.ebus_info.callback = snd_cs4231_ebus_capture_callback; 2186 chip->c_dma.ebus_info.client_cookie = chip; 2187 chip->c_dma.ebus_info.irq = edev->irqs[0]; 2188 strcpy(chip->p_dma.ebus_info.name, "cs4231(play)"); 2189 chip->p_dma.ebus_info.flags = EBUS_DMA_FLAG_USE_EBDMA_HANDLER; 2190 chip->p_dma.ebus_info.callback = snd_cs4231_ebus_play_callback; 2191 chip->p_dma.ebus_info.client_cookie = chip; 2192 chip->p_dma.ebus_info.irq = edev->irqs[1]; 2193 2194 chip->p_dma.prepare = _ebus_dma_prepare; 2195 chip->p_dma.enable = _ebus_dma_enable; 2196 chip->p_dma.request = _ebus_dma_request; 2197 chip->p_dma.address = _ebus_dma_addr; 2198 chip->p_dma.reset = _ebus_dma_reset; 2199 chip->p_dma.preallocate = _ebus_dma_preallocate; 2200 2201 chip->c_dma.prepare = _ebus_dma_prepare; 2202 chip->c_dma.enable = _ebus_dma_enable; 2203 chip->c_dma.request = _ebus_dma_request; 2204 chip->c_dma.address = _ebus_dma_addr; 2205 chip->c_dma.reset = _ebus_dma_reset; 2206 chip->c_dma.preallocate = _ebus_dma_preallocate; 2207 2208 chip->port = ioremap(edev->resource[0].start, 0x10); 2209 chip->p_dma.ebus_info.regs = ioremap(edev->resource[1].start, 0x10); 2210 chip->c_dma.ebus_info.regs = ioremap(edev->resource[2].start, 0x10); 2211 if (!chip->port || !chip->p_dma.ebus_info.regs || !chip->c_dma.ebus_info.regs) { 2212 snd_cs4231_ebus_free(chip); 2213 snd_printdd("cs4231-%d: Unable to map chip registers.\n", dev); 2214 return -EIO; 2215 } 2216 2217 if (ebus_dma_register(&chip->c_dma.ebus_info)) { 2218 snd_cs4231_ebus_free(chip); 2219 snd_printdd("cs4231-%d: Unable to register EBUS capture DMA\n", dev); 2220 return -EBUSY; 2221 } 2222 if (ebus_dma_irq_enable(&chip->c_dma.ebus_info, 1)) { 2223 snd_cs4231_ebus_free(chip); 2224 snd_printdd("cs4231-%d: Unable to enable EBUS capture IRQ\n", dev); 2225 return -EBUSY; 2226 } 2227 2228 if (ebus_dma_register(&chip->p_dma.ebus_info)) { 2229 snd_cs4231_ebus_free(chip); 2230 snd_printdd("cs4231-%d: Unable to register EBUS play DMA\n", dev); 2231 return -EBUSY; 2232 } 2233 if (ebus_dma_irq_enable(&chip->p_dma.ebus_info, 1)) { 2234 snd_cs4231_ebus_free(chip); 2235 snd_printdd("cs4231-%d: Unable to enable EBUS play IRQ\n", dev); 2236 return -EBUSY; 2237 } 2238 2239 if (snd_cs4231_probe(chip) < 0) { 2240 snd_cs4231_ebus_free(chip); 2241 return -ENODEV; 2242 } 2243 snd_cs4231_init(chip); 2244 2245 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, 2246 chip, &snd_cs4231_ebus_dev_ops)) < 0) { 2247 snd_cs4231_ebus_free(chip); 2248 return err; 2249 } 2250 2251 *rchip = chip; 2252 return 0; 2253 } 2254 2255 static int cs4231_ebus_attach(struct linux_ebus_device *edev) 2256 { 2257 snd_card_t *card; 2258 cs4231_t *chip; 2259 int err; 2260 2261 err = cs4231_attach_begin(&card); 2262 if (err) 2263 return err; 2264 2265 sprintf(card->longname, "%s at 0x%lx, irq %s", 2266 card->shortname, 2267 edev->resource[0].start, 2268 __irq_itoa(edev->irqs[0])); 2269 2270 if ((err = snd_cs4231_ebus_create(card, edev, dev, &chip)) < 0) { 2271 snd_card_free(card); 2272 return err; 2273 } 2274 2275 return cs4231_attach_finish(card, chip); 2276 } 2277 #endif 2278 2279 static int __init cs4231_init(void) 2280 { 2281 #ifdef SBUS_SUPPORT 2282 struct sbus_bus *sbus; 2283 struct sbus_dev *sdev; 2284 #endif 2285 #ifdef EBUS_SUPPORT 2286 struct linux_ebus *ebus; 2287 struct linux_ebus_device *edev; 2288 #endif 2289 int found; 2290 2291 found = 0; 2292 2293 #ifdef SBUS_SUPPORT 2294 for_all_sbusdev(sdev, sbus) { 2295 if (!strcmp(sdev->prom_name, "SUNW,CS4231")) { 2296 if (cs4231_sbus_attach(sdev) == 0) 2297 found++; 2298 } 2299 } 2300 #endif 2301 #ifdef EBUS_SUPPORT 2302 for_each_ebus(ebus) { 2303 for_each_ebusdev(edev, ebus) { 2304 int match = 0; 2305 2306 if (!strcmp(edev->prom_name, "SUNW,CS4231")) { 2307 match = 1; 2308 } else if (!strcmp(edev->prom_name, "audio")) { 2309 char compat[16]; 2310 2311 prom_getstring(edev->prom_node, "compatible", 2312 compat, sizeof(compat)); 2313 compat[15] = '\0'; 2314 if (!strcmp(compat, "SUNW,CS4231")) 2315 match = 1; 2316 } 2317 2318 if (match && 2319 cs4231_ebus_attach(edev) == 0) 2320 found++; 2321 } 2322 } 2323 #endif 2324 2325 2326 return (found > 0) ? 0 : -EIO; 2327 } 2328 2329 static void __exit cs4231_exit(void) 2330 { 2331 cs4231_t *p = cs4231_list; 2332 2333 while (p != NULL) { 2334 cs4231_t *next = p->next; 2335 2336 snd_card_free(p->card); 2337 2338 p = next; 2339 } 2340 2341 cs4231_list = NULL; 2342 } 2343 2344 module_init(cs4231_init); 2345 module_exit(cs4231_exit); 2346