xref: /linux/sound/soc/spear/spdif_out_regs.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*1a59d1b8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2e584f9b4SVipin Kumar /*
3e584f9b4SVipin Kumar  * SPEAr SPDIF OUT controller header file
4e584f9b4SVipin Kumar  *
5e584f9b4SVipin Kumar  * Copyright (ST) 2011 Vipin Kumar (vipin.kumar@st.com)
6e584f9b4SVipin Kumar  */
7e584f9b4SVipin Kumar 
8e584f9b4SVipin Kumar #ifndef SPDIF_OUT_REGS_H
9e584f9b4SVipin Kumar #define SPDIF_OUT_REGS_H
10e584f9b4SVipin Kumar 
11e584f9b4SVipin Kumar #define SPDIF_OUT_SOFT_RST	0x00
12e584f9b4SVipin Kumar 	#define SPDIF_OUT_RESET		(1 << 0)
13e584f9b4SVipin Kumar #define SPDIF_OUT_FIFO_DATA	0x04
14e584f9b4SVipin Kumar #define SPDIF_OUT_INT_STA	0x08
15e584f9b4SVipin Kumar #define SPDIF_OUT_INT_STA_CLR	0x0C
16e584f9b4SVipin Kumar 	#define SPDIF_INT_UNDERFLOW	(1 << 0)
17e584f9b4SVipin Kumar 	#define SPDIF_INT_EODATA	(1 << 1)
18e584f9b4SVipin Kumar 	#define SPDIF_INT_EOBLOCK	(1 << 2)
19e584f9b4SVipin Kumar 	#define SPDIF_INT_EOLATENCY	(1 << 3)
20e584f9b4SVipin Kumar 	#define SPDIF_INT_EOPD_DATA	(1 << 4)
21e584f9b4SVipin Kumar 	#define SPDIF_INT_MEMFULLREAD	(1 << 5)
22e584f9b4SVipin Kumar 	#define SPDIF_INT_EOPD_PAUSE	(1 << 6)
23e584f9b4SVipin Kumar 
24e584f9b4SVipin Kumar #define SPDIF_OUT_INT_EN	0x10
25e584f9b4SVipin Kumar #define SPDIF_OUT_INT_EN_SET	0x14
26e584f9b4SVipin Kumar #define SPDIF_OUT_INT_EN_CLR	0x18
27e584f9b4SVipin Kumar #define SPDIF_OUT_CTRL		0x1C
28e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_MASK	(7 << 0)
29e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_OFF	(0 << 0)
30e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_MUTE_PCM	(1 << 0)
31e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_MUTE_PAUSE	(2 << 0)
32e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_AUD_DATA	(3 << 0)
33e584f9b4SVipin Kumar 	#define SPDIF_OPMODE_ENCODE	(4 << 0)
34e584f9b4SVipin Kumar 	#define SPDIF_STATE_NORMAL	(1 << 3)
35e584f9b4SVipin Kumar 	#define SPDIF_DIVIDER_MASK	(0xff << 5)
36e584f9b4SVipin Kumar 	#define SPDIF_DIVIDER_SHIFT	(5)
37e584f9b4SVipin Kumar 	#define SPDIF_SAMPLEREAD_MASK	(0x1ffff << 15)
38e584f9b4SVipin Kumar 	#define SPDIF_SAMPLEREAD_SHIFT	(15)
39e584f9b4SVipin Kumar #define SPDIF_OUT_STA		0x20
40e584f9b4SVipin Kumar #define SPDIF_OUT_PA_PB		0x24
41e584f9b4SVipin Kumar #define SPDIF_OUT_PC_PD		0x28
42e584f9b4SVipin Kumar #define SPDIF_OUT_CL1		0x2C
43e584f9b4SVipin Kumar #define SPDIF_OUT_CR1		0x30
44e584f9b4SVipin Kumar #define SPDIF_OUT_CL2_CR2_UV	0x34
45e584f9b4SVipin Kumar #define SPDIF_OUT_PAUSE_LAT	0x38
46e584f9b4SVipin Kumar #define SPDIF_OUT_FRMLEN_BRST	0x3C
47e584f9b4SVipin Kumar #define SPDIF_OUT_CFG		0x40
48e584f9b4SVipin Kumar 	#define SPDIF_OUT_MEMFMT_16_0	(0 << 5)
49e584f9b4SVipin Kumar 	#define SPDIF_OUT_MEMFMT_16_16	(1 << 5)
50e584f9b4SVipin Kumar 	#define SPDIF_OUT_VALID_DMA	(0 << 3)
51e584f9b4SVipin Kumar 	#define SPDIF_OUT_VALID_HW	(1 << 3)
52e584f9b4SVipin Kumar 	#define SPDIF_OUT_USER_DMA	(0 << 2)
53e584f9b4SVipin Kumar 	#define SPDIF_OUT_USER_HW	(1 << 2)
54e584f9b4SVipin Kumar 	#define SPDIF_OUT_CHNLSTA_DMA	(0 << 1)
55e584f9b4SVipin Kumar 	#define SPDIF_OUT_CHNLSTA_HW	(1 << 1)
56e584f9b4SVipin Kumar 	#define SPDIF_OUT_PARITY_HW	(0 << 0)
57e584f9b4SVipin Kumar 	#define SPDIF_OUT_PARITY_DMA	(1 << 0)
58e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_2	(2 << 8)
59e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_6	(6 << 8)
60e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_8	(8 << 8)
61e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_10	(10 << 8)
62e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_12	(12 << 8)
63e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_16	(16 << 8)
64e584f9b4SVipin Kumar 	#define SPDIF_OUT_FDMA_TRIG_18	(18 << 8)
65e584f9b4SVipin Kumar 
66e584f9b4SVipin Kumar #endif /* SPDIF_OUT_REGS_H */
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