1 /* 2 * wm8962.c -- WM8962 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Wolfson Microelectronics plc 5 * 6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/delay.h> 18 #include <linux/pm.h> 19 #include <linux/gcd.h> 20 #include <linux/gpio.h> 21 #include <linux/i2c.h> 22 #include <linux/input.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/slab.h> 26 #include <linux/workqueue.h> 27 #include <sound/core.h> 28 #include <sound/jack.h> 29 #include <sound/pcm.h> 30 #include <sound/pcm_params.h> 31 #include <sound/soc.h> 32 #include <sound/initval.h> 33 #include <sound/tlv.h> 34 #include <sound/wm8962.h> 35 #include <trace/events/asoc.h> 36 37 #include "wm8962.h" 38 39 #define WM8962_NUM_SUPPLIES 8 40 static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = { 41 "DCVDD", 42 "DBVDD", 43 "AVDD", 44 "CPVDD", 45 "MICVDD", 46 "PLLVDD", 47 "SPKVDD1", 48 "SPKVDD2", 49 }; 50 51 /* codec private data */ 52 struct wm8962_priv { 53 struct regmap *regmap; 54 struct snd_soc_codec *codec; 55 56 int sysclk; 57 int sysclk_rate; 58 59 int bclk; /* Desired BCLK */ 60 int lrclk; 61 62 struct completion fll_lock; 63 int fll_src; 64 int fll_fref; 65 int fll_fout; 66 67 u16 dsp2_ena; 68 69 struct delayed_work mic_work; 70 struct snd_soc_jack *jack; 71 72 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES]; 73 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES]; 74 75 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) 76 struct input_dev *beep; 77 struct work_struct beep_work; 78 int beep_rate; 79 #endif 80 81 #ifdef CONFIG_GPIOLIB 82 struct gpio_chip gpio_chip; 83 #endif 84 85 int irq; 86 }; 87 88 /* We can't use the same notifier block for more than one supply and 89 * there's no way I can see to get from a callback to the caller 90 * except container_of(). 91 */ 92 #define WM8962_REGULATOR_EVENT(n) \ 93 static int wm8962_regulator_event_##n(struct notifier_block *nb, \ 94 unsigned long event, void *data) \ 95 { \ 96 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \ 97 disable_nb[n]); \ 98 if (event & REGULATOR_EVENT_DISABLE) { \ 99 regcache_mark_dirty(wm8962->regmap); \ 100 } \ 101 return 0; \ 102 } 103 104 WM8962_REGULATOR_EVENT(0) 105 WM8962_REGULATOR_EVENT(1) 106 WM8962_REGULATOR_EVENT(2) 107 WM8962_REGULATOR_EVENT(3) 108 WM8962_REGULATOR_EVENT(4) 109 WM8962_REGULATOR_EVENT(5) 110 WM8962_REGULATOR_EVENT(6) 111 WM8962_REGULATOR_EVENT(7) 112 113 static struct reg_default wm8962_reg[] = { 114 { 0, 0x009F }, /* R0 - Left Input volume */ 115 { 1, 0x049F }, /* R1 - Right Input volume */ 116 { 2, 0x0000 }, /* R2 - HPOUTL volume */ 117 { 3, 0x0000 }, /* R3 - HPOUTR volume */ 118 { 4, 0x0020 }, /* R4 - Clocking1 */ 119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */ 120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */ 121 { 7, 0x000A }, /* R7 - Audio Interface 0 */ 122 { 8, 0x01E4 }, /* R8 - Clocking2 */ 123 { 9, 0x0300 }, /* R9 - Audio Interface 1 */ 124 { 10, 0x00C0 }, /* R10 - Left DAC volume */ 125 { 11, 0x00C0 }, /* R11 - Right DAC volume */ 126 127 { 14, 0x0040 }, /* R14 - Audio Interface 2 */ 128 { 15, 0x6243 }, /* R15 - Software Reset */ 129 130 { 17, 0x007B }, /* R17 - ALC1 */ 131 { 18, 0x0000 }, /* R18 - ALC2 */ 132 { 19, 0x1C32 }, /* R19 - ALC3 */ 133 { 20, 0x3200 }, /* R20 - Noise Gate */ 134 { 21, 0x00C0 }, /* R21 - Left ADC volume */ 135 { 22, 0x00C0 }, /* R22 - Right ADC volume */ 136 { 23, 0x0160 }, /* R23 - Additional control(1) */ 137 { 24, 0x0000 }, /* R24 - Additional control(2) */ 138 { 25, 0x0000 }, /* R25 - Pwr Mgmt (1) */ 139 { 26, 0x0000 }, /* R26 - Pwr Mgmt (2) */ 140 { 27, 0x0010 }, /* R27 - Additional Control (3) */ 141 { 28, 0x0000 }, /* R28 - Anti-pop */ 142 143 { 30, 0x005E }, /* R30 - Clocking 3 */ 144 { 31, 0x0000 }, /* R31 - Input mixer control (1) */ 145 { 32, 0x0145 }, /* R32 - Left input mixer volume */ 146 { 33, 0x0145 }, /* R33 - Right input mixer volume */ 147 { 34, 0x0009 }, /* R34 - Input mixer control (2) */ 148 { 35, 0x0003 }, /* R35 - Input bias control */ 149 { 37, 0x0008 }, /* R37 - Left input PGA control */ 150 { 38, 0x0008 }, /* R38 - Right input PGA control */ 151 152 { 40, 0x0000 }, /* R40 - SPKOUTL volume */ 153 { 41, 0x0000 }, /* R41 - SPKOUTR volume */ 154 155 { 47, 0x0000 }, /* R47 - Thermal Shutdown Status */ 156 { 48, 0x8027 }, /* R48 - Additional Control (4) */ 157 { 49, 0x0010 }, /* R49 - Class D Control 1 */ 158 159 { 51, 0x0003 }, /* R51 - Class D Control 2 */ 160 161 { 56, 0x0506 }, /* R56 - Clocking 4 */ 162 { 57, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ 163 { 58, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ 164 165 { 60, 0x0300 }, /* R60 - DC Servo 0 */ 166 { 61, 0x0300 }, /* R61 - DC Servo 1 */ 167 168 { 64, 0x0810 }, /* R64 - DC Servo 4 */ 169 170 { 66, 0x0000 }, /* R66 - DC Servo 6 */ 171 172 { 68, 0x001B }, /* R68 - Analogue PGA Bias */ 173 { 69, 0x0000 }, /* R69 - Analogue HP 0 */ 174 175 { 71, 0x01FB }, /* R71 - Analogue HP 2 */ 176 { 72, 0x0000 }, /* R72 - Charge Pump 1 */ 177 178 { 82, 0x0004 }, /* R82 - Charge Pump B */ 179 180 { 87, 0x0000 }, /* R87 - Write Sequencer Control 1 */ 181 182 { 90, 0x0000 }, /* R90 - Write Sequencer Control 2 */ 183 184 { 93, 0x0000 }, /* R93 - Write Sequencer Control 3 */ 185 { 94, 0x0000 }, /* R94 - Control Interface */ 186 187 { 99, 0x0000 }, /* R99 - Mixer Enables */ 188 { 100, 0x0000 }, /* R100 - Headphone Mixer (1) */ 189 { 101, 0x0000 }, /* R101 - Headphone Mixer (2) */ 190 { 102, 0x013F }, /* R102 - Headphone Mixer (3) */ 191 { 103, 0x013F }, /* R103 - Headphone Mixer (4) */ 192 193 { 105, 0x0000 }, /* R105 - Speaker Mixer (1) */ 194 { 106, 0x0000 }, /* R106 - Speaker Mixer (2) */ 195 { 107, 0x013F }, /* R107 - Speaker Mixer (3) */ 196 { 108, 0x013F }, /* R108 - Speaker Mixer (4) */ 197 { 109, 0x0003 }, /* R109 - Speaker Mixer (5) */ 198 { 110, 0x0002 }, /* R110 - Beep Generator (1) */ 199 200 { 115, 0x0006 }, /* R115 - Oscillator Trim (3) */ 201 { 116, 0x0026 }, /* R116 - Oscillator Trim (4) */ 202 203 { 119, 0x0000 }, /* R119 - Oscillator Trim (7) */ 204 205 { 124, 0x0011 }, /* R124 - Analogue Clocking1 */ 206 { 125, 0x004B }, /* R125 - Analogue Clocking2 */ 207 { 126, 0x000D }, /* R126 - Analogue Clocking3 */ 208 { 127, 0x0000 }, /* R127 - PLL Software Reset */ 209 210 { 129, 0x0000 }, /* R129 - PLL2 */ 211 212 { 131, 0x0000 }, /* R131 - PLL 4 */ 213 214 { 136, 0x0067 }, /* R136 - PLL 9 */ 215 { 137, 0x001C }, /* R137 - PLL 10 */ 216 { 138, 0x0071 }, /* R138 - PLL 11 */ 217 { 139, 0x00C7 }, /* R139 - PLL 12 */ 218 { 140, 0x0067 }, /* R140 - PLL 13 */ 219 { 141, 0x0048 }, /* R141 - PLL 14 */ 220 { 142, 0x0022 }, /* R142 - PLL 15 */ 221 { 143, 0x0097 }, /* R143 - PLL 16 */ 222 223 { 155, 0x000C }, /* R155 - FLL Control (1) */ 224 { 156, 0x0039 }, /* R156 - FLL Control (2) */ 225 { 157, 0x0180 }, /* R157 - FLL Control (3) */ 226 227 { 159, 0x0032 }, /* R159 - FLL Control (5) */ 228 { 160, 0x0018 }, /* R160 - FLL Control (6) */ 229 { 161, 0x007D }, /* R161 - FLL Control (7) */ 230 { 162, 0x0008 }, /* R162 - FLL Control (8) */ 231 232 { 252, 0x0005 }, /* R252 - General test 1 */ 233 234 { 256, 0x0000 }, /* R256 - DF1 */ 235 { 257, 0x0000 }, /* R257 - DF2 */ 236 { 258, 0x0000 }, /* R258 - DF3 */ 237 { 259, 0x0000 }, /* R259 - DF4 */ 238 { 260, 0x0000 }, /* R260 - DF5 */ 239 { 261, 0x0000 }, /* R261 - DF6 */ 240 { 262, 0x0000 }, /* R262 - DF7 */ 241 242 { 264, 0x0000 }, /* R264 - LHPF1 */ 243 { 265, 0x0000 }, /* R265 - LHPF2 */ 244 245 { 268, 0x0000 }, /* R268 - THREED1 */ 246 { 269, 0x0000 }, /* R269 - THREED2 */ 247 { 270, 0x0000 }, /* R270 - THREED3 */ 248 { 271, 0x0000 }, /* R271 - THREED4 */ 249 250 { 276, 0x000C }, /* R276 - DRC 1 */ 251 { 277, 0x0925 }, /* R277 - DRC 2 */ 252 { 278, 0x0000 }, /* R278 - DRC 3 */ 253 { 279, 0x0000 }, /* R279 - DRC 4 */ 254 { 280, 0x0000 }, /* R280 - DRC 5 */ 255 256 { 285, 0x0000 }, /* R285 - Tloopback */ 257 258 { 335, 0x0004 }, /* R335 - EQ1 */ 259 { 336, 0x6318 }, /* R336 - EQ2 */ 260 { 337, 0x6300 }, /* R337 - EQ3 */ 261 { 338, 0x0FCA }, /* R338 - EQ4 */ 262 { 339, 0x0400 }, /* R339 - EQ5 */ 263 { 340, 0x00D8 }, /* R340 - EQ6 */ 264 { 341, 0x1EB5 }, /* R341 - EQ7 */ 265 { 342, 0xF145 }, /* R342 - EQ8 */ 266 { 343, 0x0B75 }, /* R343 - EQ9 */ 267 { 344, 0x01C5 }, /* R344 - EQ10 */ 268 { 345, 0x1C58 }, /* R345 - EQ11 */ 269 { 346, 0xF373 }, /* R346 - EQ12 */ 270 { 347, 0x0A54 }, /* R347 - EQ13 */ 271 { 348, 0x0558 }, /* R348 - EQ14 */ 272 { 349, 0x168E }, /* R349 - EQ15 */ 273 { 350, 0xF829 }, /* R350 - EQ16 */ 274 { 351, 0x07AD }, /* R351 - EQ17 */ 275 { 352, 0x1103 }, /* R352 - EQ18 */ 276 { 353, 0x0564 }, /* R353 - EQ19 */ 277 { 354, 0x0559 }, /* R354 - EQ20 */ 278 { 355, 0x4000 }, /* R355 - EQ21 */ 279 { 356, 0x6318 }, /* R356 - EQ22 */ 280 { 357, 0x6300 }, /* R357 - EQ23 */ 281 { 358, 0x0FCA }, /* R358 - EQ24 */ 282 { 359, 0x0400 }, /* R359 - EQ25 */ 283 { 360, 0x00D8 }, /* R360 - EQ26 */ 284 { 361, 0x1EB5 }, /* R361 - EQ27 */ 285 { 362, 0xF145 }, /* R362 - EQ28 */ 286 { 363, 0x0B75 }, /* R363 - EQ29 */ 287 { 364, 0x01C5 }, /* R364 - EQ30 */ 288 { 365, 0x1C58 }, /* R365 - EQ31 */ 289 { 366, 0xF373 }, /* R366 - EQ32 */ 290 { 367, 0x0A54 }, /* R367 - EQ33 */ 291 { 368, 0x0558 }, /* R368 - EQ34 */ 292 { 369, 0x168E }, /* R369 - EQ35 */ 293 { 370, 0xF829 }, /* R370 - EQ36 */ 294 { 371, 0x07AD }, /* R371 - EQ37 */ 295 { 372, 0x1103 }, /* R372 - EQ38 */ 296 { 373, 0x0564 }, /* R373 - EQ39 */ 297 { 374, 0x0559 }, /* R374 - EQ40 */ 298 { 375, 0x4000 }, /* R375 - EQ41 */ 299 300 { 513, 0x0000 }, /* R513 - GPIO 2 */ 301 { 514, 0x0000 }, /* R514 - GPIO 3 */ 302 303 { 516, 0x8100 }, /* R516 - GPIO 5 */ 304 { 517, 0x8100 }, /* R517 - GPIO 6 */ 305 306 { 560, 0x0000 }, /* R560 - Interrupt Status 1 */ 307 { 561, 0x0000 }, /* R561 - Interrupt Status 2 */ 308 309 { 568, 0x0030 }, /* R568 - Interrupt Status 1 Mask */ 310 { 569, 0xFFED }, /* R569 - Interrupt Status 2 Mask */ 311 312 { 576, 0x0000 }, /* R576 - Interrupt Control */ 313 314 { 584, 0x002D }, /* R584 - IRQ Debounce */ 315 316 { 586, 0x0000 }, /* R586 - MICINT Source Pol */ 317 318 { 768, 0x1C00 }, /* R768 - DSP2 Power Management */ 319 320 { 1037, 0x0000 }, /* R1037 - DSP2_ExecControl */ 321 322 { 8192, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ 323 324 { 9216, 0x0030 }, /* R9216 - DSP2 Address RAM 2 */ 325 { 9217, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ 326 { 9218, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ 327 328 { 12288, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ 329 { 12289, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ 330 331 { 13312, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ 332 { 13313, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ 333 334 { 14336, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ 335 { 14337, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ 336 337 { 15360, 0x000A }, /* R15360 - DSP2 Coeff RAM 0 */ 338 339 { 16384, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ 340 { 16385, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ 341 { 16386, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ 342 { 16387, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ 343 { 16388, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ 344 { 16389, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ 345 346 { 16896, 0x0002 }, /* R16896 - HDBASS_AI_1 */ 347 { 16897, 0xBD12 }, /* R16897 - HDBASS_AI_0 */ 348 { 16898, 0x007C }, /* R16898 - HDBASS_AR_1 */ 349 { 16899, 0x586C }, /* R16899 - HDBASS_AR_0 */ 350 { 16900, 0x0053 }, /* R16900 - HDBASS_B_1 */ 351 { 16901, 0x8121 }, /* R16901 - HDBASS_B_0 */ 352 { 16902, 0x003F }, /* R16902 - HDBASS_K_1 */ 353 { 16903, 0x8BD8 }, /* R16903 - HDBASS_K_0 */ 354 { 16904, 0x0032 }, /* R16904 - HDBASS_N1_1 */ 355 { 16905, 0xF52D }, /* R16905 - HDBASS_N1_0 */ 356 { 16906, 0x0065 }, /* R16906 - HDBASS_N2_1 */ 357 { 16907, 0xAC8C }, /* R16907 - HDBASS_N2_0 */ 358 { 16908, 0x006B }, /* R16908 - HDBASS_N3_1 */ 359 { 16909, 0xE087 }, /* R16909 - HDBASS_N3_0 */ 360 { 16910, 0x0072 }, /* R16910 - HDBASS_N4_1 */ 361 { 16911, 0x1483 }, /* R16911 - HDBASS_N4_0 */ 362 { 16912, 0x0072 }, /* R16912 - HDBASS_N5_1 */ 363 { 16913, 0x1483 }, /* R16913 - HDBASS_N5_0 */ 364 { 16914, 0x0043 }, /* R16914 - HDBASS_X1_1 */ 365 { 16915, 0x3525 }, /* R16915 - HDBASS_X1_0 */ 366 { 16916, 0x0006 }, /* R16916 - HDBASS_X2_1 */ 367 { 16917, 0x6A4A }, /* R16917 - HDBASS_X2_0 */ 368 { 16918, 0x0043 }, /* R16918 - HDBASS_X3_1 */ 369 { 16919, 0x6079 }, /* R16919 - HDBASS_X3_0 */ 370 { 16920, 0x0008 }, /* R16920 - HDBASS_ATK_1 */ 371 { 16921, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ 372 { 16922, 0x0001 }, /* R16922 - HDBASS_DCY_1 */ 373 { 16923, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ 374 { 16924, 0x0059 }, /* R16924 - HDBASS_PG_1 */ 375 { 16925, 0x999A }, /* R16925 - HDBASS_PG_0 */ 376 377 { 17048, 0x0083 }, /* R17408 - HPF_C_1 */ 378 { 17049, 0x98AD }, /* R17409 - HPF_C_0 */ 379 380 { 17920, 0x007F }, /* R17920 - ADCL_RETUNE_C1_1 */ 381 { 17921, 0xFFFF }, /* R17921 - ADCL_RETUNE_C1_0 */ 382 { 17922, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ 383 { 17923, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ 384 { 17924, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ 385 { 17925, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ 386 { 17926, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ 387 { 17927, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ 388 { 17928, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ 389 { 17929, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ 390 { 17930, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ 391 { 17931, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ 392 { 17932, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ 393 { 17933, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ 394 { 17934, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ 395 { 17935, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ 396 { 17936, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ 397 { 17937, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ 398 { 17938, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ 399 { 17939, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ 400 { 17940, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ 401 { 17941, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ 402 { 17942, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ 403 { 17943, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ 404 { 17944, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ 405 { 17945, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ 406 { 17946, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ 407 { 17947, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ 408 { 17948, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ 409 { 17949, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ 410 { 17950, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ 411 { 17951, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ 412 { 17952, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ 413 { 17953, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ 414 { 17954, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ 415 { 17955, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ 416 { 17956, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ 417 { 17957, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ 418 { 17958, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ 419 { 17959, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ 420 { 17960, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ 421 { 17961, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ 422 { 17962, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ 423 { 17963, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ 424 { 17964, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ 425 { 17965, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ 426 { 17966, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ 427 { 17967, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ 428 { 17968, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ 429 { 17969, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ 430 { 17970, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ 431 { 17971, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ 432 { 17972, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ 433 { 17973, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ 434 { 17974, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ 435 { 17975, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ 436 { 17976, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ 437 { 17977, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ 438 { 17978, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ 439 { 17979, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ 440 { 17980, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ 441 { 17981, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ 442 { 17982, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ 443 { 17983, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ 444 445 { 18432, 0x0020 }, /* R18432 - RETUNEADC_PG2_1 */ 446 { 18433, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ 447 { 18434, 0x0040 }, /* R18434 - RETUNEADC_PG_1 */ 448 { 18435, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ 449 450 { 18944, 0x007F }, /* R18944 - ADCR_RETUNE_C1_1 */ 451 { 18945, 0xFFFF }, /* R18945 - ADCR_RETUNE_C1_0 */ 452 { 18946, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ 453 { 18947, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ 454 { 18948, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ 455 { 18949, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ 456 { 18950, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ 457 { 18951, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ 458 { 18952, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ 459 { 18953, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ 460 { 18954, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ 461 { 18955, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ 462 { 18956, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ 463 { 18957, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ 464 { 18958, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ 465 { 18959, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ 466 { 18960, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ 467 { 18961, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ 468 { 18962, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ 469 { 18963, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ 470 { 18964, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ 471 { 18965, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ 472 { 18966, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ 473 { 18967, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ 474 { 18968, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ 475 { 18969, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ 476 { 18970, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ 477 { 18971, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ 478 { 18972, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ 479 { 18973, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ 480 { 18974, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ 481 { 18975, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ 482 { 18976, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ 483 { 18977, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ 484 { 18978, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ 485 { 18979, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ 486 { 18980, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ 487 { 18981, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ 488 { 18982, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ 489 { 18983, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ 490 { 18984, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ 491 { 18985, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ 492 { 18986, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ 493 { 18987, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ 494 { 18988, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ 495 { 18989, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ 496 { 18990, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ 497 { 18991, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ 498 { 18992, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ 499 { 18993, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ 500 { 18994, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ 501 { 18995, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ 502 { 18996, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ 503 { 18997, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ 504 { 18998, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ 505 { 18999, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ 506 { 19000, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ 507 { 19001, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ 508 { 19002, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ 509 { 19003, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ 510 { 19004, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ 511 { 19005, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ 512 { 19006, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ 513 { 19007, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ 514 515 { 19456, 0x007F }, /* R19456 - DACL_RETUNE_C1_1 */ 516 { 19457, 0xFFFF }, /* R19457 - DACL_RETUNE_C1_0 */ 517 { 19458, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ 518 { 19459, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ 519 { 19460, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ 520 { 19461, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ 521 { 19462, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ 522 { 19463, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ 523 { 19464, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ 524 { 19465, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ 525 { 19466, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ 526 { 19467, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ 527 { 19468, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ 528 { 19469, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ 529 { 19470, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ 530 { 19471, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ 531 { 19472, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ 532 { 19473, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ 533 { 19474, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ 534 { 19475, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ 535 { 19476, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ 536 { 19477, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ 537 { 19478, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ 538 { 19479, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ 539 { 19480, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ 540 { 19481, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ 541 { 19482, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ 542 { 19483, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ 543 { 19484, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ 544 { 19485, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ 545 { 19486, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ 546 { 19487, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ 547 { 19488, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ 548 { 19489, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ 549 { 19490, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ 550 { 19491, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ 551 { 19492, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ 552 { 19493, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ 553 { 19494, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ 554 { 19495, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ 555 { 19496, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ 556 { 19497, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ 557 { 19498, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ 558 { 19499, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ 559 { 19500, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ 560 { 19501, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ 561 { 19502, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ 562 { 19503, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ 563 { 19504, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ 564 { 19505, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ 565 { 19506, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ 566 { 19507, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ 567 { 19508, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ 568 { 19509, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ 569 { 19510, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ 570 { 19511, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ 571 { 19512, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ 572 { 19513, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ 573 { 19514, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ 574 { 19515, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ 575 { 19516, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ 576 { 19517, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ 577 { 19518, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ 578 { 19519, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ 579 580 { 19968, 0x0020 }, /* R19968 - RETUNEDAC_PG2_1 */ 581 { 19969, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ 582 { 19970, 0x0040 }, /* R19970 - RETUNEDAC_PG_1 */ 583 { 19971, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ 584 585 { 20480, 0x007F }, /* R20480 - DACR_RETUNE_C1_1 */ 586 { 20481, 0xFFFF }, /* R20481 - DACR_RETUNE_C1_0 */ 587 { 20482, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ 588 { 20483, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ 589 { 20484, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ 590 { 20485, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ 591 { 20486, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ 592 { 20487, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ 593 { 20488, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ 594 { 20489, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ 595 { 20490, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ 596 { 20491, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ 597 { 20492, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ 598 { 20493, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ 599 { 20494, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ 600 { 20495, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ 601 { 20496, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ 602 { 20497, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ 603 { 20498, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ 604 { 20499, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ 605 { 20500, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ 606 { 20501, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ 607 { 20502, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ 608 { 20503, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ 609 { 20504, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ 610 { 20505, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ 611 { 20506, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ 612 { 20507, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ 613 { 20508, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ 614 { 20509, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ 615 { 20510, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ 616 { 20511, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ 617 { 20512, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ 618 { 20513, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ 619 { 20514, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ 620 { 20515, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ 621 { 20516, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ 622 { 20517, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ 623 { 20518, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ 624 { 20519, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ 625 { 20520, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ 626 { 20521, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ 627 { 20522, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ 628 { 20523, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ 629 { 20524, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ 630 { 20525, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ 631 { 20526, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ 632 { 20527, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ 633 { 20528, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ 634 { 20529, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ 635 { 20530, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ 636 { 20531, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ 637 { 20532, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ 638 { 20533, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ 639 { 20534, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ 640 { 20535, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ 641 { 20536, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ 642 { 20537, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ 643 { 20538, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ 644 { 20539, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ 645 { 20540, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ 646 { 20541, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ 647 { 20542, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ 648 { 20543, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ 649 650 { 20992, 0x008C }, /* R20992 - VSS_XHD2_1 */ 651 { 20993, 0x0200 }, /* R20993 - VSS_XHD2_0 */ 652 { 20994, 0x0035 }, /* R20994 - VSS_XHD3_1 */ 653 { 20995, 0x0700 }, /* R20995 - VSS_XHD3_0 */ 654 { 20996, 0x003A }, /* R20996 - VSS_XHN1_1 */ 655 { 20997, 0x4100 }, /* R20997 - VSS_XHN1_0 */ 656 { 20998, 0x008B }, /* R20998 - VSS_XHN2_1 */ 657 { 20999, 0x7D00 }, /* R20999 - VSS_XHN2_0 */ 658 { 21000, 0x003A }, /* R21000 - VSS_XHN3_1 */ 659 { 21001, 0x4100 }, /* R21001 - VSS_XHN3_0 */ 660 { 21002, 0x008C }, /* R21002 - VSS_XLA_1 */ 661 { 21003, 0xFEE8 }, /* R21003 - VSS_XLA_0 */ 662 { 21004, 0x0078 }, /* R21004 - VSS_XLB_1 */ 663 { 21005, 0x0000 }, /* R21005 - VSS_XLB_0 */ 664 { 21006, 0x003F }, /* R21006 - VSS_XLG_1 */ 665 { 21007, 0xB260 }, /* R21007 - VSS_XLG_0 */ 666 { 21008, 0x002D }, /* R21008 - VSS_PG2_1 */ 667 { 21009, 0x1818 }, /* R21009 - VSS_PG2_0 */ 668 { 21010, 0x0020 }, /* R21010 - VSS_PG_1 */ 669 { 21011, 0x0000 }, /* R21011 - VSS_PG_0 */ 670 { 21012, 0x00F1 }, /* R21012 - VSS_XTD1_1 */ 671 { 21013, 0x8340 }, /* R21013 - VSS_XTD1_0 */ 672 { 21014, 0x00FB }, /* R21014 - VSS_XTD2_1 */ 673 { 21015, 0x8300 }, /* R21015 - VSS_XTD2_0 */ 674 { 21016, 0x00EE }, /* R21016 - VSS_XTD3_1 */ 675 { 21017, 0xAEC0 }, /* R21017 - VSS_XTD3_0 */ 676 { 21018, 0x00FB }, /* R21018 - VSS_XTD4_1 */ 677 { 21019, 0xAC40 }, /* R21019 - VSS_XTD4_0 */ 678 { 21020, 0x00F1 }, /* R21020 - VSS_XTD5_1 */ 679 { 21021, 0x7F80 }, /* R21021 - VSS_XTD5_0 */ 680 { 21022, 0x00F4 }, /* R21022 - VSS_XTD6_1 */ 681 { 21023, 0x3B40 }, /* R21023 - VSS_XTD6_0 */ 682 { 21024, 0x00F5 }, /* R21024 - VSS_XTD7_1 */ 683 { 21025, 0xFB00 }, /* R21025 - VSS_XTD7_0 */ 684 { 21026, 0x00EA }, /* R21026 - VSS_XTD8_1 */ 685 { 21027, 0x10C0 }, /* R21027 - VSS_XTD8_0 */ 686 { 21028, 0x00FC }, /* R21028 - VSS_XTD9_1 */ 687 { 21029, 0xC580 }, /* R21029 - VSS_XTD9_0 */ 688 { 21030, 0x00E2 }, /* R21030 - VSS_XTD10_1 */ 689 { 21031, 0x75C0 }, /* R21031 - VSS_XTD10_0 */ 690 { 21032, 0x0004 }, /* R21032 - VSS_XTD11_1 */ 691 { 21033, 0xB480 }, /* R21033 - VSS_XTD11_0 */ 692 { 21034, 0x00D4 }, /* R21034 - VSS_XTD12_1 */ 693 { 21035, 0xF980 }, /* R21035 - VSS_XTD12_0 */ 694 { 21036, 0x0004 }, /* R21036 - VSS_XTD13_1 */ 695 { 21037, 0x9140 }, /* R21037 - VSS_XTD13_0 */ 696 { 21038, 0x00D8 }, /* R21038 - VSS_XTD14_1 */ 697 { 21039, 0xA480 }, /* R21039 - VSS_XTD14_0 */ 698 { 21040, 0x0002 }, /* R21040 - VSS_XTD15_1 */ 699 { 21041, 0x3DC0 }, /* R21041 - VSS_XTD15_0 */ 700 { 21042, 0x00CF }, /* R21042 - VSS_XTD16_1 */ 701 { 21043, 0x7A80 }, /* R21043 - VSS_XTD16_0 */ 702 { 21044, 0x00DC }, /* R21044 - VSS_XTD17_1 */ 703 { 21045, 0x0600 }, /* R21045 - VSS_XTD17_0 */ 704 { 21046, 0x00F2 }, /* R21046 - VSS_XTD18_1 */ 705 { 21047, 0xDAC0 }, /* R21047 - VSS_XTD18_0 */ 706 { 21048, 0x00BA }, /* R21048 - VSS_XTD19_1 */ 707 { 21049, 0xF340 }, /* R21049 - VSS_XTD19_0 */ 708 { 21050, 0x000A }, /* R21050 - VSS_XTD20_1 */ 709 { 21051, 0x7940 }, /* R21051 - VSS_XTD20_0 */ 710 { 21052, 0x001C }, /* R21052 - VSS_XTD21_1 */ 711 { 21053, 0x0680 }, /* R21053 - VSS_XTD21_0 */ 712 { 21054, 0x00FD }, /* R21054 - VSS_XTD22_1 */ 713 { 21055, 0x2D00 }, /* R21055 - VSS_XTD22_0 */ 714 { 21056, 0x001C }, /* R21056 - VSS_XTD23_1 */ 715 { 21057, 0xE840 }, /* R21057 - VSS_XTD23_0 */ 716 { 21058, 0x000D }, /* R21058 - VSS_XTD24_1 */ 717 { 21059, 0xDC40 }, /* R21059 - VSS_XTD24_0 */ 718 { 21060, 0x00FC }, /* R21060 - VSS_XTD25_1 */ 719 { 21061, 0x9D00 }, /* R21061 - VSS_XTD25_0 */ 720 { 21062, 0x0009 }, /* R21062 - VSS_XTD26_1 */ 721 { 21063, 0x5580 }, /* R21063 - VSS_XTD26_0 */ 722 { 21064, 0x00FE }, /* R21064 - VSS_XTD27_1 */ 723 { 21065, 0x7E80 }, /* R21065 - VSS_XTD27_0 */ 724 { 21066, 0x000E }, /* R21066 - VSS_XTD28_1 */ 725 { 21067, 0xAB40 }, /* R21067 - VSS_XTD28_0 */ 726 { 21068, 0x00F9 }, /* R21068 - VSS_XTD29_1 */ 727 { 21069, 0x9880 }, /* R21069 - VSS_XTD29_0 */ 728 { 21070, 0x0009 }, /* R21070 - VSS_XTD30_1 */ 729 { 21071, 0x87C0 }, /* R21071 - VSS_XTD30_0 */ 730 { 21072, 0x00FD }, /* R21072 - VSS_XTD31_1 */ 731 { 21073, 0x2C40 }, /* R21073 - VSS_XTD31_0 */ 732 { 21074, 0x0009 }, /* R21074 - VSS_XTD32_1 */ 733 { 21075, 0x4800 }, /* R21075 - VSS_XTD32_0 */ 734 { 21076, 0x0003 }, /* R21076 - VSS_XTS1_1 */ 735 { 21077, 0x5F40 }, /* R21077 - VSS_XTS1_0 */ 736 { 21078, 0x0000 }, /* R21078 - VSS_XTS2_1 */ 737 { 21079, 0x8700 }, /* R21079 - VSS_XTS2_0 */ 738 { 21080, 0x00FA }, /* R21080 - VSS_XTS3_1 */ 739 { 21081, 0xE4C0 }, /* R21081 - VSS_XTS3_0 */ 740 { 21082, 0x0000 }, /* R21082 - VSS_XTS4_1 */ 741 { 21083, 0x0B40 }, /* R21083 - VSS_XTS4_0 */ 742 { 21084, 0x0004 }, /* R21084 - VSS_XTS5_1 */ 743 { 21085, 0xE180 }, /* R21085 - VSS_XTS5_0 */ 744 { 21086, 0x0001 }, /* R21086 - VSS_XTS6_1 */ 745 { 21087, 0x1F40 }, /* R21087 - VSS_XTS6_0 */ 746 { 21088, 0x00F8 }, /* R21088 - VSS_XTS7_1 */ 747 { 21089, 0xB000 }, /* R21089 - VSS_XTS7_0 */ 748 { 21090, 0x00FB }, /* R21090 - VSS_XTS8_1 */ 749 { 21091, 0xCBC0 }, /* R21091 - VSS_XTS8_0 */ 750 { 21092, 0x0004 }, /* R21092 - VSS_XTS9_1 */ 751 { 21093, 0xF380 }, /* R21093 - VSS_XTS9_0 */ 752 { 21094, 0x0007 }, /* R21094 - VSS_XTS10_1 */ 753 { 21095, 0xDF40 }, /* R21095 - VSS_XTS10_0 */ 754 { 21096, 0x00FF }, /* R21096 - VSS_XTS11_1 */ 755 { 21097, 0x0700 }, /* R21097 - VSS_XTS11_0 */ 756 { 21098, 0x00EF }, /* R21098 - VSS_XTS12_1 */ 757 { 21099, 0xD700 }, /* R21099 - VSS_XTS12_0 */ 758 { 21100, 0x00FB }, /* R21100 - VSS_XTS13_1 */ 759 { 21101, 0xAF40 }, /* R21101 - VSS_XTS13_0 */ 760 { 21102, 0x0010 }, /* R21102 - VSS_XTS14_1 */ 761 { 21103, 0x8A80 }, /* R21103 - VSS_XTS14_0 */ 762 { 21104, 0x0011 }, /* R21104 - VSS_XTS15_1 */ 763 { 21105, 0x07C0 }, /* R21105 - VSS_XTS15_0 */ 764 { 21106, 0x00E0 }, /* R21106 - VSS_XTS16_1 */ 765 { 21107, 0x0800 }, /* R21107 - VSS_XTS16_0 */ 766 { 21108, 0x00D2 }, /* R21108 - VSS_XTS17_1 */ 767 { 21109, 0x7600 }, /* R21109 - VSS_XTS17_0 */ 768 { 21110, 0x0020 }, /* R21110 - VSS_XTS18_1 */ 769 { 21111, 0xCF40 }, /* R21111 - VSS_XTS18_0 */ 770 { 21112, 0x0030 }, /* R21112 - VSS_XTS19_1 */ 771 { 21113, 0x2340 }, /* R21113 - VSS_XTS19_0 */ 772 { 21114, 0x00FD }, /* R21114 - VSS_XTS20_1 */ 773 { 21115, 0x69C0 }, /* R21115 - VSS_XTS20_0 */ 774 { 21116, 0x0028 }, /* R21116 - VSS_XTS21_1 */ 775 { 21117, 0x3500 }, /* R21117 - VSS_XTS21_0 */ 776 { 21118, 0x0006 }, /* R21118 - VSS_XTS22_1 */ 777 { 21119, 0x3300 }, /* R21119 - VSS_XTS22_0 */ 778 { 21120, 0x00D9 }, /* R21120 - VSS_XTS23_1 */ 779 { 21121, 0xF6C0 }, /* R21121 - VSS_XTS23_0 */ 780 { 21122, 0x00F3 }, /* R21122 - VSS_XTS24_1 */ 781 { 21123, 0x3340 }, /* R21123 - VSS_XTS24_0 */ 782 { 21124, 0x000F }, /* R21124 - VSS_XTS25_1 */ 783 { 21125, 0x4200 }, /* R21125 - VSS_XTS25_0 */ 784 { 21126, 0x0004 }, /* R21126 - VSS_XTS26_1 */ 785 { 21127, 0x0C80 }, /* R21127 - VSS_XTS26_0 */ 786 { 21128, 0x00FB }, /* R21128 - VSS_XTS27_1 */ 787 { 21129, 0x3F80 }, /* R21129 - VSS_XTS27_0 */ 788 { 21130, 0x00F7 }, /* R21130 - VSS_XTS28_1 */ 789 { 21131, 0x57C0 }, /* R21131 - VSS_XTS28_0 */ 790 { 21132, 0x0003 }, /* R21132 - VSS_XTS29_1 */ 791 { 21133, 0x5400 }, /* R21133 - VSS_XTS29_0 */ 792 { 21134, 0x0000 }, /* R21134 - VSS_XTS30_1 */ 793 { 21135, 0xC6C0 }, /* R21135 - VSS_XTS30_0 */ 794 { 21136, 0x0003 }, /* R21136 - VSS_XTS31_1 */ 795 { 21137, 0x12C0 }, /* R21137 - VSS_XTS31_0 */ 796 { 21138, 0x00FD }, /* R21138 - VSS_XTS32_1 */ 797 { 21139, 0x8580 }, /* R21139 - VSS_XTS32_0 */ 798 }; 799 800 static const struct wm8962_reg_access { 801 u16 read; 802 u16 write; 803 u16 vol; 804 } wm8962_reg_access[WM8962_MAX_REGISTER + 1] = { 805 [0] = { 0x00FF, 0x01FF, 0x0000 }, /* R0 - Left Input volume */ 806 [1] = { 0xFEFF, 0x01FF, 0x0000 }, /* R1 - Right Input volume */ 807 [2] = { 0x00FF, 0x01FF, 0x0000 }, /* R2 - HPOUTL volume */ 808 [3] = { 0x00FF, 0x01FF, 0x0000 }, /* R3 - HPOUTR volume */ 809 [4] = { 0x07FE, 0x07FE, 0xFFFF }, /* R4 - Clocking1 */ 810 [5] = { 0x007F, 0x007F, 0x0000 }, /* R5 - ADC & DAC Control 1 */ 811 [6] = { 0x37ED, 0x37ED, 0x0000 }, /* R6 - ADC & DAC Control 2 */ 812 [7] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R7 - Audio Interface 0 */ 813 [8] = { 0x0FEF, 0x0FEF, 0xFFFF }, /* R8 - Clocking2 */ 814 [9] = { 0x0B9F, 0x039F, 0x0000 }, /* R9 - Audio Interface 1 */ 815 [10] = { 0x00FF, 0x01FF, 0x0000 }, /* R10 - Left DAC volume */ 816 [11] = { 0x00FF, 0x01FF, 0x0000 }, /* R11 - Right DAC volume */ 817 [14] = { 0x07FF, 0x07FF, 0x0000 }, /* R14 - Audio Interface 2 */ 818 [15] = { 0xFFFF, 0xFFFF, 0xFFFF }, /* R15 - Software Reset */ 819 [17] = { 0x07FF, 0x07FF, 0x0000 }, /* R17 - ALC1 */ 820 [18] = { 0xF8FF, 0x00FF, 0xFFFF }, /* R18 - ALC2 */ 821 [19] = { 0x1DFF, 0x1DFF, 0x0000 }, /* R19 - ALC3 */ 822 [20] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20 - Noise Gate */ 823 [21] = { 0x00FF, 0x01FF, 0x0000 }, /* R21 - Left ADC volume */ 824 [22] = { 0x00FF, 0x01FF, 0x0000 }, /* R22 - Right ADC volume */ 825 [23] = { 0x0161, 0x0161, 0x0000 }, /* R23 - Additional control(1) */ 826 [24] = { 0x0008, 0x0008, 0x0000 }, /* R24 - Additional control(2) */ 827 [25] = { 0x07FE, 0x07FE, 0x0000 }, /* R25 - Pwr Mgmt (1) */ 828 [26] = { 0x01FB, 0x01FB, 0x0000 }, /* R26 - Pwr Mgmt (2) */ 829 [27] = { 0x0017, 0x0017, 0x0000 }, /* R27 - Additional Control (3) */ 830 [28] = { 0x001C, 0x001C, 0x0000 }, /* R28 - Anti-pop */ 831 832 [30] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R30 - Clocking 3 */ 833 [31] = { 0x000F, 0x000F, 0x0000 }, /* R31 - Input mixer control (1) */ 834 [32] = { 0x01FF, 0x01FF, 0x0000 }, /* R32 - Left input mixer volume */ 835 [33] = { 0x01FF, 0x01FF, 0x0000 }, /* R33 - Right input mixer volume */ 836 [34] = { 0x003F, 0x003F, 0x0000 }, /* R34 - Input mixer control (2) */ 837 [35] = { 0x003F, 0x003F, 0x0000 }, /* R35 - Input bias control */ 838 [37] = { 0x001F, 0x001F, 0x0000 }, /* R37 - Left input PGA control */ 839 [38] = { 0x001F, 0x001F, 0x0000 }, /* R38 - Right input PGA control */ 840 [40] = { 0x00FF, 0x01FF, 0x0000 }, /* R40 - SPKOUTL volume */ 841 [41] = { 0x00FF, 0x01FF, 0x0000 }, /* R41 - SPKOUTR volume */ 842 843 [47] = { 0x000F, 0x0000, 0xFFFF }, /* R47 - Thermal Shutdown Status */ 844 [48] = { 0x7EC7, 0x7E07, 0xFFFF }, /* R48 - Additional Control (4) */ 845 [49] = { 0x00D3, 0x00D7, 0xFFFF }, /* R49 - Class D Control 1 */ 846 [51] = { 0x0047, 0x0047, 0x0000 }, /* R51 - Class D Control 2 */ 847 [56] = { 0x001E, 0x001E, 0x0000 }, /* R56 - Clocking 4 */ 848 [57] = { 0x02FC, 0x02FC, 0x0000 }, /* R57 - DAC DSP Mixing (1) */ 849 [58] = { 0x00FC, 0x00FC, 0x0000 }, /* R58 - DAC DSP Mixing (2) */ 850 [60] = { 0x00CC, 0x00CC, 0x0000 }, /* R60 - DC Servo 0 */ 851 [61] = { 0x00DD, 0x00DD, 0x0000 }, /* R61 - DC Servo 1 */ 852 [64] = { 0x3F80, 0x3F80, 0x0000 }, /* R64 - DC Servo 4 */ 853 [66] = { 0x0780, 0x0000, 0xFFFF }, /* R66 - DC Servo 6 */ 854 [68] = { 0x0007, 0x0007, 0x0000 }, /* R68 - Analogue PGA Bias */ 855 [69] = { 0x00FF, 0x00FF, 0x0000 }, /* R69 - Analogue HP 0 */ 856 [71] = { 0x01FF, 0x01FF, 0x0000 }, /* R71 - Analogue HP 2 */ 857 [72] = { 0x0001, 0x0001, 0x0000 }, /* R72 - Charge Pump 1 */ 858 [82] = { 0x0001, 0x0001, 0x0000 }, /* R82 - Charge Pump B */ 859 [87] = { 0x00A0, 0x00A0, 0x0000 }, /* R87 - Write Sequencer Control 1 */ 860 [90] = { 0x007F, 0x01FF, 0x0000 }, /* R90 - Write Sequencer Control 2 */ 861 [93] = { 0x03F9, 0x0000, 0x0000 }, /* R93 - Write Sequencer Control 3 */ 862 [94] = { 0x0070, 0x0070, 0x0000 }, /* R94 - Control Interface */ 863 [99] = { 0x000F, 0x000F, 0x0000 }, /* R99 - Mixer Enables */ 864 [100] = { 0x00BF, 0x00BF, 0x0000 }, /* R100 - Headphone Mixer (1) */ 865 [101] = { 0x00BF, 0x00BF, 0x0000 }, /* R101 - Headphone Mixer (2) */ 866 [102] = { 0x01FF, 0x01FF, 0x0000 }, /* R102 - Headphone Mixer (3) */ 867 [103] = { 0x01FF, 0x01FF, 0x0000 }, /* R103 - Headphone Mixer (4) */ 868 [105] = { 0x00BF, 0x00BF, 0x0000 }, /* R105 - Speaker Mixer (1) */ 869 [106] = { 0x00BF, 0x00BF, 0x0000 }, /* R106 - Speaker Mixer (2) */ 870 [107] = { 0x01FF, 0x01FF, 0x0000 }, /* R107 - Speaker Mixer (3) */ 871 [108] = { 0x01FF, 0x01FF, 0x0000 }, /* R108 - Speaker Mixer (4) */ 872 [109] = { 0x00F0, 0x00F0, 0x0000 }, /* R109 - Speaker Mixer (5) */ 873 [110] = { 0x00F7, 0x00F7, 0x0000 }, /* R110 - Beep Generator (1) */ 874 [115] = { 0x001F, 0x001F, 0x0000 }, /* R115 - Oscillator Trim (3) */ 875 [116] = { 0x001F, 0x001F, 0x0000 }, /* R116 - Oscillator Trim (4) */ 876 [119] = { 0x00FF, 0x00FF, 0x0000 }, /* R119 - Oscillator Trim (7) */ 877 [124] = { 0x0079, 0x0079, 0x0000 }, /* R124 - Analogue Clocking1 */ 878 [125] = { 0x00DF, 0x00DF, 0x0000 }, /* R125 - Analogue Clocking2 */ 879 [126] = { 0x000D, 0x000D, 0x0000 }, /* R126 - Analogue Clocking3 */ 880 [127] = { 0x0000, 0xFFFF, 0x0000 }, /* R127 - PLL Software Reset */ 881 [129] = { 0x00B0, 0x00B0, 0x0000 }, /* R129 - PLL2 */ 882 [131] = { 0x0003, 0x0003, 0x0000 }, /* R131 - PLL 4 */ 883 [136] = { 0x005F, 0x005F, 0x0000 }, /* R136 - PLL 9 */ 884 [137] = { 0x00FF, 0x00FF, 0x0000 }, /* R137 - PLL 10 */ 885 [138] = { 0x00FF, 0x00FF, 0x0000 }, /* R138 - PLL 11 */ 886 [139] = { 0x00FF, 0x00FF, 0x0000 }, /* R139 - PLL 12 */ 887 [140] = { 0x005F, 0x005F, 0x0000 }, /* R140 - PLL 13 */ 888 [141] = { 0x00FF, 0x00FF, 0x0000 }, /* R141 - PLL 14 */ 889 [142] = { 0x00FF, 0x00FF, 0x0000 }, /* R142 - PLL 15 */ 890 [143] = { 0x00FF, 0x00FF, 0x0000 }, /* R143 - PLL 16 */ 891 [155] = { 0x0067, 0x0067, 0x0000 }, /* R155 - FLL Control (1) */ 892 [156] = { 0x01FB, 0x01FB, 0x0000 }, /* R156 - FLL Control (2) */ 893 [157] = { 0x0007, 0x0007, 0x0000 }, /* R157 - FLL Control (3) */ 894 [159] = { 0x007F, 0x007F, 0x0000 }, /* R159 - FLL Control (5) */ 895 [160] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R160 - FLL Control (6) */ 896 [161] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R161 - FLL Control (7) */ 897 [162] = { 0x03FF, 0x03FF, 0x0000 }, /* R162 - FLL Control (8) */ 898 [252] = { 0x0005, 0x0005, 0x0000 }, /* R252 - General test 1 */ 899 [256] = { 0x000F, 0x000F, 0x0000 }, /* R256 - DF1 */ 900 [257] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R257 - DF2 */ 901 [258] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R258 - DF3 */ 902 [259] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R259 - DF4 */ 903 [260] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R260 - DF5 */ 904 [261] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R261 - DF6 */ 905 [262] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R262 - DF7 */ 906 [264] = { 0x0003, 0x0003, 0x0000 }, /* R264 - LHPF1 */ 907 [265] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R265 - LHPF2 */ 908 [268] = { 0x0077, 0x0077, 0x0000 }, /* R268 - THREED1 */ 909 [269] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R269 - THREED2 */ 910 [270] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R270 - THREED3 */ 911 [271] = { 0xFFFC, 0xFFFC, 0x0000 }, /* R271 - THREED4 */ 912 [276] = { 0x7FFF, 0x7FFF, 0x0000 }, /* R276 - DRC 1 */ 913 [277] = { 0x1FFF, 0x1FFF, 0x0000 }, /* R277 - DRC 2 */ 914 [278] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R278 - DRC 3 */ 915 [279] = { 0x07FF, 0x07FF, 0x0000 }, /* R279 - DRC 4 */ 916 [280] = { 0x03FF, 0x03FF, 0x0000 }, /* R280 - DRC 5 */ 917 [285] = { 0x0003, 0x0003, 0x0000 }, /* R285 - Tloopback */ 918 [335] = { 0x0007, 0x0007, 0x0000 }, /* R335 - EQ1 */ 919 [336] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R336 - EQ2 */ 920 [337] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R337 - EQ3 */ 921 [338] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R338 - EQ4 */ 922 [339] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R339 - EQ5 */ 923 [340] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R340 - EQ6 */ 924 [341] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R341 - EQ7 */ 925 [342] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R342 - EQ8 */ 926 [343] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R343 - EQ9 */ 927 [344] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R344 - EQ10 */ 928 [345] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R345 - EQ11 */ 929 [346] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R346 - EQ12 */ 930 [347] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R347 - EQ13 */ 931 [348] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R348 - EQ14 */ 932 [349] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R349 - EQ15 */ 933 [350] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R350 - EQ16 */ 934 [351] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R351 - EQ17 */ 935 [352] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R352 - EQ18 */ 936 [353] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R353 - EQ19 */ 937 [354] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R354 - EQ20 */ 938 [355] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R355 - EQ21 */ 939 [356] = { 0xFFFE, 0xFFFE, 0x0000 }, /* R356 - EQ22 */ 940 [357] = { 0xFFC0, 0xFFC0, 0x0000 }, /* R357 - EQ23 */ 941 [358] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R358 - EQ24 */ 942 [359] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R359 - EQ25 */ 943 [360] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R360 - EQ26 */ 944 [361] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R361 - EQ27 */ 945 [362] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R362 - EQ28 */ 946 [363] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R363 - EQ29 */ 947 [364] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R364 - EQ30 */ 948 [365] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R365 - EQ31 */ 949 [366] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R366 - EQ32 */ 950 [367] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R367 - EQ33 */ 951 [368] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R368 - EQ34 */ 952 [369] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R369 - EQ35 */ 953 [370] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R370 - EQ36 */ 954 [371] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R371 - EQ37 */ 955 [372] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R372 - EQ38 */ 956 [373] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R373 - EQ39 */ 957 [374] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R374 - EQ40 */ 958 [375] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R375 - EQ41 */ 959 [513] = { 0x045F, 0x045F, 0x0000 }, /* R513 - GPIO 2 */ 960 [514] = { 0x045F, 0x045F, 0x0000 }, /* R514 - GPIO 3 */ 961 [516] = { 0xE75F, 0xE75F, 0x0000 }, /* R516 - GPIO 5 */ 962 [517] = { 0xE75F, 0xE75F, 0x0000 }, /* R517 - GPIO 6 */ 963 [560] = { 0x0030, 0x0030, 0xFFFF }, /* R560 - Interrupt Status 1 */ 964 [561] = { 0xFFED, 0xFFED, 0xFFFF }, /* R561 - Interrupt Status 2 */ 965 [568] = { 0x0030, 0x0030, 0x0000 }, /* R568 - Interrupt Status 1 Mask */ 966 [569] = { 0xFFED, 0xFFED, 0x0000 }, /* R569 - Interrupt Status 2 Mask */ 967 [576] = { 0x0001, 0x0001, 0x0000 }, /* R576 - Interrupt Control */ 968 [584] = { 0x002D, 0x002D, 0x0000 }, /* R584 - IRQ Debounce */ 969 [586] = { 0xC000, 0xC000, 0x0000 }, /* R586 - MICINT Source Pol */ 970 [768] = { 0x0001, 0x0001, 0x0000 }, /* R768 - DSP2 Power Management */ 971 [1037] = { 0x0000, 0x003F, 0xFFFF }, /* R1037 - DSP2_ExecControl */ 972 [4096] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4096 - Write Sequencer 0 */ 973 [4097] = { 0x00FF, 0x00FF, 0x0000 }, /* R4097 - Write Sequencer 1 */ 974 [4098] = { 0x070F, 0x070F, 0x0000 }, /* R4098 - Write Sequencer 2 */ 975 [4099] = { 0x010F, 0x010F, 0x0000 }, /* R4099 - Write Sequencer 3 */ 976 [4100] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4100 - Write Sequencer 4 */ 977 [4101] = { 0x00FF, 0x00FF, 0x0000 }, /* R4101 - Write Sequencer 5 */ 978 [4102] = { 0x070F, 0x070F, 0x0000 }, /* R4102 - Write Sequencer 6 */ 979 [4103] = { 0x010F, 0x010F, 0x0000 }, /* R4103 - Write Sequencer 7 */ 980 [4104] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4104 - Write Sequencer 8 */ 981 [4105] = { 0x00FF, 0x00FF, 0x0000 }, /* R4105 - Write Sequencer 9 */ 982 [4106] = { 0x070F, 0x070F, 0x0000 }, /* R4106 - Write Sequencer 10 */ 983 [4107] = { 0x010F, 0x010F, 0x0000 }, /* R4107 - Write Sequencer 11 */ 984 [4108] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4108 - Write Sequencer 12 */ 985 [4109] = { 0x00FF, 0x00FF, 0x0000 }, /* R4109 - Write Sequencer 13 */ 986 [4110] = { 0x070F, 0x070F, 0x0000 }, /* R4110 - Write Sequencer 14 */ 987 [4111] = { 0x010F, 0x010F, 0x0000 }, /* R4111 - Write Sequencer 15 */ 988 [4112] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4112 - Write Sequencer 16 */ 989 [4113] = { 0x00FF, 0x00FF, 0x0000 }, /* R4113 - Write Sequencer 17 */ 990 [4114] = { 0x070F, 0x070F, 0x0000 }, /* R4114 - Write Sequencer 18 */ 991 [4115] = { 0x010F, 0x010F, 0x0000 }, /* R4115 - Write Sequencer 19 */ 992 [4116] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4116 - Write Sequencer 20 */ 993 [4117] = { 0x00FF, 0x00FF, 0x0000 }, /* R4117 - Write Sequencer 21 */ 994 [4118] = { 0x070F, 0x070F, 0x0000 }, /* R4118 - Write Sequencer 22 */ 995 [4119] = { 0x010F, 0x010F, 0x0000 }, /* R4119 - Write Sequencer 23 */ 996 [4120] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4120 - Write Sequencer 24 */ 997 [4121] = { 0x00FF, 0x00FF, 0x0000 }, /* R4121 - Write Sequencer 25 */ 998 [4122] = { 0x070F, 0x070F, 0x0000 }, /* R4122 - Write Sequencer 26 */ 999 [4123] = { 0x010F, 0x010F, 0x0000 }, /* R4123 - Write Sequencer 27 */ 1000 [4124] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4124 - Write Sequencer 28 */ 1001 [4125] = { 0x00FF, 0x00FF, 0x0000 }, /* R4125 - Write Sequencer 29 */ 1002 [4126] = { 0x070F, 0x070F, 0x0000 }, /* R4126 - Write Sequencer 30 */ 1003 [4127] = { 0x010F, 0x010F, 0x0000 }, /* R4127 - Write Sequencer 31 */ 1004 [4128] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4128 - Write Sequencer 32 */ 1005 [4129] = { 0x00FF, 0x00FF, 0x0000 }, /* R4129 - Write Sequencer 33 */ 1006 [4130] = { 0x070F, 0x070F, 0x0000 }, /* R4130 - Write Sequencer 34 */ 1007 [4131] = { 0x010F, 0x010F, 0x0000 }, /* R4131 - Write Sequencer 35 */ 1008 [4132] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4132 - Write Sequencer 36 */ 1009 [4133] = { 0x00FF, 0x00FF, 0x0000 }, /* R4133 - Write Sequencer 37 */ 1010 [4134] = { 0x070F, 0x070F, 0x0000 }, /* R4134 - Write Sequencer 38 */ 1011 [4135] = { 0x010F, 0x010F, 0x0000 }, /* R4135 - Write Sequencer 39 */ 1012 [4136] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4136 - Write Sequencer 40 */ 1013 [4137] = { 0x00FF, 0x00FF, 0x0000 }, /* R4137 - Write Sequencer 41 */ 1014 [4138] = { 0x070F, 0x070F, 0x0000 }, /* R4138 - Write Sequencer 42 */ 1015 [4139] = { 0x010F, 0x010F, 0x0000 }, /* R4139 - Write Sequencer 43 */ 1016 [4140] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4140 - Write Sequencer 44 */ 1017 [4141] = { 0x00FF, 0x00FF, 0x0000 }, /* R4141 - Write Sequencer 45 */ 1018 [4142] = { 0x070F, 0x070F, 0x0000 }, /* R4142 - Write Sequencer 46 */ 1019 [4143] = { 0x010F, 0x010F, 0x0000 }, /* R4143 - Write Sequencer 47 */ 1020 [4144] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4144 - Write Sequencer 48 */ 1021 [4145] = { 0x00FF, 0x00FF, 0x0000 }, /* R4145 - Write Sequencer 49 */ 1022 [4146] = { 0x070F, 0x070F, 0x0000 }, /* R4146 - Write Sequencer 50 */ 1023 [4147] = { 0x010F, 0x010F, 0x0000 }, /* R4147 - Write Sequencer 51 */ 1024 [4148] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4148 - Write Sequencer 52 */ 1025 [4149] = { 0x00FF, 0x00FF, 0x0000 }, /* R4149 - Write Sequencer 53 */ 1026 [4150] = { 0x070F, 0x070F, 0x0000 }, /* R4150 - Write Sequencer 54 */ 1027 [4151] = { 0x010F, 0x010F, 0x0000 }, /* R4151 - Write Sequencer 55 */ 1028 [4152] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4152 - Write Sequencer 56 */ 1029 [4153] = { 0x00FF, 0x00FF, 0x0000 }, /* R4153 - Write Sequencer 57 */ 1030 [4154] = { 0x070F, 0x070F, 0x0000 }, /* R4154 - Write Sequencer 58 */ 1031 [4155] = { 0x010F, 0x010F, 0x0000 }, /* R4155 - Write Sequencer 59 */ 1032 [4156] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4156 - Write Sequencer 60 */ 1033 [4157] = { 0x00FF, 0x00FF, 0x0000 }, /* R4157 - Write Sequencer 61 */ 1034 [4158] = { 0x070F, 0x070F, 0x0000 }, /* R4158 - Write Sequencer 62 */ 1035 [4159] = { 0x010F, 0x010F, 0x0000 }, /* R4159 - Write Sequencer 63 */ 1036 [4160] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4160 - Write Sequencer 64 */ 1037 [4161] = { 0x00FF, 0x00FF, 0x0000 }, /* R4161 - Write Sequencer 65 */ 1038 [4162] = { 0x070F, 0x070F, 0x0000 }, /* R4162 - Write Sequencer 66 */ 1039 [4163] = { 0x010F, 0x010F, 0x0000 }, /* R4163 - Write Sequencer 67 */ 1040 [4164] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4164 - Write Sequencer 68 */ 1041 [4165] = { 0x00FF, 0x00FF, 0x0000 }, /* R4165 - Write Sequencer 69 */ 1042 [4166] = { 0x070F, 0x070F, 0x0000 }, /* R4166 - Write Sequencer 70 */ 1043 [4167] = { 0x010F, 0x010F, 0x0000 }, /* R4167 - Write Sequencer 71 */ 1044 [4168] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4168 - Write Sequencer 72 */ 1045 [4169] = { 0x00FF, 0x00FF, 0x0000 }, /* R4169 - Write Sequencer 73 */ 1046 [4170] = { 0x070F, 0x070F, 0x0000 }, /* R4170 - Write Sequencer 74 */ 1047 [4171] = { 0x010F, 0x010F, 0x0000 }, /* R4171 - Write Sequencer 75 */ 1048 [4172] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4172 - Write Sequencer 76 */ 1049 [4173] = { 0x00FF, 0x00FF, 0x0000 }, /* R4173 - Write Sequencer 77 */ 1050 [4174] = { 0x070F, 0x070F, 0x0000 }, /* R4174 - Write Sequencer 78 */ 1051 [4175] = { 0x010F, 0x010F, 0x0000 }, /* R4175 - Write Sequencer 79 */ 1052 [4176] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4176 - Write Sequencer 80 */ 1053 [4177] = { 0x00FF, 0x00FF, 0x0000 }, /* R4177 - Write Sequencer 81 */ 1054 [4178] = { 0x070F, 0x070F, 0x0000 }, /* R4178 - Write Sequencer 82 */ 1055 [4179] = { 0x010F, 0x010F, 0x0000 }, /* R4179 - Write Sequencer 83 */ 1056 [4180] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4180 - Write Sequencer 84 */ 1057 [4181] = { 0x00FF, 0x00FF, 0x0000 }, /* R4181 - Write Sequencer 85 */ 1058 [4182] = { 0x070F, 0x070F, 0x0000 }, /* R4182 - Write Sequencer 86 */ 1059 [4183] = { 0x010F, 0x010F, 0x0000 }, /* R4183 - Write Sequencer 87 */ 1060 [4184] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4184 - Write Sequencer 88 */ 1061 [4185] = { 0x00FF, 0x00FF, 0x0000 }, /* R4185 - Write Sequencer 89 */ 1062 [4186] = { 0x070F, 0x070F, 0x0000 }, /* R4186 - Write Sequencer 90 */ 1063 [4187] = { 0x010F, 0x010F, 0x0000 }, /* R4187 - Write Sequencer 91 */ 1064 [4188] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4188 - Write Sequencer 92 */ 1065 [4189] = { 0x00FF, 0x00FF, 0x0000 }, /* R4189 - Write Sequencer 93 */ 1066 [4190] = { 0x070F, 0x070F, 0x0000 }, /* R4190 - Write Sequencer 94 */ 1067 [4191] = { 0x010F, 0x010F, 0x0000 }, /* R4191 - Write Sequencer 95 */ 1068 [4192] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4192 - Write Sequencer 96 */ 1069 [4193] = { 0x00FF, 0x00FF, 0x0000 }, /* R4193 - Write Sequencer 97 */ 1070 [4194] = { 0x070F, 0x070F, 0x0000 }, /* R4194 - Write Sequencer 98 */ 1071 [4195] = { 0x010F, 0x010F, 0x0000 }, /* R4195 - Write Sequencer 99 */ 1072 [4196] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4196 - Write Sequencer 100 */ 1073 [4197] = { 0x00FF, 0x00FF, 0x0000 }, /* R4197 - Write Sequencer 101 */ 1074 [4198] = { 0x070F, 0x070F, 0x0000 }, /* R4198 - Write Sequencer 102 */ 1075 [4199] = { 0x010F, 0x010F, 0x0000 }, /* R4199 - Write Sequencer 103 */ 1076 [4200] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4200 - Write Sequencer 104 */ 1077 [4201] = { 0x00FF, 0x00FF, 0x0000 }, /* R4201 - Write Sequencer 105 */ 1078 [4202] = { 0x070F, 0x070F, 0x0000 }, /* R4202 - Write Sequencer 106 */ 1079 [4203] = { 0x010F, 0x010F, 0x0000 }, /* R4203 - Write Sequencer 107 */ 1080 [4204] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4204 - Write Sequencer 108 */ 1081 [4205] = { 0x00FF, 0x00FF, 0x0000 }, /* R4205 - Write Sequencer 109 */ 1082 [4206] = { 0x070F, 0x070F, 0x0000 }, /* R4206 - Write Sequencer 110 */ 1083 [4207] = { 0x010F, 0x010F, 0x0000 }, /* R4207 - Write Sequencer 111 */ 1084 [4208] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4208 - Write Sequencer 112 */ 1085 [4209] = { 0x00FF, 0x00FF, 0x0000 }, /* R4209 - Write Sequencer 113 */ 1086 [4210] = { 0x070F, 0x070F, 0x0000 }, /* R4210 - Write Sequencer 114 */ 1087 [4211] = { 0x010F, 0x010F, 0x0000 }, /* R4211 - Write Sequencer 115 */ 1088 [4212] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4212 - Write Sequencer 116 */ 1089 [4213] = { 0x00FF, 0x00FF, 0x0000 }, /* R4213 - Write Sequencer 117 */ 1090 [4214] = { 0x070F, 0x070F, 0x0000 }, /* R4214 - Write Sequencer 118 */ 1091 [4215] = { 0x010F, 0x010F, 0x0000 }, /* R4215 - Write Sequencer 119 */ 1092 [4216] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4216 - Write Sequencer 120 */ 1093 [4217] = { 0x00FF, 0x00FF, 0x0000 }, /* R4217 - Write Sequencer 121 */ 1094 [4218] = { 0x070F, 0x070F, 0x0000 }, /* R4218 - Write Sequencer 122 */ 1095 [4219] = { 0x010F, 0x010F, 0x0000 }, /* R4219 - Write Sequencer 123 */ 1096 [4220] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4220 - Write Sequencer 124 */ 1097 [4221] = { 0x00FF, 0x00FF, 0x0000 }, /* R4221 - Write Sequencer 125 */ 1098 [4222] = { 0x070F, 0x070F, 0x0000 }, /* R4222 - Write Sequencer 126 */ 1099 [4223] = { 0x010F, 0x010F, 0x0000 }, /* R4223 - Write Sequencer 127 */ 1100 [4224] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4224 - Write Sequencer 128 */ 1101 [4225] = { 0x00FF, 0x00FF, 0x0000 }, /* R4225 - Write Sequencer 129 */ 1102 [4226] = { 0x070F, 0x070F, 0x0000 }, /* R4226 - Write Sequencer 130 */ 1103 [4227] = { 0x010F, 0x010F, 0x0000 }, /* R4227 - Write Sequencer 131 */ 1104 [4228] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4228 - Write Sequencer 132 */ 1105 [4229] = { 0x00FF, 0x00FF, 0x0000 }, /* R4229 - Write Sequencer 133 */ 1106 [4230] = { 0x070F, 0x070F, 0x0000 }, /* R4230 - Write Sequencer 134 */ 1107 [4231] = { 0x010F, 0x010F, 0x0000 }, /* R4231 - Write Sequencer 135 */ 1108 [4232] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4232 - Write Sequencer 136 */ 1109 [4233] = { 0x00FF, 0x00FF, 0x0000 }, /* R4233 - Write Sequencer 137 */ 1110 [4234] = { 0x070F, 0x070F, 0x0000 }, /* R4234 - Write Sequencer 138 */ 1111 [4235] = { 0x010F, 0x010F, 0x0000 }, /* R4235 - Write Sequencer 139 */ 1112 [4236] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4236 - Write Sequencer 140 */ 1113 [4237] = { 0x00FF, 0x00FF, 0x0000 }, /* R4237 - Write Sequencer 141 */ 1114 [4238] = { 0x070F, 0x070F, 0x0000 }, /* R4238 - Write Sequencer 142 */ 1115 [4239] = { 0x010F, 0x010F, 0x0000 }, /* R4239 - Write Sequencer 143 */ 1116 [4240] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4240 - Write Sequencer 144 */ 1117 [4241] = { 0x00FF, 0x00FF, 0x0000 }, /* R4241 - Write Sequencer 145 */ 1118 [4242] = { 0x070F, 0x070F, 0x0000 }, /* R4242 - Write Sequencer 146 */ 1119 [4243] = { 0x010F, 0x010F, 0x0000 }, /* R4243 - Write Sequencer 147 */ 1120 [4244] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4244 - Write Sequencer 148 */ 1121 [4245] = { 0x00FF, 0x00FF, 0x0000 }, /* R4245 - Write Sequencer 149 */ 1122 [4246] = { 0x070F, 0x070F, 0x0000 }, /* R4246 - Write Sequencer 150 */ 1123 [4247] = { 0x010F, 0x010F, 0x0000 }, /* R4247 - Write Sequencer 151 */ 1124 [4248] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4248 - Write Sequencer 152 */ 1125 [4249] = { 0x00FF, 0x00FF, 0x0000 }, /* R4249 - Write Sequencer 153 */ 1126 [4250] = { 0x070F, 0x070F, 0x0000 }, /* R4250 - Write Sequencer 154 */ 1127 [4251] = { 0x010F, 0x010F, 0x0000 }, /* R4251 - Write Sequencer 155 */ 1128 [4252] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4252 - Write Sequencer 156 */ 1129 [4253] = { 0x00FF, 0x00FF, 0x0000 }, /* R4253 - Write Sequencer 157 */ 1130 [4254] = { 0x070F, 0x070F, 0x0000 }, /* R4254 - Write Sequencer 158 */ 1131 [4255] = { 0x010F, 0x010F, 0x0000 }, /* R4255 - Write Sequencer 159 */ 1132 [4256] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4256 - Write Sequencer 160 */ 1133 [4257] = { 0x00FF, 0x00FF, 0x0000 }, /* R4257 - Write Sequencer 161 */ 1134 [4258] = { 0x070F, 0x070F, 0x0000 }, /* R4258 - Write Sequencer 162 */ 1135 [4259] = { 0x010F, 0x010F, 0x0000 }, /* R4259 - Write Sequencer 163 */ 1136 [4260] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4260 - Write Sequencer 164 */ 1137 [4261] = { 0x00FF, 0x00FF, 0x0000 }, /* R4261 - Write Sequencer 165 */ 1138 [4262] = { 0x070F, 0x070F, 0x0000 }, /* R4262 - Write Sequencer 166 */ 1139 [4263] = { 0x010F, 0x010F, 0x0000 }, /* R4263 - Write Sequencer 167 */ 1140 [4264] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4264 - Write Sequencer 168 */ 1141 [4265] = { 0x00FF, 0x00FF, 0x0000 }, /* R4265 - Write Sequencer 169 */ 1142 [4266] = { 0x070F, 0x070F, 0x0000 }, /* R4266 - Write Sequencer 170 */ 1143 [4267] = { 0x010F, 0x010F, 0x0000 }, /* R4267 - Write Sequencer 171 */ 1144 [4268] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4268 - Write Sequencer 172 */ 1145 [4269] = { 0x00FF, 0x00FF, 0x0000 }, /* R4269 - Write Sequencer 173 */ 1146 [4270] = { 0x070F, 0x070F, 0x0000 }, /* R4270 - Write Sequencer 174 */ 1147 [4271] = { 0x010F, 0x010F, 0x0000 }, /* R4271 - Write Sequencer 175 */ 1148 [4272] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4272 - Write Sequencer 176 */ 1149 [4273] = { 0x00FF, 0x00FF, 0x0000 }, /* R4273 - Write Sequencer 177 */ 1150 [4274] = { 0x070F, 0x070F, 0x0000 }, /* R4274 - Write Sequencer 178 */ 1151 [4275] = { 0x010F, 0x010F, 0x0000 }, /* R4275 - Write Sequencer 179 */ 1152 [4276] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4276 - Write Sequencer 180 */ 1153 [4277] = { 0x00FF, 0x00FF, 0x0000 }, /* R4277 - Write Sequencer 181 */ 1154 [4278] = { 0x070F, 0x070F, 0x0000 }, /* R4278 - Write Sequencer 182 */ 1155 [4279] = { 0x010F, 0x010F, 0x0000 }, /* R4279 - Write Sequencer 183 */ 1156 [4280] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4280 - Write Sequencer 184 */ 1157 [4281] = { 0x00FF, 0x00FF, 0x0000 }, /* R4281 - Write Sequencer 185 */ 1158 [4282] = { 0x070F, 0x070F, 0x0000 }, /* R4282 - Write Sequencer 186 */ 1159 [4283] = { 0x010F, 0x010F, 0x0000 }, /* R4283 - Write Sequencer 187 */ 1160 [4284] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4284 - Write Sequencer 188 */ 1161 [4285] = { 0x00FF, 0x00FF, 0x0000 }, /* R4285 - Write Sequencer 189 */ 1162 [4286] = { 0x070F, 0x070F, 0x0000 }, /* R4286 - Write Sequencer 190 */ 1163 [4287] = { 0x010F, 0x010F, 0x0000 }, /* R4287 - Write Sequencer 191 */ 1164 [4288] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4288 - Write Sequencer 192 */ 1165 [4289] = { 0x00FF, 0x00FF, 0x0000 }, /* R4289 - Write Sequencer 193 */ 1166 [4290] = { 0x070F, 0x070F, 0x0000 }, /* R4290 - Write Sequencer 194 */ 1167 [4291] = { 0x010F, 0x010F, 0x0000 }, /* R4291 - Write Sequencer 195 */ 1168 [4292] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4292 - Write Sequencer 196 */ 1169 [4293] = { 0x00FF, 0x00FF, 0x0000 }, /* R4293 - Write Sequencer 197 */ 1170 [4294] = { 0x070F, 0x070F, 0x0000 }, /* R4294 - Write Sequencer 198 */ 1171 [4295] = { 0x010F, 0x010F, 0x0000 }, /* R4295 - Write Sequencer 199 */ 1172 [4296] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4296 - Write Sequencer 200 */ 1173 [4297] = { 0x00FF, 0x00FF, 0x0000 }, /* R4297 - Write Sequencer 201 */ 1174 [4298] = { 0x070F, 0x070F, 0x0000 }, /* R4298 - Write Sequencer 202 */ 1175 [4299] = { 0x010F, 0x010F, 0x0000 }, /* R4299 - Write Sequencer 203 */ 1176 [4300] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4300 - Write Sequencer 204 */ 1177 [4301] = { 0x00FF, 0x00FF, 0x0000 }, /* R4301 - Write Sequencer 205 */ 1178 [4302] = { 0x070F, 0x070F, 0x0000 }, /* R4302 - Write Sequencer 206 */ 1179 [4303] = { 0x010F, 0x010F, 0x0000 }, /* R4303 - Write Sequencer 207 */ 1180 [4304] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4304 - Write Sequencer 208 */ 1181 [4305] = { 0x00FF, 0x00FF, 0x0000 }, /* R4305 - Write Sequencer 209 */ 1182 [4306] = { 0x070F, 0x070F, 0x0000 }, /* R4306 - Write Sequencer 210 */ 1183 [4307] = { 0x010F, 0x010F, 0x0000 }, /* R4307 - Write Sequencer 211 */ 1184 [4308] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4308 - Write Sequencer 212 */ 1185 [4309] = { 0x00FF, 0x00FF, 0x0000 }, /* R4309 - Write Sequencer 213 */ 1186 [4310] = { 0x070F, 0x070F, 0x0000 }, /* R4310 - Write Sequencer 214 */ 1187 [4311] = { 0x010F, 0x010F, 0x0000 }, /* R4311 - Write Sequencer 215 */ 1188 [4312] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4312 - Write Sequencer 216 */ 1189 [4313] = { 0x00FF, 0x00FF, 0x0000 }, /* R4313 - Write Sequencer 217 */ 1190 [4314] = { 0x070F, 0x070F, 0x0000 }, /* R4314 - Write Sequencer 218 */ 1191 [4315] = { 0x010F, 0x010F, 0x0000 }, /* R4315 - Write Sequencer 219 */ 1192 [4316] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4316 - Write Sequencer 220 */ 1193 [4317] = { 0x00FF, 0x00FF, 0x0000 }, /* R4317 - Write Sequencer 221 */ 1194 [4318] = { 0x070F, 0x070F, 0x0000 }, /* R4318 - Write Sequencer 222 */ 1195 [4319] = { 0x010F, 0x010F, 0x0000 }, /* R4319 - Write Sequencer 223 */ 1196 [4320] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4320 - Write Sequencer 224 */ 1197 [4321] = { 0x00FF, 0x00FF, 0x0000 }, /* R4321 - Write Sequencer 225 */ 1198 [4322] = { 0x070F, 0x070F, 0x0000 }, /* R4322 - Write Sequencer 226 */ 1199 [4323] = { 0x010F, 0x010F, 0x0000 }, /* R4323 - Write Sequencer 227 */ 1200 [4324] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4324 - Write Sequencer 228 */ 1201 [4325] = { 0x00FF, 0x00FF, 0x0000 }, /* R4325 - Write Sequencer 229 */ 1202 [4326] = { 0x070F, 0x070F, 0x0000 }, /* R4326 - Write Sequencer 230 */ 1203 [4327] = { 0x010F, 0x010F, 0x0000 }, /* R4327 - Write Sequencer 231 */ 1204 [4328] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4328 - Write Sequencer 232 */ 1205 [4329] = { 0x00FF, 0x00FF, 0x0000 }, /* R4329 - Write Sequencer 233 */ 1206 [4330] = { 0x070F, 0x070F, 0x0000 }, /* R4330 - Write Sequencer 234 */ 1207 [4331] = { 0x010F, 0x010F, 0x0000 }, /* R4331 - Write Sequencer 235 */ 1208 [4332] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4332 - Write Sequencer 236 */ 1209 [4333] = { 0x00FF, 0x00FF, 0x0000 }, /* R4333 - Write Sequencer 237 */ 1210 [4334] = { 0x070F, 0x070F, 0x0000 }, /* R4334 - Write Sequencer 238 */ 1211 [4335] = { 0x010F, 0x010F, 0x0000 }, /* R4335 - Write Sequencer 239 */ 1212 [4336] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4336 - Write Sequencer 240 */ 1213 [4337] = { 0x00FF, 0x00FF, 0x0000 }, /* R4337 - Write Sequencer 241 */ 1214 [4338] = { 0x070F, 0x070F, 0x0000 }, /* R4338 - Write Sequencer 242 */ 1215 [4339] = { 0x010F, 0x010F, 0x0000 }, /* R4339 - Write Sequencer 243 */ 1216 [4340] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4340 - Write Sequencer 244 */ 1217 [4341] = { 0x00FF, 0x00FF, 0x0000 }, /* R4341 - Write Sequencer 245 */ 1218 [4342] = { 0x070F, 0x070F, 0x0000 }, /* R4342 - Write Sequencer 246 */ 1219 [4343] = { 0x010F, 0x010F, 0x0000 }, /* R4343 - Write Sequencer 247 */ 1220 [4344] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4344 - Write Sequencer 248 */ 1221 [4345] = { 0x00FF, 0x00FF, 0x0000 }, /* R4345 - Write Sequencer 249 */ 1222 [4346] = { 0x070F, 0x070F, 0x0000 }, /* R4346 - Write Sequencer 250 */ 1223 [4347] = { 0x010F, 0x010F, 0x0000 }, /* R4347 - Write Sequencer 251 */ 1224 [4348] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4348 - Write Sequencer 252 */ 1225 [4349] = { 0x00FF, 0x00FF, 0x0000 }, /* R4349 - Write Sequencer 253 */ 1226 [4350] = { 0x070F, 0x070F, 0x0000 }, /* R4350 - Write Sequencer 254 */ 1227 [4351] = { 0x010F, 0x010F, 0x0000 }, /* R4351 - Write Sequencer 255 */ 1228 [4352] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4352 - Write Sequencer 256 */ 1229 [4353] = { 0x00FF, 0x00FF, 0x0000 }, /* R4353 - Write Sequencer 257 */ 1230 [4354] = { 0x070F, 0x070F, 0x0000 }, /* R4354 - Write Sequencer 258 */ 1231 [4355] = { 0x010F, 0x010F, 0x0000 }, /* R4355 - Write Sequencer 259 */ 1232 [4356] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4356 - Write Sequencer 260 */ 1233 [4357] = { 0x00FF, 0x00FF, 0x0000 }, /* R4357 - Write Sequencer 261 */ 1234 [4358] = { 0x070F, 0x070F, 0x0000 }, /* R4358 - Write Sequencer 262 */ 1235 [4359] = { 0x010F, 0x010F, 0x0000 }, /* R4359 - Write Sequencer 263 */ 1236 [4360] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4360 - Write Sequencer 264 */ 1237 [4361] = { 0x00FF, 0x00FF, 0x0000 }, /* R4361 - Write Sequencer 265 */ 1238 [4362] = { 0x070F, 0x070F, 0x0000 }, /* R4362 - Write Sequencer 266 */ 1239 [4363] = { 0x010F, 0x010F, 0x0000 }, /* R4363 - Write Sequencer 267 */ 1240 [4364] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4364 - Write Sequencer 268 */ 1241 [4365] = { 0x00FF, 0x00FF, 0x0000 }, /* R4365 - Write Sequencer 269 */ 1242 [4366] = { 0x070F, 0x070F, 0x0000 }, /* R4366 - Write Sequencer 270 */ 1243 [4367] = { 0x010F, 0x010F, 0x0000 }, /* R4367 - Write Sequencer 271 */ 1244 [4368] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4368 - Write Sequencer 272 */ 1245 [4369] = { 0x00FF, 0x00FF, 0x0000 }, /* R4369 - Write Sequencer 273 */ 1246 [4370] = { 0x070F, 0x070F, 0x0000 }, /* R4370 - Write Sequencer 274 */ 1247 [4371] = { 0x010F, 0x010F, 0x0000 }, /* R4371 - Write Sequencer 275 */ 1248 [4372] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4372 - Write Sequencer 276 */ 1249 [4373] = { 0x00FF, 0x00FF, 0x0000 }, /* R4373 - Write Sequencer 277 */ 1250 [4374] = { 0x070F, 0x070F, 0x0000 }, /* R4374 - Write Sequencer 278 */ 1251 [4375] = { 0x010F, 0x010F, 0x0000 }, /* R4375 - Write Sequencer 279 */ 1252 [4376] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4376 - Write Sequencer 280 */ 1253 [4377] = { 0x00FF, 0x00FF, 0x0000 }, /* R4377 - Write Sequencer 281 */ 1254 [4378] = { 0x070F, 0x070F, 0x0000 }, /* R4378 - Write Sequencer 282 */ 1255 [4379] = { 0x010F, 0x010F, 0x0000 }, /* R4379 - Write Sequencer 283 */ 1256 [4380] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4380 - Write Sequencer 284 */ 1257 [4381] = { 0x00FF, 0x00FF, 0x0000 }, /* R4381 - Write Sequencer 285 */ 1258 [4382] = { 0x070F, 0x070F, 0x0000 }, /* R4382 - Write Sequencer 286 */ 1259 [4383] = { 0x010F, 0x010F, 0x0000 }, /* R4383 - Write Sequencer 287 */ 1260 [4384] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4384 - Write Sequencer 288 */ 1261 [4385] = { 0x00FF, 0x00FF, 0x0000 }, /* R4385 - Write Sequencer 289 */ 1262 [4386] = { 0x070F, 0x070F, 0x0000 }, /* R4386 - Write Sequencer 290 */ 1263 [4387] = { 0x010F, 0x010F, 0x0000 }, /* R4387 - Write Sequencer 291 */ 1264 [4388] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4388 - Write Sequencer 292 */ 1265 [4389] = { 0x00FF, 0x00FF, 0x0000 }, /* R4389 - Write Sequencer 293 */ 1266 [4390] = { 0x070F, 0x070F, 0x0000 }, /* R4390 - Write Sequencer 294 */ 1267 [4391] = { 0x010F, 0x010F, 0x0000 }, /* R4391 - Write Sequencer 295 */ 1268 [4392] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4392 - Write Sequencer 296 */ 1269 [4393] = { 0x00FF, 0x00FF, 0x0000 }, /* R4393 - Write Sequencer 297 */ 1270 [4394] = { 0x070F, 0x070F, 0x0000 }, /* R4394 - Write Sequencer 298 */ 1271 [4395] = { 0x010F, 0x010F, 0x0000 }, /* R4395 - Write Sequencer 299 */ 1272 [4396] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4396 - Write Sequencer 300 */ 1273 [4397] = { 0x00FF, 0x00FF, 0x0000 }, /* R4397 - Write Sequencer 301 */ 1274 [4398] = { 0x070F, 0x070F, 0x0000 }, /* R4398 - Write Sequencer 302 */ 1275 [4399] = { 0x010F, 0x010F, 0x0000 }, /* R4399 - Write Sequencer 303 */ 1276 [4400] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4400 - Write Sequencer 304 */ 1277 [4401] = { 0x00FF, 0x00FF, 0x0000 }, /* R4401 - Write Sequencer 305 */ 1278 [4402] = { 0x070F, 0x070F, 0x0000 }, /* R4402 - Write Sequencer 306 */ 1279 [4403] = { 0x010F, 0x010F, 0x0000 }, /* R4403 - Write Sequencer 307 */ 1280 [4404] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4404 - Write Sequencer 308 */ 1281 [4405] = { 0x00FF, 0x00FF, 0x0000 }, /* R4405 - Write Sequencer 309 */ 1282 [4406] = { 0x070F, 0x070F, 0x0000 }, /* R4406 - Write Sequencer 310 */ 1283 [4407] = { 0x010F, 0x010F, 0x0000 }, /* R4407 - Write Sequencer 311 */ 1284 [4408] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4408 - Write Sequencer 312 */ 1285 [4409] = { 0x00FF, 0x00FF, 0x0000 }, /* R4409 - Write Sequencer 313 */ 1286 [4410] = { 0x070F, 0x070F, 0x0000 }, /* R4410 - Write Sequencer 314 */ 1287 [4411] = { 0x010F, 0x010F, 0x0000 }, /* R4411 - Write Sequencer 315 */ 1288 [4412] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4412 - Write Sequencer 316 */ 1289 [4413] = { 0x00FF, 0x00FF, 0x0000 }, /* R4413 - Write Sequencer 317 */ 1290 [4414] = { 0x070F, 0x070F, 0x0000 }, /* R4414 - Write Sequencer 318 */ 1291 [4415] = { 0x010F, 0x010F, 0x0000 }, /* R4415 - Write Sequencer 319 */ 1292 [4416] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4416 - Write Sequencer 320 */ 1293 [4417] = { 0x00FF, 0x00FF, 0x0000 }, /* R4417 - Write Sequencer 321 */ 1294 [4418] = { 0x070F, 0x070F, 0x0000 }, /* R4418 - Write Sequencer 322 */ 1295 [4419] = { 0x010F, 0x010F, 0x0000 }, /* R4419 - Write Sequencer 323 */ 1296 [4420] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4420 - Write Sequencer 324 */ 1297 [4421] = { 0x00FF, 0x00FF, 0x0000 }, /* R4421 - Write Sequencer 325 */ 1298 [4422] = { 0x070F, 0x070F, 0x0000 }, /* R4422 - Write Sequencer 326 */ 1299 [4423] = { 0x010F, 0x010F, 0x0000 }, /* R4423 - Write Sequencer 327 */ 1300 [4424] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4424 - Write Sequencer 328 */ 1301 [4425] = { 0x00FF, 0x00FF, 0x0000 }, /* R4425 - Write Sequencer 329 */ 1302 [4426] = { 0x070F, 0x070F, 0x0000 }, /* R4426 - Write Sequencer 330 */ 1303 [4427] = { 0x010F, 0x010F, 0x0000 }, /* R4427 - Write Sequencer 331 */ 1304 [4428] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4428 - Write Sequencer 332 */ 1305 [4429] = { 0x00FF, 0x00FF, 0x0000 }, /* R4429 - Write Sequencer 333 */ 1306 [4430] = { 0x070F, 0x070F, 0x0000 }, /* R4430 - Write Sequencer 334 */ 1307 [4431] = { 0x010F, 0x010F, 0x0000 }, /* R4431 - Write Sequencer 335 */ 1308 [4432] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4432 - Write Sequencer 336 */ 1309 [4433] = { 0x00FF, 0x00FF, 0x0000 }, /* R4433 - Write Sequencer 337 */ 1310 [4434] = { 0x070F, 0x070F, 0x0000 }, /* R4434 - Write Sequencer 338 */ 1311 [4435] = { 0x010F, 0x010F, 0x0000 }, /* R4435 - Write Sequencer 339 */ 1312 [4436] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4436 - Write Sequencer 340 */ 1313 [4437] = { 0x00FF, 0x00FF, 0x0000 }, /* R4437 - Write Sequencer 341 */ 1314 [4438] = { 0x070F, 0x070F, 0x0000 }, /* R4438 - Write Sequencer 342 */ 1315 [4439] = { 0x010F, 0x010F, 0x0000 }, /* R4439 - Write Sequencer 343 */ 1316 [4440] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4440 - Write Sequencer 344 */ 1317 [4441] = { 0x00FF, 0x00FF, 0x0000 }, /* R4441 - Write Sequencer 345 */ 1318 [4442] = { 0x070F, 0x070F, 0x0000 }, /* R4442 - Write Sequencer 346 */ 1319 [4443] = { 0x010F, 0x010F, 0x0000 }, /* R4443 - Write Sequencer 347 */ 1320 [4444] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4444 - Write Sequencer 348 */ 1321 [4445] = { 0x00FF, 0x00FF, 0x0000 }, /* R4445 - Write Sequencer 349 */ 1322 [4446] = { 0x070F, 0x070F, 0x0000 }, /* R4446 - Write Sequencer 350 */ 1323 [4447] = { 0x010F, 0x010F, 0x0000 }, /* R4447 - Write Sequencer 351 */ 1324 [4448] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4448 - Write Sequencer 352 */ 1325 [4449] = { 0x00FF, 0x00FF, 0x0000 }, /* R4449 - Write Sequencer 353 */ 1326 [4450] = { 0x070F, 0x070F, 0x0000 }, /* R4450 - Write Sequencer 354 */ 1327 [4451] = { 0x010F, 0x010F, 0x0000 }, /* R4451 - Write Sequencer 355 */ 1328 [4452] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4452 - Write Sequencer 356 */ 1329 [4453] = { 0x00FF, 0x00FF, 0x0000 }, /* R4453 - Write Sequencer 357 */ 1330 [4454] = { 0x070F, 0x070F, 0x0000 }, /* R4454 - Write Sequencer 358 */ 1331 [4455] = { 0x010F, 0x010F, 0x0000 }, /* R4455 - Write Sequencer 359 */ 1332 [4456] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4456 - Write Sequencer 360 */ 1333 [4457] = { 0x00FF, 0x00FF, 0x0000 }, /* R4457 - Write Sequencer 361 */ 1334 [4458] = { 0x070F, 0x070F, 0x0000 }, /* R4458 - Write Sequencer 362 */ 1335 [4459] = { 0x010F, 0x010F, 0x0000 }, /* R4459 - Write Sequencer 363 */ 1336 [4460] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4460 - Write Sequencer 364 */ 1337 [4461] = { 0x00FF, 0x00FF, 0x0000 }, /* R4461 - Write Sequencer 365 */ 1338 [4462] = { 0x070F, 0x070F, 0x0000 }, /* R4462 - Write Sequencer 366 */ 1339 [4463] = { 0x010F, 0x010F, 0x0000 }, /* R4463 - Write Sequencer 367 */ 1340 [4464] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4464 - Write Sequencer 368 */ 1341 [4465] = { 0x00FF, 0x00FF, 0x0000 }, /* R4465 - Write Sequencer 369 */ 1342 [4466] = { 0x070F, 0x070F, 0x0000 }, /* R4466 - Write Sequencer 370 */ 1343 [4467] = { 0x010F, 0x010F, 0x0000 }, /* R4467 - Write Sequencer 371 */ 1344 [4468] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4468 - Write Sequencer 372 */ 1345 [4469] = { 0x00FF, 0x00FF, 0x0000 }, /* R4469 - Write Sequencer 373 */ 1346 [4470] = { 0x070F, 0x070F, 0x0000 }, /* R4470 - Write Sequencer 374 */ 1347 [4471] = { 0x010F, 0x010F, 0x0000 }, /* R4471 - Write Sequencer 375 */ 1348 [4472] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4472 - Write Sequencer 376 */ 1349 [4473] = { 0x00FF, 0x00FF, 0x0000 }, /* R4473 - Write Sequencer 377 */ 1350 [4474] = { 0x070F, 0x070F, 0x0000 }, /* R4474 - Write Sequencer 378 */ 1351 [4475] = { 0x010F, 0x010F, 0x0000 }, /* R4475 - Write Sequencer 379 */ 1352 [4476] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4476 - Write Sequencer 380 */ 1353 [4477] = { 0x00FF, 0x00FF, 0x0000 }, /* R4477 - Write Sequencer 381 */ 1354 [4478] = { 0x070F, 0x070F, 0x0000 }, /* R4478 - Write Sequencer 382 */ 1355 [4479] = { 0x010F, 0x010F, 0x0000 }, /* R4479 - Write Sequencer 383 */ 1356 [4480] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4480 - Write Sequencer 384 */ 1357 [4481] = { 0x00FF, 0x00FF, 0x0000 }, /* R4481 - Write Sequencer 385 */ 1358 [4482] = { 0x070F, 0x070F, 0x0000 }, /* R4482 - Write Sequencer 386 */ 1359 [4483] = { 0x010F, 0x010F, 0x0000 }, /* R4483 - Write Sequencer 387 */ 1360 [4484] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4484 - Write Sequencer 388 */ 1361 [4485] = { 0x00FF, 0x00FF, 0x0000 }, /* R4485 - Write Sequencer 389 */ 1362 [4486] = { 0x070F, 0x070F, 0x0000 }, /* R4486 - Write Sequencer 390 */ 1363 [4487] = { 0x010F, 0x010F, 0x0000 }, /* R4487 - Write Sequencer 391 */ 1364 [4488] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4488 - Write Sequencer 392 */ 1365 [4489] = { 0x00FF, 0x00FF, 0x0000 }, /* R4489 - Write Sequencer 393 */ 1366 [4490] = { 0x070F, 0x070F, 0x0000 }, /* R4490 - Write Sequencer 394 */ 1367 [4491] = { 0x010F, 0x010F, 0x0000 }, /* R4491 - Write Sequencer 395 */ 1368 [4492] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4492 - Write Sequencer 396 */ 1369 [4493] = { 0x00FF, 0x00FF, 0x0000 }, /* R4493 - Write Sequencer 397 */ 1370 [4494] = { 0x070F, 0x070F, 0x0000 }, /* R4494 - Write Sequencer 398 */ 1371 [4495] = { 0x010F, 0x010F, 0x0000 }, /* R4495 - Write Sequencer 399 */ 1372 [4496] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4496 - Write Sequencer 400 */ 1373 [4497] = { 0x00FF, 0x00FF, 0x0000 }, /* R4497 - Write Sequencer 401 */ 1374 [4498] = { 0x070F, 0x070F, 0x0000 }, /* R4498 - Write Sequencer 402 */ 1375 [4499] = { 0x010F, 0x010F, 0x0000 }, /* R4499 - Write Sequencer 403 */ 1376 [4500] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4500 - Write Sequencer 404 */ 1377 [4501] = { 0x00FF, 0x00FF, 0x0000 }, /* R4501 - Write Sequencer 405 */ 1378 [4502] = { 0x070F, 0x070F, 0x0000 }, /* R4502 - Write Sequencer 406 */ 1379 [4503] = { 0x010F, 0x010F, 0x0000 }, /* R4503 - Write Sequencer 407 */ 1380 [4504] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4504 - Write Sequencer 408 */ 1381 [4505] = { 0x00FF, 0x00FF, 0x0000 }, /* R4505 - Write Sequencer 409 */ 1382 [4506] = { 0x070F, 0x070F, 0x0000 }, /* R4506 - Write Sequencer 410 */ 1383 [4507] = { 0x010F, 0x010F, 0x0000 }, /* R4507 - Write Sequencer 411 */ 1384 [4508] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4508 - Write Sequencer 412 */ 1385 [4509] = { 0x00FF, 0x00FF, 0x0000 }, /* R4509 - Write Sequencer 413 */ 1386 [4510] = { 0x070F, 0x070F, 0x0000 }, /* R4510 - Write Sequencer 414 */ 1387 [4511] = { 0x010F, 0x010F, 0x0000 }, /* R4511 - Write Sequencer 415 */ 1388 [4512] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4512 - Write Sequencer 416 */ 1389 [4513] = { 0x00FF, 0x00FF, 0x0000 }, /* R4513 - Write Sequencer 417 */ 1390 [4514] = { 0x070F, 0x070F, 0x0000 }, /* R4514 - Write Sequencer 418 */ 1391 [4515] = { 0x010F, 0x010F, 0x0000 }, /* R4515 - Write Sequencer 419 */ 1392 [4516] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4516 - Write Sequencer 420 */ 1393 [4517] = { 0x00FF, 0x00FF, 0x0000 }, /* R4517 - Write Sequencer 421 */ 1394 [4518] = { 0x070F, 0x070F, 0x0000 }, /* R4518 - Write Sequencer 422 */ 1395 [4519] = { 0x010F, 0x010F, 0x0000 }, /* R4519 - Write Sequencer 423 */ 1396 [4520] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4520 - Write Sequencer 424 */ 1397 [4521] = { 0x00FF, 0x00FF, 0x0000 }, /* R4521 - Write Sequencer 425 */ 1398 [4522] = { 0x070F, 0x070F, 0x0000 }, /* R4522 - Write Sequencer 426 */ 1399 [4523] = { 0x010F, 0x010F, 0x0000 }, /* R4523 - Write Sequencer 427 */ 1400 [4524] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4524 - Write Sequencer 428 */ 1401 [4525] = { 0x00FF, 0x00FF, 0x0000 }, /* R4525 - Write Sequencer 429 */ 1402 [4526] = { 0x070F, 0x070F, 0x0000 }, /* R4526 - Write Sequencer 430 */ 1403 [4527] = { 0x010F, 0x010F, 0x0000 }, /* R4527 - Write Sequencer 431 */ 1404 [4528] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4528 - Write Sequencer 432 */ 1405 [4529] = { 0x00FF, 0x00FF, 0x0000 }, /* R4529 - Write Sequencer 433 */ 1406 [4530] = { 0x070F, 0x070F, 0x0000 }, /* R4530 - Write Sequencer 434 */ 1407 [4531] = { 0x010F, 0x010F, 0x0000 }, /* R4531 - Write Sequencer 435 */ 1408 [4532] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4532 - Write Sequencer 436 */ 1409 [4533] = { 0x00FF, 0x00FF, 0x0000 }, /* R4533 - Write Sequencer 437 */ 1410 [4534] = { 0x070F, 0x070F, 0x0000 }, /* R4534 - Write Sequencer 438 */ 1411 [4535] = { 0x010F, 0x010F, 0x0000 }, /* R4535 - Write Sequencer 439 */ 1412 [4536] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4536 - Write Sequencer 440 */ 1413 [4537] = { 0x00FF, 0x00FF, 0x0000 }, /* R4537 - Write Sequencer 441 */ 1414 [4538] = { 0x070F, 0x070F, 0x0000 }, /* R4538 - Write Sequencer 442 */ 1415 [4539] = { 0x010F, 0x010F, 0x0000 }, /* R4539 - Write Sequencer 443 */ 1416 [4540] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4540 - Write Sequencer 444 */ 1417 [4541] = { 0x00FF, 0x00FF, 0x0000 }, /* R4541 - Write Sequencer 445 */ 1418 [4542] = { 0x070F, 0x070F, 0x0000 }, /* R4542 - Write Sequencer 446 */ 1419 [4543] = { 0x010F, 0x010F, 0x0000 }, /* R4543 - Write Sequencer 447 */ 1420 [4544] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4544 - Write Sequencer 448 */ 1421 [4545] = { 0x00FF, 0x00FF, 0x0000 }, /* R4545 - Write Sequencer 449 */ 1422 [4546] = { 0x070F, 0x070F, 0x0000 }, /* R4546 - Write Sequencer 450 */ 1423 [4547] = { 0x010F, 0x010F, 0x0000 }, /* R4547 - Write Sequencer 451 */ 1424 [4548] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4548 - Write Sequencer 452 */ 1425 [4549] = { 0x00FF, 0x00FF, 0x0000 }, /* R4549 - Write Sequencer 453 */ 1426 [4550] = { 0x070F, 0x070F, 0x0000 }, /* R4550 - Write Sequencer 454 */ 1427 [4551] = { 0x010F, 0x010F, 0x0000 }, /* R4551 - Write Sequencer 455 */ 1428 [4552] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4552 - Write Sequencer 456 */ 1429 [4553] = { 0x00FF, 0x00FF, 0x0000 }, /* R4553 - Write Sequencer 457 */ 1430 [4554] = { 0x070F, 0x070F, 0x0000 }, /* R4554 - Write Sequencer 458 */ 1431 [4555] = { 0x010F, 0x010F, 0x0000 }, /* R4555 - Write Sequencer 459 */ 1432 [4556] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4556 - Write Sequencer 460 */ 1433 [4557] = { 0x00FF, 0x00FF, 0x0000 }, /* R4557 - Write Sequencer 461 */ 1434 [4558] = { 0x070F, 0x070F, 0x0000 }, /* R4558 - Write Sequencer 462 */ 1435 [4559] = { 0x010F, 0x010F, 0x0000 }, /* R4559 - Write Sequencer 463 */ 1436 [4560] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4560 - Write Sequencer 464 */ 1437 [4561] = { 0x00FF, 0x00FF, 0x0000 }, /* R4561 - Write Sequencer 465 */ 1438 [4562] = { 0x070F, 0x070F, 0x0000 }, /* R4562 - Write Sequencer 466 */ 1439 [4563] = { 0x010F, 0x010F, 0x0000 }, /* R4563 - Write Sequencer 467 */ 1440 [4564] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4564 - Write Sequencer 468 */ 1441 [4565] = { 0x00FF, 0x00FF, 0x0000 }, /* R4565 - Write Sequencer 469 */ 1442 [4566] = { 0x070F, 0x070F, 0x0000 }, /* R4566 - Write Sequencer 470 */ 1443 [4567] = { 0x010F, 0x010F, 0x0000 }, /* R4567 - Write Sequencer 471 */ 1444 [4568] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4568 - Write Sequencer 472 */ 1445 [4569] = { 0x00FF, 0x00FF, 0x0000 }, /* R4569 - Write Sequencer 473 */ 1446 [4570] = { 0x070F, 0x070F, 0x0000 }, /* R4570 - Write Sequencer 474 */ 1447 [4571] = { 0x010F, 0x010F, 0x0000 }, /* R4571 - Write Sequencer 475 */ 1448 [4572] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4572 - Write Sequencer 476 */ 1449 [4573] = { 0x00FF, 0x00FF, 0x0000 }, /* R4573 - Write Sequencer 477 */ 1450 [4574] = { 0x070F, 0x070F, 0x0000 }, /* R4574 - Write Sequencer 478 */ 1451 [4575] = { 0x010F, 0x010F, 0x0000 }, /* R4575 - Write Sequencer 479 */ 1452 [4576] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4576 - Write Sequencer 480 */ 1453 [4577] = { 0x00FF, 0x00FF, 0x0000 }, /* R4577 - Write Sequencer 481 */ 1454 [4578] = { 0x070F, 0x070F, 0x0000 }, /* R4578 - Write Sequencer 482 */ 1455 [4579] = { 0x010F, 0x010F, 0x0000 }, /* R4579 - Write Sequencer 483 */ 1456 [4580] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4580 - Write Sequencer 484 */ 1457 [4581] = { 0x00FF, 0x00FF, 0x0000 }, /* R4581 - Write Sequencer 485 */ 1458 [4582] = { 0x070F, 0x070F, 0x0000 }, /* R4582 - Write Sequencer 486 */ 1459 [4583] = { 0x010F, 0x010F, 0x0000 }, /* R4583 - Write Sequencer 487 */ 1460 [4584] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4584 - Write Sequencer 488 */ 1461 [4585] = { 0x00FF, 0x00FF, 0x0000 }, /* R4585 - Write Sequencer 489 */ 1462 [4586] = { 0x070F, 0x070F, 0x0000 }, /* R4586 - Write Sequencer 490 */ 1463 [4587] = { 0x010F, 0x010F, 0x0000 }, /* R4587 - Write Sequencer 491 */ 1464 [4588] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4588 - Write Sequencer 492 */ 1465 [4589] = { 0x00FF, 0x00FF, 0x0000 }, /* R4589 - Write Sequencer 493 */ 1466 [4590] = { 0x070F, 0x070F, 0x0000 }, /* R4590 - Write Sequencer 494 */ 1467 [4591] = { 0x010F, 0x010F, 0x0000 }, /* R4591 - Write Sequencer 495 */ 1468 [4592] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4592 - Write Sequencer 496 */ 1469 [4593] = { 0x00FF, 0x00FF, 0x0000 }, /* R4593 - Write Sequencer 497 */ 1470 [4594] = { 0x070F, 0x070F, 0x0000 }, /* R4594 - Write Sequencer 498 */ 1471 [4595] = { 0x010F, 0x010F, 0x0000 }, /* R4595 - Write Sequencer 499 */ 1472 [4596] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4596 - Write Sequencer 500 */ 1473 [4597] = { 0x00FF, 0x00FF, 0x0000 }, /* R4597 - Write Sequencer 501 */ 1474 [4598] = { 0x070F, 0x070F, 0x0000 }, /* R4598 - Write Sequencer 502 */ 1475 [4599] = { 0x010F, 0x010F, 0x0000 }, /* R4599 - Write Sequencer 503 */ 1476 [4600] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4600 - Write Sequencer 504 */ 1477 [4601] = { 0x00FF, 0x00FF, 0x0000 }, /* R4601 - Write Sequencer 505 */ 1478 [4602] = { 0x070F, 0x070F, 0x0000 }, /* R4602 - Write Sequencer 506 */ 1479 [4603] = { 0x010F, 0x010F, 0x0000 }, /* R4603 - Write Sequencer 507 */ 1480 [4604] = { 0x3FFF, 0x3FFF, 0x0000 }, /* R4604 - Write Sequencer 508 */ 1481 [4605] = { 0x00FF, 0x00FF, 0x0000 }, /* R4605 - Write Sequencer 509 */ 1482 [4606] = { 0x070F, 0x070F, 0x0000 }, /* R4606 - Write Sequencer 510 */ 1483 [4607] = { 0x010F, 0x010F, 0x0000 }, /* R4607 - Write Sequencer 511 */ 1484 [8192] = { 0x03FF, 0x03FF, 0x0000 }, /* R8192 - DSP2 Instruction RAM 0 */ 1485 [9216] = { 0x003F, 0x003F, 0x0000 }, /* R9216 - DSP2 Address RAM 2 */ 1486 [9217] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9217 - DSP2 Address RAM 1 */ 1487 [9218] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R9218 - DSP2 Address RAM 0 */ 1488 [12288] = { 0x00FF, 0x00FF, 0x0000 }, /* R12288 - DSP2 Data1 RAM 1 */ 1489 [12289] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R12289 - DSP2 Data1 RAM 0 */ 1490 [13312] = { 0x00FF, 0x00FF, 0x0000 }, /* R13312 - DSP2 Data2 RAM 1 */ 1491 [13313] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R13313 - DSP2 Data2 RAM 0 */ 1492 [14336] = { 0x00FF, 0x00FF, 0x0000 }, /* R14336 - DSP2 Data3 RAM 1 */ 1493 [14337] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R14337 - DSP2 Data3 RAM 0 */ 1494 [15360] = { 0x07FF, 0x07FF, 0x0000 }, /* R15360 - DSP2 Coeff RAM 0 */ 1495 [16384] = { 0x00FF, 0x00FF, 0x0000 }, /* R16384 - RETUNEADC_SHARED_COEFF_1 */ 1496 [16385] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16385 - RETUNEADC_SHARED_COEFF_0 */ 1497 [16386] = { 0x00FF, 0x00FF, 0x0000 }, /* R16386 - RETUNEDAC_SHARED_COEFF_1 */ 1498 [16387] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16387 - RETUNEDAC_SHARED_COEFF_0 */ 1499 [16388] = { 0x00FF, 0x00FF, 0x0000 }, /* R16388 - SOUNDSTAGE_ENABLES_1 */ 1500 [16389] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16389 - SOUNDSTAGE_ENABLES_0 */ 1501 [16896] = { 0x00FF, 0x00FF, 0x0000 }, /* R16896 - HDBASS_AI_1 */ 1502 [16897] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16897 - HDBASS_AI_0 */ 1503 [16898] = { 0x00FF, 0x00FF, 0x0000 }, /* R16898 - HDBASS_AR_1 */ 1504 [16899] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16899 - HDBASS_AR_0 */ 1505 [16900] = { 0x00FF, 0x00FF, 0x0000 }, /* R16900 - HDBASS_B_1 */ 1506 [16901] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16901 - HDBASS_B_0 */ 1507 [16902] = { 0x00FF, 0x00FF, 0x0000 }, /* R16902 - HDBASS_K_1 */ 1508 [16903] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16903 - HDBASS_K_0 */ 1509 [16904] = { 0x00FF, 0x00FF, 0x0000 }, /* R16904 - HDBASS_N1_1 */ 1510 [16905] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16905 - HDBASS_N1_0 */ 1511 [16906] = { 0x00FF, 0x00FF, 0x0000 }, /* R16906 - HDBASS_N2_1 */ 1512 [16907] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16907 - HDBASS_N2_0 */ 1513 [16908] = { 0x00FF, 0x00FF, 0x0000 }, /* R16908 - HDBASS_N3_1 */ 1514 [16909] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16909 - HDBASS_N3_0 */ 1515 [16910] = { 0x00FF, 0x00FF, 0x0000 }, /* R16910 - HDBASS_N4_1 */ 1516 [16911] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16911 - HDBASS_N4_0 */ 1517 [16912] = { 0x00FF, 0x00FF, 0x0000 }, /* R16912 - HDBASS_N5_1 */ 1518 [16913] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16913 - HDBASS_N5_0 */ 1519 [16914] = { 0x00FF, 0x00FF, 0x0000 }, /* R16914 - HDBASS_X1_1 */ 1520 [16915] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16915 - HDBASS_X1_0 */ 1521 [16916] = { 0x00FF, 0x00FF, 0x0000 }, /* R16916 - HDBASS_X2_1 */ 1522 [16917] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16917 - HDBASS_X2_0 */ 1523 [16918] = { 0x00FF, 0x00FF, 0x0000 }, /* R16918 - HDBASS_X3_1 */ 1524 [16919] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16919 - HDBASS_X3_0 */ 1525 [16920] = { 0x00FF, 0x00FF, 0x0000 }, /* R16920 - HDBASS_ATK_1 */ 1526 [16921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16921 - HDBASS_ATK_0 */ 1527 [16922] = { 0x00FF, 0x00FF, 0x0000 }, /* R16922 - HDBASS_DCY_1 */ 1528 [16923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16923 - HDBASS_DCY_0 */ 1529 [16924] = { 0x00FF, 0x00FF, 0x0000 }, /* R16924 - HDBASS_PG_1 */ 1530 [16925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R16925 - HDBASS_PG_0 */ 1531 [17408] = { 0x00FF, 0x00FF, 0x0000 }, /* R17408 - HPF_C_1 */ 1532 [17409] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17409 - HPF_C_0 */ 1533 [17920] = { 0x00FF, 0x00FF, 0x0000 }, /* R17920 - ADCL_RETUNE_C1_1 */ 1534 [17921] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17921 - ADCL_RETUNE_C1_0 */ 1535 [17922] = { 0x00FF, 0x00FF, 0x0000 }, /* R17922 - ADCL_RETUNE_C2_1 */ 1536 [17923] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17923 - ADCL_RETUNE_C2_0 */ 1537 [17924] = { 0x00FF, 0x00FF, 0x0000 }, /* R17924 - ADCL_RETUNE_C3_1 */ 1538 [17925] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17925 - ADCL_RETUNE_C3_0 */ 1539 [17926] = { 0x00FF, 0x00FF, 0x0000 }, /* R17926 - ADCL_RETUNE_C4_1 */ 1540 [17927] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17927 - ADCL_RETUNE_C4_0 */ 1541 [17928] = { 0x00FF, 0x00FF, 0x0000 }, /* R17928 - ADCL_RETUNE_C5_1 */ 1542 [17929] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17929 - ADCL_RETUNE_C5_0 */ 1543 [17930] = { 0x00FF, 0x00FF, 0x0000 }, /* R17930 - ADCL_RETUNE_C6_1 */ 1544 [17931] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17931 - ADCL_RETUNE_C6_0 */ 1545 [17932] = { 0x00FF, 0x00FF, 0x0000 }, /* R17932 - ADCL_RETUNE_C7_1 */ 1546 [17933] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17933 - ADCL_RETUNE_C7_0 */ 1547 [17934] = { 0x00FF, 0x00FF, 0x0000 }, /* R17934 - ADCL_RETUNE_C8_1 */ 1548 [17935] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17935 - ADCL_RETUNE_C8_0 */ 1549 [17936] = { 0x00FF, 0x00FF, 0x0000 }, /* R17936 - ADCL_RETUNE_C9_1 */ 1550 [17937] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17937 - ADCL_RETUNE_C9_0 */ 1551 [17938] = { 0x00FF, 0x00FF, 0x0000 }, /* R17938 - ADCL_RETUNE_C10_1 */ 1552 [17939] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17939 - ADCL_RETUNE_C10_0 */ 1553 [17940] = { 0x00FF, 0x00FF, 0x0000 }, /* R17940 - ADCL_RETUNE_C11_1 */ 1554 [17941] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17941 - ADCL_RETUNE_C11_0 */ 1555 [17942] = { 0x00FF, 0x00FF, 0x0000 }, /* R17942 - ADCL_RETUNE_C12_1 */ 1556 [17943] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17943 - ADCL_RETUNE_C12_0 */ 1557 [17944] = { 0x00FF, 0x00FF, 0x0000 }, /* R17944 - ADCL_RETUNE_C13_1 */ 1558 [17945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17945 - ADCL_RETUNE_C13_0 */ 1559 [17946] = { 0x00FF, 0x00FF, 0x0000 }, /* R17946 - ADCL_RETUNE_C14_1 */ 1560 [17947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17947 - ADCL_RETUNE_C14_0 */ 1561 [17948] = { 0x00FF, 0x00FF, 0x0000 }, /* R17948 - ADCL_RETUNE_C15_1 */ 1562 [17949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17949 - ADCL_RETUNE_C15_0 */ 1563 [17950] = { 0x00FF, 0x00FF, 0x0000 }, /* R17950 - ADCL_RETUNE_C16_1 */ 1564 [17951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17951 - ADCL_RETUNE_C16_0 */ 1565 [17952] = { 0x00FF, 0x00FF, 0x0000 }, /* R17952 - ADCL_RETUNE_C17_1 */ 1566 [17953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17953 - ADCL_RETUNE_C17_0 */ 1567 [17954] = { 0x00FF, 0x00FF, 0x0000 }, /* R17954 - ADCL_RETUNE_C18_1 */ 1568 [17955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17955 - ADCL_RETUNE_C18_0 */ 1569 [17956] = { 0x00FF, 0x00FF, 0x0000 }, /* R17956 - ADCL_RETUNE_C19_1 */ 1570 [17957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17957 - ADCL_RETUNE_C19_0 */ 1571 [17958] = { 0x00FF, 0x00FF, 0x0000 }, /* R17958 - ADCL_RETUNE_C20_1 */ 1572 [17959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17959 - ADCL_RETUNE_C20_0 */ 1573 [17960] = { 0x00FF, 0x00FF, 0x0000 }, /* R17960 - ADCL_RETUNE_C21_1 */ 1574 [17961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17961 - ADCL_RETUNE_C21_0 */ 1575 [17962] = { 0x00FF, 0x00FF, 0x0000 }, /* R17962 - ADCL_RETUNE_C22_1 */ 1576 [17963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17963 - ADCL_RETUNE_C22_0 */ 1577 [17964] = { 0x00FF, 0x00FF, 0x0000 }, /* R17964 - ADCL_RETUNE_C23_1 */ 1578 [17965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17965 - ADCL_RETUNE_C23_0 */ 1579 [17966] = { 0x00FF, 0x00FF, 0x0000 }, /* R17966 - ADCL_RETUNE_C24_1 */ 1580 [17967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17967 - ADCL_RETUNE_C24_0 */ 1581 [17968] = { 0x00FF, 0x00FF, 0x0000 }, /* R17968 - ADCL_RETUNE_C25_1 */ 1582 [17969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17969 - ADCL_RETUNE_C25_0 */ 1583 [17970] = { 0x00FF, 0x00FF, 0x0000 }, /* R17970 - ADCL_RETUNE_C26_1 */ 1584 [17971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17971 - ADCL_RETUNE_C26_0 */ 1585 [17972] = { 0x00FF, 0x00FF, 0x0000 }, /* R17972 - ADCL_RETUNE_C27_1 */ 1586 [17973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17973 - ADCL_RETUNE_C27_0 */ 1587 [17974] = { 0x00FF, 0x00FF, 0x0000 }, /* R17974 - ADCL_RETUNE_C28_1 */ 1588 [17975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17975 - ADCL_RETUNE_C28_0 */ 1589 [17976] = { 0x00FF, 0x00FF, 0x0000 }, /* R17976 - ADCL_RETUNE_C29_1 */ 1590 [17977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17977 - ADCL_RETUNE_C29_0 */ 1591 [17978] = { 0x00FF, 0x00FF, 0x0000 }, /* R17978 - ADCL_RETUNE_C30_1 */ 1592 [17979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17979 - ADCL_RETUNE_C30_0 */ 1593 [17980] = { 0x00FF, 0x00FF, 0x0000 }, /* R17980 - ADCL_RETUNE_C31_1 */ 1594 [17981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17981 - ADCL_RETUNE_C31_0 */ 1595 [17982] = { 0x00FF, 0x00FF, 0x0000 }, /* R17982 - ADCL_RETUNE_C32_1 */ 1596 [17983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R17983 - ADCL_RETUNE_C32_0 */ 1597 [18432] = { 0x00FF, 0x00FF, 0x0000 }, /* R18432 - RETUNEADC_PG2_1 */ 1598 [18433] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18433 - RETUNEADC_PG2_0 */ 1599 [18434] = { 0x00FF, 0x00FF, 0x0000 }, /* R18434 - RETUNEADC_PG_1 */ 1600 [18435] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18435 - RETUNEADC_PG_0 */ 1601 [18944] = { 0x00FF, 0x00FF, 0x0000 }, /* R18944 - ADCR_RETUNE_C1_1 */ 1602 [18945] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18945 - ADCR_RETUNE_C1_0 */ 1603 [18946] = { 0x00FF, 0x00FF, 0x0000 }, /* R18946 - ADCR_RETUNE_C2_1 */ 1604 [18947] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18947 - ADCR_RETUNE_C2_0 */ 1605 [18948] = { 0x00FF, 0x00FF, 0x0000 }, /* R18948 - ADCR_RETUNE_C3_1 */ 1606 [18949] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18949 - ADCR_RETUNE_C3_0 */ 1607 [18950] = { 0x00FF, 0x00FF, 0x0000 }, /* R18950 - ADCR_RETUNE_C4_1 */ 1608 [18951] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18951 - ADCR_RETUNE_C4_0 */ 1609 [18952] = { 0x00FF, 0x00FF, 0x0000 }, /* R18952 - ADCR_RETUNE_C5_1 */ 1610 [18953] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18953 - ADCR_RETUNE_C5_0 */ 1611 [18954] = { 0x00FF, 0x00FF, 0x0000 }, /* R18954 - ADCR_RETUNE_C6_1 */ 1612 [18955] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18955 - ADCR_RETUNE_C6_0 */ 1613 [18956] = { 0x00FF, 0x00FF, 0x0000 }, /* R18956 - ADCR_RETUNE_C7_1 */ 1614 [18957] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18957 - ADCR_RETUNE_C7_0 */ 1615 [18958] = { 0x00FF, 0x00FF, 0x0000 }, /* R18958 - ADCR_RETUNE_C8_1 */ 1616 [18959] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18959 - ADCR_RETUNE_C8_0 */ 1617 [18960] = { 0x00FF, 0x00FF, 0x0000 }, /* R18960 - ADCR_RETUNE_C9_1 */ 1618 [18961] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18961 - ADCR_RETUNE_C9_0 */ 1619 [18962] = { 0x00FF, 0x00FF, 0x0000 }, /* R18962 - ADCR_RETUNE_C10_1 */ 1620 [18963] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18963 - ADCR_RETUNE_C10_0 */ 1621 [18964] = { 0x00FF, 0x00FF, 0x0000 }, /* R18964 - ADCR_RETUNE_C11_1 */ 1622 [18965] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18965 - ADCR_RETUNE_C11_0 */ 1623 [18966] = { 0x00FF, 0x00FF, 0x0000 }, /* R18966 - ADCR_RETUNE_C12_1 */ 1624 [18967] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18967 - ADCR_RETUNE_C12_0 */ 1625 [18968] = { 0x00FF, 0x00FF, 0x0000 }, /* R18968 - ADCR_RETUNE_C13_1 */ 1626 [18969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18969 - ADCR_RETUNE_C13_0 */ 1627 [18970] = { 0x00FF, 0x00FF, 0x0000 }, /* R18970 - ADCR_RETUNE_C14_1 */ 1628 [18971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18971 - ADCR_RETUNE_C14_0 */ 1629 [18972] = { 0x00FF, 0x00FF, 0x0000 }, /* R18972 - ADCR_RETUNE_C15_1 */ 1630 [18973] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18973 - ADCR_RETUNE_C15_0 */ 1631 [18974] = { 0x00FF, 0x00FF, 0x0000 }, /* R18974 - ADCR_RETUNE_C16_1 */ 1632 [18975] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18975 - ADCR_RETUNE_C16_0 */ 1633 [18976] = { 0x00FF, 0x00FF, 0x0000 }, /* R18976 - ADCR_RETUNE_C17_1 */ 1634 [18977] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18977 - ADCR_RETUNE_C17_0 */ 1635 [18978] = { 0x00FF, 0x00FF, 0x0000 }, /* R18978 - ADCR_RETUNE_C18_1 */ 1636 [18979] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18979 - ADCR_RETUNE_C18_0 */ 1637 [18980] = { 0x00FF, 0x00FF, 0x0000 }, /* R18980 - ADCR_RETUNE_C19_1 */ 1638 [18981] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18981 - ADCR_RETUNE_C19_0 */ 1639 [18982] = { 0x00FF, 0x00FF, 0x0000 }, /* R18982 - ADCR_RETUNE_C20_1 */ 1640 [18983] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18983 - ADCR_RETUNE_C20_0 */ 1641 [18984] = { 0x00FF, 0x00FF, 0x0000 }, /* R18984 - ADCR_RETUNE_C21_1 */ 1642 [18985] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18985 - ADCR_RETUNE_C21_0 */ 1643 [18986] = { 0x00FF, 0x00FF, 0x0000 }, /* R18986 - ADCR_RETUNE_C22_1 */ 1644 [18987] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18987 - ADCR_RETUNE_C22_0 */ 1645 [18988] = { 0x00FF, 0x00FF, 0x0000 }, /* R18988 - ADCR_RETUNE_C23_1 */ 1646 [18989] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18989 - ADCR_RETUNE_C23_0 */ 1647 [18990] = { 0x00FF, 0x00FF, 0x0000 }, /* R18990 - ADCR_RETUNE_C24_1 */ 1648 [18991] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18991 - ADCR_RETUNE_C24_0 */ 1649 [18992] = { 0x00FF, 0x00FF, 0x0000 }, /* R18992 - ADCR_RETUNE_C25_1 */ 1650 [18993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18993 - ADCR_RETUNE_C25_0 */ 1651 [18994] = { 0x00FF, 0x00FF, 0x0000 }, /* R18994 - ADCR_RETUNE_C26_1 */ 1652 [18995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18995 - ADCR_RETUNE_C26_0 */ 1653 [18996] = { 0x00FF, 0x00FF, 0x0000 }, /* R18996 - ADCR_RETUNE_C27_1 */ 1654 [18997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18997 - ADCR_RETUNE_C27_0 */ 1655 [18998] = { 0x00FF, 0x00FF, 0x0000 }, /* R18998 - ADCR_RETUNE_C28_1 */ 1656 [18999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R18999 - ADCR_RETUNE_C28_0 */ 1657 [19000] = { 0x00FF, 0x00FF, 0x0000 }, /* R19000 - ADCR_RETUNE_C29_1 */ 1658 [19001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19001 - ADCR_RETUNE_C29_0 */ 1659 [19002] = { 0x00FF, 0x00FF, 0x0000 }, /* R19002 - ADCR_RETUNE_C30_1 */ 1660 [19003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19003 - ADCR_RETUNE_C30_0 */ 1661 [19004] = { 0x00FF, 0x00FF, 0x0000 }, /* R19004 - ADCR_RETUNE_C31_1 */ 1662 [19005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19005 - ADCR_RETUNE_C31_0 */ 1663 [19006] = { 0x00FF, 0x00FF, 0x0000 }, /* R19006 - ADCR_RETUNE_C32_1 */ 1664 [19007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19007 - ADCR_RETUNE_C32_0 */ 1665 [19456] = { 0x00FF, 0x00FF, 0x0000 }, /* R19456 - DACL_RETUNE_C1_1 */ 1666 [19457] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19457 - DACL_RETUNE_C1_0 */ 1667 [19458] = { 0x00FF, 0x00FF, 0x0000 }, /* R19458 - DACL_RETUNE_C2_1 */ 1668 [19459] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19459 - DACL_RETUNE_C2_0 */ 1669 [19460] = { 0x00FF, 0x00FF, 0x0000 }, /* R19460 - DACL_RETUNE_C3_1 */ 1670 [19461] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19461 - DACL_RETUNE_C3_0 */ 1671 [19462] = { 0x00FF, 0x00FF, 0x0000 }, /* R19462 - DACL_RETUNE_C4_1 */ 1672 [19463] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19463 - DACL_RETUNE_C4_0 */ 1673 [19464] = { 0x00FF, 0x00FF, 0x0000 }, /* R19464 - DACL_RETUNE_C5_1 */ 1674 [19465] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19465 - DACL_RETUNE_C5_0 */ 1675 [19466] = { 0x00FF, 0x00FF, 0x0000 }, /* R19466 - DACL_RETUNE_C6_1 */ 1676 [19467] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19467 - DACL_RETUNE_C6_0 */ 1677 [19468] = { 0x00FF, 0x00FF, 0x0000 }, /* R19468 - DACL_RETUNE_C7_1 */ 1678 [19469] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19469 - DACL_RETUNE_C7_0 */ 1679 [19470] = { 0x00FF, 0x00FF, 0x0000 }, /* R19470 - DACL_RETUNE_C8_1 */ 1680 [19471] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19471 - DACL_RETUNE_C8_0 */ 1681 [19472] = { 0x00FF, 0x00FF, 0x0000 }, /* R19472 - DACL_RETUNE_C9_1 */ 1682 [19473] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19473 - DACL_RETUNE_C9_0 */ 1683 [19474] = { 0x00FF, 0x00FF, 0x0000 }, /* R19474 - DACL_RETUNE_C10_1 */ 1684 [19475] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19475 - DACL_RETUNE_C10_0 */ 1685 [19476] = { 0x00FF, 0x00FF, 0x0000 }, /* R19476 - DACL_RETUNE_C11_1 */ 1686 [19477] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19477 - DACL_RETUNE_C11_0 */ 1687 [19478] = { 0x00FF, 0x00FF, 0x0000 }, /* R19478 - DACL_RETUNE_C12_1 */ 1688 [19479] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19479 - DACL_RETUNE_C12_0 */ 1689 [19480] = { 0x00FF, 0x00FF, 0x0000 }, /* R19480 - DACL_RETUNE_C13_1 */ 1690 [19481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19481 - DACL_RETUNE_C13_0 */ 1691 [19482] = { 0x00FF, 0x00FF, 0x0000 }, /* R19482 - DACL_RETUNE_C14_1 */ 1692 [19483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19483 - DACL_RETUNE_C14_0 */ 1693 [19484] = { 0x00FF, 0x00FF, 0x0000 }, /* R19484 - DACL_RETUNE_C15_1 */ 1694 [19485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19485 - DACL_RETUNE_C15_0 */ 1695 [19486] = { 0x00FF, 0x00FF, 0x0000 }, /* R19486 - DACL_RETUNE_C16_1 */ 1696 [19487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19487 - DACL_RETUNE_C16_0 */ 1697 [19488] = { 0x00FF, 0x00FF, 0x0000 }, /* R19488 - DACL_RETUNE_C17_1 */ 1698 [19489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19489 - DACL_RETUNE_C17_0 */ 1699 [19490] = { 0x00FF, 0x00FF, 0x0000 }, /* R19490 - DACL_RETUNE_C18_1 */ 1700 [19491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19491 - DACL_RETUNE_C18_0 */ 1701 [19492] = { 0x00FF, 0x00FF, 0x0000 }, /* R19492 - DACL_RETUNE_C19_1 */ 1702 [19493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19493 - DACL_RETUNE_C19_0 */ 1703 [19494] = { 0x00FF, 0x00FF, 0x0000 }, /* R19494 - DACL_RETUNE_C20_1 */ 1704 [19495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19495 - DACL_RETUNE_C20_0 */ 1705 [19496] = { 0x00FF, 0x00FF, 0x0000 }, /* R19496 - DACL_RETUNE_C21_1 */ 1706 [19497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19497 - DACL_RETUNE_C21_0 */ 1707 [19498] = { 0x00FF, 0x00FF, 0x0000 }, /* R19498 - DACL_RETUNE_C22_1 */ 1708 [19499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19499 - DACL_RETUNE_C22_0 */ 1709 [19500] = { 0x00FF, 0x00FF, 0x0000 }, /* R19500 - DACL_RETUNE_C23_1 */ 1710 [19501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19501 - DACL_RETUNE_C23_0 */ 1711 [19502] = { 0x00FF, 0x00FF, 0x0000 }, /* R19502 - DACL_RETUNE_C24_1 */ 1712 [19503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19503 - DACL_RETUNE_C24_0 */ 1713 [19504] = { 0x00FF, 0x00FF, 0x0000 }, /* R19504 - DACL_RETUNE_C25_1 */ 1714 [19505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19505 - DACL_RETUNE_C25_0 */ 1715 [19506] = { 0x00FF, 0x00FF, 0x0000 }, /* R19506 - DACL_RETUNE_C26_1 */ 1716 [19507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19507 - DACL_RETUNE_C26_0 */ 1717 [19508] = { 0x00FF, 0x00FF, 0x0000 }, /* R19508 - DACL_RETUNE_C27_1 */ 1718 [19509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19509 - DACL_RETUNE_C27_0 */ 1719 [19510] = { 0x00FF, 0x00FF, 0x0000 }, /* R19510 - DACL_RETUNE_C28_1 */ 1720 [19511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19511 - DACL_RETUNE_C28_0 */ 1721 [19512] = { 0x00FF, 0x00FF, 0x0000 }, /* R19512 - DACL_RETUNE_C29_1 */ 1722 [19513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19513 - DACL_RETUNE_C29_0 */ 1723 [19514] = { 0x00FF, 0x00FF, 0x0000 }, /* R19514 - DACL_RETUNE_C30_1 */ 1724 [19515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19515 - DACL_RETUNE_C30_0 */ 1725 [19516] = { 0x00FF, 0x00FF, 0x0000 }, /* R19516 - DACL_RETUNE_C31_1 */ 1726 [19517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19517 - DACL_RETUNE_C31_0 */ 1727 [19518] = { 0x00FF, 0x00FF, 0x0000 }, /* R19518 - DACL_RETUNE_C32_1 */ 1728 [19519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19519 - DACL_RETUNE_C32_0 */ 1729 [19968] = { 0x00FF, 0x00FF, 0x0000 }, /* R19968 - RETUNEDAC_PG2_1 */ 1730 [19969] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19969 - RETUNEDAC_PG2_0 */ 1731 [19970] = { 0x00FF, 0x00FF, 0x0000 }, /* R19970 - RETUNEDAC_PG_1 */ 1732 [19971] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R19971 - RETUNEDAC_PG_0 */ 1733 [20480] = { 0x00FF, 0x00FF, 0x0000 }, /* R20480 - DACR_RETUNE_C1_1 */ 1734 [20481] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20481 - DACR_RETUNE_C1_0 */ 1735 [20482] = { 0x00FF, 0x00FF, 0x0000 }, /* R20482 - DACR_RETUNE_C2_1 */ 1736 [20483] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20483 - DACR_RETUNE_C2_0 */ 1737 [20484] = { 0x00FF, 0x00FF, 0x0000 }, /* R20484 - DACR_RETUNE_C3_1 */ 1738 [20485] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20485 - DACR_RETUNE_C3_0 */ 1739 [20486] = { 0x00FF, 0x00FF, 0x0000 }, /* R20486 - DACR_RETUNE_C4_1 */ 1740 [20487] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20487 - DACR_RETUNE_C4_0 */ 1741 [20488] = { 0x00FF, 0x00FF, 0x0000 }, /* R20488 - DACR_RETUNE_C5_1 */ 1742 [20489] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20489 - DACR_RETUNE_C5_0 */ 1743 [20490] = { 0x00FF, 0x00FF, 0x0000 }, /* R20490 - DACR_RETUNE_C6_1 */ 1744 [20491] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20491 - DACR_RETUNE_C6_0 */ 1745 [20492] = { 0x00FF, 0x00FF, 0x0000 }, /* R20492 - DACR_RETUNE_C7_1 */ 1746 [20493] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20493 - DACR_RETUNE_C7_0 */ 1747 [20494] = { 0x00FF, 0x00FF, 0x0000 }, /* R20494 - DACR_RETUNE_C8_1 */ 1748 [20495] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20495 - DACR_RETUNE_C8_0 */ 1749 [20496] = { 0x00FF, 0x00FF, 0x0000 }, /* R20496 - DACR_RETUNE_C9_1 */ 1750 [20497] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20497 - DACR_RETUNE_C9_0 */ 1751 [20498] = { 0x00FF, 0x00FF, 0x0000 }, /* R20498 - DACR_RETUNE_C10_1 */ 1752 [20499] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20499 - DACR_RETUNE_C10_0 */ 1753 [20500] = { 0x00FF, 0x00FF, 0x0000 }, /* R20500 - DACR_RETUNE_C11_1 */ 1754 [20501] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20501 - DACR_RETUNE_C11_0 */ 1755 [20502] = { 0x00FF, 0x00FF, 0x0000 }, /* R20502 - DACR_RETUNE_C12_1 */ 1756 [20503] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20503 - DACR_RETUNE_C12_0 */ 1757 [20504] = { 0x00FF, 0x00FF, 0x0000 }, /* R20504 - DACR_RETUNE_C13_1 */ 1758 [20505] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20505 - DACR_RETUNE_C13_0 */ 1759 [20506] = { 0x00FF, 0x00FF, 0x0000 }, /* R20506 - DACR_RETUNE_C14_1 */ 1760 [20507] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20507 - DACR_RETUNE_C14_0 */ 1761 [20508] = { 0x00FF, 0x00FF, 0x0000 }, /* R20508 - DACR_RETUNE_C15_1 */ 1762 [20509] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20509 - DACR_RETUNE_C15_0 */ 1763 [20510] = { 0x00FF, 0x00FF, 0x0000 }, /* R20510 - DACR_RETUNE_C16_1 */ 1764 [20511] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20511 - DACR_RETUNE_C16_0 */ 1765 [20512] = { 0x00FF, 0x00FF, 0x0000 }, /* R20512 - DACR_RETUNE_C17_1 */ 1766 [20513] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20513 - DACR_RETUNE_C17_0 */ 1767 [20514] = { 0x00FF, 0x00FF, 0x0000 }, /* R20514 - DACR_RETUNE_C18_1 */ 1768 [20515] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20515 - DACR_RETUNE_C18_0 */ 1769 [20516] = { 0x00FF, 0x00FF, 0x0000 }, /* R20516 - DACR_RETUNE_C19_1 */ 1770 [20517] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20517 - DACR_RETUNE_C19_0 */ 1771 [20518] = { 0x00FF, 0x00FF, 0x0000 }, /* R20518 - DACR_RETUNE_C20_1 */ 1772 [20519] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20519 - DACR_RETUNE_C20_0 */ 1773 [20520] = { 0x00FF, 0x00FF, 0x0000 }, /* R20520 - DACR_RETUNE_C21_1 */ 1774 [20521] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20521 - DACR_RETUNE_C21_0 */ 1775 [20522] = { 0x00FF, 0x00FF, 0x0000 }, /* R20522 - DACR_RETUNE_C22_1 */ 1776 [20523] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20523 - DACR_RETUNE_C22_0 */ 1777 [20524] = { 0x00FF, 0x00FF, 0x0000 }, /* R20524 - DACR_RETUNE_C23_1 */ 1778 [20525] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20525 - DACR_RETUNE_C23_0 */ 1779 [20526] = { 0x00FF, 0x00FF, 0x0000 }, /* R20526 - DACR_RETUNE_C24_1 */ 1780 [20527] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20527 - DACR_RETUNE_C24_0 */ 1781 [20528] = { 0x00FF, 0x00FF, 0x0000 }, /* R20528 - DACR_RETUNE_C25_1 */ 1782 [20529] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20529 - DACR_RETUNE_C25_0 */ 1783 [20530] = { 0x00FF, 0x00FF, 0x0000 }, /* R20530 - DACR_RETUNE_C26_1 */ 1784 [20531] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20531 - DACR_RETUNE_C26_0 */ 1785 [20532] = { 0x00FF, 0x00FF, 0x0000 }, /* R20532 - DACR_RETUNE_C27_1 */ 1786 [20533] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20533 - DACR_RETUNE_C27_0 */ 1787 [20534] = { 0x00FF, 0x00FF, 0x0000 }, /* R20534 - DACR_RETUNE_C28_1 */ 1788 [20535] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20535 - DACR_RETUNE_C28_0 */ 1789 [20536] = { 0x00FF, 0x00FF, 0x0000 }, /* R20536 - DACR_RETUNE_C29_1 */ 1790 [20537] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20537 - DACR_RETUNE_C29_0 */ 1791 [20538] = { 0x00FF, 0x00FF, 0x0000 }, /* R20538 - DACR_RETUNE_C30_1 */ 1792 [20539] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20539 - DACR_RETUNE_C30_0 */ 1793 [20540] = { 0x00FF, 0x00FF, 0x0000 }, /* R20540 - DACR_RETUNE_C31_1 */ 1794 [20541] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20541 - DACR_RETUNE_C31_0 */ 1795 [20542] = { 0x00FF, 0x00FF, 0x0000 }, /* R20542 - DACR_RETUNE_C32_1 */ 1796 [20543] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20543 - DACR_RETUNE_C32_0 */ 1797 [20992] = { 0x00FF, 0x00FF, 0x0000 }, /* R20992 - VSS_XHD2_1 */ 1798 [20993] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20993 - VSS_XHD2_0 */ 1799 [20994] = { 0x00FF, 0x00FF, 0x0000 }, /* R20994 - VSS_XHD3_1 */ 1800 [20995] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20995 - VSS_XHD3_0 */ 1801 [20996] = { 0x00FF, 0x00FF, 0x0000 }, /* R20996 - VSS_XHN1_1 */ 1802 [20997] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20997 - VSS_XHN1_0 */ 1803 [20998] = { 0x00FF, 0x00FF, 0x0000 }, /* R20998 - VSS_XHN2_1 */ 1804 [20999] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R20999 - VSS_XHN2_0 */ 1805 [21000] = { 0x00FF, 0x00FF, 0x0000 }, /* R21000 - VSS_XHN3_1 */ 1806 [21001] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21001 - VSS_XHN3_0 */ 1807 [21002] = { 0x00FF, 0x00FF, 0x0000 }, /* R21002 - VSS_XLA_1 */ 1808 [21003] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21003 - VSS_XLA_0 */ 1809 [21004] = { 0x00FF, 0x00FF, 0x0000 }, /* R21004 - VSS_XLB_1 */ 1810 [21005] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21005 - VSS_XLB_0 */ 1811 [21006] = { 0x00FF, 0x00FF, 0x0000 }, /* R21006 - VSS_XLG_1 */ 1812 [21007] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21007 - VSS_XLG_0 */ 1813 [21008] = { 0x00FF, 0x00FF, 0x0000 }, /* R21008 - VSS_PG2_1 */ 1814 [21009] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21009 - VSS_PG2_0 */ 1815 [21010] = { 0x00FF, 0x00FF, 0x0000 }, /* R21010 - VSS_PG_1 */ 1816 [21011] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21011 - VSS_PG_0 */ 1817 [21012] = { 0x00FF, 0x00FF, 0x0000 }, /* R21012 - VSS_XTD1_1 */ 1818 [21013] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21013 - VSS_XTD1_0 */ 1819 [21014] = { 0x00FF, 0x00FF, 0x0000 }, /* R21014 - VSS_XTD2_1 */ 1820 [21015] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21015 - VSS_XTD2_0 */ 1821 [21016] = { 0x00FF, 0x00FF, 0x0000 }, /* R21016 - VSS_XTD3_1 */ 1822 [21017] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21017 - VSS_XTD3_0 */ 1823 [21018] = { 0x00FF, 0x00FF, 0x0000 }, /* R21018 - VSS_XTD4_1 */ 1824 [21019] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21019 - VSS_XTD4_0 */ 1825 [21020] = { 0x00FF, 0x00FF, 0x0000 }, /* R21020 - VSS_XTD5_1 */ 1826 [21021] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21021 - VSS_XTD5_0 */ 1827 [21022] = { 0x00FF, 0x00FF, 0x0000 }, /* R21022 - VSS_XTD6_1 */ 1828 [21023] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21023 - VSS_XTD6_0 */ 1829 [21024] = { 0x00FF, 0x00FF, 0x0000 }, /* R21024 - VSS_XTD7_1 */ 1830 [21025] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21025 - VSS_XTD7_0 */ 1831 [21026] = { 0x00FF, 0x00FF, 0x0000 }, /* R21026 - VSS_XTD8_1 */ 1832 [21027] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21027 - VSS_XTD8_0 */ 1833 [21028] = { 0x00FF, 0x00FF, 0x0000 }, /* R21028 - VSS_XTD9_1 */ 1834 [21029] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21029 - VSS_XTD9_0 */ 1835 [21030] = { 0x00FF, 0x00FF, 0x0000 }, /* R21030 - VSS_XTD10_1 */ 1836 [21031] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21031 - VSS_XTD10_0 */ 1837 [21032] = { 0x00FF, 0x00FF, 0x0000 }, /* R21032 - VSS_XTD11_1 */ 1838 [21033] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21033 - VSS_XTD11_0 */ 1839 [21034] = { 0x00FF, 0x00FF, 0x0000 }, /* R21034 - VSS_XTD12_1 */ 1840 [21035] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21035 - VSS_XTD12_0 */ 1841 [21036] = { 0x00FF, 0x00FF, 0x0000 }, /* R21036 - VSS_XTD13_1 */ 1842 [21037] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21037 - VSS_XTD13_0 */ 1843 [21038] = { 0x00FF, 0x00FF, 0x0000 }, /* R21038 - VSS_XTD14_1 */ 1844 [21039] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21039 - VSS_XTD14_0 */ 1845 [21040] = { 0x00FF, 0x00FF, 0x0000 }, /* R21040 - VSS_XTD15_1 */ 1846 [21041] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21041 - VSS_XTD15_0 */ 1847 [21042] = { 0x00FF, 0x00FF, 0x0000 }, /* R21042 - VSS_XTD16_1 */ 1848 [21043] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21043 - VSS_XTD16_0 */ 1849 [21044] = { 0x00FF, 0x00FF, 0x0000 }, /* R21044 - VSS_XTD17_1 */ 1850 [21045] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21045 - VSS_XTD17_0 */ 1851 [21046] = { 0x00FF, 0x00FF, 0x0000 }, /* R21046 - VSS_XTD18_1 */ 1852 [21047] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21047 - VSS_XTD18_0 */ 1853 [21048] = { 0x00FF, 0x00FF, 0x0000 }, /* R21048 - VSS_XTD19_1 */ 1854 [21049] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21049 - VSS_XTD19_0 */ 1855 [21050] = { 0x00FF, 0x00FF, 0x0000 }, /* R21050 - VSS_XTD20_1 */ 1856 [21051] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21051 - VSS_XTD20_0 */ 1857 [21052] = { 0x00FF, 0x00FF, 0x0000 }, /* R21052 - VSS_XTD21_1 */ 1858 [21053] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21053 - VSS_XTD21_0 */ 1859 [21054] = { 0x00FF, 0x00FF, 0x0000 }, /* R21054 - VSS_XTD22_1 */ 1860 [21055] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21055 - VSS_XTD22_0 */ 1861 [21056] = { 0x00FF, 0x00FF, 0x0000 }, /* R21056 - VSS_XTD23_1 */ 1862 [21057] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21057 - VSS_XTD23_0 */ 1863 [21058] = { 0x00FF, 0x00FF, 0x0000 }, /* R21058 - VSS_XTD24_1 */ 1864 [21059] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21059 - VSS_XTD24_0 */ 1865 [21060] = { 0x00FF, 0x00FF, 0x0000 }, /* R21060 - VSS_XTD25_1 */ 1866 [21061] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21061 - VSS_XTD25_0 */ 1867 [21062] = { 0x00FF, 0x00FF, 0x0000 }, /* R21062 - VSS_XTD26_1 */ 1868 [21063] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21063 - VSS_XTD26_0 */ 1869 [21064] = { 0x00FF, 0x00FF, 0x0000 }, /* R21064 - VSS_XTD27_1 */ 1870 [21065] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21065 - VSS_XTD27_0 */ 1871 [21066] = { 0x00FF, 0x00FF, 0x0000 }, /* R21066 - VSS_XTD28_1 */ 1872 [21067] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21067 - VSS_XTD28_0 */ 1873 [21068] = { 0x00FF, 0x00FF, 0x0000 }, /* R21068 - VSS_XTD29_1 */ 1874 [21069] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21069 - VSS_XTD29_0 */ 1875 [21070] = { 0x00FF, 0x00FF, 0x0000 }, /* R21070 - VSS_XTD30_1 */ 1876 [21071] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21071 - VSS_XTD30_0 */ 1877 [21072] = { 0x00FF, 0x00FF, 0x0000 }, /* R21072 - VSS_XTD31_1 */ 1878 [21073] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21073 - VSS_XTD31_0 */ 1879 [21074] = { 0x00FF, 0x00FF, 0x0000 }, /* R21074 - VSS_XTD32_1 */ 1880 [21075] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21075 - VSS_XTD32_0 */ 1881 [21076] = { 0x00FF, 0x00FF, 0x0000 }, /* R21076 - VSS_XTS1_1 */ 1882 [21077] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21077 - VSS_XTS1_0 */ 1883 [21078] = { 0x00FF, 0x00FF, 0x0000 }, /* R21078 - VSS_XTS2_1 */ 1884 [21079] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21079 - VSS_XTS2_0 */ 1885 [21080] = { 0x00FF, 0x00FF, 0x0000 }, /* R21080 - VSS_XTS3_1 */ 1886 [21081] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21081 - VSS_XTS3_0 */ 1887 [21082] = { 0x00FF, 0x00FF, 0x0000 }, /* R21082 - VSS_XTS4_1 */ 1888 [21083] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21083 - VSS_XTS4_0 */ 1889 [21084] = { 0x00FF, 0x00FF, 0x0000 }, /* R21084 - VSS_XTS5_1 */ 1890 [21085] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21085 - VSS_XTS5_0 */ 1891 [21086] = { 0x00FF, 0x00FF, 0x0000 }, /* R21086 - VSS_XTS6_1 */ 1892 [21087] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21087 - VSS_XTS6_0 */ 1893 [21088] = { 0x00FF, 0x00FF, 0x0000 }, /* R21088 - VSS_XTS7_1 */ 1894 [21089] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21089 - VSS_XTS7_0 */ 1895 [21090] = { 0x00FF, 0x00FF, 0x0000 }, /* R21090 - VSS_XTS8_1 */ 1896 [21091] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21091 - VSS_XTS8_0 */ 1897 [21092] = { 0x00FF, 0x00FF, 0x0000 }, /* R21092 - VSS_XTS9_1 */ 1898 [21093] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21093 - VSS_XTS9_0 */ 1899 [21094] = { 0x00FF, 0x00FF, 0x0000 }, /* R21094 - VSS_XTS10_1 */ 1900 [21095] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21095 - VSS_XTS10_0 */ 1901 [21096] = { 0x00FF, 0x00FF, 0x0000 }, /* R21096 - VSS_XTS11_1 */ 1902 [21097] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21097 - VSS_XTS11_0 */ 1903 [21098] = { 0x00FF, 0x00FF, 0x0000 }, /* R21098 - VSS_XTS12_1 */ 1904 [21099] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21099 - VSS_XTS12_0 */ 1905 [21100] = { 0x00FF, 0x00FF, 0x0000 }, /* R21100 - VSS_XTS13_1 */ 1906 [21101] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21101 - VSS_XTS13_0 */ 1907 [21102] = { 0x00FF, 0x00FF, 0x0000 }, /* R21102 - VSS_XTS14_1 */ 1908 [21103] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21103 - VSS_XTS14_0 */ 1909 [21104] = { 0x00FF, 0x00FF, 0x0000 }, /* R21104 - VSS_XTS15_1 */ 1910 [21105] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21105 - VSS_XTS15_0 */ 1911 [21106] = { 0x00FF, 0x00FF, 0x0000 }, /* R21106 - VSS_XTS16_1 */ 1912 [21107] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21107 - VSS_XTS16_0 */ 1913 [21108] = { 0x00FF, 0x00FF, 0x0000 }, /* R21108 - VSS_XTS17_1 */ 1914 [21109] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21109 - VSS_XTS17_0 */ 1915 [21110] = { 0x00FF, 0x00FF, 0x0000 }, /* R21110 - VSS_XTS18_1 */ 1916 [21111] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21111 - VSS_XTS18_0 */ 1917 [21112] = { 0x00FF, 0x00FF, 0x0000 }, /* R21112 - VSS_XTS19_1 */ 1918 [21113] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21113 - VSS_XTS19_0 */ 1919 [21114] = { 0x00FF, 0x00FF, 0x0000 }, /* R21114 - VSS_XTS20_1 */ 1920 [21115] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21115 - VSS_XTS20_0 */ 1921 [21116] = { 0x00FF, 0x00FF, 0x0000 }, /* R21116 - VSS_XTS21_1 */ 1922 [21117] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21117 - VSS_XTS21_0 */ 1923 [21118] = { 0x00FF, 0x00FF, 0x0000 }, /* R21118 - VSS_XTS22_1 */ 1924 [21119] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21119 - VSS_XTS22_0 */ 1925 [21120] = { 0x00FF, 0x00FF, 0x0000 }, /* R21120 - VSS_XTS23_1 */ 1926 [21121] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21121 - VSS_XTS23_0 */ 1927 [21122] = { 0x00FF, 0x00FF, 0x0000 }, /* R21122 - VSS_XTS24_1 */ 1928 [21123] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21123 - VSS_XTS24_0 */ 1929 [21124] = { 0x00FF, 0x00FF, 0x0000 }, /* R21124 - VSS_XTS25_1 */ 1930 [21125] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21125 - VSS_XTS25_0 */ 1931 [21126] = { 0x00FF, 0x00FF, 0x0000 }, /* R21126 - VSS_XTS26_1 */ 1932 [21127] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21127 - VSS_XTS26_0 */ 1933 [21128] = { 0x00FF, 0x00FF, 0x0000 }, /* R21128 - VSS_XTS27_1 */ 1934 [21129] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21129 - VSS_XTS27_0 */ 1935 [21130] = { 0x00FF, 0x00FF, 0x0000 }, /* R21130 - VSS_XTS28_1 */ 1936 [21131] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21131 - VSS_XTS28_0 */ 1937 [21132] = { 0x00FF, 0x00FF, 0x0000 }, /* R21132 - VSS_XTS29_1 */ 1938 [21133] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21133 - VSS_XTS29_0 */ 1939 [21134] = { 0x00FF, 0x00FF, 0x0000 }, /* R21134 - VSS_XTS30_1 */ 1940 [21135] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21135 - VSS_XTS30_0 */ 1941 [21136] = { 0x00FF, 0x00FF, 0x0000 }, /* R21136 - VSS_XTS31_1 */ 1942 [21137] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21137 - VSS_XTS31_0 */ 1943 [21138] = { 0x00FF, 0x00FF, 0x0000 }, /* R21138 - VSS_XTS32_1 */ 1944 [21139] = { 0xFFFF, 0xFFFF, 0x0000 }, /* R21139 - VSS_XTS32_0 */ 1945 }; 1946 1947 static bool wm8962_volatile_register(struct device *dev, unsigned int reg) 1948 { 1949 if (wm8962_reg_access[reg].vol) 1950 return 1; 1951 else 1952 return 0; 1953 } 1954 1955 static bool wm8962_readable_register(struct device *dev, unsigned int reg) 1956 { 1957 if (wm8962_reg_access[reg].read) 1958 return 1; 1959 else 1960 return 0; 1961 } 1962 1963 static int wm8962_reset(struct wm8962_priv *wm8962) 1964 { 1965 int ret; 1966 1967 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243); 1968 if (ret != 0) 1969 return ret; 1970 1971 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0); 1972 } 1973 1974 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0); 1975 static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0); 1976 static const unsigned int mixinpga_tlv[] = { 1977 TLV_DB_RANGE_HEAD(5), 1978 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0), 1979 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0), 1980 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0), 1981 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0), 1982 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0), 1983 }; 1984 static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1); 1985 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1); 1986 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0); 1987 static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0); 1988 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0); 1989 static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1); 1990 static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0); 1991 static const unsigned int classd_tlv[] = { 1992 TLV_DB_RANGE_HEAD(2), 1993 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0), 1994 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0), 1995 }; 1996 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0); 1997 1998 static int wm8962_dsp2_write_config(struct snd_soc_codec *codec) 1999 { 2000 return 0; 2001 } 2002 2003 static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val) 2004 { 2005 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME); 2006 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME); 2007 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1); 2008 2009 /* Mute the ADCs and DACs */ 2010 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0); 2011 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU); 2012 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 2013 WM8962_DAC_MUTE, WM8962_DAC_MUTE); 2014 2015 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val); 2016 2017 /* Restore the ADCs and DACs */ 2018 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl); 2019 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr); 2020 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 2021 WM8962_DAC_MUTE, dac); 2022 2023 return 0; 2024 } 2025 2026 static int wm8962_dsp2_start(struct snd_soc_codec *codec) 2027 { 2028 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2029 2030 wm8962_dsp2_write_config(codec); 2031 2032 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR); 2033 2034 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); 2035 2036 return 0; 2037 } 2038 2039 static int wm8962_dsp2_stop(struct snd_soc_codec *codec) 2040 { 2041 wm8962_dsp2_set_enable(codec, 0); 2042 2043 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP); 2044 2045 return 0; 2046 } 2047 2048 #define WM8962_DSP2_ENABLE(xname, xshift) \ 2049 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 2050 .info = wm8962_dsp2_ena_info, \ 2051 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \ 2052 .private_value = xshift } 2053 2054 static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol, 2055 struct snd_ctl_elem_info *uinfo) 2056 { 2057 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 2058 2059 uinfo->count = 1; 2060 uinfo->value.integer.min = 0; 2061 uinfo->value.integer.max = 1; 2062 2063 return 0; 2064 } 2065 2066 static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol, 2067 struct snd_ctl_elem_value *ucontrol) 2068 { 2069 int shift = kcontrol->private_value; 2070 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2071 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2072 2073 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift); 2074 2075 return 0; 2076 } 2077 2078 static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol, 2079 struct snd_ctl_elem_value *ucontrol) 2080 { 2081 int shift = kcontrol->private_value; 2082 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2083 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2084 int old = wm8962->dsp2_ena; 2085 int ret = 0; 2086 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) & 2087 WM8962_DSP2_ENA; 2088 2089 mutex_lock(&codec->mutex); 2090 2091 if (ucontrol->value.integer.value[0]) 2092 wm8962->dsp2_ena |= 1 << shift; 2093 else 2094 wm8962->dsp2_ena &= ~(1 << shift); 2095 2096 if (wm8962->dsp2_ena == old) 2097 goto out; 2098 2099 ret = 1; 2100 2101 if (dsp2_running) { 2102 if (wm8962->dsp2_ena) 2103 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena); 2104 else 2105 wm8962_dsp2_stop(codec); 2106 } 2107 2108 out: 2109 mutex_unlock(&codec->mutex); 2110 2111 return ret; 2112 } 2113 2114 /* The VU bits for the headphones are in a different register to the mute 2115 * bits and only take effect on the PGA if it is actually powered. 2116 */ 2117 static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol, 2118 struct snd_ctl_elem_value *ucontrol) 2119 { 2120 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2121 u16 *reg_cache = codec->reg_cache; 2122 int ret; 2123 2124 /* Apply the update (if any) */ 2125 ret = snd_soc_put_volsw(kcontrol, ucontrol); 2126 if (ret == 0) 2127 return 0; 2128 2129 /* If the left PGA is enabled hit that VU bit... */ 2130 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA) 2131 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME, 2132 reg_cache[WM8962_HPOUTL_VOLUME]); 2133 2134 /* ...otherwise the right. The VU is stereo. */ 2135 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA) 2136 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME, 2137 reg_cache[WM8962_HPOUTR_VOLUME]); 2138 2139 return 0; 2140 } 2141 2142 /* The VU bits for the speakers are in a different register to the mute 2143 * bits and only take effect on the PGA if it is actually powered. 2144 */ 2145 static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol, 2146 struct snd_ctl_elem_value *ucontrol) 2147 { 2148 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2149 int ret; 2150 2151 /* Apply the update (if any) */ 2152 ret = snd_soc_put_volsw(kcontrol, ucontrol); 2153 if (ret == 0) 2154 return 0; 2155 2156 /* If the left PGA is enabled hit that VU bit... */ 2157 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2); 2158 if (ret & WM8962_SPKOUTL_PGA_ENA) { 2159 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME, 2160 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME)); 2161 return 1; 2162 } 2163 2164 /* ...otherwise the right. The VU is stereo. */ 2165 if (ret & WM8962_SPKOUTR_PGA_ENA) 2166 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME, 2167 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME)); 2168 2169 return 1; 2170 } 2171 2172 static const char *cap_hpf_mode_text[] = { 2173 "Hi-fi", "Application" 2174 }; 2175 2176 static const struct soc_enum cap_hpf_mode = 2177 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text); 2178 2179 2180 static const char *cap_lhpf_mode_text[] = { 2181 "LPF", "HPF" 2182 }; 2183 2184 static const struct soc_enum cap_lhpf_mode = 2185 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text); 2186 2187 static const struct snd_kcontrol_new wm8962_snd_controls[] = { 2188 SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1), 2189 2190 SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0, 2191 mixin_tlv), 2192 SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0, 2193 mixinpga_tlv), 2194 SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0, 2195 mixin_tlv), 2196 2197 SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0, 2198 mixin_tlv), 2199 SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0, 2200 mixinpga_tlv), 2201 SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0, 2202 mixin_tlv), 2203 2204 SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME, 2205 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv), 2206 SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME, 2207 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv), 2208 SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME, 2209 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1), 2210 SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME, 2211 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1), 2212 SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1), 2213 SOC_ENUM("Capture HPF Mode", cap_hpf_mode), 2214 SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0), 2215 SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0), 2216 SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode), 2217 2218 SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1, 2219 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv), 2220 2221 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME, 2222 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv), 2223 SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0), 2224 2225 SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1, 2226 5, 1, 0), 2227 2228 SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv), 2229 2230 SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME, 2231 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv), 2232 SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1, 2233 snd_soc_get_volsw, wm8962_put_hp_sw), 2234 SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME, 2235 7, 1, 0), 2236 SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0, 2237 hp_tlv), 2238 2239 SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3, 2240 WM8962_HEADPHONE_MIXER_4, 8, 1, 1), 2241 2242 SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3, 2243 3, 7, 0, bypass_tlv), 2244 SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3, 2245 0, 7, 0, bypass_tlv), 2246 SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3, 2247 7, 1, 1, inmix_tlv), 2248 SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3, 2249 6, 1, 1, inmix_tlv), 2250 2251 SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4, 2252 3, 7, 0, bypass_tlv), 2253 SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4, 2254 0, 7, 0, bypass_tlv), 2255 SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4, 2256 7, 1, 1, inmix_tlv), 2257 SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4, 2258 6, 1, 1, inmix_tlv), 2259 2260 SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0, 2261 classd_tlv), 2262 2263 SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0), 2264 SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22, 2265 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv), 2266 SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22, 2267 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv), 2268 SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22, 2269 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv), 2270 SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23, 2271 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv), 2272 SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23, 2273 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv), 2274 2275 WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT), 2276 WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT), 2277 WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT), 2278 WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT), 2279 }; 2280 2281 static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = { 2282 SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv), 2283 SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1, 2284 snd_soc_get_volsw, wm8962_put_spk_sw), 2285 SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0), 2286 2287 SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1), 2288 SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 2289 3, 7, 0, bypass_tlv), 2290 SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 2291 0, 7, 0, bypass_tlv), 2292 SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 2293 7, 1, 1, inmix_tlv), 2294 SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 2295 6, 1, 1, inmix_tlv), 2296 SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 2297 7, 1, 0, inmix_tlv), 2298 SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 2299 6, 1, 0, inmix_tlv), 2300 }; 2301 2302 static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = { 2303 SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 2304 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv), 2305 SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1, 2306 snd_soc_get_volsw, wm8962_put_spk_sw), 2307 SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME, 2308 7, 1, 0), 2309 2310 SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 2311 WM8962_SPEAKER_MIXER_4, 8, 1, 1), 2312 2313 SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3, 2314 3, 7, 0, bypass_tlv), 2315 SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3, 2316 0, 7, 0, bypass_tlv), 2317 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3, 2318 7, 1, 1, inmix_tlv), 2319 SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3, 2320 6, 1, 1, inmix_tlv), 2321 SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 2322 7, 1, 0, inmix_tlv), 2323 SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 2324 6, 1, 0, inmix_tlv), 2325 2326 SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4, 2327 3, 7, 0, bypass_tlv), 2328 SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4, 2329 0, 7, 0, bypass_tlv), 2330 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4, 2331 7, 1, 1, inmix_tlv), 2332 SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4, 2333 6, 1, 1, inmix_tlv), 2334 SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5, 2335 5, 1, 0, inmix_tlv), 2336 SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5, 2337 4, 1, 0, inmix_tlv), 2338 }; 2339 2340 static int sysclk_event(struct snd_soc_dapm_widget *w, 2341 struct snd_kcontrol *kcontrol, int event) 2342 { 2343 struct snd_soc_codec *codec = w->codec; 2344 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2345 unsigned long timeout; 2346 int src; 2347 int fll; 2348 2349 /* Ignore attempts to run the event during startup */ 2350 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 2351 return 0; 2352 2353 src = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_SRC_MASK; 2354 2355 switch (src) { 2356 case 0: /* MCLK */ 2357 fll = 0; 2358 break; 2359 case 0x200: /* FLL */ 2360 fll = 1; 2361 break; 2362 default: 2363 dev_err(codec->dev, "Unknown SYSCLK source %x\n", src); 2364 return -EINVAL; 2365 } 2366 2367 switch (event) { 2368 case SND_SOC_DAPM_PRE_PMU: 2369 if (fll) { 2370 try_wait_for_completion(&wm8962->fll_lock); 2371 2372 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 2373 WM8962_FLL_ENA, WM8962_FLL_ENA); 2374 2375 timeout = msecs_to_jiffies(5); 2376 timeout = wait_for_completion_timeout(&wm8962->fll_lock, 2377 timeout); 2378 2379 if (wm8962->irq && timeout == 0) 2380 dev_err(codec->dev, 2381 "Timed out starting FLL\n"); 2382 } 2383 break; 2384 2385 case SND_SOC_DAPM_POST_PMD: 2386 if (fll) 2387 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 2388 WM8962_FLL_ENA, 0); 2389 break; 2390 2391 default: 2392 BUG(); 2393 return -EINVAL; 2394 } 2395 2396 return 0; 2397 } 2398 2399 static int cp_event(struct snd_soc_dapm_widget *w, 2400 struct snd_kcontrol *kcontrol, int event) 2401 { 2402 switch (event) { 2403 case SND_SOC_DAPM_POST_PMU: 2404 msleep(5); 2405 break; 2406 2407 default: 2408 BUG(); 2409 return -EINVAL; 2410 } 2411 2412 return 0; 2413 } 2414 2415 static int hp_event(struct snd_soc_dapm_widget *w, 2416 struct snd_kcontrol *kcontrol, int event) 2417 { 2418 struct snd_soc_codec *codec = w->codec; 2419 int timeout; 2420 int reg; 2421 int expected = (WM8962_DCS_STARTUP_DONE_HP1L | 2422 WM8962_DCS_STARTUP_DONE_HP1R); 2423 2424 switch (event) { 2425 case SND_SOC_DAPM_POST_PMU: 2426 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2427 WM8962_HP1L_ENA | WM8962_HP1R_ENA, 2428 WM8962_HP1L_ENA | WM8962_HP1R_ENA); 2429 udelay(20); 2430 2431 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2432 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY, 2433 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY); 2434 2435 /* Start the DC servo */ 2436 snd_soc_update_bits(codec, WM8962_DC_SERVO_1, 2437 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 2438 WM8962_HP1L_DCS_STARTUP | 2439 WM8962_HP1R_DCS_STARTUP, 2440 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 2441 WM8962_HP1L_DCS_STARTUP | 2442 WM8962_HP1R_DCS_STARTUP); 2443 2444 /* Wait for it to complete, should be well under 100ms */ 2445 timeout = 0; 2446 do { 2447 msleep(1); 2448 reg = snd_soc_read(codec, WM8962_DC_SERVO_6); 2449 if (reg < 0) { 2450 dev_err(codec->dev, 2451 "Failed to read DCS status: %d\n", 2452 reg); 2453 continue; 2454 } 2455 dev_dbg(codec->dev, "DCS status: %x\n", reg); 2456 } while (++timeout < 200 && (reg & expected) != expected); 2457 2458 if ((reg & expected) != expected) 2459 dev_err(codec->dev, "DC servo timed out\n"); 2460 else 2461 dev_dbg(codec->dev, "DC servo complete after %dms\n", 2462 timeout); 2463 2464 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2465 WM8962_HP1L_ENA_OUTP | 2466 WM8962_HP1R_ENA_OUTP, 2467 WM8962_HP1L_ENA_OUTP | 2468 WM8962_HP1R_ENA_OUTP); 2469 udelay(20); 2470 2471 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2472 WM8962_HP1L_RMV_SHORT | 2473 WM8962_HP1R_RMV_SHORT, 2474 WM8962_HP1L_RMV_SHORT | 2475 WM8962_HP1R_RMV_SHORT); 2476 break; 2477 2478 case SND_SOC_DAPM_PRE_PMD: 2479 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2480 WM8962_HP1L_RMV_SHORT | 2481 WM8962_HP1R_RMV_SHORT, 0); 2482 2483 udelay(20); 2484 2485 snd_soc_update_bits(codec, WM8962_DC_SERVO_1, 2486 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA | 2487 WM8962_HP1L_DCS_STARTUP | 2488 WM8962_HP1R_DCS_STARTUP, 2489 0); 2490 2491 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0, 2492 WM8962_HP1L_ENA | WM8962_HP1R_ENA | 2493 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY | 2494 WM8962_HP1L_ENA_OUTP | 2495 WM8962_HP1R_ENA_OUTP, 0); 2496 2497 break; 2498 2499 default: 2500 BUG(); 2501 return -EINVAL; 2502 2503 } 2504 2505 return 0; 2506 } 2507 2508 /* VU bits for the output PGAs only take effect while the PGA is powered */ 2509 static int out_pga_event(struct snd_soc_dapm_widget *w, 2510 struct snd_kcontrol *kcontrol, int event) 2511 { 2512 struct snd_soc_codec *codec = w->codec; 2513 int reg; 2514 2515 switch (w->shift) { 2516 case WM8962_HPOUTR_PGA_ENA_SHIFT: 2517 reg = WM8962_HPOUTR_VOLUME; 2518 break; 2519 case WM8962_HPOUTL_PGA_ENA_SHIFT: 2520 reg = WM8962_HPOUTL_VOLUME; 2521 break; 2522 case WM8962_SPKOUTR_PGA_ENA_SHIFT: 2523 reg = WM8962_SPKOUTR_VOLUME; 2524 break; 2525 case WM8962_SPKOUTL_PGA_ENA_SHIFT: 2526 reg = WM8962_SPKOUTL_VOLUME; 2527 break; 2528 default: 2529 BUG(); 2530 return -EINVAL; 2531 } 2532 2533 switch (event) { 2534 case SND_SOC_DAPM_POST_PMU: 2535 return snd_soc_write(codec, reg, snd_soc_read(codec, reg)); 2536 default: 2537 BUG(); 2538 return -EINVAL; 2539 } 2540 } 2541 2542 static int dsp2_event(struct snd_soc_dapm_widget *w, 2543 struct snd_kcontrol *kcontrol, int event) 2544 { 2545 struct snd_soc_codec *codec = w->codec; 2546 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2547 2548 switch (event) { 2549 case SND_SOC_DAPM_POST_PMU: 2550 if (wm8962->dsp2_ena) 2551 wm8962_dsp2_start(codec); 2552 break; 2553 2554 case SND_SOC_DAPM_PRE_PMD: 2555 if (wm8962->dsp2_ena) 2556 wm8962_dsp2_stop(codec); 2557 break; 2558 2559 default: 2560 BUG(); 2561 return -EINVAL; 2562 } 2563 2564 return 0; 2565 } 2566 2567 static const char *st_text[] = { "None", "Left", "Right" }; 2568 2569 static const struct soc_enum str_enum = 2570 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text); 2571 2572 static const struct snd_kcontrol_new str_mux = 2573 SOC_DAPM_ENUM("Right Sidetone", str_enum); 2574 2575 static const struct soc_enum stl_enum = 2576 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text); 2577 2578 static const struct snd_kcontrol_new stl_mux = 2579 SOC_DAPM_ENUM("Left Sidetone", stl_enum); 2580 2581 static const char *outmux_text[] = { "DAC", "Mixer" }; 2582 2583 static const struct soc_enum spkoutr_enum = 2584 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text); 2585 2586 static const struct snd_kcontrol_new spkoutr_mux = 2587 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum); 2588 2589 static const struct soc_enum spkoutl_enum = 2590 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text); 2591 2592 static const struct snd_kcontrol_new spkoutl_mux = 2593 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum); 2594 2595 static const struct soc_enum hpoutr_enum = 2596 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text); 2597 2598 static const struct snd_kcontrol_new hpoutr_mux = 2599 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum); 2600 2601 static const struct soc_enum hpoutl_enum = 2602 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text); 2603 2604 static const struct snd_kcontrol_new hpoutl_mux = 2605 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum); 2606 2607 static const struct snd_kcontrol_new inpgal[] = { 2608 SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0), 2609 SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0), 2610 SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0), 2611 SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0), 2612 }; 2613 2614 static const struct snd_kcontrol_new inpgar[] = { 2615 SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0), 2616 SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0), 2617 SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0), 2618 SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0), 2619 }; 2620 2621 static const struct snd_kcontrol_new mixinl[] = { 2622 SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0), 2623 SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0), 2624 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0), 2625 }; 2626 2627 static const struct snd_kcontrol_new mixinr[] = { 2628 SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0), 2629 SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0), 2630 SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0), 2631 }; 2632 2633 static const struct snd_kcontrol_new hpmixl[] = { 2634 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0), 2635 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0), 2636 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0), 2637 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0), 2638 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0), 2639 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0), 2640 }; 2641 2642 static const struct snd_kcontrol_new hpmixr[] = { 2643 SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0), 2644 SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0), 2645 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0), 2646 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0), 2647 SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0), 2648 SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0), 2649 }; 2650 2651 static const struct snd_kcontrol_new spkmixl[] = { 2652 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0), 2653 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0), 2654 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0), 2655 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0), 2656 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0), 2657 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0), 2658 }; 2659 2660 static const struct snd_kcontrol_new spkmixr[] = { 2661 SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0), 2662 SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0), 2663 SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0), 2664 SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0), 2665 SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0), 2666 SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0), 2667 }; 2668 2669 static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = { 2670 SND_SOC_DAPM_INPUT("IN1L"), 2671 SND_SOC_DAPM_INPUT("IN1R"), 2672 SND_SOC_DAPM_INPUT("IN2L"), 2673 SND_SOC_DAPM_INPUT("IN2R"), 2674 SND_SOC_DAPM_INPUT("IN3L"), 2675 SND_SOC_DAPM_INPUT("IN3R"), 2676 SND_SOC_DAPM_INPUT("IN4L"), 2677 SND_SOC_DAPM_INPUT("IN4R"), 2678 SND_SOC_DAPM_SIGGEN("Beep"), 2679 SND_SOC_DAPM_INPUT("DMICDAT"), 2680 2681 SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0), 2682 2683 SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0), 2684 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, sysclk_event, 2685 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2686 SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event, 2687 SND_SOC_DAPM_POST_PMU), 2688 SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0), 2689 SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT, 2690 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event, 2691 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2692 SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0), 2693 SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0), 2694 2695 SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0, 2696 inpgal, ARRAY_SIZE(inpgal)), 2697 SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0, 2698 inpgar, ARRAY_SIZE(inpgar)), 2699 SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0, 2700 mixinl, ARRAY_SIZE(mixinl)), 2701 SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0, 2702 mixinr, ARRAY_SIZE(mixinr)), 2703 2704 SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0), 2705 2706 SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0), 2707 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0), 2708 2709 SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux), 2710 SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux), 2711 2712 SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0), 2713 SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0), 2714 2715 SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2716 SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0), 2717 2718 SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0, 2719 hpmixl, ARRAY_SIZE(hpmixl)), 2720 SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0, 2721 hpmixr, ARRAY_SIZE(hpmixr)), 2722 2723 SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux, 2724 out_pga_event, SND_SOC_DAPM_POST_PMU), 2725 SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux, 2726 out_pga_event, SND_SOC_DAPM_POST_PMU), 2727 2728 SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event, 2729 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2730 2731 SND_SOC_DAPM_OUTPUT("HPOUTL"), 2732 SND_SOC_DAPM_OUTPUT("HPOUTR"), 2733 }; 2734 2735 static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = { 2736 SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0, 2737 spkmixl, ARRAY_SIZE(spkmixl)), 2738 SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2739 out_pga_event, SND_SOC_DAPM_POST_PMU), 2740 SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2741 SND_SOC_DAPM_OUTPUT("SPKOUT"), 2742 }; 2743 2744 static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = { 2745 SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0, 2746 spkmixl, ARRAY_SIZE(spkmixl)), 2747 SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0, 2748 spkmixr, ARRAY_SIZE(spkmixr)), 2749 2750 SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux, 2751 out_pga_event, SND_SOC_DAPM_POST_PMU), 2752 SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux, 2753 out_pga_event, SND_SOC_DAPM_POST_PMU), 2754 2755 SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0), 2756 SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0), 2757 2758 SND_SOC_DAPM_OUTPUT("SPKOUTL"), 2759 SND_SOC_DAPM_OUTPUT("SPKOUTR"), 2760 }; 2761 2762 static const struct snd_soc_dapm_route wm8962_intercon[] = { 2763 { "INPGAL", "IN1L Switch", "IN1L" }, 2764 { "INPGAL", "IN2L Switch", "IN2L" }, 2765 { "INPGAL", "IN3L Switch", "IN3L" }, 2766 { "INPGAL", "IN4L Switch", "IN4L" }, 2767 2768 { "INPGAR", "IN1R Switch", "IN1R" }, 2769 { "INPGAR", "IN2R Switch", "IN2R" }, 2770 { "INPGAR", "IN3R Switch", "IN3R" }, 2771 { "INPGAR", "IN4R Switch", "IN4R" }, 2772 2773 { "MIXINL", "IN2L Switch", "IN2L" }, 2774 { "MIXINL", "IN3L Switch", "IN3L" }, 2775 { "MIXINL", "PGA Switch", "INPGAL" }, 2776 2777 { "MIXINR", "IN2R Switch", "IN2R" }, 2778 { "MIXINR", "IN3R Switch", "IN3R" }, 2779 { "MIXINR", "PGA Switch", "INPGAR" }, 2780 2781 { "MICBIAS", NULL, "SYSCLK" }, 2782 2783 { "DMIC_ENA", NULL, "DMICDAT" }, 2784 2785 { "ADCL", NULL, "SYSCLK" }, 2786 { "ADCL", NULL, "TOCLK" }, 2787 { "ADCL", NULL, "MIXINL" }, 2788 { "ADCL", NULL, "DMIC_ENA" }, 2789 { "ADCL", NULL, "DSP2" }, 2790 2791 { "ADCR", NULL, "SYSCLK" }, 2792 { "ADCR", NULL, "TOCLK" }, 2793 { "ADCR", NULL, "MIXINR" }, 2794 { "ADCR", NULL, "DMIC_ENA" }, 2795 { "ADCR", NULL, "DSP2" }, 2796 2797 { "STL", "Left", "ADCL" }, 2798 { "STL", "Right", "ADCR" }, 2799 2800 { "STR", "Left", "ADCL" }, 2801 { "STR", "Right", "ADCR" }, 2802 2803 { "DACL", NULL, "SYSCLK" }, 2804 { "DACL", NULL, "TOCLK" }, 2805 { "DACL", NULL, "Beep" }, 2806 { "DACL", NULL, "STL" }, 2807 { "DACL", NULL, "DSP2" }, 2808 2809 { "DACR", NULL, "SYSCLK" }, 2810 { "DACR", NULL, "TOCLK" }, 2811 { "DACR", NULL, "Beep" }, 2812 { "DACR", NULL, "STR" }, 2813 { "DACR", NULL, "DSP2" }, 2814 2815 { "HPMIXL", "IN4L Switch", "IN4L" }, 2816 { "HPMIXL", "IN4R Switch", "IN4R" }, 2817 { "HPMIXL", "DACL Switch", "DACL" }, 2818 { "HPMIXL", "DACR Switch", "DACR" }, 2819 { "HPMIXL", "MIXINL Switch", "MIXINL" }, 2820 { "HPMIXL", "MIXINR Switch", "MIXINR" }, 2821 2822 { "HPMIXR", "IN4L Switch", "IN4L" }, 2823 { "HPMIXR", "IN4R Switch", "IN4R" }, 2824 { "HPMIXR", "DACL Switch", "DACL" }, 2825 { "HPMIXR", "DACR Switch", "DACR" }, 2826 { "HPMIXR", "MIXINL Switch", "MIXINL" }, 2827 { "HPMIXR", "MIXINR Switch", "MIXINR" }, 2828 2829 { "Left Bypass", NULL, "HPMIXL" }, 2830 { "Left Bypass", NULL, "Class G" }, 2831 2832 { "Right Bypass", NULL, "HPMIXR" }, 2833 { "Right Bypass", NULL, "Class G" }, 2834 2835 { "HPOUTL PGA", "Mixer", "Left Bypass" }, 2836 { "HPOUTL PGA", "DAC", "DACL" }, 2837 2838 { "HPOUTR PGA", "Mixer", "Right Bypass" }, 2839 { "HPOUTR PGA", "DAC", "DACR" }, 2840 2841 { "HPOUT", NULL, "HPOUTL PGA" }, 2842 { "HPOUT", NULL, "HPOUTR PGA" }, 2843 { "HPOUT", NULL, "Charge Pump" }, 2844 { "HPOUT", NULL, "SYSCLK" }, 2845 { "HPOUT", NULL, "TOCLK" }, 2846 2847 { "HPOUTL", NULL, "HPOUT" }, 2848 { "HPOUTR", NULL, "HPOUT" }, 2849 2850 { "HPOUTL", NULL, "TEMP_HP" }, 2851 { "HPOUTR", NULL, "TEMP_HP" }, 2852 }; 2853 2854 static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = { 2855 { "Speaker Mixer", "IN4L Switch", "IN4L" }, 2856 { "Speaker Mixer", "IN4R Switch", "IN4R" }, 2857 { "Speaker Mixer", "DACL Switch", "DACL" }, 2858 { "Speaker Mixer", "DACR Switch", "DACR" }, 2859 { "Speaker Mixer", "MIXINL Switch", "MIXINL" }, 2860 { "Speaker Mixer", "MIXINR Switch", "MIXINR" }, 2861 2862 { "Speaker PGA", "Mixer", "Speaker Mixer" }, 2863 { "Speaker PGA", "DAC", "DACL" }, 2864 2865 { "Speaker Output", NULL, "Speaker PGA" }, 2866 { "Speaker Output", NULL, "SYSCLK" }, 2867 { "Speaker Output", NULL, "TOCLK" }, 2868 { "Speaker Output", NULL, "TEMP_SPK" }, 2869 2870 { "SPKOUT", NULL, "Speaker Output" }, 2871 }; 2872 2873 static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = { 2874 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" }, 2875 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" }, 2876 { "SPKOUTL Mixer", "DACL Switch", "DACL" }, 2877 { "SPKOUTL Mixer", "DACR Switch", "DACR" }, 2878 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" }, 2879 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" }, 2880 2881 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" }, 2882 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" }, 2883 { "SPKOUTR Mixer", "DACL Switch", "DACL" }, 2884 { "SPKOUTR Mixer", "DACR Switch", "DACR" }, 2885 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" }, 2886 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" }, 2887 2888 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" }, 2889 { "SPKOUTL PGA", "DAC", "DACL" }, 2890 2891 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" }, 2892 { "SPKOUTR PGA", "DAC", "DACR" }, 2893 2894 { "SPKOUTL Output", NULL, "SPKOUTL PGA" }, 2895 { "SPKOUTL Output", NULL, "SYSCLK" }, 2896 { "SPKOUTL Output", NULL, "TOCLK" }, 2897 { "SPKOUTL Output", NULL, "TEMP_SPK" }, 2898 2899 { "SPKOUTR Output", NULL, "SPKOUTR PGA" }, 2900 { "SPKOUTR Output", NULL, "SYSCLK" }, 2901 { "SPKOUTR Output", NULL, "TOCLK" }, 2902 { "SPKOUTR Output", NULL, "TEMP_SPK" }, 2903 2904 { "SPKOUTL", NULL, "SPKOUTL Output" }, 2905 { "SPKOUTR", NULL, "SPKOUTR Output" }, 2906 }; 2907 2908 static int wm8962_add_widgets(struct snd_soc_codec *codec) 2909 { 2910 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 2911 struct snd_soc_dapm_context *dapm = &codec->dapm; 2912 2913 snd_soc_add_controls(codec, wm8962_snd_controls, 2914 ARRAY_SIZE(wm8962_snd_controls)); 2915 if (pdata && pdata->spk_mono) 2916 snd_soc_add_controls(codec, wm8962_spk_mono_controls, 2917 ARRAY_SIZE(wm8962_spk_mono_controls)); 2918 else 2919 snd_soc_add_controls(codec, wm8962_spk_stereo_controls, 2920 ARRAY_SIZE(wm8962_spk_stereo_controls)); 2921 2922 2923 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets, 2924 ARRAY_SIZE(wm8962_dapm_widgets)); 2925 if (pdata && pdata->spk_mono) 2926 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets, 2927 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets)); 2928 else 2929 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets, 2930 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets)); 2931 2932 snd_soc_dapm_add_routes(dapm, wm8962_intercon, 2933 ARRAY_SIZE(wm8962_intercon)); 2934 if (pdata && pdata->spk_mono) 2935 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon, 2936 ARRAY_SIZE(wm8962_spk_mono_intercon)); 2937 else 2938 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon, 2939 ARRAY_SIZE(wm8962_spk_stereo_intercon)); 2940 2941 2942 snd_soc_dapm_disable_pin(dapm, "Beep"); 2943 2944 return 0; 2945 } 2946 2947 /* -1 for reserved values */ 2948 static const int bclk_divs[] = { 2949 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32 2950 }; 2951 2952 static const int sysclk_rates[] = { 2953 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 2954 }; 2955 2956 static void wm8962_configure_bclk(struct snd_soc_codec *codec) 2957 { 2958 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 2959 int dspclk, i; 2960 int clocking2 = 0; 2961 int clocking4 = 0; 2962 int aif2 = 0; 2963 2964 if (!wm8962->sysclk_rate) { 2965 dev_dbg(codec->dev, "No SYSCLK configured\n"); 2966 return; 2967 } 2968 2969 if (!wm8962->bclk || !wm8962->lrclk) { 2970 dev_dbg(codec->dev, "No audio clocks configured\n"); 2971 return; 2972 } 2973 2974 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) { 2975 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) { 2976 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT; 2977 break; 2978 } 2979 } 2980 2981 if (i == ARRAY_SIZE(sysclk_rates)) { 2982 dev_err(codec->dev, "Unsupported sysclk ratio %d\n", 2983 wm8962->sysclk_rate / wm8962->lrclk); 2984 return; 2985 } 2986 2987 snd_soc_update_bits(codec, WM8962_CLOCKING_4, 2988 WM8962_SYSCLK_RATE_MASK, clocking4); 2989 2990 dspclk = snd_soc_read(codec, WM8962_CLOCKING1); 2991 if (dspclk < 0) { 2992 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk); 2993 return; 2994 } 2995 2996 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT; 2997 switch (dspclk) { 2998 case 0: 2999 dspclk = wm8962->sysclk_rate; 3000 break; 3001 case 1: 3002 dspclk = wm8962->sysclk_rate / 2; 3003 break; 3004 case 2: 3005 dspclk = wm8962->sysclk_rate / 4; 3006 break; 3007 default: 3008 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n"); 3009 dspclk = wm8962->sysclk; 3010 } 3011 3012 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); 3013 3014 /* We're expecting an exact match */ 3015 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) { 3016 if (bclk_divs[i] < 0) 3017 continue; 3018 3019 if (dspclk / bclk_divs[i] == wm8962->bclk) { 3020 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n", 3021 bclk_divs[i], wm8962->bclk); 3022 clocking2 |= i; 3023 break; 3024 } 3025 } 3026 if (i == ARRAY_SIZE(bclk_divs)) { 3027 dev_err(codec->dev, "Unsupported BCLK ratio %d\n", 3028 dspclk / wm8962->bclk); 3029 return; 3030 } 3031 3032 aif2 |= wm8962->bclk / wm8962->lrclk; 3033 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n", 3034 wm8962->bclk / wm8962->lrclk, wm8962->lrclk); 3035 3036 snd_soc_update_bits(codec, WM8962_CLOCKING2, 3037 WM8962_BCLK_DIV_MASK, clocking2); 3038 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2, 3039 WM8962_AIF_RATE_MASK, aif2); 3040 } 3041 3042 static int wm8962_set_bias_level(struct snd_soc_codec *codec, 3043 enum snd_soc_bias_level level) 3044 { 3045 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3046 int ret; 3047 3048 if (level == codec->dapm.bias_level) 3049 return 0; 3050 3051 switch (level) { 3052 case SND_SOC_BIAS_ON: 3053 break; 3054 3055 case SND_SOC_BIAS_PREPARE: 3056 /* VMID 2*50k */ 3057 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 3058 WM8962_VMID_SEL_MASK, 0x80); 3059 3060 wm8962_configure_bclk(codec); 3061 break; 3062 3063 case SND_SOC_BIAS_STANDBY: 3064 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 3065 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 3066 wm8962->supplies); 3067 if (ret != 0) { 3068 dev_err(codec->dev, 3069 "Failed to enable supplies: %d\n", 3070 ret); 3071 return ret; 3072 } 3073 3074 regcache_cache_only(wm8962->regmap, false); 3075 regcache_sync(wm8962->regmap); 3076 3077 snd_soc_update_bits(codec, WM8962_ANTI_POP, 3078 WM8962_STARTUP_BIAS_ENA | 3079 WM8962_VMID_BUF_ENA, 3080 WM8962_STARTUP_BIAS_ENA | 3081 WM8962_VMID_BUF_ENA); 3082 3083 /* Bias enable at 2*50k for ramp */ 3084 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 3085 WM8962_VMID_SEL_MASK | 3086 WM8962_BIAS_ENA, 3087 WM8962_BIAS_ENA | 0x180); 3088 3089 msleep(5); 3090 } 3091 3092 /* VMID 2*250k */ 3093 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 3094 WM8962_VMID_SEL_MASK, 0x100); 3095 break; 3096 3097 case SND_SOC_BIAS_OFF: 3098 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1, 3099 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0); 3100 3101 snd_soc_update_bits(codec, WM8962_ANTI_POP, 3102 WM8962_STARTUP_BIAS_ENA | 3103 WM8962_VMID_BUF_ENA, 0); 3104 3105 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), 3106 wm8962->supplies); 3107 break; 3108 } 3109 codec->dapm.bias_level = level; 3110 return 0; 3111 } 3112 3113 static const struct { 3114 int rate; 3115 int reg; 3116 } sr_vals[] = { 3117 { 48000, 0 }, 3118 { 44100, 0 }, 3119 { 32000, 1 }, 3120 { 22050, 2 }, 3121 { 24000, 2 }, 3122 { 16000, 3 }, 3123 { 11025, 4 }, 3124 { 12000, 4 }, 3125 { 8000, 5 }, 3126 { 88200, 6 }, 3127 { 96000, 6 }, 3128 }; 3129 3130 static int wm8962_hw_params(struct snd_pcm_substream *substream, 3131 struct snd_pcm_hw_params *params, 3132 struct snd_soc_dai *dai) 3133 { 3134 struct snd_soc_pcm_runtime *rtd = substream->private_data; 3135 struct snd_soc_codec *codec = rtd->codec; 3136 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3137 int i; 3138 int aif0 = 0; 3139 int adctl3 = 0; 3140 3141 wm8962->bclk = snd_soc_params_to_bclk(params); 3142 wm8962->lrclk = params_rate(params); 3143 3144 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) { 3145 if (sr_vals[i].rate == wm8962->lrclk) { 3146 adctl3 |= sr_vals[i].reg; 3147 break; 3148 } 3149 } 3150 if (i == ARRAY_SIZE(sr_vals)) { 3151 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk); 3152 return -EINVAL; 3153 } 3154 3155 if (wm8962->lrclk % 8000 == 0) 3156 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE; 3157 3158 switch (params_format(params)) { 3159 case SNDRV_PCM_FORMAT_S16_LE: 3160 break; 3161 case SNDRV_PCM_FORMAT_S20_3LE: 3162 aif0 |= 0x4; 3163 break; 3164 case SNDRV_PCM_FORMAT_S24_LE: 3165 aif0 |= 0x8; 3166 break; 3167 case SNDRV_PCM_FORMAT_S32_LE: 3168 aif0 |= 0xc; 3169 break; 3170 default: 3171 return -EINVAL; 3172 } 3173 3174 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, 3175 WM8962_WL_MASK, aif0); 3176 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3, 3177 WM8962_SAMPLE_RATE_INT_MODE | 3178 WM8962_SAMPLE_RATE_MASK, adctl3); 3179 3180 wm8962_configure_bclk(codec); 3181 3182 return 0; 3183 } 3184 3185 static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id, 3186 unsigned int freq, int dir) 3187 { 3188 struct snd_soc_codec *codec = dai->codec; 3189 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3190 int src; 3191 3192 switch (clk_id) { 3193 case WM8962_SYSCLK_MCLK: 3194 wm8962->sysclk = WM8962_SYSCLK_MCLK; 3195 src = 0; 3196 break; 3197 case WM8962_SYSCLK_FLL: 3198 wm8962->sysclk = WM8962_SYSCLK_FLL; 3199 src = 1 << WM8962_SYSCLK_SRC_SHIFT; 3200 break; 3201 default: 3202 return -EINVAL; 3203 } 3204 3205 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK, 3206 src); 3207 3208 wm8962->sysclk_rate = freq; 3209 3210 return 0; 3211 } 3212 3213 static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt) 3214 { 3215 struct snd_soc_codec *codec = dai->codec; 3216 int aif0 = 0; 3217 3218 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 3219 case SND_SOC_DAIFMT_DSP_B: 3220 aif0 |= WM8962_LRCLK_INV | 3; 3221 case SND_SOC_DAIFMT_DSP_A: 3222 aif0 |= 3; 3223 3224 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3225 case SND_SOC_DAIFMT_NB_NF: 3226 case SND_SOC_DAIFMT_IB_NF: 3227 break; 3228 default: 3229 return -EINVAL; 3230 } 3231 break; 3232 3233 case SND_SOC_DAIFMT_RIGHT_J: 3234 break; 3235 case SND_SOC_DAIFMT_LEFT_J: 3236 aif0 |= 1; 3237 break; 3238 case SND_SOC_DAIFMT_I2S: 3239 aif0 |= 2; 3240 break; 3241 default: 3242 return -EINVAL; 3243 } 3244 3245 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 3246 case SND_SOC_DAIFMT_NB_NF: 3247 break; 3248 case SND_SOC_DAIFMT_IB_NF: 3249 aif0 |= WM8962_BCLK_INV; 3250 break; 3251 case SND_SOC_DAIFMT_NB_IF: 3252 aif0 |= WM8962_LRCLK_INV; 3253 break; 3254 case SND_SOC_DAIFMT_IB_IF: 3255 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV; 3256 break; 3257 default: 3258 return -EINVAL; 3259 } 3260 3261 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 3262 case SND_SOC_DAIFMT_CBM_CFM: 3263 aif0 |= WM8962_MSTR; 3264 break; 3265 case SND_SOC_DAIFMT_CBS_CFS: 3266 break; 3267 default: 3268 return -EINVAL; 3269 } 3270 3271 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0, 3272 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR | 3273 WM8962_LRCLK_INV, aif0); 3274 3275 return 0; 3276 } 3277 3278 struct _fll_div { 3279 u16 fll_fratio; 3280 u16 fll_outdiv; 3281 u16 fll_refclk_div; 3282 u16 n; 3283 u16 theta; 3284 u16 lambda; 3285 }; 3286 3287 /* The size in bits of the FLL divide multiplied by 10 3288 * to allow rounding later */ 3289 #define FIXED_FLL_SIZE ((1 << 16) * 10) 3290 3291 static struct { 3292 unsigned int min; 3293 unsigned int max; 3294 u16 fll_fratio; 3295 int ratio; 3296 } fll_fratios[] = { 3297 { 0, 64000, 4, 16 }, 3298 { 64000, 128000, 3, 8 }, 3299 { 128000, 256000, 2, 4 }, 3300 { 256000, 1000000, 1, 2 }, 3301 { 1000000, 13500000, 0, 1 }, 3302 }; 3303 3304 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, 3305 unsigned int Fout) 3306 { 3307 unsigned int target; 3308 unsigned int div; 3309 unsigned int fratio, gcd_fll; 3310 int i; 3311 3312 /* Fref must be <=13.5MHz */ 3313 div = 1; 3314 fll_div->fll_refclk_div = 0; 3315 while ((Fref / div) > 13500000) { 3316 div *= 2; 3317 fll_div->fll_refclk_div++; 3318 3319 if (div > 4) { 3320 pr_err("Can't scale %dMHz input down to <=13.5MHz\n", 3321 Fref); 3322 return -EINVAL; 3323 } 3324 } 3325 3326 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout); 3327 3328 /* Apply the division for our remaining calculations */ 3329 Fref /= div; 3330 3331 /* Fvco should be 90-100MHz; don't check the upper bound */ 3332 div = 2; 3333 while (Fout * div < 90000000) { 3334 div++; 3335 if (div > 64) { 3336 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n", 3337 Fout); 3338 return -EINVAL; 3339 } 3340 } 3341 target = Fout * div; 3342 fll_div->fll_outdiv = div - 1; 3343 3344 pr_debug("FLL Fvco=%dHz\n", target); 3345 3346 /* Find an appropriate FLL_FRATIO and factor it out of the target */ 3347 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) { 3348 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) { 3349 fll_div->fll_fratio = fll_fratios[i].fll_fratio; 3350 fratio = fll_fratios[i].ratio; 3351 break; 3352 } 3353 } 3354 if (i == ARRAY_SIZE(fll_fratios)) { 3355 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref); 3356 return -EINVAL; 3357 } 3358 3359 fll_div->n = target / (fratio * Fref); 3360 3361 if (target % Fref == 0) { 3362 fll_div->theta = 0; 3363 fll_div->lambda = 0; 3364 } else { 3365 gcd_fll = gcd(target, fratio * Fref); 3366 3367 fll_div->theta = (target - (fll_div->n * fratio * Fref)) 3368 / gcd_fll; 3369 fll_div->lambda = (fratio * Fref) / gcd_fll; 3370 } 3371 3372 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n", 3373 fll_div->n, fll_div->theta, fll_div->lambda); 3374 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n", 3375 fll_div->fll_fratio, fll_div->fll_outdiv, 3376 fll_div->fll_refclk_div); 3377 3378 return 0; 3379 } 3380 3381 static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source, 3382 unsigned int Fref, unsigned int Fout) 3383 { 3384 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3385 struct _fll_div fll_div; 3386 unsigned long timeout; 3387 int ret; 3388 int fll1 = snd_soc_read(codec, WM8962_FLL_CONTROL_1) & WM8962_FLL_ENA; 3389 int sysclk = snd_soc_read(codec, WM8962_CLOCKING2) & WM8962_SYSCLK_ENA; 3390 3391 /* Any change? */ 3392 if (source == wm8962->fll_src && Fref == wm8962->fll_fref && 3393 Fout == wm8962->fll_fout) 3394 return 0; 3395 3396 if (Fout == 0) { 3397 dev_dbg(codec->dev, "FLL disabled\n"); 3398 3399 wm8962->fll_fref = 0; 3400 wm8962->fll_fout = 0; 3401 3402 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 3403 WM8962_FLL_ENA, 0); 3404 3405 return 0; 3406 } 3407 3408 ret = fll_factors(&fll_div, Fref, Fout); 3409 if (ret != 0) 3410 return ret; 3411 3412 switch (fll_id) { 3413 case WM8962_FLL_MCLK: 3414 case WM8962_FLL_BCLK: 3415 case WM8962_FLL_OSC: 3416 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT; 3417 break; 3418 case WM8962_FLL_INT: 3419 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 3420 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA); 3421 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5, 3422 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO); 3423 break; 3424 default: 3425 dev_err(codec->dev, "Unknown FLL source %d\n", ret); 3426 return -EINVAL; 3427 } 3428 3429 if (fll_div.theta || fll_div.lambda) 3430 fll1 |= WM8962_FLL_FRAC; 3431 3432 /* Stop the FLL while we reconfigure */ 3433 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0); 3434 3435 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2, 3436 WM8962_FLL_OUTDIV_MASK | 3437 WM8962_FLL_REFCLK_DIV_MASK, 3438 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) | 3439 (fll_div.fll_refclk_div)); 3440 3441 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3, 3442 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio); 3443 3444 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta); 3445 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda); 3446 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n); 3447 3448 try_wait_for_completion(&wm8962->fll_lock); 3449 3450 if (sysclk) 3451 fll1 |= WM8962_FLL_ENA; 3452 3453 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, 3454 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK | 3455 WM8962_FLL_ENA, fll1); 3456 3457 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout); 3458 3459 ret = 0; 3460 3461 if (fll1 & WM8962_FLL_ENA) { 3462 /* This should be a massive overestimate but go even 3463 * higher if we'll error out 3464 */ 3465 if (wm8962->irq) 3466 timeout = msecs_to_jiffies(5); 3467 else 3468 timeout = msecs_to_jiffies(1); 3469 3470 timeout = wait_for_completion_timeout(&wm8962->fll_lock, 3471 timeout); 3472 3473 if (timeout == 0 && wm8962->irq) { 3474 dev_err(codec->dev, "FLL lock timed out"); 3475 ret = -ETIMEDOUT; 3476 } 3477 } 3478 3479 wm8962->fll_fref = Fref; 3480 wm8962->fll_fout = Fout; 3481 wm8962->fll_src = source; 3482 3483 return ret; 3484 } 3485 3486 static int wm8962_mute(struct snd_soc_dai *dai, int mute) 3487 { 3488 struct snd_soc_codec *codec = dai->codec; 3489 int val; 3490 3491 if (mute) 3492 val = WM8962_DAC_MUTE; 3493 else 3494 val = 0; 3495 3496 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1, 3497 WM8962_DAC_MUTE, val); 3498 } 3499 3500 #define WM8962_RATES SNDRV_PCM_RATE_8000_96000 3501 3502 #define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 3503 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3504 3505 static const struct snd_soc_dai_ops wm8962_dai_ops = { 3506 .hw_params = wm8962_hw_params, 3507 .set_sysclk = wm8962_set_dai_sysclk, 3508 .set_fmt = wm8962_set_dai_fmt, 3509 .digital_mute = wm8962_mute, 3510 }; 3511 3512 static struct snd_soc_dai_driver wm8962_dai = { 3513 .name = "wm8962", 3514 .playback = { 3515 .stream_name = "Playback", 3516 .channels_min = 2, 3517 .channels_max = 2, 3518 .rates = WM8962_RATES, 3519 .formats = WM8962_FORMATS, 3520 }, 3521 .capture = { 3522 .stream_name = "Capture", 3523 .channels_min = 2, 3524 .channels_max = 2, 3525 .rates = WM8962_RATES, 3526 .formats = WM8962_FORMATS, 3527 }, 3528 .ops = &wm8962_dai_ops, 3529 .symmetric_rates = 1, 3530 }; 3531 3532 static void wm8962_mic_work(struct work_struct *work) 3533 { 3534 struct wm8962_priv *wm8962 = container_of(work, 3535 struct wm8962_priv, 3536 mic_work.work); 3537 struct snd_soc_codec *codec = wm8962->codec; 3538 int status = 0; 3539 int irq_pol = 0; 3540 int reg; 3541 3542 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4); 3543 3544 if (reg & WM8962_MICDET_STS) { 3545 status |= SND_JACK_MICROPHONE; 3546 irq_pol |= WM8962_MICD_IRQ_POL; 3547 } 3548 3549 if (reg & WM8962_MICSHORT_STS) { 3550 status |= SND_JACK_BTN_0; 3551 irq_pol |= WM8962_MICSCD_IRQ_POL; 3552 } 3553 3554 snd_soc_jack_report(wm8962->jack, status, 3555 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3556 3557 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL, 3558 WM8962_MICSCD_IRQ_POL | 3559 WM8962_MICD_IRQ_POL, irq_pol); 3560 } 3561 3562 static irqreturn_t wm8962_irq(int irq, void *data) 3563 { 3564 struct snd_soc_codec *codec = data; 3565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3566 int mask; 3567 int active; 3568 int reg; 3569 3570 mask = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2_MASK); 3571 3572 active = snd_soc_read(codec, WM8962_INTERRUPT_STATUS_2); 3573 active &= ~mask; 3574 3575 if (!active) 3576 return IRQ_NONE; 3577 3578 /* Acknowledge the interrupts */ 3579 snd_soc_write(codec, WM8962_INTERRUPT_STATUS_2, active); 3580 3581 if (active & WM8962_FLL_LOCK_EINT) { 3582 dev_dbg(codec->dev, "FLL locked\n"); 3583 complete(&wm8962->fll_lock); 3584 } 3585 3586 if (active & WM8962_FIFOS_ERR_EINT) 3587 dev_err(codec->dev, "FIFO error\n"); 3588 3589 if (active & WM8962_TEMP_SHUT_EINT) { 3590 dev_crit(codec->dev, "Thermal shutdown\n"); 3591 3592 reg = snd_soc_read(codec, WM8962_THERMAL_SHUTDOWN_STATUS); 3593 3594 if (reg & WM8962_TEMP_ERR_HP) 3595 dev_crit(codec->dev, "Headphone thermal error\n"); 3596 if (reg & WM8962_TEMP_WARN_HP) 3597 dev_crit(codec->dev, "Headphone thermal warning\n"); 3598 if (reg & WM8962_TEMP_ERR_SPK) 3599 dev_crit(codec->dev, "Speaker thermal error\n"); 3600 if (reg & WM8962_TEMP_WARN_SPK) 3601 dev_crit(codec->dev, "Speaker thermal warning\n"); 3602 } 3603 3604 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) { 3605 dev_dbg(codec->dev, "Microphone event detected\n"); 3606 3607 #ifndef CONFIG_SND_SOC_WM8962_MODULE 3608 trace_snd_soc_jack_irq(dev_name(codec->dev)); 3609 #endif 3610 3611 pm_wakeup_event(codec->dev, 300); 3612 3613 schedule_delayed_work(&wm8962->mic_work, 3614 msecs_to_jiffies(250)); 3615 } 3616 3617 return IRQ_HANDLED; 3618 } 3619 3620 /** 3621 * wm8962_mic_detect - Enable microphone detection via the WM8962 IRQ 3622 * 3623 * @codec: WM8962 codec 3624 * @jack: jack to report detection events on 3625 * 3626 * Enable microphone detection via IRQ on the WM8962. If GPIOs are 3627 * being used to bring out signals to the processor then only platform 3628 * data configuration is needed for WM8962 and processor GPIOs should 3629 * be configured using snd_soc_jack_add_gpios() instead. 3630 * 3631 * If no jack is supplied detection will be disabled. 3632 */ 3633 int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack) 3634 { 3635 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3636 int irq_mask, enable; 3637 3638 wm8962->jack = jack; 3639 if (jack) { 3640 irq_mask = 0; 3641 enable = WM8962_MICDET_ENA; 3642 } else { 3643 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT; 3644 enable = 0; 3645 } 3646 3647 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK, 3648 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask); 3649 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, 3650 WM8962_MICDET_ENA, enable); 3651 3652 /* Send an initial empty report */ 3653 snd_soc_jack_report(wm8962->jack, 0, 3654 SND_JACK_MICROPHONE | SND_JACK_BTN_0); 3655 3656 if (jack) { 3657 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK"); 3658 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS"); 3659 } else { 3660 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK"); 3661 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS"); 3662 } 3663 3664 return 0; 3665 } 3666 EXPORT_SYMBOL_GPL(wm8962_mic_detect); 3667 3668 #if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE) 3669 static int beep_rates[] = { 3670 500, 1000, 2000, 4000, 3671 }; 3672 3673 static void wm8962_beep_work(struct work_struct *work) 3674 { 3675 struct wm8962_priv *wm8962 = 3676 container_of(work, struct wm8962_priv, beep_work); 3677 struct snd_soc_codec *codec = wm8962->codec; 3678 struct snd_soc_dapm_context *dapm = &codec->dapm; 3679 int i; 3680 int reg = 0; 3681 int best = 0; 3682 3683 if (wm8962->beep_rate) { 3684 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) { 3685 if (abs(wm8962->beep_rate - beep_rates[i]) < 3686 abs(wm8962->beep_rate - beep_rates[best])) 3687 best = i; 3688 } 3689 3690 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n", 3691 beep_rates[best], wm8962->beep_rate); 3692 3693 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT); 3694 3695 snd_soc_dapm_enable_pin(dapm, "Beep"); 3696 } else { 3697 dev_dbg(codec->dev, "Disabling beep\n"); 3698 snd_soc_dapm_disable_pin(dapm, "Beep"); 3699 } 3700 3701 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, 3702 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg); 3703 3704 snd_soc_dapm_sync(dapm); 3705 } 3706 3707 /* For usability define a way of injecting beep events for the device - 3708 * many systems will not have a keyboard. 3709 */ 3710 static int wm8962_beep_event(struct input_dev *dev, unsigned int type, 3711 unsigned int code, int hz) 3712 { 3713 struct snd_soc_codec *codec = input_get_drvdata(dev); 3714 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3715 3716 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz); 3717 3718 switch (code) { 3719 case SND_BELL: 3720 if (hz) 3721 hz = 1000; 3722 case SND_TONE: 3723 break; 3724 default: 3725 return -1; 3726 } 3727 3728 /* Kick the beep from a workqueue */ 3729 wm8962->beep_rate = hz; 3730 schedule_work(&wm8962->beep_work); 3731 return 0; 3732 } 3733 3734 static ssize_t wm8962_beep_set(struct device *dev, 3735 struct device_attribute *attr, 3736 const char *buf, size_t count) 3737 { 3738 struct wm8962_priv *wm8962 = dev_get_drvdata(dev); 3739 long int time; 3740 int ret; 3741 3742 ret = strict_strtol(buf, 10, &time); 3743 if (ret != 0) 3744 return ret; 3745 3746 input_event(wm8962->beep, EV_SND, SND_TONE, time); 3747 3748 return count; 3749 } 3750 3751 static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set); 3752 3753 static void wm8962_init_beep(struct snd_soc_codec *codec) 3754 { 3755 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3756 int ret; 3757 3758 wm8962->beep = input_allocate_device(); 3759 if (!wm8962->beep) { 3760 dev_err(codec->dev, "Failed to allocate beep device\n"); 3761 return; 3762 } 3763 3764 INIT_WORK(&wm8962->beep_work, wm8962_beep_work); 3765 wm8962->beep_rate = 0; 3766 3767 wm8962->beep->name = "WM8962 Beep Generator"; 3768 wm8962->beep->phys = dev_name(codec->dev); 3769 wm8962->beep->id.bustype = BUS_I2C; 3770 3771 wm8962->beep->evbit[0] = BIT_MASK(EV_SND); 3772 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE); 3773 wm8962->beep->event = wm8962_beep_event; 3774 wm8962->beep->dev.parent = codec->dev; 3775 input_set_drvdata(wm8962->beep, codec); 3776 3777 ret = input_register_device(wm8962->beep); 3778 if (ret != 0) { 3779 input_free_device(wm8962->beep); 3780 wm8962->beep = NULL; 3781 dev_err(codec->dev, "Failed to register beep device\n"); 3782 } 3783 3784 ret = device_create_file(codec->dev, &dev_attr_beep); 3785 if (ret != 0) { 3786 dev_err(codec->dev, "Failed to create keyclick file: %d\n", 3787 ret); 3788 } 3789 } 3790 3791 static void wm8962_free_beep(struct snd_soc_codec *codec) 3792 { 3793 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3794 3795 device_remove_file(codec->dev, &dev_attr_beep); 3796 input_unregister_device(wm8962->beep); 3797 cancel_work_sync(&wm8962->beep_work); 3798 wm8962->beep = NULL; 3799 3800 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0); 3801 } 3802 #else 3803 static void wm8962_init_beep(struct snd_soc_codec *codec) 3804 { 3805 } 3806 3807 static void wm8962_free_beep(struct snd_soc_codec *codec) 3808 { 3809 } 3810 #endif 3811 3812 static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio) 3813 { 3814 int mask = 0; 3815 int val = 0; 3816 3817 /* Some of the GPIOs are behind MFP configuration and need to 3818 * be put into GPIO mode. */ 3819 switch (gpio) { 3820 case 2: 3821 mask = WM8962_CLKOUT2_SEL_MASK; 3822 val = 1 << WM8962_CLKOUT2_SEL_SHIFT; 3823 break; 3824 case 3: 3825 mask = WM8962_CLKOUT3_SEL_MASK; 3826 val = 1 << WM8962_CLKOUT3_SEL_SHIFT; 3827 break; 3828 default: 3829 break; 3830 } 3831 3832 if (mask) 3833 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1, 3834 mask, val); 3835 } 3836 3837 #ifdef CONFIG_GPIOLIB 3838 static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip) 3839 { 3840 return container_of(chip, struct wm8962_priv, gpio_chip); 3841 } 3842 3843 static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset) 3844 { 3845 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3846 struct snd_soc_codec *codec = wm8962->codec; 3847 3848 /* The WM8962 GPIOs aren't linearly numbered. For simplicity 3849 * we export linear numbers and error out if the unsupported 3850 * ones are requsted. 3851 */ 3852 switch (offset + 1) { 3853 case 2: 3854 case 3: 3855 case 5: 3856 case 6: 3857 break; 3858 default: 3859 return -EINVAL; 3860 } 3861 3862 wm8962_set_gpio_mode(codec, offset + 1); 3863 3864 return 0; 3865 } 3866 3867 static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 3868 { 3869 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3870 struct snd_soc_codec *codec = wm8962->codec; 3871 3872 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, 3873 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT); 3874 } 3875 3876 static int wm8962_gpio_direction_out(struct gpio_chip *chip, 3877 unsigned offset, int value) 3878 { 3879 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip); 3880 struct snd_soc_codec *codec = wm8962->codec; 3881 int ret, val; 3882 3883 /* Force function 1 (logic output) */ 3884 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT); 3885 3886 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset, 3887 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val); 3888 if (ret < 0) 3889 return ret; 3890 3891 return 0; 3892 } 3893 3894 static struct gpio_chip wm8962_template_chip = { 3895 .label = "wm8962", 3896 .owner = THIS_MODULE, 3897 .request = wm8962_gpio_request, 3898 .direction_output = wm8962_gpio_direction_out, 3899 .set = wm8962_gpio_set, 3900 .can_sleep = 1, 3901 }; 3902 3903 static void wm8962_init_gpio(struct snd_soc_codec *codec) 3904 { 3905 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3906 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 3907 int ret; 3908 3909 wm8962->gpio_chip = wm8962_template_chip; 3910 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO; 3911 wm8962->gpio_chip.dev = codec->dev; 3912 3913 if (pdata && pdata->gpio_base) 3914 wm8962->gpio_chip.base = pdata->gpio_base; 3915 else 3916 wm8962->gpio_chip.base = -1; 3917 3918 ret = gpiochip_add(&wm8962->gpio_chip); 3919 if (ret != 0) 3920 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret); 3921 } 3922 3923 static void wm8962_free_gpio(struct snd_soc_codec *codec) 3924 { 3925 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3926 int ret; 3927 3928 ret = gpiochip_remove(&wm8962->gpio_chip); 3929 if (ret != 0) 3930 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret); 3931 } 3932 #else 3933 static void wm8962_init_gpio(struct snd_soc_codec *codec) 3934 { 3935 } 3936 3937 static void wm8962_free_gpio(struct snd_soc_codec *codec) 3938 { 3939 } 3940 #endif 3941 3942 static int wm8962_probe(struct snd_soc_codec *codec) 3943 { 3944 int ret; 3945 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 3946 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev); 3947 u16 *reg_cache = codec->reg_cache; 3948 int i, trigger, irq_pol; 3949 bool dmicclk, dmicdat; 3950 3951 wm8962->codec = codec; 3952 codec->control_data = wm8962->regmap; 3953 3954 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP); 3955 if (ret != 0) { 3956 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 3957 return ret; 3958 } 3959 3960 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0; 3961 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1; 3962 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2; 3963 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3; 3964 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4; 3965 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5; 3966 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6; 3967 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7; 3968 3969 /* This should really be moved into the regulator core */ 3970 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) { 3971 ret = regulator_register_notifier(wm8962->supplies[i].consumer, 3972 &wm8962->disable_nb[i]); 3973 if (ret != 0) { 3974 dev_err(codec->dev, 3975 "Failed to register regulator notifier: %d\n", 3976 ret); 3977 } 3978 } 3979 3980 /* SYSCLK defaults to on; make sure it is off so we can safely 3981 * write to registers if the device is declocked. 3982 */ 3983 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0); 3984 3985 /* Ensure we have soft control over all registers */ 3986 snd_soc_update_bits(codec, WM8962_CLOCKING2, 3987 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD); 3988 3989 /* Ensure that the oscillator and PLLs are disabled */ 3990 snd_soc_update_bits(codec, WM8962_PLL2, 3991 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA, 3992 0); 3993 3994 if (pdata) { 3995 /* Apply static configuration for GPIOs */ 3996 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++) 3997 if (pdata->gpio_init[i]) { 3998 wm8962_set_gpio_mode(codec, i + 1); 3999 snd_soc_write(codec, 0x200 + i, 4000 pdata->gpio_init[i] & 0xffff); 4001 } 4002 4003 /* Put the speakers into mono mode? */ 4004 if (pdata->spk_mono) 4005 reg_cache[WM8962_CLASS_D_CONTROL_2] 4006 |= WM8962_SPK_MONO; 4007 4008 /* Micbias setup, detection enable and detection 4009 * threasholds. */ 4010 if (pdata->mic_cfg) 4011 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4, 4012 WM8962_MICDET_ENA | 4013 WM8962_MICDET_THR_MASK | 4014 WM8962_MICSHORT_THR_MASK | 4015 WM8962_MICBIAS_LVL, 4016 pdata->mic_cfg); 4017 } 4018 4019 /* Latch volume update bits */ 4020 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME, 4021 WM8962_IN_VU, WM8962_IN_VU); 4022 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME, 4023 WM8962_IN_VU, WM8962_IN_VU); 4024 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME, 4025 WM8962_ADC_VU, WM8962_ADC_VU); 4026 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME, 4027 WM8962_ADC_VU, WM8962_ADC_VU); 4028 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME, 4029 WM8962_DAC_VU, WM8962_DAC_VU); 4030 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME, 4031 WM8962_DAC_VU, WM8962_DAC_VU); 4032 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME, 4033 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 4034 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME, 4035 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU); 4036 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME, 4037 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 4038 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME, 4039 WM8962_HPOUT_VU, WM8962_HPOUT_VU); 4040 4041 /* Stereo control for EQ */ 4042 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0); 4043 4044 /* Don't debouce interrupts so we don't need SYSCLK */ 4045 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE, 4046 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB | 4047 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB, 4048 0); 4049 4050 wm8962_add_widgets(codec); 4051 4052 /* Save boards having to disable DMIC when not in use */ 4053 dmicclk = false; 4054 dmicdat = false; 4055 for (i = 0; i < WM8962_MAX_GPIO; i++) { 4056 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i) 4057 & WM8962_GP2_FN_MASK) { 4058 case WM8962_GPIO_FN_DMICCLK: 4059 dmicclk = true; 4060 break; 4061 case WM8962_GPIO_FN_DMICDAT: 4062 dmicdat = true; 4063 break; 4064 default: 4065 break; 4066 } 4067 } 4068 if (!dmicclk || !dmicdat) { 4069 dev_dbg(codec->dev, "DMIC not in use, disabling\n"); 4070 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT"); 4071 } 4072 if (dmicclk != dmicdat) 4073 dev_warn(codec->dev, "DMIC GPIOs partially configured\n"); 4074 4075 wm8962_init_beep(codec); 4076 wm8962_init_gpio(codec); 4077 4078 if (wm8962->irq) { 4079 if (pdata && pdata->irq_active_low) { 4080 trigger = IRQF_TRIGGER_LOW; 4081 irq_pol = WM8962_IRQ_POL; 4082 } else { 4083 trigger = IRQF_TRIGGER_HIGH; 4084 irq_pol = 0; 4085 } 4086 4087 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL, 4088 WM8962_IRQ_POL, irq_pol); 4089 4090 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq, 4091 trigger | IRQF_ONESHOT, 4092 "wm8962", codec); 4093 if (ret != 0) { 4094 dev_err(codec->dev, "Failed to request IRQ %d: %d\n", 4095 wm8962->irq, ret); 4096 wm8962->irq = 0; 4097 /* Non-fatal */ 4098 } else { 4099 /* Enable some IRQs by default */ 4100 snd_soc_update_bits(codec, 4101 WM8962_INTERRUPT_STATUS_2_MASK, 4102 WM8962_FLL_LOCK_EINT | 4103 WM8962_TEMP_SHUT_EINT | 4104 WM8962_FIFOS_ERR_EINT, 0); 4105 } 4106 } 4107 4108 return 0; 4109 } 4110 4111 static int wm8962_remove(struct snd_soc_codec *codec) 4112 { 4113 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec); 4114 int i; 4115 4116 if (wm8962->irq) 4117 free_irq(wm8962->irq, codec); 4118 4119 cancel_delayed_work_sync(&wm8962->mic_work); 4120 4121 wm8962_free_gpio(codec); 4122 wm8962_free_beep(codec); 4123 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 4124 regulator_unregister_notifier(wm8962->supplies[i].consumer, 4125 &wm8962->disable_nb[i]); 4126 4127 return 0; 4128 } 4129 4130 static int wm8962_soc_volatile(struct snd_soc_codec *codec, 4131 unsigned int reg) 4132 { 4133 return true; 4134 } 4135 4136 4137 static struct snd_soc_codec_driver soc_codec_dev_wm8962 = { 4138 .probe = wm8962_probe, 4139 .remove = wm8962_remove, 4140 .set_bias_level = wm8962_set_bias_level, 4141 .set_pll = wm8962_set_fll, 4142 .reg_cache_size = WM8962_MAX_REGISTER, 4143 .volatile_register = wm8962_soc_volatile, 4144 }; 4145 4146 static const struct regmap_config wm8962_regmap = { 4147 .reg_bits = 16, 4148 .val_bits = 16, 4149 4150 .max_register = WM8962_MAX_REGISTER, 4151 .reg_defaults = wm8962_reg, 4152 .num_reg_defaults = ARRAY_SIZE(wm8962_reg), 4153 .volatile_reg = wm8962_volatile_register, 4154 .readable_reg = wm8962_readable_register, 4155 .cache_type = REGCACHE_RBTREE, 4156 }; 4157 4158 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 4159 static __devinit int wm8962_i2c_probe(struct i2c_client *i2c, 4160 const struct i2c_device_id *id) 4161 { 4162 struct wm8962_priv *wm8962; 4163 unsigned int reg; 4164 int ret, i; 4165 4166 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv), 4167 GFP_KERNEL); 4168 if (wm8962 == NULL) 4169 return -ENOMEM; 4170 4171 i2c_set_clientdata(i2c, wm8962); 4172 4173 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work); 4174 init_completion(&wm8962->fll_lock); 4175 wm8962->irq = i2c->irq; 4176 4177 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) 4178 wm8962->supplies[i].supply = wm8962_supply_names[i]; 4179 4180 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies), 4181 wm8962->supplies); 4182 if (ret != 0) { 4183 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); 4184 goto err; 4185 } 4186 4187 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies), 4188 wm8962->supplies); 4189 if (ret != 0) { 4190 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret); 4191 goto err_get; 4192 } 4193 4194 wm8962->regmap = regmap_init_i2c(i2c, &wm8962_regmap); 4195 if (IS_ERR(wm8962->regmap)) { 4196 ret = PTR_ERR(wm8962->regmap); 4197 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 4198 goto err_enable; 4199 } 4200 4201 /* 4202 * We haven't marked the chip revision as volatile due to 4203 * sharing a register with the right input volume; explicitly 4204 * bypass the cache to read it. 4205 */ 4206 regcache_cache_bypass(wm8962->regmap, true); 4207 4208 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®); 4209 if (ret < 0) { 4210 dev_err(&i2c->dev, "Failed to read ID register\n"); 4211 goto err_regmap; 4212 } 4213 if (reg != 0x6243) { 4214 dev_err(&i2c->dev, 4215 "Device is not a WM8962, ID %x != 0x6243\n", ret); 4216 ret = -EINVAL; 4217 goto err_regmap; 4218 } 4219 4220 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®); 4221 if (ret < 0) { 4222 dev_err(&i2c->dev, "Failed to read device revision: %d\n", 4223 ret); 4224 goto err_regmap; 4225 } 4226 4227 dev_info(&i2c->dev, "customer id %x revision %c\n", 4228 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT, 4229 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT) 4230 + 'A'); 4231 4232 regcache_cache_bypass(wm8962->regmap, false); 4233 4234 ret = wm8962_reset(wm8962); 4235 if (ret < 0) { 4236 dev_err(&i2c->dev, "Failed to issue reset\n"); 4237 goto err_regmap; 4238 } 4239 4240 regcache_cache_only(wm8962->regmap, true); 4241 4242 ret = snd_soc_register_codec(&i2c->dev, 4243 &soc_codec_dev_wm8962, &wm8962_dai, 1); 4244 if (ret < 0) 4245 goto err_regmap; 4246 4247 /* The drivers should power up as needed */ 4248 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 4249 4250 return 0; 4251 4252 err_regmap: 4253 regmap_exit(wm8962->regmap); 4254 err_enable: 4255 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 4256 err_get: 4257 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 4258 err: 4259 return ret; 4260 } 4261 4262 static __devexit int wm8962_i2c_remove(struct i2c_client *client) 4263 { 4264 struct wm8962_priv *wm8962 = dev_get_drvdata(&client->dev); 4265 4266 snd_soc_unregister_codec(&client->dev); 4267 regmap_exit(wm8962->regmap); 4268 regulator_bulk_free(ARRAY_SIZE(wm8962->supplies), wm8962->supplies); 4269 return 0; 4270 } 4271 4272 static const struct i2c_device_id wm8962_i2c_id[] = { 4273 { "wm8962", 0 }, 4274 { } 4275 }; 4276 MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id); 4277 4278 static struct i2c_driver wm8962_i2c_driver = { 4279 .driver = { 4280 .name = "wm8962", 4281 .owner = THIS_MODULE, 4282 }, 4283 .probe = wm8962_i2c_probe, 4284 .remove = __devexit_p(wm8962_i2c_remove), 4285 .id_table = wm8962_i2c_id, 4286 }; 4287 #endif 4288 4289 static int __init wm8962_modinit(void) 4290 { 4291 int ret; 4292 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 4293 ret = i2c_add_driver(&wm8962_i2c_driver); 4294 if (ret != 0) { 4295 printk(KERN_ERR "Failed to register WM8962 I2C driver: %d\n", 4296 ret); 4297 } 4298 #endif 4299 return 0; 4300 } 4301 module_init(wm8962_modinit); 4302 4303 static void __exit wm8962_exit(void) 4304 { 4305 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 4306 i2c_del_driver(&wm8962_i2c_driver); 4307 #endif 4308 } 4309 module_exit(wm8962_exit); 4310 4311 MODULE_DESCRIPTION("ASoC WM8962 driver"); 4312 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 4313 MODULE_LICENSE("GPL"); 4314