1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c1644e3dSJohn Hsu /* 3c1644e3dSJohn Hsu * NAU85L40 ALSA SoC audio driver 4c1644e3dSJohn Hsu * 5c1644e3dSJohn Hsu * Copyright 2016 Nuvoton Technology Corp. 6c1644e3dSJohn Hsu * Author: John Hsu <KCHSU0@nuvoton.com> 7c1644e3dSJohn Hsu */ 8c1644e3dSJohn Hsu 9c1644e3dSJohn Hsu #include <linux/module.h> 10c1644e3dSJohn Hsu #include <linux/moduleparam.h> 11c1644e3dSJohn Hsu #include <linux/init.h> 12c1644e3dSJohn Hsu #include <linux/delay.h> 13c1644e3dSJohn Hsu #include <linux/pm.h> 14c1644e3dSJohn Hsu #include <linux/i2c.h> 15c1644e3dSJohn Hsu #include <linux/regmap.h> 16c1644e3dSJohn Hsu #include <linux/regulator/consumer.h> 17c1644e3dSJohn Hsu #include <linux/spi/spi.h> 18c1644e3dSJohn Hsu #include <linux/slab.h> 19340d79a1SRob Herring #include <linux/of.h> 20c1644e3dSJohn Hsu #include <sound/core.h> 21c1644e3dSJohn Hsu #include <sound/pcm.h> 22c1644e3dSJohn Hsu #include <sound/pcm_params.h> 23c1644e3dSJohn Hsu #include <sound/soc.h> 24c1644e3dSJohn Hsu #include <sound/soc-dapm.h> 25c1644e3dSJohn Hsu #include <sound/initval.h> 26c1644e3dSJohn Hsu #include <sound/tlv.h> 27c1644e3dSJohn Hsu #include "nau8540.h" 28c1644e3dSJohn Hsu 29c1644e3dSJohn Hsu 30c1644e3dSJohn Hsu #define NAU_FREF_MAX 13500000 31c1644e3dSJohn Hsu #define NAU_FVCO_MAX 100000000 32c1644e3dSJohn Hsu #define NAU_FVCO_MIN 90000000 33c1644e3dSJohn Hsu 34c1644e3dSJohn Hsu /* the maximum frequency of CLK_ADC */ 35c1644e3dSJohn Hsu #define CLK_ADC_MAX 6144000 36c1644e3dSJohn Hsu 37c1644e3dSJohn Hsu /* scaling for mclk from sysclk_src output */ 38c1644e3dSJohn Hsu static const struct nau8540_fll_attr mclk_src_scaling[] = { 39c1644e3dSJohn Hsu { 1, 0x0 }, 40c1644e3dSJohn Hsu { 2, 0x2 }, 41c1644e3dSJohn Hsu { 4, 0x3 }, 42c1644e3dSJohn Hsu { 8, 0x4 }, 43c1644e3dSJohn Hsu { 16, 0x5 }, 44c1644e3dSJohn Hsu { 32, 0x6 }, 45c1644e3dSJohn Hsu { 3, 0x7 }, 46c1644e3dSJohn Hsu { 6, 0xa }, 47c1644e3dSJohn Hsu { 12, 0xb }, 48c1644e3dSJohn Hsu { 24, 0xc }, 49c1644e3dSJohn Hsu }; 50c1644e3dSJohn Hsu 51c1644e3dSJohn Hsu /* ratio for input clk freq */ 52c1644e3dSJohn Hsu static const struct nau8540_fll_attr fll_ratio[] = { 53c1644e3dSJohn Hsu { 512000, 0x01 }, 54c1644e3dSJohn Hsu { 256000, 0x02 }, 55c1644e3dSJohn Hsu { 128000, 0x04 }, 56c1644e3dSJohn Hsu { 64000, 0x08 }, 57c1644e3dSJohn Hsu { 32000, 0x10 }, 58c1644e3dSJohn Hsu { 8000, 0x20 }, 59c1644e3dSJohn Hsu { 4000, 0x40 }, 60c1644e3dSJohn Hsu }; 61c1644e3dSJohn Hsu 62c1644e3dSJohn Hsu static const struct nau8540_fll_attr fll_pre_scalar[] = { 63c1644e3dSJohn Hsu { 1, 0x0 }, 64c1644e3dSJohn Hsu { 2, 0x1 }, 65c1644e3dSJohn Hsu { 4, 0x2 }, 66c1644e3dSJohn Hsu { 8, 0x3 }, 67c1644e3dSJohn Hsu }; 68c1644e3dSJohn Hsu 69c1644e3dSJohn Hsu /* over sampling rate */ 70c1644e3dSJohn Hsu static const struct nau8540_osr_attr osr_adc_sel[] = { 71c1644e3dSJohn Hsu { 32, 3 }, /* OSR 32, SRC 1/8 */ 72c1644e3dSJohn Hsu { 64, 2 }, /* OSR 64, SRC 1/4 */ 73c1644e3dSJohn Hsu { 128, 1 }, /* OSR 128, SRC 1/2 */ 74c1644e3dSJohn Hsu { 256, 0 }, /* OSR 256, SRC 1 */ 75c1644e3dSJohn Hsu }; 76c1644e3dSJohn Hsu 77c1644e3dSJohn Hsu static const struct reg_default nau8540_reg_defaults[] = { 78c1644e3dSJohn Hsu {NAU8540_REG_POWER_MANAGEMENT, 0x0000}, 79c1644e3dSJohn Hsu {NAU8540_REG_CLOCK_CTRL, 0x0000}, 80c1644e3dSJohn Hsu {NAU8540_REG_CLOCK_SRC, 0x0000}, 81c1644e3dSJohn Hsu {NAU8540_REG_FLL1, 0x0001}, 82c1644e3dSJohn Hsu {NAU8540_REG_FLL2, 0x3126}, 83c1644e3dSJohn Hsu {NAU8540_REG_FLL3, 0x0008}, 84c1644e3dSJohn Hsu {NAU8540_REG_FLL4, 0x0010}, 85c1644e3dSJohn Hsu {NAU8540_REG_FLL5, 0xC000}, 86c1644e3dSJohn Hsu {NAU8540_REG_FLL6, 0x6000}, 87c1644e3dSJohn Hsu {NAU8540_REG_FLL_VCO_RSV, 0xF13C}, 88c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL0, 0x000B}, 89c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL1, 0x3010}, 90c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL2, 0x0800}, 91c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL3, 0x0000}, 92c1644e3dSJohn Hsu {NAU8540_REG_PCM_CTRL4, 0x000F}, 93c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_1, 0x0000}, 94c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_2, 0x700B}, 95c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_3, 0x0022}, 96c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_4, 0x1010}, 97c1644e3dSJohn Hsu {NAU8540_REG_ALC_CONTROL_5, 0x1010}, 98c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH1, 0x0000}, 99c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH1, 0x0000}, 100c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH2, 0x0000}, 101c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH2, 0x0000}, 102c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH3, 0x0000}, 103c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH3, 0x0000}, 104c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL1_CH4, 0x0000}, 105c1644e3dSJohn Hsu {NAU8540_REG_NOTCH_FIL2_CH4, 0x0000}, 106c1644e3dSJohn Hsu {NAU8540_REG_HPF_FILTER_CH12, 0x0000}, 107c1644e3dSJohn Hsu {NAU8540_REG_HPF_FILTER_CH34, 0x0000}, 108c1644e3dSJohn Hsu {NAU8540_REG_ADC_SAMPLE_RATE, 0x0002}, 109c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH1, 0x0400}, 110c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH2, 0x0400}, 111c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH3, 0x0400}, 112c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_GAIN_CH4, 0x0400}, 113c1644e3dSJohn Hsu {NAU8540_REG_DIGITAL_MUX, 0x00E4}, 114c1644e3dSJohn Hsu {NAU8540_REG_GPIO_CTRL, 0x0000}, 115c1644e3dSJohn Hsu {NAU8540_REG_MISC_CTRL, 0x0000}, 116c1644e3dSJohn Hsu {NAU8540_REG_I2C_CTRL, 0xEFFF}, 117c1644e3dSJohn Hsu {NAU8540_REG_VMID_CTRL, 0x0000}, 118c1644e3dSJohn Hsu {NAU8540_REG_MUTE, 0x0000}, 119c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_ADC1, 0x0011}, 120c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_ADC2, 0x0020}, 121c1644e3dSJohn Hsu {NAU8540_REG_ANALOG_PWR, 0x0000}, 122c1644e3dSJohn Hsu {NAU8540_REG_MIC_BIAS, 0x0004}, 123c1644e3dSJohn Hsu {NAU8540_REG_REFERENCE, 0x0000}, 124c1644e3dSJohn Hsu {NAU8540_REG_FEPGA1, 0x0000}, 125c1644e3dSJohn Hsu {NAU8540_REG_FEPGA2, 0x0000}, 126c1644e3dSJohn Hsu {NAU8540_REG_FEPGA3, 0x0101}, 127c1644e3dSJohn Hsu {NAU8540_REG_FEPGA4, 0x0101}, 128c1644e3dSJohn Hsu {NAU8540_REG_PWR, 0x0000}, 129c1644e3dSJohn Hsu }; 130c1644e3dSJohn Hsu 131c1644e3dSJohn Hsu static bool nau8540_readable_reg(struct device *dev, unsigned int reg) 132c1644e3dSJohn Hsu { 133c1644e3dSJohn Hsu switch (reg) { 134c1644e3dSJohn Hsu case NAU8540_REG_POWER_MANAGEMENT ... NAU8540_REG_FLL_VCO_RSV: 135c1644e3dSJohn Hsu case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: 136c1644e3dSJohn Hsu case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: 137c1644e3dSJohn Hsu case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ADC_SAMPLE_RATE: 138c1644e3dSJohn Hsu case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: 139c1644e3dSJohn Hsu case NAU8540_REG_P2P_CH1 ... NAU8540_REG_I2C_CTRL: 140c1644e3dSJohn Hsu case NAU8540_REG_I2C_DEVICE_ID: 141c1644e3dSJohn Hsu case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: 142c1644e3dSJohn Hsu case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: 143c1644e3dSJohn Hsu return true; 144c1644e3dSJohn Hsu default: 145c1644e3dSJohn Hsu return false; 146c1644e3dSJohn Hsu } 147c1644e3dSJohn Hsu 148c1644e3dSJohn Hsu } 149c1644e3dSJohn Hsu 150c1644e3dSJohn Hsu static bool nau8540_writeable_reg(struct device *dev, unsigned int reg) 151c1644e3dSJohn Hsu { 152c1644e3dSJohn Hsu switch (reg) { 153c1644e3dSJohn Hsu case NAU8540_REG_SW_RESET ... NAU8540_REG_FLL_VCO_RSV: 154c1644e3dSJohn Hsu case NAU8540_REG_PCM_CTRL0 ... NAU8540_REG_PCM_CTRL4: 155c1644e3dSJohn Hsu case NAU8540_REG_ALC_CONTROL_1 ... NAU8540_REG_ALC_CONTROL_5: 156c1644e3dSJohn Hsu case NAU8540_REG_NOTCH_FIL1_CH1 ... NAU8540_REG_ADC_SAMPLE_RATE: 157c1644e3dSJohn Hsu case NAU8540_REG_DIGITAL_GAIN_CH1 ... NAU8540_REG_DIGITAL_MUX: 158c1644e3dSJohn Hsu case NAU8540_REG_GPIO_CTRL ... NAU8540_REG_I2C_CTRL: 159c1644e3dSJohn Hsu case NAU8540_REG_RST: 160c1644e3dSJohn Hsu case NAU8540_REG_VMID_CTRL ... NAU8540_REG_MUTE: 161c1644e3dSJohn Hsu case NAU8540_REG_ANALOG_ADC1 ... NAU8540_REG_PWR: 162c1644e3dSJohn Hsu return true; 163c1644e3dSJohn Hsu default: 164c1644e3dSJohn Hsu return false; 165c1644e3dSJohn Hsu } 166c1644e3dSJohn Hsu } 167c1644e3dSJohn Hsu 168c1644e3dSJohn Hsu static bool nau8540_volatile_reg(struct device *dev, unsigned int reg) 169c1644e3dSJohn Hsu { 170c1644e3dSJohn Hsu switch (reg) { 171c1644e3dSJohn Hsu case NAU8540_REG_SW_RESET: 172c1644e3dSJohn Hsu case NAU8540_REG_ALC_GAIN_CH12 ... NAU8540_REG_ALC_STATUS: 173c1644e3dSJohn Hsu case NAU8540_REG_P2P_CH1 ... NAU8540_REG_PEAK_CH4: 174c1644e3dSJohn Hsu case NAU8540_REG_I2C_DEVICE_ID: 175c1644e3dSJohn Hsu case NAU8540_REG_RST: 176c1644e3dSJohn Hsu return true; 177c1644e3dSJohn Hsu default: 178c1644e3dSJohn Hsu return false; 179c1644e3dSJohn Hsu } 180c1644e3dSJohn Hsu } 181c1644e3dSJohn Hsu 182c1644e3dSJohn Hsu 183c1644e3dSJohn Hsu static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600); 184c1644e3dSJohn Hsu static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600); 185c1644e3dSJohn Hsu 186c1644e3dSJohn Hsu static const struct snd_kcontrol_new nau8540_snd_controls[] = { 187c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic1 Volume", NAU8540_REG_DIGITAL_GAIN_CH1, 188c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv), 189c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic2 Volume", NAU8540_REG_DIGITAL_GAIN_CH2, 190c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv), 191c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic3 Volume", NAU8540_REG_DIGITAL_GAIN_CH3, 192c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv), 193c1644e3dSJohn Hsu SOC_SINGLE_TLV("Mic4 Volume", NAU8540_REG_DIGITAL_GAIN_CH4, 194c1644e3dSJohn Hsu 0, 0x520, 0, adc_vol_tlv), 195c1644e3dSJohn Hsu 196c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA1 Volume", NAU8540_REG_FEPGA3, 197c1644e3dSJohn Hsu 0, 0x25, 0, fepga_gain_tlv), 198c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA2 Volume", NAU8540_REG_FEPGA3, 199c1644e3dSJohn Hsu 8, 0x25, 0, fepga_gain_tlv), 200c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA3 Volume", NAU8540_REG_FEPGA4, 201c1644e3dSJohn Hsu 0, 0x25, 0, fepga_gain_tlv), 202c1644e3dSJohn Hsu SOC_SINGLE_TLV("Frontend PGA4 Volume", NAU8540_REG_FEPGA4, 203c1644e3dSJohn Hsu 8, 0x25, 0, fepga_gain_tlv), 204c1644e3dSJohn Hsu }; 205c1644e3dSJohn Hsu 206c1644e3dSJohn Hsu static const char * const adc_channel[] = { 207c1644e3dSJohn Hsu "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4" 208c1644e3dSJohn Hsu }; 209c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL( 210c1644e3dSJohn Hsu digital_ch4_enum, NAU8540_REG_DIGITAL_MUX, 6, adc_channel); 211c1644e3dSJohn Hsu 212c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch4_mux = 213c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH4 Select", digital_ch4_enum); 214c1644e3dSJohn Hsu 215c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL( 216c1644e3dSJohn Hsu digital_ch3_enum, NAU8540_REG_DIGITAL_MUX, 4, adc_channel); 217c1644e3dSJohn Hsu 218c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch3_mux = 219c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH3 Select", digital_ch3_enum); 220c1644e3dSJohn Hsu 221c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL( 222c1644e3dSJohn Hsu digital_ch2_enum, NAU8540_REG_DIGITAL_MUX, 2, adc_channel); 223c1644e3dSJohn Hsu 224c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch2_mux = 225c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH2 Select", digital_ch2_enum); 226c1644e3dSJohn Hsu 227c1644e3dSJohn Hsu static SOC_ENUM_SINGLE_DECL( 228c1644e3dSJohn Hsu digital_ch1_enum, NAU8540_REG_DIGITAL_MUX, 0, adc_channel); 229c1644e3dSJohn Hsu 230c1644e3dSJohn Hsu static const struct snd_kcontrol_new digital_ch1_mux = 231c1644e3dSJohn Hsu SOC_DAPM_ENUM("Digital CH1 Select", digital_ch1_enum); 232c1644e3dSJohn Hsu 2336573c051SJohn Hsu static int adc_power_control(struct snd_soc_dapm_widget *w, 2346573c051SJohn Hsu struct snd_kcontrol *k, int event) 2356573c051SJohn Hsu { 236415bc3a0SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 237415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 2386573c051SJohn Hsu 2396573c051SJohn Hsu if (SND_SOC_DAPM_EVENT_ON(event)) { 2406573c051SJohn Hsu msleep(300); 2416573c051SJohn Hsu /* DO12 and DO34 pad output enable */ 2426573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 2436573c051SJohn Hsu NAU8540_I2S_DO12_TRI, 0); 2446573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 2456573c051SJohn Hsu NAU8540_I2S_DO34_TRI, 0); 2466573c051SJohn Hsu } else if (SND_SOC_DAPM_EVENT_OFF(event)) { 2476573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 2486573c051SJohn Hsu NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); 2496573c051SJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 2506573c051SJohn Hsu NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); 2516573c051SJohn Hsu } 2526573c051SJohn Hsu return 0; 2536573c051SJohn Hsu } 2546573c051SJohn Hsu 255e4d0db60SJohn Hsu static int aiftx_power_control(struct snd_soc_dapm_widget *w, 256e4d0db60SJohn Hsu struct snd_kcontrol *k, int event) 257e4d0db60SJohn Hsu { 258415bc3a0SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 259415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 260e4d0db60SJohn Hsu 261e4d0db60SJohn Hsu if (SND_SOC_DAPM_EVENT_OFF(event)) { 262e4d0db60SJohn Hsu regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001); 263e4d0db60SJohn Hsu regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000); 264e4d0db60SJohn Hsu } 265e4d0db60SJohn Hsu return 0; 266e4d0db60SJohn Hsu } 267e4d0db60SJohn Hsu 268c1644e3dSJohn Hsu static const struct snd_soc_dapm_widget nau8540_dapm_widgets[] = { 269c1644e3dSJohn Hsu SND_SOC_DAPM_SUPPLY("MICBIAS2", NAU8540_REG_MIC_BIAS, 11, 0, NULL, 0), 270c1644e3dSJohn Hsu SND_SOC_DAPM_SUPPLY("MICBIAS1", NAU8540_REG_MIC_BIAS, 10, 0, NULL, 0), 271c1644e3dSJohn Hsu 272c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC1"), 273c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC2"), 274c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC3"), 275c1644e3dSJohn Hsu SND_SOC_DAPM_INPUT("MIC4"), 276c1644e3dSJohn Hsu 277c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("Frontend PGA1", NAU8540_REG_PWR, 12, 0, NULL, 0), 278c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("Frontend PGA2", NAU8540_REG_PWR, 13, 0, NULL, 0), 279c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("Frontend PGA3", NAU8540_REG_PWR, 14, 0, NULL, 0), 280c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("Frontend PGA4", NAU8540_REG_PWR, 15, 0, NULL, 0), 281c1644e3dSJohn Hsu 2826573c051SJohn Hsu SND_SOC_DAPM_ADC_E("ADC1", NULL, 2836573c051SJohn Hsu NAU8540_REG_POWER_MANAGEMENT, 0, 0, adc_power_control, 2846573c051SJohn Hsu SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2856573c051SJohn Hsu SND_SOC_DAPM_ADC_E("ADC2", NULL, 2866573c051SJohn Hsu NAU8540_REG_POWER_MANAGEMENT, 1, 0, adc_power_control, 2876573c051SJohn Hsu SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2886573c051SJohn Hsu SND_SOC_DAPM_ADC_E("ADC3", NULL, 2896573c051SJohn Hsu NAU8540_REG_POWER_MANAGEMENT, 2, 0, adc_power_control, 2906573c051SJohn Hsu SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2916573c051SJohn Hsu SND_SOC_DAPM_ADC_E("ADC4", NULL, 2926573c051SJohn Hsu NAU8540_REG_POWER_MANAGEMENT, 3, 0, adc_power_control, 2936573c051SJohn Hsu SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 294c1644e3dSJohn Hsu 295c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("ADC CH1", NAU8540_REG_ANALOG_PWR, 0, 0, NULL, 0), 296c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("ADC CH2", NAU8540_REG_ANALOG_PWR, 1, 0, NULL, 0), 297c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("ADC CH3", NAU8540_REG_ANALOG_PWR, 2, 0, NULL, 0), 298c1644e3dSJohn Hsu SND_SOC_DAPM_PGA("ADC CH4", NAU8540_REG_ANALOG_PWR, 3, 0, NULL, 0), 299c1644e3dSJohn Hsu 300c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH4 Mux", 301c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch4_mux), 302c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH3 Mux", 303c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch3_mux), 304c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH2 Mux", 305c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch2_mux), 306c1644e3dSJohn Hsu SND_SOC_DAPM_MUX("Digital CH1 Mux", 307c1644e3dSJohn Hsu SND_SOC_NOPM, 0, 0, &digital_ch1_mux), 308c1644e3dSJohn Hsu 309e4d0db60SJohn Hsu SND_SOC_DAPM_AIF_OUT_E("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0, 310e4d0db60SJohn Hsu aiftx_power_control, SND_SOC_DAPM_POST_PMD), 311c1644e3dSJohn Hsu }; 312c1644e3dSJohn Hsu 313c1644e3dSJohn Hsu static const struct snd_soc_dapm_route nau8540_dapm_routes[] = { 314c1644e3dSJohn Hsu {"Frontend PGA1", NULL, "MIC1"}, 315c1644e3dSJohn Hsu {"Frontend PGA2", NULL, "MIC2"}, 316c1644e3dSJohn Hsu {"Frontend PGA3", NULL, "MIC3"}, 317c1644e3dSJohn Hsu {"Frontend PGA4", NULL, "MIC4"}, 318c1644e3dSJohn Hsu 319c1644e3dSJohn Hsu {"ADC1", NULL, "Frontend PGA1"}, 320c1644e3dSJohn Hsu {"ADC2", NULL, "Frontend PGA2"}, 321c1644e3dSJohn Hsu {"ADC3", NULL, "Frontend PGA3"}, 322c1644e3dSJohn Hsu {"ADC4", NULL, "Frontend PGA4"}, 323c1644e3dSJohn Hsu 324c1644e3dSJohn Hsu {"ADC CH1", NULL, "ADC1"}, 325c1644e3dSJohn Hsu {"ADC CH2", NULL, "ADC2"}, 326c1644e3dSJohn Hsu {"ADC CH3", NULL, "ADC3"}, 327c1644e3dSJohn Hsu {"ADC CH4", NULL, "ADC4"}, 328c1644e3dSJohn Hsu 329c1644e3dSJohn Hsu {"ADC1", NULL, "MICBIAS1"}, 330c1644e3dSJohn Hsu {"ADC2", NULL, "MICBIAS1"}, 331c1644e3dSJohn Hsu {"ADC3", NULL, "MICBIAS2"}, 332c1644e3dSJohn Hsu {"ADC4", NULL, "MICBIAS2"}, 333c1644e3dSJohn Hsu 334c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"}, 335c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"}, 336c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"}, 337c1644e3dSJohn Hsu {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"}, 338c1644e3dSJohn Hsu 339c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"}, 340c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"}, 341c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"}, 342c1644e3dSJohn Hsu {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"}, 343c1644e3dSJohn Hsu 344c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"}, 345c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"}, 346c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"}, 347c1644e3dSJohn Hsu {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"}, 348c1644e3dSJohn Hsu 349c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"}, 350c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"}, 351c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"}, 352c1644e3dSJohn Hsu {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"}, 353c1644e3dSJohn Hsu 354c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH1 Mux"}, 355c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH2 Mux"}, 356c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH3 Mux"}, 357c1644e3dSJohn Hsu {"AIFTX", NULL, "Digital CH4 Mux"}, 358c1644e3dSJohn Hsu }; 359c1644e3dSJohn Hsu 360be919239STakashi Iwai static const struct nau8540_osr_attr * 361be919239STakashi Iwai nau8540_get_osr(struct nau8540 *nau8540) 362c1644e3dSJohn Hsu { 363be919239STakashi Iwai unsigned int osr; 364c1644e3dSJohn Hsu 365be919239STakashi Iwai regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr); 366be919239STakashi Iwai osr &= NAU8540_ADC_OSR_MASK; 367be919239STakashi Iwai if (osr >= ARRAY_SIZE(osr_adc_sel)) 368be919239STakashi Iwai return NULL; 369be919239STakashi Iwai return &osr_adc_sel[osr]; 370c1644e3dSJohn Hsu } 371c1644e3dSJohn Hsu 372be919239STakashi Iwai static int nau8540_dai_startup(struct snd_pcm_substream *substream, 373be919239STakashi Iwai struct snd_soc_dai *dai) 374be919239STakashi Iwai { 375be919239STakashi Iwai struct snd_soc_component *component = dai->component; 376be919239STakashi Iwai struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 377be919239STakashi Iwai const struct nau8540_osr_attr *osr; 378be919239STakashi Iwai 379be919239STakashi Iwai osr = nau8540_get_osr(nau8540); 380be919239STakashi Iwai if (!osr || !osr->osr) 381be919239STakashi Iwai return -EINVAL; 382be919239STakashi Iwai 383be919239STakashi Iwai return snd_pcm_hw_constraint_minmax(substream->runtime, 384be919239STakashi Iwai SNDRV_PCM_HW_PARAM_RATE, 385be919239STakashi Iwai 0, CLK_ADC_MAX / osr->osr); 386c1644e3dSJohn Hsu } 387c1644e3dSJohn Hsu 388c1644e3dSJohn Hsu static int nau8540_hw_params(struct snd_pcm_substream *substream, 389c1644e3dSJohn Hsu struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 390c1644e3dSJohn Hsu { 391415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component; 392415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 393be919239STakashi Iwai unsigned int val_len = 0; 394be919239STakashi Iwai const struct nau8540_osr_attr *osr; 395c1644e3dSJohn Hsu 396c1644e3dSJohn Hsu /* CLK_ADC = OSR * FS 397c1644e3dSJohn Hsu * ADC clock frequency is defined as Over Sampling Rate (OSR) 398c1644e3dSJohn Hsu * multiplied by the audio sample rate (Fs). Note that the OSR and Fs 399c1644e3dSJohn Hsu * values must be selected such that the maximum frequency is less 400c1644e3dSJohn Hsu * than 6.144 MHz. 401c1644e3dSJohn Hsu */ 402be919239STakashi Iwai osr = nau8540_get_osr(nau8540); 403be919239STakashi Iwai if (!osr || !osr->osr) 404be919239STakashi Iwai return -EINVAL; 405be919239STakashi Iwai if (params_rate(params) * osr->osr > CLK_ADC_MAX) 406c1644e3dSJohn Hsu return -EINVAL; 407c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 408c1644e3dSJohn Hsu NAU8540_CLK_ADC_SRC_MASK, 409be919239STakashi Iwai osr->clk_src << NAU8540_CLK_ADC_SRC_SFT); 410c1644e3dSJohn Hsu 411c1644e3dSJohn Hsu switch (params_width(params)) { 412c1644e3dSJohn Hsu case 16: 413c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_16; 414c1644e3dSJohn Hsu break; 415c1644e3dSJohn Hsu case 20: 416c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_20; 417c1644e3dSJohn Hsu break; 418c1644e3dSJohn Hsu case 24: 419c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_24; 420c1644e3dSJohn Hsu break; 421c1644e3dSJohn Hsu case 32: 422c1644e3dSJohn Hsu val_len |= NAU8540_I2S_DL_32; 423c1644e3dSJohn Hsu break; 424c1644e3dSJohn Hsu default: 425c1644e3dSJohn Hsu return -EINVAL; 426c1644e3dSJohn Hsu } 427c1644e3dSJohn Hsu 428c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, 429c1644e3dSJohn Hsu NAU8540_I2S_DL_MASK, val_len); 430c1644e3dSJohn Hsu 431c1644e3dSJohn Hsu return 0; 432c1644e3dSJohn Hsu } 433c1644e3dSJohn Hsu 434c1644e3dSJohn Hsu static int nau8540_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 435c1644e3dSJohn Hsu { 436415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component; 437415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 438c1644e3dSJohn Hsu unsigned int ctrl1_val = 0, ctrl2_val = 0; 439c1644e3dSJohn Hsu 440c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 441c1644e3dSJohn Hsu case SND_SOC_DAIFMT_CBM_CFM: 442c1644e3dSJohn Hsu ctrl2_val |= NAU8540_I2S_MS_MASTER; 443c1644e3dSJohn Hsu break; 444c1644e3dSJohn Hsu case SND_SOC_DAIFMT_CBS_CFS: 445c1644e3dSJohn Hsu break; 446c1644e3dSJohn Hsu default: 447c1644e3dSJohn Hsu return -EINVAL; 448c1644e3dSJohn Hsu } 449c1644e3dSJohn Hsu 450c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 451c1644e3dSJohn Hsu case SND_SOC_DAIFMT_NB_NF: 452c1644e3dSJohn Hsu break; 453c1644e3dSJohn Hsu case SND_SOC_DAIFMT_IB_NF: 454c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_BP_INV; 455c1644e3dSJohn Hsu break; 456c1644e3dSJohn Hsu default: 457c1644e3dSJohn Hsu return -EINVAL; 458c1644e3dSJohn Hsu } 459c1644e3dSJohn Hsu 460c1644e3dSJohn Hsu switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 461c1644e3dSJohn Hsu case SND_SOC_DAIFMT_I2S: 462c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_I2S; 463c1644e3dSJohn Hsu break; 464c1644e3dSJohn Hsu case SND_SOC_DAIFMT_LEFT_J: 465c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_LEFT; 466c1644e3dSJohn Hsu break; 467c1644e3dSJohn Hsu case SND_SOC_DAIFMT_RIGHT_J: 468c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_RIGTH; 469c1644e3dSJohn Hsu break; 470c1644e3dSJohn Hsu case SND_SOC_DAIFMT_DSP_A: 471c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_PCM_AB; 472c1644e3dSJohn Hsu break; 473c1644e3dSJohn Hsu case SND_SOC_DAIFMT_DSP_B: 474c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_DF_PCM_AB; 475c1644e3dSJohn Hsu ctrl1_val |= NAU8540_I2S_PCMB_EN; 476c1644e3dSJohn Hsu break; 477c1644e3dSJohn Hsu default: 478c1644e3dSJohn Hsu return -EINVAL; 479c1644e3dSJohn Hsu } 480c1644e3dSJohn Hsu 481c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0, 482c1644e3dSJohn Hsu NAU8540_I2S_DL_MASK | NAU8540_I2S_DF_MASK | 483c1644e3dSJohn Hsu NAU8540_I2S_BP_INV | NAU8540_I2S_PCMB_EN, ctrl1_val); 484c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 485c1644e3dSJohn Hsu NAU8540_I2S_MS_MASK | NAU8540_I2S_DO12_OE, ctrl2_val); 486c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 487c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE, 0); 488c1644e3dSJohn Hsu 489c1644e3dSJohn Hsu return 0; 490c1644e3dSJohn Hsu } 491c1644e3dSJohn Hsu 492c1644e3dSJohn Hsu /** 493c1644e3dSJohn Hsu * nau8540_set_tdm_slot - configure DAI TX TDM. 494c1644e3dSJohn Hsu * @dai: DAI 495c1644e3dSJohn Hsu * @tx_mask: bitmask representing active TX slots. Ex. 496c1644e3dSJohn Hsu * 0xf for normal 4 channel TDM. 497c1644e3dSJohn Hsu * 0xf0 for shifted 4 channel TDM 498c1644e3dSJohn Hsu * @rx_mask: no used. 499c1644e3dSJohn Hsu * @slots: Number of slots in use. 500c1644e3dSJohn Hsu * @slot_width: Width in bits for each slot. 501c1644e3dSJohn Hsu * 502c1644e3dSJohn Hsu * Configures a DAI for TDM operation. Only support 4 slots TDM. 503c1644e3dSJohn Hsu */ 504c1644e3dSJohn Hsu static int nau8540_set_tdm_slot(struct snd_soc_dai *dai, 505c1644e3dSJohn Hsu unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 506c1644e3dSJohn Hsu { 507415bc3a0SKuninori Morimoto struct snd_soc_component *component = dai->component; 508415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 509c1644e3dSJohn Hsu unsigned int ctrl2_val = 0, ctrl4_val = 0; 510c1644e3dSJohn Hsu 511c1644e3dSJohn Hsu if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf))) 512c1644e3dSJohn Hsu return -EINVAL; 513c1644e3dSJohn Hsu 514c1644e3dSJohn Hsu ctrl4_val |= (NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN); 515c1644e3dSJohn Hsu if (tx_mask & 0xf0) { 516c1644e3dSJohn Hsu ctrl2_val = 4 * slot_width; 517c1644e3dSJohn Hsu ctrl4_val |= (tx_mask >> 4); 518c1644e3dSJohn Hsu } else { 519c1644e3dSJohn Hsu ctrl4_val |= tx_mask; 520c1644e3dSJohn Hsu } 521c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4, 522c1644e3dSJohn Hsu NAU8540_TDM_MODE | NAU8540_TDM_OFFSET_EN | 523c1644e3dSJohn Hsu NAU8540_TDM_TX_MASK, ctrl4_val); 524c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1, 525c1644e3dSJohn Hsu NAU8540_I2S_DO12_OE, NAU8540_I2S_DO12_OE); 526c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2, 527c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE | NAU8540_I2S_TSLOT_L_MASK, 528c1644e3dSJohn Hsu NAU8540_I2S_DO34_OE | ctrl2_val); 529c1644e3dSJohn Hsu 530c1644e3dSJohn Hsu return 0; 531c1644e3dSJohn Hsu } 532c1644e3dSJohn Hsu 533*a60a609bSDavid Lin static int nau8540_dai_trigger(struct snd_pcm_substream *substream, 534*a60a609bSDavid Lin int cmd, struct snd_soc_dai *dai) 535*a60a609bSDavid Lin { 536*a60a609bSDavid Lin struct snd_soc_component *component = dai->component; 537*a60a609bSDavid Lin struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 538*a60a609bSDavid Lin struct regmap *regmap = nau8540->regmap; 539*a60a609bSDavid Lin unsigned int val; 540*a60a609bSDavid Lin int ret = 0; 541*a60a609bSDavid Lin 542*a60a609bSDavid Lin /* Reading the peak data to detect abnormal data in the ADC channel. 543*a60a609bSDavid Lin * If abnormal data happens, the driver takes recovery actions to 544*a60a609bSDavid Lin * refresh the ADC channel. 545*a60a609bSDavid Lin */ 546*a60a609bSDavid Lin switch (cmd) { 547*a60a609bSDavid Lin case SNDRV_PCM_TRIGGER_START: 548*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 549*a60a609bSDavid Lin NAU8540_CLK_AGC_EN, NAU8540_CLK_AGC_EN); 550*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3, 551*a60a609bSDavid Lin NAU8540_ALC_CH_ALL_EN, NAU8540_ALC_CH_ALL_EN); 552*a60a609bSDavid Lin 553*a60a609bSDavid Lin regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val); 554*a60a609bSDavid Lin dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val); 555*a60a609bSDavid Lin if (!val) { 556*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_MUTE, 557*a60a609bSDavid Lin NAU8540_PGA_CH_ALL_MUTE, NAU8540_PGA_CH_ALL_MUTE); 558*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_MUTE, 559*a60a609bSDavid Lin NAU8540_PGA_CH_ALL_MUTE, 0); 560*a60a609bSDavid Lin regmap_write(regmap, NAU8540_REG_RST, 0x1); 561*a60a609bSDavid Lin regmap_write(regmap, NAU8540_REG_RST, 0); 562*a60a609bSDavid Lin regmap_read(regmap, NAU8540_REG_PEAK_CH1, &val); 563*a60a609bSDavid Lin dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val); 564*a60a609bSDavid Lin if (!val) { 565*a60a609bSDavid Lin dev_err(nau8540->dev, "Channel recovery failed!!"); 566*a60a609bSDavid Lin ret = -EIO; 567*a60a609bSDavid Lin } 568*a60a609bSDavid Lin } 569*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 570*a60a609bSDavid Lin NAU8540_CLK_AGC_EN, 0); 571*a60a609bSDavid Lin regmap_update_bits(regmap, NAU8540_REG_ALC_CONTROL_3, 572*a60a609bSDavid Lin NAU8540_ALC_CH_ALL_EN, 0); 573*a60a609bSDavid Lin break; 574*a60a609bSDavid Lin 575*a60a609bSDavid Lin default: 576*a60a609bSDavid Lin break; 577*a60a609bSDavid Lin } 578*a60a609bSDavid Lin 579*a60a609bSDavid Lin return ret; 580*a60a609bSDavid Lin } 581c1644e3dSJohn Hsu 582c1644e3dSJohn Hsu static const struct snd_soc_dai_ops nau8540_dai_ops = { 583be919239STakashi Iwai .startup = nau8540_dai_startup, 584c1644e3dSJohn Hsu .hw_params = nau8540_hw_params, 585c1644e3dSJohn Hsu .set_fmt = nau8540_set_fmt, 586c1644e3dSJohn Hsu .set_tdm_slot = nau8540_set_tdm_slot, 587*a60a609bSDavid Lin .trigger = nau8540_dai_trigger, 588c1644e3dSJohn Hsu }; 589c1644e3dSJohn Hsu 590c1644e3dSJohn Hsu #define NAU8540_RATES SNDRV_PCM_RATE_8000_48000 591c1644e3dSJohn Hsu #define NAU8540_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ 592c1644e3dSJohn Hsu | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 593c1644e3dSJohn Hsu 594c1644e3dSJohn Hsu static struct snd_soc_dai_driver nau8540_dai = { 595c1644e3dSJohn Hsu .name = "nau8540-hifi", 596c1644e3dSJohn Hsu .capture = { 597c1644e3dSJohn Hsu .stream_name = "Capture", 598c1644e3dSJohn Hsu .channels_min = 1, 599c1644e3dSJohn Hsu .channels_max = 4, 600c1644e3dSJohn Hsu .rates = NAU8540_RATES, 601c1644e3dSJohn Hsu .formats = NAU8540_FORMATS, 602c1644e3dSJohn Hsu }, 603c1644e3dSJohn Hsu .ops = &nau8540_dai_ops, 604c1644e3dSJohn Hsu }; 605c1644e3dSJohn Hsu 606c1644e3dSJohn Hsu /** 607c1644e3dSJohn Hsu * nau8540_calc_fll_param - Calculate FLL parameters. 608c1644e3dSJohn Hsu * @fll_in: external clock provided to codec. 609c1644e3dSJohn Hsu * @fs: sampling rate. 610c1644e3dSJohn Hsu * @fll_param: Pointer to structure of FLL parameters. 611c1644e3dSJohn Hsu * 612c1644e3dSJohn Hsu * Calculate FLL parameters to configure codec. 613c1644e3dSJohn Hsu * 614c1644e3dSJohn Hsu * Returns 0 for success or negative error code. 615c1644e3dSJohn Hsu */ 616c1644e3dSJohn Hsu static int nau8540_calc_fll_param(unsigned int fll_in, 617c1644e3dSJohn Hsu unsigned int fs, struct nau8540_fll *fll_param) 618c1644e3dSJohn Hsu { 619c1644e3dSJohn Hsu u64 fvco, fvco_max; 620c1644e3dSJohn Hsu unsigned int fref, i, fvco_sel; 621c1644e3dSJohn Hsu 622c1644e3dSJohn Hsu /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing 623c1644e3dSJohn Hsu * freq_in by 1, 2, 4, or 8 using FLL pre-scalar. 624c1644e3dSJohn Hsu * FREF = freq_in / NAU8540_FLL_REF_DIV_MASK 625c1644e3dSJohn Hsu */ 626c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) { 627c1644e3dSJohn Hsu fref = fll_in / fll_pre_scalar[i].param; 628c1644e3dSJohn Hsu if (fref <= NAU_FREF_MAX) 629c1644e3dSJohn Hsu break; 630c1644e3dSJohn Hsu } 631c1644e3dSJohn Hsu if (i == ARRAY_SIZE(fll_pre_scalar)) 632c1644e3dSJohn Hsu return -EINVAL; 633c1644e3dSJohn Hsu fll_param->clk_ref_div = fll_pre_scalar[i].val; 634c1644e3dSJohn Hsu 635c1644e3dSJohn Hsu /* Choose the FLL ratio based on FREF */ 636c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) { 637c1644e3dSJohn Hsu if (fref >= fll_ratio[i].param) 638c1644e3dSJohn Hsu break; 639c1644e3dSJohn Hsu } 640c1644e3dSJohn Hsu if (i == ARRAY_SIZE(fll_ratio)) 641c1644e3dSJohn Hsu return -EINVAL; 642c1644e3dSJohn Hsu fll_param->ratio = fll_ratio[i].val; 643c1644e3dSJohn Hsu 644c1644e3dSJohn Hsu /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs. 645c1644e3dSJohn Hsu * FDCO must be within the 90MHz - 124MHz or the FFL cannot be 646c1644e3dSJohn Hsu * guaranteed across the full range of operation. 647c1644e3dSJohn Hsu * FDCO = freq_out * 2 * mclk_src_scaling 648c1644e3dSJohn Hsu */ 649c1644e3dSJohn Hsu fvco_max = 0; 650c1644e3dSJohn Hsu fvco_sel = ARRAY_SIZE(mclk_src_scaling); 651c1644e3dSJohn Hsu for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) { 652cd7fdc45SYoung_X fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param; 653c1644e3dSJohn Hsu if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX && 654c1644e3dSJohn Hsu fvco_max < fvco) { 655c1644e3dSJohn Hsu fvco_max = fvco; 656c1644e3dSJohn Hsu fvco_sel = i; 657c1644e3dSJohn Hsu } 658c1644e3dSJohn Hsu } 659c1644e3dSJohn Hsu if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel) 660c1644e3dSJohn Hsu return -EINVAL; 661c1644e3dSJohn Hsu fll_param->mclk_src = mclk_src_scaling[fvco_sel].val; 662c1644e3dSJohn Hsu 663c1644e3dSJohn Hsu /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional 664c1644e3dSJohn Hsu * input based on FDCO, FREF and FLL ratio. 665c1644e3dSJohn Hsu */ 666c1644e3dSJohn Hsu fvco = div_u64(fvco_max << 16, fref * fll_param->ratio); 667c1644e3dSJohn Hsu fll_param->fll_int = (fvco >> 16) & 0x3FF; 668c1644e3dSJohn Hsu fll_param->fll_frac = fvco & 0xFFFF; 669c1644e3dSJohn Hsu return 0; 670c1644e3dSJohn Hsu } 671c1644e3dSJohn Hsu 672c1644e3dSJohn Hsu static void nau8540_fll_apply(struct regmap *regmap, 673c1644e3dSJohn Hsu struct nau8540_fll *fll_param) 674c1644e3dSJohn Hsu { 675c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_CLOCK_SRC, 676c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK | NAU8540_CLK_MCLK_SRC_MASK, 677c1644e3dSJohn Hsu NAU8540_CLK_SRC_MCLK | fll_param->mclk_src); 678c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL1, 679fe83b1b7SJohn Hsu NAU8540_FLL_RATIO_MASK | NAU8540_ICTRL_LATCH_MASK, 680fe83b1b7SJohn Hsu fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT)); 681c1644e3dSJohn Hsu /* FLL 16-bit fractional input */ 682c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac); 683c1644e3dSJohn Hsu /* FLL 10-bit integer input */ 684c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL3, 685c1644e3dSJohn Hsu NAU8540_FLL_INTEGER_MASK, fll_param->fll_int); 686c1644e3dSJohn Hsu /* FLL pre-scaler */ 687c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL4, 688c1644e3dSJohn Hsu NAU8540_FLL_REF_DIV_MASK, 689c1644e3dSJohn Hsu fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT); 690c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5, 691c1644e3dSJohn Hsu NAU8540_FLL_CLK_SW_MASK, NAU8540_FLL_CLK_SW_REF); 692c1644e3dSJohn Hsu regmap_update_bits(regmap, 693c1644e3dSJohn Hsu NAU8540_REG_FLL6, NAU8540_DCO_EN, 0); 694c1644e3dSJohn Hsu if (fll_param->fll_frac) { 695c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5, 696c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 697c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_MASK, 698c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 699c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_FILTER); 700c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL6, 701fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500, 702fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500); 703c1644e3dSJohn Hsu } else { 704c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL5, 705c1644e3dSJohn Hsu NAU8540_FLL_PDB_DAC_EN | NAU8540_FLL_LOOP_FTR_EN | 706c1644e3dSJohn Hsu NAU8540_FLL_FTR_SW_MASK, NAU8540_FLL_FTR_SW_ACCU); 707fe83b1b7SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FLL6, 708fe83b1b7SJohn Hsu NAU8540_SDM_EN | NAU8540_CUTOFF500, 0); 709c1644e3dSJohn Hsu } 710c1644e3dSJohn Hsu } 711c1644e3dSJohn Hsu 712c1644e3dSJohn Hsu /* freq_out must be 256*Fs in order to achieve the best performance */ 713415bc3a0SKuninori Morimoto static int nau8540_set_pll(struct snd_soc_component *component, int pll_id, int source, 714c1644e3dSJohn Hsu unsigned int freq_in, unsigned int freq_out) 715c1644e3dSJohn Hsu { 716415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 717c1644e3dSJohn Hsu struct nau8540_fll fll_param; 718c1644e3dSJohn Hsu int ret, fs; 719c1644e3dSJohn Hsu 720c1644e3dSJohn Hsu switch (pll_id) { 721c1644e3dSJohn Hsu case NAU8540_CLK_FLL_MCLK: 722c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 723fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 724fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MCLK | 0); 725c1644e3dSJohn Hsu break; 726c1644e3dSJohn Hsu 727c1644e3dSJohn Hsu case NAU8540_CLK_FLL_BLK: 728c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 729fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 730fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_BLK | 731fe83b1b7SJohn Hsu (0xf << NAU8540_GAIN_ERR_SFT)); 732c1644e3dSJohn Hsu break; 733c1644e3dSJohn Hsu 734c1644e3dSJohn Hsu case NAU8540_CLK_FLL_FS: 735c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3, 736fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_MASK | NAU8540_GAIN_ERR_MASK, 737fe83b1b7SJohn Hsu NAU8540_FLL_CLK_SRC_FS | 738fe83b1b7SJohn Hsu (0xf << NAU8540_GAIN_ERR_SFT)); 739c1644e3dSJohn Hsu break; 740c1644e3dSJohn Hsu 741c1644e3dSJohn Hsu default: 742c1644e3dSJohn Hsu dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id); 743c1644e3dSJohn Hsu return -EINVAL; 744c1644e3dSJohn Hsu } 745c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", 746c1644e3dSJohn Hsu freq_out, pll_id); 747c1644e3dSJohn Hsu 748c1644e3dSJohn Hsu fs = freq_out / 256; 749c1644e3dSJohn Hsu ret = nau8540_calc_fll_param(freq_in, fs, &fll_param); 750c1644e3dSJohn Hsu if (ret < 0) { 751c1644e3dSJohn Hsu dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in); 752c1644e3dSJohn Hsu return ret; 753c1644e3dSJohn Hsu } 754c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n", 755c1644e3dSJohn Hsu fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac, 756c1644e3dSJohn Hsu fll_param.fll_int, fll_param.clk_ref_div); 757c1644e3dSJohn Hsu 758c1644e3dSJohn Hsu nau8540_fll_apply(nau8540->regmap, &fll_param); 759c1644e3dSJohn Hsu mdelay(2); 760c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 761c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); 762c1644e3dSJohn Hsu 763c1644e3dSJohn Hsu return 0; 764c1644e3dSJohn Hsu } 765c1644e3dSJohn Hsu 766415bc3a0SKuninori Morimoto static int nau8540_set_sysclk(struct snd_soc_component *component, 767c1644e3dSJohn Hsu int clk_id, int source, unsigned int freq, int dir) 768c1644e3dSJohn Hsu { 769415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 770c1644e3dSJohn Hsu 771c1644e3dSJohn Hsu switch (clk_id) { 772c1644e3dSJohn Hsu case NAU8540_CLK_DIS: 773c1644e3dSJohn Hsu case NAU8540_CLK_MCLK: 774c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 775c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_MCLK); 776c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, 777c1644e3dSJohn Hsu NAU8540_DCO_EN, 0); 778c1644e3dSJohn Hsu break; 779c1644e3dSJohn Hsu 780c1644e3dSJohn Hsu case NAU8540_CLK_INTERNAL: 781c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6, 782c1644e3dSJohn Hsu NAU8540_DCO_EN, NAU8540_DCO_EN); 783c1644e3dSJohn Hsu regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC, 784c1644e3dSJohn Hsu NAU8540_CLK_SRC_MASK, NAU8540_CLK_SRC_VCO); 785c1644e3dSJohn Hsu break; 786c1644e3dSJohn Hsu 787c1644e3dSJohn Hsu default: 788c1644e3dSJohn Hsu dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id); 789c1644e3dSJohn Hsu return -EINVAL; 790c1644e3dSJohn Hsu } 791c1644e3dSJohn Hsu 792c1644e3dSJohn Hsu dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n", 793c1644e3dSJohn Hsu freq, clk_id); 794c1644e3dSJohn Hsu 795c1644e3dSJohn Hsu return 0; 796c1644e3dSJohn Hsu } 797c1644e3dSJohn Hsu 798c1644e3dSJohn Hsu static void nau8540_reset_chip(struct regmap *regmap) 799c1644e3dSJohn Hsu { 800c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); 801c1644e3dSJohn Hsu regmap_write(regmap, NAU8540_REG_SW_RESET, 0x00); 802c1644e3dSJohn Hsu } 803c1644e3dSJohn Hsu 804c1644e3dSJohn Hsu static void nau8540_init_regs(struct nau8540 *nau8540) 805c1644e3dSJohn Hsu { 806c1644e3dSJohn Hsu struct regmap *regmap = nau8540->regmap; 807c1644e3dSJohn Hsu 808c1644e3dSJohn Hsu /* Enable Bias/VMID/VMID Tieoff */ 809c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_VMID_CTRL, 810c1644e3dSJohn Hsu NAU8540_VMID_EN | NAU8540_VMID_SEL_MASK, 811c1644e3dSJohn Hsu NAU8540_VMID_EN | (0x2 << NAU8540_VMID_SEL_SFT)); 812c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_REFERENCE, 813c1644e3dSJohn Hsu NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN, 814c1644e3dSJohn Hsu NAU8540_PRECHARGE_DIS | NAU8540_GLOBAL_BIAS_EN); 815c1644e3dSJohn Hsu mdelay(2); 816c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_MIC_BIAS, 817c1644e3dSJohn Hsu NAU8540_PU_PRE, NAU8540_PU_PRE); 818c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_CLOCK_CTRL, 819c1644e3dSJohn Hsu NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN, 820c1644e3dSJohn Hsu NAU8540_CLK_ADC_EN | NAU8540_CLK_I2S_EN); 821e4d0db60SJohn Hsu /* ADC OSR selection, CLK_ADC = Fs * OSR; 822e4d0db60SJohn Hsu * Channel time alignment enable. 823e4d0db60SJohn Hsu */ 824c1644e3dSJohn Hsu regmap_update_bits(regmap, NAU8540_REG_ADC_SAMPLE_RATE, 825e4d0db60SJohn Hsu NAU8540_CH_SYNC | NAU8540_ADC_OSR_MASK, 826e4d0db60SJohn Hsu NAU8540_CH_SYNC | NAU8540_ADC_OSR_64); 82714323ff8SJohn Hsu /* PGA input mode selection */ 82814323ff8SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FEPGA1, 82914323ff8SJohn Hsu NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT, 83014323ff8SJohn Hsu NAU8540_FEPGA1_MODCH2_SHT | NAU8540_FEPGA1_MODCH1_SHT); 83114323ff8SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_FEPGA2, 83214323ff8SJohn Hsu NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT, 83314323ff8SJohn Hsu NAU8540_FEPGA2_MODCH4_SHT | NAU8540_FEPGA2_MODCH3_SHT); 8346573c051SJohn Hsu /* DO12 and DO34 pad output disable */ 8356573c051SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL1, 8366573c051SJohn Hsu NAU8540_I2S_DO12_TRI, NAU8540_I2S_DO12_TRI); 8376573c051SJohn Hsu regmap_update_bits(regmap, NAU8540_REG_PCM_CTRL2, 8386573c051SJohn Hsu NAU8540_I2S_DO34_TRI, NAU8540_I2S_DO34_TRI); 839c1644e3dSJohn Hsu } 840c1644e3dSJohn Hsu 841415bc3a0SKuninori Morimoto static int __maybe_unused nau8540_suspend(struct snd_soc_component *component) 842c1644e3dSJohn Hsu { 843415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 844c1644e3dSJohn Hsu 845c1644e3dSJohn Hsu regcache_cache_only(nau8540->regmap, true); 846c1644e3dSJohn Hsu regcache_mark_dirty(nau8540->regmap); 847c1644e3dSJohn Hsu 848c1644e3dSJohn Hsu return 0; 849c1644e3dSJohn Hsu } 850c1644e3dSJohn Hsu 851415bc3a0SKuninori Morimoto static int __maybe_unused nau8540_resume(struct snd_soc_component *component) 852c1644e3dSJohn Hsu { 853415bc3a0SKuninori Morimoto struct nau8540 *nau8540 = snd_soc_component_get_drvdata(component); 854c1644e3dSJohn Hsu 855c1644e3dSJohn Hsu regcache_cache_only(nau8540->regmap, false); 856c1644e3dSJohn Hsu regcache_sync(nau8540->regmap); 857c1644e3dSJohn Hsu 858c1644e3dSJohn Hsu return 0; 859c1644e3dSJohn Hsu } 860c1644e3dSJohn Hsu 861415bc3a0SKuninori Morimoto static const struct snd_soc_component_driver nau8540_component_driver = { 862c1644e3dSJohn Hsu .set_sysclk = nau8540_set_sysclk, 863c1644e3dSJohn Hsu .set_pll = nau8540_set_pll, 864c1644e3dSJohn Hsu .suspend = nau8540_suspend, 865c1644e3dSJohn Hsu .resume = nau8540_resume, 866c1644e3dSJohn Hsu .controls = nau8540_snd_controls, 867c1644e3dSJohn Hsu .num_controls = ARRAY_SIZE(nau8540_snd_controls), 868c1644e3dSJohn Hsu .dapm_widgets = nau8540_dapm_widgets, 869c1644e3dSJohn Hsu .num_dapm_widgets = ARRAY_SIZE(nau8540_dapm_widgets), 870c1644e3dSJohn Hsu .dapm_routes = nau8540_dapm_routes, 871c1644e3dSJohn Hsu .num_dapm_routes = ARRAY_SIZE(nau8540_dapm_routes), 872415bc3a0SKuninori Morimoto .suspend_bias_off = 1, 873415bc3a0SKuninori Morimoto .idle_bias_on = 1, 874415bc3a0SKuninori Morimoto .use_pmdown_time = 1, 875415bc3a0SKuninori Morimoto .endianness = 1, 876c1644e3dSJohn Hsu }; 877c1644e3dSJohn Hsu 878c1644e3dSJohn Hsu static const struct regmap_config nau8540_regmap_config = { 879c1644e3dSJohn Hsu .val_bits = 16, 880c1644e3dSJohn Hsu .reg_bits = 16, 881c1644e3dSJohn Hsu 882c1644e3dSJohn Hsu .max_register = NAU8540_REG_MAX, 883c1644e3dSJohn Hsu .readable_reg = nau8540_readable_reg, 884c1644e3dSJohn Hsu .writeable_reg = nau8540_writeable_reg, 885c1644e3dSJohn Hsu .volatile_reg = nau8540_volatile_reg, 886c1644e3dSJohn Hsu 887c1644e3dSJohn Hsu .cache_type = REGCACHE_RBTREE, 888c1644e3dSJohn Hsu .reg_defaults = nau8540_reg_defaults, 889c1644e3dSJohn Hsu .num_reg_defaults = ARRAY_SIZE(nau8540_reg_defaults), 890c1644e3dSJohn Hsu }; 891c1644e3dSJohn Hsu 8927325ed4dSStephen Kitt static int nau8540_i2c_probe(struct i2c_client *i2c) 893c1644e3dSJohn Hsu { 894c1644e3dSJohn Hsu struct device *dev = &i2c->dev; 895c1644e3dSJohn Hsu struct nau8540 *nau8540 = dev_get_platdata(dev); 896c1644e3dSJohn Hsu int ret, value; 897c1644e3dSJohn Hsu 898c1644e3dSJohn Hsu if (!nau8540) { 899c1644e3dSJohn Hsu nau8540 = devm_kzalloc(dev, sizeof(*nau8540), GFP_KERNEL); 900c1644e3dSJohn Hsu if (!nau8540) 901c1644e3dSJohn Hsu return -ENOMEM; 902c1644e3dSJohn Hsu } 903c1644e3dSJohn Hsu i2c_set_clientdata(i2c, nau8540); 904c1644e3dSJohn Hsu 905c1644e3dSJohn Hsu nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config); 906c1644e3dSJohn Hsu if (IS_ERR(nau8540->regmap)) 907c1644e3dSJohn Hsu return PTR_ERR(nau8540->regmap); 908c1644e3dSJohn Hsu ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value); 909c1644e3dSJohn Hsu if (ret < 0) { 910c1644e3dSJohn Hsu dev_err(dev, "Failed to read device id from the NAU85L40: %d\n", 911c1644e3dSJohn Hsu ret); 912c1644e3dSJohn Hsu return ret; 913c1644e3dSJohn Hsu } 914c1644e3dSJohn Hsu 915c1644e3dSJohn Hsu nau8540->dev = dev; 916c1644e3dSJohn Hsu nau8540_reset_chip(nau8540->regmap); 917c1644e3dSJohn Hsu nau8540_init_regs(nau8540); 918c1644e3dSJohn Hsu 919415bc3a0SKuninori Morimoto return devm_snd_soc_register_component(dev, 920415bc3a0SKuninori Morimoto &nau8540_component_driver, &nau8540_dai, 1); 921c1644e3dSJohn Hsu } 922c1644e3dSJohn Hsu 923c1644e3dSJohn Hsu static const struct i2c_device_id nau8540_i2c_ids[] = { 924c1644e3dSJohn Hsu { "nau8540", 0 }, 925c1644e3dSJohn Hsu { } 926c1644e3dSJohn Hsu }; 927c1644e3dSJohn Hsu MODULE_DEVICE_TABLE(i2c, nau8540_i2c_ids); 928c1644e3dSJohn Hsu 929c1644e3dSJohn Hsu #ifdef CONFIG_OF 930c1644e3dSJohn Hsu static const struct of_device_id nau8540_of_ids[] = { 931c1644e3dSJohn Hsu { .compatible = "nuvoton,nau8540", }, 932c1644e3dSJohn Hsu {} 933c1644e3dSJohn Hsu }; 934c1644e3dSJohn Hsu MODULE_DEVICE_TABLE(of, nau8540_of_ids); 935c1644e3dSJohn Hsu #endif 936c1644e3dSJohn Hsu 937c1644e3dSJohn Hsu static struct i2c_driver nau8540_i2c_driver = { 938c1644e3dSJohn Hsu .driver = { 939c1644e3dSJohn Hsu .name = "nau8540", 940c1644e3dSJohn Hsu .of_match_table = of_match_ptr(nau8540_of_ids), 941c1644e3dSJohn Hsu }, 9429abcd240SUwe Kleine-König .probe = nau8540_i2c_probe, 943c1644e3dSJohn Hsu .id_table = nau8540_i2c_ids, 944c1644e3dSJohn Hsu }; 945c1644e3dSJohn Hsu module_i2c_driver(nau8540_i2c_driver); 946c1644e3dSJohn Hsu 947c1644e3dSJohn Hsu MODULE_DESCRIPTION("ASoC NAU85L40 driver"); 948c1644e3dSJohn Hsu MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>"); 949c1644e3dSJohn Hsu MODULE_LICENSE("GPL v2"); 950