1*14bd8572SWeidong Wang // SPDX-License-Identifier: GPL-2.0-only 2*14bd8572SWeidong Wang // 3*14bd8572SWeidong Wang // aw88395_reg.h -- AW88395 chip register file 4*14bd8572SWeidong Wang // 5*14bd8572SWeidong Wang // Copyright (c) 2022-2023 AWINIC Technology CO., LTD 6*14bd8572SWeidong Wang // 7*14bd8572SWeidong Wang // Author: Bruce zhao <zhaolei@awinic.com> 8*14bd8572SWeidong Wang // 9*14bd8572SWeidong Wang 10*14bd8572SWeidong Wang #ifndef __AW88395_REG_H__ 11*14bd8572SWeidong Wang #define __AW88395_REG_H__ 12*14bd8572SWeidong Wang 13*14bd8572SWeidong Wang #define AW88395_ID_REG (0x00) 14*14bd8572SWeidong Wang #define AW88395_SYSST_REG (0x01) 15*14bd8572SWeidong Wang #define AW88395_SYSINT_REG (0x02) 16*14bd8572SWeidong Wang #define AW88395_SYSINTM_REG (0x03) 17*14bd8572SWeidong Wang #define AW88395_SYSCTRL_REG (0x04) 18*14bd8572SWeidong Wang #define AW88395_SYSCTRL2_REG (0x05) 19*14bd8572SWeidong Wang #define AW88395_I2SCTRL_REG (0x06) 20*14bd8572SWeidong Wang #define AW88395_I2SCFG1_REG (0x07) 21*14bd8572SWeidong Wang #define AW88395_I2SCFG2_REG (0x08) 22*14bd8572SWeidong Wang #define AW88395_HAGCCFG1_REG (0x09) 23*14bd8572SWeidong Wang #define AW88395_HAGCCFG2_REG (0x0A) 24*14bd8572SWeidong Wang #define AW88395_HAGCCFG3_REG (0x0B) 25*14bd8572SWeidong Wang #define AW88395_HAGCCFG4_REG (0x0C) 26*14bd8572SWeidong Wang #define AW88395_HAGCCFG5_REG (0x0D) 27*14bd8572SWeidong Wang #define AW88395_HAGCCFG6_REG (0x0E) 28*14bd8572SWeidong Wang #define AW88395_HAGCCFG7_REG (0x0F) 29*14bd8572SWeidong Wang #define AW88395_MPDCFG_REG (0x10) 30*14bd8572SWeidong Wang #define AW88395_PWMCTRL_REG (0x11) 31*14bd8572SWeidong Wang #define AW88395_I2SCFG3_REG (0x12) 32*14bd8572SWeidong Wang #define AW88395_DBGCTRL_REG (0x13) 33*14bd8572SWeidong Wang #define AW88395_HAGCST_REG (0x20) 34*14bd8572SWeidong Wang #define AW88395_VBAT_REG (0x21) 35*14bd8572SWeidong Wang #define AW88395_TEMP_REG (0x22) 36*14bd8572SWeidong Wang #define AW88395_PVDD_REG (0x23) 37*14bd8572SWeidong Wang #define AW88395_ISNDAT_REG (0x24) 38*14bd8572SWeidong Wang #define AW88395_VSNDAT_REG (0x25) 39*14bd8572SWeidong Wang #define AW88395_I2SINT_REG (0x26) 40*14bd8572SWeidong Wang #define AW88395_I2SCAPCNT_REG (0x27) 41*14bd8572SWeidong Wang #define AW88395_ANASTA1_REG (0x28) 42*14bd8572SWeidong Wang #define AW88395_ANASTA2_REG (0x29) 43*14bd8572SWeidong Wang #define AW88395_ANASTA3_REG (0x2A) 44*14bd8572SWeidong Wang #define AW88395_ANASTA4_REG (0x2B) 45*14bd8572SWeidong Wang #define AW88395_TESTDET_REG (0x2C) 46*14bd8572SWeidong Wang #define AW88395_TESTIN_REG (0x38) 47*14bd8572SWeidong Wang #define AW88395_TESTOUT_REG (0x39) 48*14bd8572SWeidong Wang #define AW88395_DSPMADD_REG (0x40) 49*14bd8572SWeidong Wang #define AW88395_DSPMDAT_REG (0x41) 50*14bd8572SWeidong Wang #define AW88395_WDT_REG (0x42) 51*14bd8572SWeidong Wang #define AW88395_ACR1_REG (0x43) 52*14bd8572SWeidong Wang #define AW88395_ACR2_REG (0x44) 53*14bd8572SWeidong Wang #define AW88395_ASR1_REG (0x45) 54*14bd8572SWeidong Wang #define AW88395_ASR2_REG (0x46) 55*14bd8572SWeidong Wang #define AW88395_DSPCFG_REG (0x47) 56*14bd8572SWeidong Wang #define AW88395_ASR3_REG (0x48) 57*14bd8572SWeidong Wang #define AW88395_ASR4_REG (0x49) 58*14bd8572SWeidong Wang #define AW88395_VSNCTRL1_REG (0x50) 59*14bd8572SWeidong Wang #define AW88395_ISNCTRL1_REG (0x51) 60*14bd8572SWeidong Wang #define AW88395_PLLCTRL1_REG (0x52) 61*14bd8572SWeidong Wang #define AW88395_PLLCTRL2_REG (0x53) 62*14bd8572SWeidong Wang #define AW88395_PLLCTRL3_REG (0x54) 63*14bd8572SWeidong Wang #define AW88395_CDACTRL1_REG (0x55) 64*14bd8572SWeidong Wang #define AW88395_CDACTRL2_REG (0x56) 65*14bd8572SWeidong Wang #define AW88395_SADCCTRL1_REG (0x57) 66*14bd8572SWeidong Wang #define AW88395_SADCCTRL2_REG (0x58) 67*14bd8572SWeidong Wang #define AW88395_CPCTRL1_REG (0x59) 68*14bd8572SWeidong Wang #define AW88395_BSTCTRL1_REG (0x60) 69*14bd8572SWeidong Wang #define AW88395_BSTCTRL2_REG (0x61) 70*14bd8572SWeidong Wang #define AW88395_BSTCTRL3_REG (0x62) 71*14bd8572SWeidong Wang #define AW88395_BSTCTRL4_REG (0x63) 72*14bd8572SWeidong Wang #define AW88395_BSTCTRL5_REG (0x64) 73*14bd8572SWeidong Wang #define AW88395_BSTCTRL6_REG (0x65) 74*14bd8572SWeidong Wang #define AW88395_BSTCTRL7_REG (0x66) 75*14bd8572SWeidong Wang #define AW88395_DSMCFG1_REG (0x67) 76*14bd8572SWeidong Wang #define AW88395_DSMCFG2_REG (0x68) 77*14bd8572SWeidong Wang #define AW88395_DSMCFG3_REG (0x69) 78*14bd8572SWeidong Wang #define AW88395_DSMCFG4_REG (0x6A) 79*14bd8572SWeidong Wang #define AW88395_DSMCFG5_REG (0x6B) 80*14bd8572SWeidong Wang #define AW88395_DSMCFG6_REG (0x6C) 81*14bd8572SWeidong Wang #define AW88395_DSMCFG7_REG (0x6D) 82*14bd8572SWeidong Wang #define AW88395_DSMCFG8_REG (0x6E) 83*14bd8572SWeidong Wang #define AW88395_TESTCTRL1_REG (0x70) 84*14bd8572SWeidong Wang #define AW88395_TESTCTRL2_REG (0x71) 85*14bd8572SWeidong Wang #define AW88395_EFCTRL1_REG (0x72) 86*14bd8572SWeidong Wang #define AW88395_EFCTRL2_REG (0x73) 87*14bd8572SWeidong Wang #define AW88395_EFWH_REG (0x74) 88*14bd8572SWeidong Wang #define AW88395_EFWM2_REG (0x75) 89*14bd8572SWeidong Wang #define AW88395_EFWM1_REG (0x76) 90*14bd8572SWeidong Wang #define AW88395_EFWL_REG (0x77) 91*14bd8572SWeidong Wang #define AW88395_EFRH_REG (0x78) 92*14bd8572SWeidong Wang #define AW88395_EFRM2_REG (0x79) 93*14bd8572SWeidong Wang #define AW88395_EFRM1_REG (0x7A) 94*14bd8572SWeidong Wang #define AW88395_EFRL_REG (0x7B) 95*14bd8572SWeidong Wang #define AW88395_TM_REG (0x7C) 96*14bd8572SWeidong Wang 97*14bd8572SWeidong Wang enum aw88395_id { 98*14bd8572SWeidong Wang AW88395_CHIP_ID = 0x2049, 99*14bd8572SWeidong Wang }; 100*14bd8572SWeidong Wang 101*14bd8572SWeidong Wang #define AW88395_REG_MAX (0x7D) 102*14bd8572SWeidong Wang 103*14bd8572SWeidong Wang #define AW88395_VOLUME_STEP_DB (6 * 8) 104*14bd8572SWeidong Wang 105*14bd8572SWeidong Wang #define AW88395_UVLS_START_BIT (14) 106*14bd8572SWeidong Wang #define AW88395_UVLS_NORMAL (0) 107*14bd8572SWeidong Wang #define AW88395_UVLS_NORMAL_VALUE \ 108*14bd8572SWeidong Wang (AW88395_UVLS_NORMAL << AW88395_UVLS_START_BIT) 109*14bd8572SWeidong Wang 110*14bd8572SWeidong Wang #define AW88395_DSPS_START_BIT (12) 111*14bd8572SWeidong Wang #define AW88395_DSPS_BITS_LEN (1) 112*14bd8572SWeidong Wang #define AW88395_DSPS_MASK \ 113*14bd8572SWeidong Wang (~(((1<<AW88395_DSPS_BITS_LEN)-1) << AW88395_DSPS_START_BIT)) 114*14bd8572SWeidong Wang 115*14bd8572SWeidong Wang #define AW88395_DSPS_NORMAL (0) 116*14bd8572SWeidong Wang #define AW88395_DSPS_NORMAL_VALUE \ 117*14bd8572SWeidong Wang (AW88395_DSPS_NORMAL << AW88395_DSPS_START_BIT) 118*14bd8572SWeidong Wang 119*14bd8572SWeidong Wang #define AW88395_BSTOCS_START_BIT (11) 120*14bd8572SWeidong Wang #define AW88395_BSTOCS_OVER_CURRENT (1) 121*14bd8572SWeidong Wang #define AW88395_BSTOCS_OVER_CURRENT_VALUE \ 122*14bd8572SWeidong Wang (AW88395_BSTOCS_OVER_CURRENT << AW88395_BSTOCS_START_BIT) 123*14bd8572SWeidong Wang 124*14bd8572SWeidong Wang #define AW88395_BSTS_START_BIT (9) 125*14bd8572SWeidong Wang #define AW88395_BSTS_FINISHED (1) 126*14bd8572SWeidong Wang #define AW88395_BSTS_FINISHED_VALUE \ 127*14bd8572SWeidong Wang (AW88395_BSTS_FINISHED << AW88395_BSTS_START_BIT) 128*14bd8572SWeidong Wang 129*14bd8572SWeidong Wang #define AW88395_SWS_START_BIT (8) 130*14bd8572SWeidong Wang #define AW88395_SWS_SWITCHING (1) 131*14bd8572SWeidong Wang #define AW88395_SWS_SWITCHING_VALUE \ 132*14bd8572SWeidong Wang (AW88395_SWS_SWITCHING << AW88395_SWS_START_BIT) 133*14bd8572SWeidong Wang 134*14bd8572SWeidong Wang #define AW88395_NOCLKS_START_BIT (5) 135*14bd8572SWeidong Wang #define AW88395_NOCLKS_NO_CLOCK (1) 136*14bd8572SWeidong Wang #define AW88395_NOCLKS_NO_CLOCK_VALUE \ 137*14bd8572SWeidong Wang (AW88395_NOCLKS_NO_CLOCK << AW88395_NOCLKS_START_BIT) 138*14bd8572SWeidong Wang 139*14bd8572SWeidong Wang #define AW88395_CLKS_START_BIT (4) 140*14bd8572SWeidong Wang #define AW88395_CLKS_STABLE (1) 141*14bd8572SWeidong Wang #define AW88395_CLKS_STABLE_VALUE \ 142*14bd8572SWeidong Wang (AW88395_CLKS_STABLE << AW88395_CLKS_START_BIT) 143*14bd8572SWeidong Wang 144*14bd8572SWeidong Wang #define AW88395_OCDS_START_BIT (3) 145*14bd8572SWeidong Wang #define AW88395_OCDS_OC (1) 146*14bd8572SWeidong Wang #define AW88395_OCDS_OC_VALUE \ 147*14bd8572SWeidong Wang (AW88395_OCDS_OC << AW88395_OCDS_START_BIT) 148*14bd8572SWeidong Wang 149*14bd8572SWeidong Wang #define AW88395_OTHS_START_BIT (1) 150*14bd8572SWeidong Wang #define AW88395_OTHS_OT (1) 151*14bd8572SWeidong Wang #define AW88395_OTHS_OT_VALUE \ 152*14bd8572SWeidong Wang (AW88395_OTHS_OT << AW88395_OTHS_START_BIT) 153*14bd8572SWeidong Wang 154*14bd8572SWeidong Wang #define AW88395_PLLS_START_BIT (0) 155*14bd8572SWeidong Wang #define AW88395_PLLS_LOCKED (1) 156*14bd8572SWeidong Wang #define AW88395_PLLS_LOCKED_VALUE \ 157*14bd8572SWeidong Wang (AW88395_PLLS_LOCKED << AW88395_PLLS_START_BIT) 158*14bd8572SWeidong Wang 159*14bd8572SWeidong Wang #define AW88395_BIT_PLL_CHECK \ 160*14bd8572SWeidong Wang (AW88395_CLKS_STABLE_VALUE | \ 161*14bd8572SWeidong Wang AW88395_PLLS_LOCKED_VALUE) 162*14bd8572SWeidong Wang 163*14bd8572SWeidong Wang #define AW88395_BIT_SYSST_CHECK_MASK \ 164*14bd8572SWeidong Wang (~(AW88395_UVLS_NORMAL_VALUE | \ 165*14bd8572SWeidong Wang AW88395_BSTOCS_OVER_CURRENT_VALUE | \ 166*14bd8572SWeidong Wang AW88395_BSTS_FINISHED_VALUE | \ 167*14bd8572SWeidong Wang AW88395_SWS_SWITCHING_VALUE | \ 168*14bd8572SWeidong Wang AW88395_NOCLKS_NO_CLOCK_VALUE | \ 169*14bd8572SWeidong Wang AW88395_CLKS_STABLE_VALUE | \ 170*14bd8572SWeidong Wang AW88395_OCDS_OC_VALUE | \ 171*14bd8572SWeidong Wang AW88395_OTHS_OT_VALUE | \ 172*14bd8572SWeidong Wang AW88395_PLLS_LOCKED_VALUE)) 173*14bd8572SWeidong Wang 174*14bd8572SWeidong Wang #define AW88395_BIT_SYSST_CHECK \ 175*14bd8572SWeidong Wang (AW88395_BSTS_FINISHED_VALUE | \ 176*14bd8572SWeidong Wang AW88395_SWS_SWITCHING_VALUE | \ 177*14bd8572SWeidong Wang AW88395_CLKS_STABLE_VALUE | \ 178*14bd8572SWeidong Wang AW88395_PLLS_LOCKED_VALUE) 179*14bd8572SWeidong Wang 180*14bd8572SWeidong Wang #define AW88395_WDI_START_BIT (6) 181*14bd8572SWeidong Wang #define AW88395_WDI_INT_VALUE (1) 182*14bd8572SWeidong Wang #define AW88395_WDI_INTERRUPT \ 183*14bd8572SWeidong Wang (AW88395_WDI_INT_VALUE << AW88395_WDI_START_BIT) 184*14bd8572SWeidong Wang 185*14bd8572SWeidong Wang #define AW88395_NOCLKI_START_BIT (5) 186*14bd8572SWeidong Wang #define AW88395_NOCLKI_INT_VALUE (1) 187*14bd8572SWeidong Wang #define AW88395_NOCLKI_INTERRUPT \ 188*14bd8572SWeidong Wang (AW88395_NOCLKI_INT_VALUE << AW88395_NOCLKI_START_BIT) 189*14bd8572SWeidong Wang 190*14bd8572SWeidong Wang #define AW88395_CLKI_START_BIT (4) 191*14bd8572SWeidong Wang #define AW88395_CLKI_INT_VALUE (1) 192*14bd8572SWeidong Wang #define AW88395_CLKI_INTERRUPT \ 193*14bd8572SWeidong Wang (AW88395_CLKI_INT_VALUE << AW88395_CLKI_START_BIT) 194*14bd8572SWeidong Wang 195*14bd8572SWeidong Wang #define AW88395_PLLI_START_BIT (0) 196*14bd8572SWeidong Wang #define AW88395_PLLI_INT_VALUE (1) 197*14bd8572SWeidong Wang #define AW88395_PLLI_INTERRUPT \ 198*14bd8572SWeidong Wang (AW88395_PLLI_INT_VALUE << AW88395_PLLI_START_BIT) 199*14bd8572SWeidong Wang 200*14bd8572SWeidong Wang #define AW88395_BIT_SYSINT_CHECK \ 201*14bd8572SWeidong Wang (AW88395_WDI_INTERRUPT | \ 202*14bd8572SWeidong Wang AW88395_CLKI_INTERRUPT | \ 203*14bd8572SWeidong Wang AW88395_NOCLKI_INTERRUPT | \ 204*14bd8572SWeidong Wang AW88395_PLLI_INTERRUPT) 205*14bd8572SWeidong Wang 206*14bd8572SWeidong Wang #define AW88395_HMUTE_START_BIT (8) 207*14bd8572SWeidong Wang #define AW88395_HMUTE_BITS_LEN (1) 208*14bd8572SWeidong Wang #define AW88395_HMUTE_MASK \ 209*14bd8572SWeidong Wang (~(((1<<AW88395_HMUTE_BITS_LEN)-1) << AW88395_HMUTE_START_BIT)) 210*14bd8572SWeidong Wang 211*14bd8572SWeidong Wang #define AW88395_HMUTE_DISABLE (0) 212*14bd8572SWeidong Wang #define AW88395_HMUTE_DISABLE_VALUE \ 213*14bd8572SWeidong Wang (AW88395_HMUTE_DISABLE << AW88395_HMUTE_START_BIT) 214*14bd8572SWeidong Wang 215*14bd8572SWeidong Wang #define AW88395_HMUTE_ENABLE (1) 216*14bd8572SWeidong Wang #define AW88395_HMUTE_ENABLE_VALUE \ 217*14bd8572SWeidong Wang (AW88395_HMUTE_ENABLE << AW88395_HMUTE_START_BIT) 218*14bd8572SWeidong Wang 219*14bd8572SWeidong Wang #define AW88395_RCV_MODE_START_BIT (7) 220*14bd8572SWeidong Wang #define AW88395_RCV_MODE_BITS_LEN (1) 221*14bd8572SWeidong Wang #define AW88395_RCV_MODE_MASK \ 222*14bd8572SWeidong Wang (~(((1<<AW88395_RCV_MODE_BITS_LEN)-1) << AW88395_RCV_MODE_START_BIT)) 223*14bd8572SWeidong Wang 224*14bd8572SWeidong Wang #define AW88395_RCV_MODE_RECEIVER (1) 225*14bd8572SWeidong Wang #define AW88395_RCV_MODE_RECEIVER_VALUE \ 226*14bd8572SWeidong Wang (AW88395_RCV_MODE_RECEIVER << AW88395_RCV_MODE_START_BIT) 227*14bd8572SWeidong Wang 228*14bd8572SWeidong Wang #define AW88395_DSPBY_START_BIT (2) 229*14bd8572SWeidong Wang #define AW88395_DSPBY_BITS_LEN (1) 230*14bd8572SWeidong Wang #define AW88395_DSPBY_MASK \ 231*14bd8572SWeidong Wang (~(((1<<AW88395_DSPBY_BITS_LEN)-1) << AW88395_DSPBY_START_BIT)) 232*14bd8572SWeidong Wang 233*14bd8572SWeidong Wang #define AW88395_DSPBY_WORKING (0) 234*14bd8572SWeidong Wang #define AW88395_DSPBY_WORKING_VALUE \ 235*14bd8572SWeidong Wang (AW88395_DSPBY_WORKING << AW88395_DSPBY_START_BIT) 236*14bd8572SWeidong Wang 237*14bd8572SWeidong Wang #define AW88395_DSPBY_BYPASS (1) 238*14bd8572SWeidong Wang #define AW88395_DSPBY_BYPASS_VALUE \ 239*14bd8572SWeidong Wang (AW88395_DSPBY_BYPASS << AW88395_DSPBY_START_BIT) 240*14bd8572SWeidong Wang 241*14bd8572SWeidong Wang #define AW88395_AMPPD_START_BIT (1) 242*14bd8572SWeidong Wang #define AW88395_AMPPD_BITS_LEN (1) 243*14bd8572SWeidong Wang #define AW88395_AMPPD_MASK \ 244*14bd8572SWeidong Wang (~(((1<<AW88395_AMPPD_BITS_LEN)-1) << AW88395_AMPPD_START_BIT)) 245*14bd8572SWeidong Wang 246*14bd8572SWeidong Wang #define AW88395_AMPPD_WORKING (0) 247*14bd8572SWeidong Wang #define AW88395_AMPPD_WORKING_VALUE \ 248*14bd8572SWeidong Wang (AW88395_AMPPD_WORKING << AW88395_AMPPD_START_BIT) 249*14bd8572SWeidong Wang 250*14bd8572SWeidong Wang #define AW88395_AMPPD_POWER_DOWN (1) 251*14bd8572SWeidong Wang #define AW88395_AMPPD_POWER_DOWN_VALUE \ 252*14bd8572SWeidong Wang (AW88395_AMPPD_POWER_DOWN << AW88395_AMPPD_START_BIT) 253*14bd8572SWeidong Wang 254*14bd8572SWeidong Wang #define AW88395_PWDN_START_BIT (0) 255*14bd8572SWeidong Wang #define AW88395_PWDN_BITS_LEN (1) 256*14bd8572SWeidong Wang #define AW88395_PWDN_MASK \ 257*14bd8572SWeidong Wang (~(((1<<AW88395_PWDN_BITS_LEN)-1) << AW88395_PWDN_START_BIT)) 258*14bd8572SWeidong Wang 259*14bd8572SWeidong Wang #define AW88395_PWDN_WORKING (0) 260*14bd8572SWeidong Wang #define AW88395_PWDN_WORKING_VALUE \ 261*14bd8572SWeidong Wang (AW88395_PWDN_WORKING << AW88395_PWDN_START_BIT) 262*14bd8572SWeidong Wang 263*14bd8572SWeidong Wang #define AW88395_PWDN_POWER_DOWN (1) 264*14bd8572SWeidong Wang #define AW88395_PWDN_POWER_DOWN_VALUE \ 265*14bd8572SWeidong Wang (AW88395_PWDN_POWER_DOWN << AW88395_PWDN_START_BIT) 266*14bd8572SWeidong Wang 267*14bd8572SWeidong Wang #define AW88395_MUTE_VOL (90 * 8) 268*14bd8572SWeidong Wang #define AW88395_VOLUME_STEP_DB (6 * 8) 269*14bd8572SWeidong Wang 270*14bd8572SWeidong Wang #define AW88395_VOL_6DB_START (6) 271*14bd8572SWeidong Wang #define AW88395_VOL_START_BIT (6) 272*14bd8572SWeidong Wang #define AW88395_VOL_BITS_LEN (10) 273*14bd8572SWeidong Wang #define AW88395_VOL_MASK \ 274*14bd8572SWeidong Wang (~(((1<<AW88395_VOL_BITS_LEN)-1) << AW88395_VOL_START_BIT)) 275*14bd8572SWeidong Wang 276*14bd8572SWeidong Wang #define AW88395_VOL_DEFAULT_VALUE (0) 277*14bd8572SWeidong Wang 278*14bd8572SWeidong Wang #define AW88395_I2STXEN_START_BIT (0) 279*14bd8572SWeidong Wang #define AW88395_I2STXEN_BITS_LEN (1) 280*14bd8572SWeidong Wang #define AW88395_I2STXEN_MASK \ 281*14bd8572SWeidong Wang (~(((1<<AW88395_I2STXEN_BITS_LEN)-1) << AW88395_I2STXEN_START_BIT)) 282*14bd8572SWeidong Wang 283*14bd8572SWeidong Wang #define AW88395_I2STXEN_DISABLE (0) 284*14bd8572SWeidong Wang #define AW88395_I2STXEN_DISABLE_VALUE \ 285*14bd8572SWeidong Wang (AW88395_I2STXEN_DISABLE << AW88395_I2STXEN_START_BIT) 286*14bd8572SWeidong Wang 287*14bd8572SWeidong Wang #define AW88395_I2STXEN_ENABLE (1) 288*14bd8572SWeidong Wang #define AW88395_I2STXEN_ENABLE_VALUE \ 289*14bd8572SWeidong Wang (AW88395_I2STXEN_ENABLE << AW88395_I2STXEN_START_BIT) 290*14bd8572SWeidong Wang 291*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_START_BIT (15) 292*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_BITS_LEN (1) 293*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_MASK \ 294*14bd8572SWeidong Wang (~(((1<<AW88395_AGC_DSP_CTL_BITS_LEN)-1) << AW88395_AGC_DSP_CTL_START_BIT)) 295*14bd8572SWeidong Wang 296*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_DISABLE (0) 297*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_DISABLE_VALUE \ 298*14bd8572SWeidong Wang (AW88395_AGC_DSP_CTL_DISABLE << AW88395_AGC_DSP_CTL_START_BIT) 299*14bd8572SWeidong Wang 300*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_ENABLE (1) 301*14bd8572SWeidong Wang #define AW88395_AGC_DSP_CTL_ENABLE_VALUE \ 302*14bd8572SWeidong Wang (AW88395_AGC_DSP_CTL_ENABLE << AW88395_AGC_DSP_CTL_START_BIT) 303*14bd8572SWeidong Wang 304*14bd8572SWeidong Wang #define AW88395_VDSEL_START_BIT (0) 305*14bd8572SWeidong Wang #define AW88395_VDSEL_BITS_LEN (1) 306*14bd8572SWeidong Wang #define AW88395_VDSEL_MASK \ 307*14bd8572SWeidong Wang (~(((1<<AW88395_VDSEL_BITS_LEN)-1) << AW88395_VDSEL_START_BIT)) 308*14bd8572SWeidong Wang 309*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_START_BIT (3) 310*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_BITS_LEN (1) 311*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_MASK \ 312*14bd8572SWeidong Wang (~(((1<<AW88395_MEM_CLKSEL_BITS_LEN)-1) << AW88395_MEM_CLKSEL_START_BIT)) 313*14bd8572SWeidong Wang 314*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_OSC_CLK (0) 315*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_OSC_CLK_VALUE \ 316*14bd8572SWeidong Wang (AW88395_MEM_CLKSEL_OSC_CLK << AW88395_MEM_CLKSEL_START_BIT) 317*14bd8572SWeidong Wang 318*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_DAP_HCLK (1) 319*14bd8572SWeidong Wang #define AW88395_MEM_CLKSEL_DAP_HCLK_VALUE \ 320*14bd8572SWeidong Wang (AW88395_MEM_CLKSEL_DAP_HCLK << AW88395_MEM_CLKSEL_START_BIT) 321*14bd8572SWeidong Wang 322*14bd8572SWeidong Wang #define AW88395_CCO_MUX_START_BIT (14) 323*14bd8572SWeidong Wang #define AW88395_CCO_MUX_BITS_LEN (1) 324*14bd8572SWeidong Wang #define AW88395_CCO_MUX_MASK \ 325*14bd8572SWeidong Wang (~(((1<<AW88395_CCO_MUX_BITS_LEN)-1) << AW88395_CCO_MUX_START_BIT)) 326*14bd8572SWeidong Wang 327*14bd8572SWeidong Wang #define AW88395_CCO_MUX_DIVIDED (0) 328*14bd8572SWeidong Wang #define AW88395_CCO_MUX_DIVIDED_VALUE \ 329*14bd8572SWeidong Wang (AW88395_CCO_MUX_DIVIDED << AW88395_CCO_MUX_START_BIT) 330*14bd8572SWeidong Wang 331*14bd8572SWeidong Wang #define AW88395_CCO_MUX_BYPASS (1) 332*14bd8572SWeidong Wang #define AW88395_CCO_MUX_BYPASS_VALUE \ 333*14bd8572SWeidong Wang (AW88395_CCO_MUX_BYPASS << AW88395_CCO_MUX_START_BIT) 334*14bd8572SWeidong Wang 335*14bd8572SWeidong Wang #define AW88395_EF_VSN_GESLP_START_BIT (0) 336*14bd8572SWeidong Wang #define AW88395_EF_VSN_GESLP_BITS_LEN (10) 337*14bd8572SWeidong Wang #define AW88395_EF_VSN_GESLP_MASK \ 338*14bd8572SWeidong Wang (~(((1<<AW88395_EF_VSN_GESLP_BITS_LEN)-1) << AW88395_EF_VSN_GESLP_START_BIT)) 339*14bd8572SWeidong Wang 340*14bd8572SWeidong Wang #define AW88395_EF_VSN_GESLP_SIGN_MASK (~(1 << 9)) 341*14bd8572SWeidong Wang #define AW88395_EF_VSN_GESLP_SIGN_NEG (0xfe00) 342*14bd8572SWeidong Wang 343*14bd8572SWeidong Wang #define AW88395_EF_ISN_GESLP_START_BIT (0) 344*14bd8572SWeidong Wang #define AW88395_EF_ISN_GESLP_BITS_LEN (10) 345*14bd8572SWeidong Wang #define AW88395_EF_ISN_GESLP_MASK \ 346*14bd8572SWeidong Wang (~(((1<<AW88395_EF_ISN_GESLP_BITS_LEN)-1) << AW88395_EF_ISN_GESLP_START_BIT)) 347*14bd8572SWeidong Wang 348*14bd8572SWeidong Wang #define AW88395_EF_ISN_GESLP_SIGN_MASK (~(1 << 9)) 349*14bd8572SWeidong Wang #define AW88395_EF_ISN_GESLP_SIGN_NEG (0xfe00) 350*14bd8572SWeidong Wang 351*14bd8572SWeidong Wang #define AW88395_CABL_BASE_VALUE (1000) 352*14bd8572SWeidong Wang #define AW88395_ICABLK_FACTOR (1) 353*14bd8572SWeidong Wang #define AW88395_VCABLK_FACTOR (1) 354*14bd8572SWeidong Wang #define AW88395_VCAL_FACTOR (1 << 12) 355*14bd8572SWeidong Wang #define AW88395_VSCAL_FACTOR (16500) 356*14bd8572SWeidong Wang #define AW88395_ISCAL_FACTOR (3667) 357*14bd8572SWeidong Wang #define AW88395_EF_VSENSE_GAIN_SHIFT (0) 358*14bd8572SWeidong Wang 359*14bd8572SWeidong Wang #define AW88395_VCABLK_FACTOR_DAC (2) 360*14bd8572SWeidong Wang #define AW88395_VSCAL_FACTOR_DAC (11790) 361*14bd8572SWeidong Wang #define AW88395_EF_DAC_GESLP_SHIFT (10) 362*14bd8572SWeidong Wang #define AW88395_EF_DAC_GESLP_SIGN_MASK (1 << 5) 363*14bd8572SWeidong Wang #define AW88395_EF_DAC_GESLP_SIGN_NEG (0xffc0) 364*14bd8572SWeidong Wang 365*14bd8572SWeidong Wang #define AW88395_VCALB_ADJ_FACTOR (12) 366*14bd8572SWeidong Wang 367*14bd8572SWeidong Wang #define AW88395_WDT_CNT_START_BIT (0) 368*14bd8572SWeidong Wang #define AW88395_WDT_CNT_BITS_LEN (8) 369*14bd8572SWeidong Wang #define AW88395_WDT_CNT_MASK \ 370*14bd8572SWeidong Wang (~(((1<<AW88395_WDT_CNT_BITS_LEN)-1) << AW88395_WDT_CNT_START_BIT)) 371*14bd8572SWeidong Wang 372*14bd8572SWeidong Wang #define AW88395_DSP_CFG_ADDR (0x9C80) 373*14bd8572SWeidong Wang #define AW88395_DSP_FW_ADDR (0x8C00) 374*14bd8572SWeidong Wang #define AW88395_DSP_REG_VMAX (0x9C94) 375*14bd8572SWeidong Wang #define AW88395_DSP_REG_CFG_ADPZ_RE (0x9D00) 376*14bd8572SWeidong Wang #define AW88395_DSP_REG_VCALB (0x9CF7) 377*14bd8572SWeidong Wang #define AW88395_DSP_RE_SHIFT (12) 378*14bd8572SWeidong Wang 379*14bd8572SWeidong Wang #define AW88395_DSP_REG_CFG_ADPZ_RA (0x9D02) 380*14bd8572SWeidong Wang #define AW88395_DSP_REG_CRC_ADDR (0x9F42) 381*14bd8572SWeidong Wang #define AW88395_DSP_CALI_F0_DELAY (0x9CFD) 382*14bd8572SWeidong Wang 383*14bd8572SWeidong Wang #endif 384