1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <sound/driver.h> 30 #include <asm/io.h> 31 #include <linux/delay.h> 32 #include <linux/interrupt.h> 33 #include <linux/init.h> 34 #include <linux/pci.h> 35 #include <linux/slab.h> 36 #include <linux/moduleparam.h> 37 #include <sound/core.h> 38 #include <sound/pcm.h> 39 #include <sound/ac97_codec.h> 40 #include <sound/info.h> 41 #include <sound/initval.h> 42 /* for 440MX workaround */ 43 #include <asm/pgtable.h> 44 #include <asm/cacheflush.h> 45 46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 50 "{Intel,82901AB-ICH0}," 51 "{Intel,82801BA-ICH2}," 52 "{Intel,82801CA-ICH3}," 53 "{Intel,82801DB-ICH4}," 54 "{Intel,ICH5}," 55 "{Intel,ICH6}," 56 "{Intel,ICH7}," 57 "{Intel,6300ESB}," 58 "{Intel,ESB2}," 59 "{Intel,MX440}," 60 "{SiS,SI7012}," 61 "{NVidia,nForce Audio}," 62 "{NVidia,nForce2 Audio}," 63 "{AMD,AMD768}," 64 "{AMD,AMD8111}," 65 "{ALI,M5455}}"); 66 67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 70 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; 71 static char *ac97_quirk[SNDRV_CARDS]; 72 static int buggy_irq[SNDRV_CARDS]; 73 static int xbox[SNDRV_CARDS]; 74 75 #ifdef SUPPORT_MIDI 76 static int mpu_port[SNDRV_CARDS]; /* disabled */ 77 #endif 78 79 module_param_array(index, int, NULL, 0444); 80 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 81 module_param_array(id, charp, NULL, 0444); 82 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 83 module_param_array(enable, bool, NULL, 0444); 84 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard."); 85 module_param_array(ac97_clock, int, NULL, 0444); 86 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 87 module_param_array(ac97_quirk, charp, NULL, 0444); 88 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 89 module_param_array(buggy_irq, bool, NULL, 0444); 90 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 91 module_param_array(xbox, bool, NULL, 0444); 92 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 93 94 /* 95 * Direct registers 96 */ 97 98 #ifndef PCI_DEVICE_ID_INTEL_82801 99 #define PCI_DEVICE_ID_INTEL_82801 0x2415 100 #endif 101 #ifndef PCI_DEVICE_ID_INTEL_82901 102 #define PCI_DEVICE_ID_INTEL_82901 0x2425 103 #endif 104 #ifndef PCI_DEVICE_ID_INTEL_82801BA 105 #define PCI_DEVICE_ID_INTEL_82801BA 0x2445 106 #endif 107 #ifndef PCI_DEVICE_ID_INTEL_440MX 108 #define PCI_DEVICE_ID_INTEL_440MX 0x7195 109 #endif 110 #ifndef PCI_DEVICE_ID_INTEL_ICH3 111 #define PCI_DEVICE_ID_INTEL_ICH3 0x2485 112 #endif 113 #ifndef PCI_DEVICE_ID_INTEL_ICH4 114 #define PCI_DEVICE_ID_INTEL_ICH4 0x24c5 115 #endif 116 #ifndef PCI_DEVICE_ID_INTEL_ICH5 117 #define PCI_DEVICE_ID_INTEL_ICH5 0x24d5 118 #endif 119 #ifndef PCI_DEVICE_ID_INTEL_ESB_5 120 #define PCI_DEVICE_ID_INTEL_ESB_5 0x25a6 121 #endif 122 #ifndef PCI_DEVICE_ID_INTEL_ICH6_18 123 #define PCI_DEVICE_ID_INTEL_ICH6_18 0x266e 124 #endif 125 #ifndef PCI_DEVICE_ID_INTEL_ICH7_20 126 #define PCI_DEVICE_ID_INTEL_ICH7_20 0x27de 127 #endif 128 #ifndef PCI_DEVICE_ID_INTEL_ESB2_14 129 #define PCI_DEVICE_ID_INTEL_ESB2_14 0x2698 130 #endif 131 #ifndef PCI_DEVICE_ID_SI_7012 132 #define PCI_DEVICE_ID_SI_7012 0x7012 133 #endif 134 #ifndef PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 135 #define PCI_DEVICE_ID_NVIDIA_MCP_AUDIO 0x01b1 136 #endif 137 #ifndef PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 138 #define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO 0x0059 139 #endif 140 #ifndef PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 141 #define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO 0x006a 142 #endif 143 #ifndef PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 144 #define PCI_DEVICE_ID_NVIDIA_CK8_AUDIO 0x008a 145 #endif 146 #ifndef PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 147 #define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO 0x00da 148 #endif 149 #ifndef PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 150 #define PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO 0x00ea 151 #endif 152 153 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 154 155 #define ICHREG(x) ICH_REG_##x 156 157 #define DEFINE_REGSET(name,base) \ 158 enum { \ 159 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 160 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 161 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 162 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 163 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 164 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 165 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 166 }; 167 168 /* busmaster blocks */ 169 DEFINE_REGSET(OFF, 0); /* offset */ 170 DEFINE_REGSET(PI, 0x00); /* PCM in */ 171 DEFINE_REGSET(PO, 0x10); /* PCM out */ 172 DEFINE_REGSET(MC, 0x20); /* Mic in */ 173 174 /* ICH4 busmaster blocks */ 175 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 176 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 177 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 178 179 /* values for each busmaster block */ 180 181 /* LVI */ 182 #define ICH_REG_LVI_MASK 0x1f 183 184 /* SR */ 185 #define ICH_FIFOE 0x10 /* FIFO error */ 186 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 187 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 188 #define ICH_CELV 0x02 /* current equals last valid */ 189 #define ICH_DCH 0x01 /* DMA controller halted */ 190 191 /* PIV */ 192 #define ICH_REG_PIV_MASK 0x1f /* mask */ 193 194 /* CR */ 195 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 196 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 197 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 198 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 199 #define ICH_STARTBM 0x01 /* start busmaster operation */ 200 201 202 /* global block */ 203 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 204 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 205 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 206 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 207 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 208 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 209 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 210 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */ 211 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 212 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 213 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 214 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 215 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 216 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 217 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 218 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 219 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 220 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 221 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 222 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 223 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 224 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 225 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 226 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 227 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 228 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 229 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 230 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 231 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 232 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 233 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 234 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 235 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 236 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 237 #define ICH_RCS 0x00008000 /* read completion status */ 238 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 239 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 240 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 241 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 242 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 243 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 244 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 245 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 246 #define ICH_POINT 0x00000040 /* playback interrupt */ 247 #define ICH_PIINT 0x00000020 /* capture interrupt */ 248 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 249 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 250 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 251 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 252 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 253 #define ICH_CAS 0x01 /* codec access semaphore */ 254 #define ICH_REG_SDM 0x80 255 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 256 #define ICH_DI2L_SHIFT 6 257 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 258 #define ICH_DI1L_SHIFT 4 259 #define ICH_SE 0x00000008 /* steer enable */ 260 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 261 262 #define ICH_MAX_FRAGS 32 /* max hw frags */ 263 264 265 /* 266 * registers for Ali5455 267 */ 268 269 /* ALi 5455 busmaster blocks */ 270 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 271 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 272 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 273 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 274 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 275 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 276 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 277 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 278 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 279 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 280 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 281 282 enum { 283 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 284 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 285 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 286 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 287 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 288 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 289 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 290 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 291 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 292 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 293 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 294 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 295 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 296 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 297 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 298 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 299 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 300 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 301 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 302 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 303 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 304 }; 305 306 #define ALI_CAS_SEM_BUSY 0x80000000 307 #define ALI_CPR_ADDR_SECONDARY 0x100 308 #define ALI_CPR_ADDR_READ 0x80 309 #define ALI_CSPSR_CODEC_READY 0x08 310 #define ALI_CSPSR_READ_OK 0x02 311 #define ALI_CSPSR_WRITE_OK 0x01 312 313 /* interrupts for the whole chip by interrupt status register finish */ 314 315 #define ALI_INT_MICIN2 (1<<26) 316 #define ALI_INT_PCMIN2 (1<<25) 317 #define ALI_INT_I2SIN (1<<24) 318 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 319 #define ALI_INT_SPDIFIN (1<<22) 320 #define ALI_INT_LFEOUT (1<<21) 321 #define ALI_INT_CENTEROUT (1<<20) 322 #define ALI_INT_CODECSPDIFOUT (1<<19) 323 #define ALI_INT_MICIN (1<<18) 324 #define ALI_INT_PCMOUT (1<<17) 325 #define ALI_INT_PCMIN (1<<16) 326 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 327 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 328 #define ALI_INT_GPIO (1<<1) 329 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 330 331 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 332 #define ICH_ALI_SC_AC97_DBL (1<<30) 333 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 334 #define ICH_ALI_SC_IN_BITS (3<<18) 335 #define ICH_ALI_SC_OUT_BITS (3<<16) 336 #define ICH_ALI_SC_6CH_CFG (3<<14) 337 #define ICH_ALI_SC_PCM_4 (1<<8) 338 #define ICH_ALI_SC_PCM_6 (2<<8) 339 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 340 341 #define ICH_ALI_SS_SEC_ID (3<<5) 342 #define ICH_ALI_SS_PRI_ID (3<<3) 343 344 #define ICH_ALI_IF_AC97SP (1<<21) 345 #define ICH_ALI_IF_MC (1<<20) 346 #define ICH_ALI_IF_PI (1<<19) 347 #define ICH_ALI_IF_MC2 (1<<18) 348 #define ICH_ALI_IF_PI2 (1<<17) 349 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 350 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 351 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 352 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 353 #define ICH_ALI_IF_PO_SPDF (1<<3) 354 #define ICH_ALI_IF_PO (1<<1) 355 356 /* 357 * 358 */ 359 360 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR }; 361 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR }; 362 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT }; 363 364 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data) 365 366 typedef struct { 367 unsigned int ichd; /* ich device number */ 368 unsigned long reg_offset; /* offset to bmaddr */ 369 u32 *bdbar; /* CPU address (32bit) */ 370 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 371 snd_pcm_substream_t *substream; 372 unsigned int physbuf; /* physical address (32bit) */ 373 unsigned int size; 374 unsigned int fragsize; 375 unsigned int fragsize1; 376 unsigned int position; 377 unsigned int pos_shift; 378 int frags; 379 int lvi; 380 int lvi_frag; 381 int civ; 382 int ack; 383 int ack_reload; 384 unsigned int ack_bit; 385 unsigned int roff_sr; 386 unsigned int roff_picb; 387 unsigned int int_sta_mask; /* interrupt status mask */ 388 unsigned int ali_slot; /* ALI DMA slot */ 389 struct ac97_pcm *pcm; 390 int pcm_open_flag; 391 unsigned int page_attr_changed: 1; 392 } ichdev_t; 393 394 typedef struct _snd_intel8x0 intel8x0_t; 395 396 struct _snd_intel8x0 { 397 unsigned int device_type; 398 399 int irq; 400 401 unsigned int mmio; 402 unsigned long addr; 403 void __iomem *remap_addr; 404 unsigned int bm_mmio; 405 unsigned long bmaddr; 406 void __iomem *remap_bmaddr; 407 408 struct pci_dev *pci; 409 snd_card_t *card; 410 411 int pcm_devs; 412 snd_pcm_t *pcm[6]; 413 ichdev_t ichd[6]; 414 415 unsigned multi4: 1, 416 multi6: 1, 417 dra: 1, 418 smp20bit: 1; 419 unsigned in_ac97_init: 1, 420 in_sdin_init: 1; 421 unsigned in_measurement: 1; /* during ac97 clock measurement */ 422 unsigned fix_nocache: 1; /* workaround for 440MX */ 423 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 424 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 425 426 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 427 428 ac97_bus_t *ac97_bus; 429 ac97_t *ac97[3]; 430 unsigned int ac97_sdin[3]; 431 432 spinlock_t reg_lock; 433 434 u32 bdbars_count; 435 struct snd_dma_buffer bdbars; 436 u32 int_sta_reg; /* interrupt status register */ 437 u32 int_sta_mask; /* interrupt status mask */ 438 }; 439 440 static struct pci_device_id snd_intel8x0_ids[] = { 441 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 442 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 443 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 444 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 445 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */ 446 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */ 447 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */ 448 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */ 449 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */ 450 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */ 451 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 452 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */ 453 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 454 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */ 455 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 456 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */ 457 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */ 458 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 459 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */ 460 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 461 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 462 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 463 { 0, } 464 }; 465 466 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 467 468 /* 469 * Lowlevel I/O - busmaster 470 */ 471 472 static u8 igetbyte(intel8x0_t *chip, u32 offset) 473 { 474 if (chip->bm_mmio) 475 return readb(chip->remap_bmaddr + offset); 476 else 477 return inb(chip->bmaddr + offset); 478 } 479 480 static u16 igetword(intel8x0_t *chip, u32 offset) 481 { 482 if (chip->bm_mmio) 483 return readw(chip->remap_bmaddr + offset); 484 else 485 return inw(chip->bmaddr + offset); 486 } 487 488 static u32 igetdword(intel8x0_t *chip, u32 offset) 489 { 490 if (chip->bm_mmio) 491 return readl(chip->remap_bmaddr + offset); 492 else 493 return inl(chip->bmaddr + offset); 494 } 495 496 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val) 497 { 498 if (chip->bm_mmio) 499 writeb(val, chip->remap_bmaddr + offset); 500 else 501 outb(val, chip->bmaddr + offset); 502 } 503 504 static void iputword(intel8x0_t *chip, u32 offset, u16 val) 505 { 506 if (chip->bm_mmio) 507 writew(val, chip->remap_bmaddr + offset); 508 else 509 outw(val, chip->bmaddr + offset); 510 } 511 512 static void iputdword(intel8x0_t *chip, u32 offset, u32 val) 513 { 514 if (chip->bm_mmio) 515 writel(val, chip->remap_bmaddr + offset); 516 else 517 outl(val, chip->bmaddr + offset); 518 } 519 520 /* 521 * Lowlevel I/O - AC'97 registers 522 */ 523 524 static u16 iagetword(intel8x0_t *chip, u32 offset) 525 { 526 if (chip->mmio) 527 return readw(chip->remap_addr + offset); 528 else 529 return inw(chip->addr + offset); 530 } 531 532 static void iaputword(intel8x0_t *chip, u32 offset, u16 val) 533 { 534 if (chip->mmio) 535 writew(val, chip->remap_addr + offset); 536 else 537 outw(val, chip->addr + offset); 538 } 539 540 /* 541 * Basic I/O 542 */ 543 544 /* 545 * access to AC97 codec via normal i/o (for ICH and SIS7012) 546 */ 547 548 /* return the GLOB_STA bit for the corresponding codec */ 549 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec) 550 { 551 static unsigned int codec_bit[3] = { 552 ICH_PCR, ICH_SCR, ICH_TCR 553 }; 554 snd_assert(codec < 3, return ICH_PCR); 555 if (chip->device_type == DEVICE_INTEL_ICH4) 556 codec = chip->ac97_sdin[codec]; 557 return codec_bit[codec]; 558 } 559 560 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec) 561 { 562 int time; 563 564 if (codec > 2) 565 return -EIO; 566 if (chip->in_sdin_init) { 567 /* we don't know the ready bit assignment at the moment */ 568 /* so we check any */ 569 codec = ICH_PCR | ICH_SCR | ICH_TCR; 570 } else { 571 codec = get_ich_codec_bit(chip, codec); 572 } 573 574 /* codec ready ? */ 575 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 576 return -EIO; 577 578 /* Anyone holding a semaphore for 1 msec should be shot... */ 579 time = 100; 580 do { 581 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 582 return 0; 583 udelay(10); 584 } while (time--); 585 586 /* access to some forbidden (non existant) ac97 registers will not 587 * reset the semaphore. So even if you don't get the semaphore, still 588 * continue the access. We don't need the semaphore anyway. */ 589 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 590 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 591 iagetword(chip, 0); /* clear semaphore flag */ 592 /* I don't care about the semaphore */ 593 return -EBUSY; 594 } 595 596 static void snd_intel8x0_codec_write(ac97_t *ac97, 597 unsigned short reg, 598 unsigned short val) 599 { 600 intel8x0_t *chip = ac97->private_data; 601 602 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 603 if (! chip->in_ac97_init) 604 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 605 } 606 iaputword(chip, reg + ac97->num * 0x80, val); 607 } 608 609 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97, 610 unsigned short reg) 611 { 612 intel8x0_t *chip = ac97->private_data; 613 unsigned short res; 614 unsigned int tmp; 615 616 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 617 if (! chip->in_ac97_init) 618 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 619 res = 0xffff; 620 } else { 621 res = iagetword(chip, reg + ac97->num * 0x80); 622 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 623 /* reset RCS and preserve other R/WC bits */ 624 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 625 if (! chip->in_ac97_init) 626 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 627 res = 0xffff; 628 } 629 } 630 return res; 631 } 632 633 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec) 634 { 635 unsigned int tmp; 636 637 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 638 iagetword(chip, codec * 0x80); 639 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 640 /* reset RCS and preserve other R/WC bits */ 641 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 642 } 643 } 644 } 645 646 /* 647 * access to AC97 for Ali5455 648 */ 649 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask) 650 { 651 int count = 0; 652 for (count = 0; count < 0x7f; count++) { 653 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 654 if (val & mask) 655 return 0; 656 } 657 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 658 return -EBUSY; 659 } 660 661 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip) 662 { 663 int time = 100; 664 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 665 udelay(1); 666 if (! time) 667 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 668 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 669 } 670 671 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg) 672 { 673 intel8x0_t *chip = ac97->private_data; 674 unsigned short data = 0xffff; 675 676 if (snd_intel8x0_ali_codec_semaphore(chip)) 677 goto __err; 678 reg |= ALI_CPR_ADDR_READ; 679 if (ac97->num) 680 reg |= ALI_CPR_ADDR_SECONDARY; 681 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 682 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 683 goto __err; 684 data = igetword(chip, ICHREG(ALI_SPR)); 685 __err: 686 return data; 687 } 688 689 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val) 690 { 691 intel8x0_t *chip = ac97->private_data; 692 693 if (snd_intel8x0_ali_codec_semaphore(chip)) 694 return; 695 iputword(chip, ICHREG(ALI_CPR), val); 696 if (ac97->num) 697 reg |= ALI_CPR_ADDR_SECONDARY; 698 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 699 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 700 } 701 702 703 /* 704 * DMA I/O 705 */ 706 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev) 707 { 708 int idx; 709 u32 *bdbar = ichdev->bdbar; 710 unsigned long port = ichdev->reg_offset; 711 712 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 713 if (ichdev->size == ichdev->fragsize) { 714 ichdev->ack_reload = ichdev->ack = 2; 715 ichdev->fragsize1 = ichdev->fragsize >> 1; 716 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 717 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 718 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 719 ichdev->fragsize1 >> ichdev->pos_shift); 720 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 721 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 722 ichdev->fragsize1 >> ichdev->pos_shift); 723 } 724 ichdev->frags = 2; 725 } else { 726 ichdev->ack_reload = ichdev->ack = 1; 727 ichdev->fragsize1 = ichdev->fragsize; 728 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 729 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 730 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 731 ichdev->fragsize >> ichdev->pos_shift); 732 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 733 } 734 ichdev->frags = ichdev->size / ichdev->fragsize; 735 } 736 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 737 ichdev->civ = 0; 738 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 739 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 740 ichdev->position = 0; 741 #if 0 742 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 743 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 744 #endif 745 /* clear interrupts */ 746 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 747 } 748 749 #ifdef __i386__ 750 /* 751 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 752 * which aborts PCI busmaster for audio transfer. A workaround is to set 753 * the pages as non-cached. For details, see the errata in 754 * http://www.intel.com/design/chipsets/specupdt/245051.htm 755 */ 756 static void fill_nocache(void *buf, int size, int nocache) 757 { 758 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 759 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL); 760 global_flush_tlb(); 761 } 762 #else 763 #define fill_nocache(buf,size,nocache) 764 #endif 765 766 /* 767 * Interrupt handler 768 */ 769 770 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev) 771 { 772 unsigned long port = ichdev->reg_offset; 773 int status, civ, i, step; 774 int ack = 0; 775 776 spin_lock(&chip->reg_lock); 777 status = igetbyte(chip, port + ichdev->roff_sr); 778 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 779 if (!(status & ICH_BCIS)) { 780 step = 0; 781 } else if (civ == ichdev->civ) { 782 // snd_printd("civ same %d\n", civ); 783 step = 1; 784 ichdev->civ++; 785 ichdev->civ &= ICH_REG_LVI_MASK; 786 } else { 787 step = civ - ichdev->civ; 788 if (step < 0) 789 step += ICH_REG_LVI_MASK + 1; 790 // if (step != 1) 791 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 792 ichdev->civ = civ; 793 } 794 795 ichdev->position += step * ichdev->fragsize1; 796 if (! chip->in_measurement) 797 ichdev->position %= ichdev->size; 798 ichdev->lvi += step; 799 ichdev->lvi &= ICH_REG_LVI_MASK; 800 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 801 for (i = 0; i < step; i++) { 802 ichdev->lvi_frag++; 803 ichdev->lvi_frag %= ichdev->frags; 804 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 805 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR)); 806 if (--ichdev->ack == 0) { 807 ichdev->ack = ichdev->ack_reload; 808 ack = 1; 809 } 810 } 811 spin_unlock(&chip->reg_lock); 812 if (ack && ichdev->substream) { 813 snd_pcm_period_elapsed(ichdev->substream); 814 } 815 iputbyte(chip, port + ichdev->roff_sr, 816 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 817 } 818 819 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs) 820 { 821 intel8x0_t *chip = dev_id; 822 ichdev_t *ichdev; 823 unsigned int status; 824 unsigned int i; 825 826 status = igetdword(chip, chip->int_sta_reg); 827 if (status == 0xffffffff) /* we are not yet resumed */ 828 return IRQ_NONE; 829 830 if ((status & chip->int_sta_mask) == 0) { 831 if (status) { 832 /* ack */ 833 iputdword(chip, chip->int_sta_reg, status); 834 if (! chip->buggy_irq) 835 status = 0; 836 } 837 return IRQ_RETVAL(status); 838 } 839 840 for (i = 0; i < chip->bdbars_count; i++) { 841 ichdev = &chip->ichd[i]; 842 if (status & ichdev->int_sta_mask) 843 snd_intel8x0_update(chip, ichdev); 844 } 845 846 /* ack them */ 847 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 848 849 return IRQ_HANDLED; 850 } 851 852 /* 853 * PCM part 854 */ 855 856 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 857 { 858 intel8x0_t *chip = snd_pcm_substream_chip(substream); 859 ichdev_t *ichdev = get_ichdev(substream); 860 unsigned char val = 0; 861 unsigned long port = ichdev->reg_offset; 862 863 switch (cmd) { 864 case SNDRV_PCM_TRIGGER_START: 865 case SNDRV_PCM_TRIGGER_RESUME: 866 val = ICH_IOCE | ICH_STARTBM; 867 break; 868 case SNDRV_PCM_TRIGGER_STOP: 869 case SNDRV_PCM_TRIGGER_SUSPEND: 870 val = 0; 871 break; 872 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 873 val = ICH_IOCE; 874 break; 875 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 876 val = ICH_IOCE | ICH_STARTBM; 877 break; 878 default: 879 return -EINVAL; 880 } 881 iputbyte(chip, port + ICH_REG_OFF_CR, val); 882 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 883 /* wait until DMA stopped */ 884 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 885 /* reset whole DMA things */ 886 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 887 } 888 return 0; 889 } 890 891 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd) 892 { 893 intel8x0_t *chip = snd_pcm_substream_chip(substream); 894 ichdev_t *ichdev = get_ichdev(substream); 895 unsigned long port = ichdev->reg_offset; 896 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) }; 897 unsigned int val, fifo; 898 899 val = igetdword(chip, ICHREG(ALI_DMACR)); 900 switch (cmd) { 901 case SNDRV_PCM_TRIGGER_START: 902 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 903 case SNDRV_PCM_TRIGGER_RESUME: 904 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 905 /* clear FIFO for synchronization of channels */ 906 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 907 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 908 fifo |= 0x83 << (ichdev->ali_slot % 4); 909 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 910 } 911 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 912 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 913 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */ 914 break; 915 case SNDRV_PCM_TRIGGER_STOP: 916 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 917 case SNDRV_PCM_TRIGGER_SUSPEND: 918 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */ 919 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 920 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 921 ; 922 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 923 break; 924 /* reset whole DMA things */ 925 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 926 /* clear interrupts */ 927 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 928 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 929 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 930 break; 931 default: 932 return -EINVAL; 933 } 934 return 0; 935 } 936 937 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream, 938 snd_pcm_hw_params_t * hw_params) 939 { 940 intel8x0_t *chip = snd_pcm_substream_chip(substream); 941 ichdev_t *ichdev = get_ichdev(substream); 942 snd_pcm_runtime_t *runtime = substream->runtime; 943 int dbl = params_rate(hw_params) > 48000; 944 int err; 945 946 if (chip->fix_nocache && ichdev->page_attr_changed) { 947 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 948 ichdev->page_attr_changed = 0; 949 } 950 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 951 if (err < 0) 952 return err; 953 if (chip->fix_nocache) { 954 if (runtime->dma_area && ! ichdev->page_attr_changed) { 955 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 956 ichdev->page_attr_changed = 1; 957 } 958 } 959 if (ichdev->pcm_open_flag) { 960 snd_ac97_pcm_close(ichdev->pcm); 961 ichdev->pcm_open_flag = 0; 962 } 963 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 964 params_channels(hw_params), 965 ichdev->pcm->r[dbl].slots); 966 if (err >= 0) { 967 ichdev->pcm_open_flag = 1; 968 /* Force SPDIF setting */ 969 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 970 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params)); 971 } 972 return err; 973 } 974 975 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream) 976 { 977 intel8x0_t *chip = snd_pcm_substream_chip(substream); 978 ichdev_t *ichdev = get_ichdev(substream); 979 980 if (ichdev->pcm_open_flag) { 981 snd_ac97_pcm_close(ichdev->pcm); 982 ichdev->pcm_open_flag = 0; 983 } 984 if (chip->fix_nocache && ichdev->page_attr_changed) { 985 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 986 ichdev->page_attr_changed = 0; 987 } 988 return snd_pcm_lib_free_pages(substream); 989 } 990 991 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip, 992 snd_pcm_runtime_t *runtime) 993 { 994 unsigned int cnt; 995 int dbl = runtime->rate > 48000; 996 switch (chip->device_type) { 997 case DEVICE_ALI: 998 cnt = igetdword(chip, ICHREG(ALI_SCR)); 999 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 1000 if (runtime->channels == 4 || dbl) 1001 cnt |= ICH_ALI_SC_PCM_4; 1002 else if (runtime->channels == 6) 1003 cnt |= ICH_ALI_SC_PCM_6; 1004 iputdword(chip, ICHREG(ALI_SCR), cnt); 1005 break; 1006 case DEVICE_SIS: 1007 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1008 cnt &= ~ICH_SIS_PCM_246_MASK; 1009 if (runtime->channels == 4 || dbl) 1010 cnt |= ICH_SIS_PCM_4; 1011 else if (runtime->channels == 6) 1012 cnt |= ICH_SIS_PCM_6; 1013 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1014 break; 1015 default: 1016 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 1017 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 1018 if (runtime->channels == 4 || dbl) 1019 cnt |= ICH_PCM_4; 1020 else if (runtime->channels == 6) 1021 cnt |= ICH_PCM_6; 1022 if (chip->device_type == DEVICE_NFORCE) { 1023 /* reset to 2ch once to keep the 6 channel data in alignment, 1024 * to start from Front Left always 1025 */ 1026 if (cnt & ICH_PCM_246_MASK) { 1027 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 1028 spin_unlock_irq(&chip->reg_lock); 1029 msleep(50); /* grrr... */ 1030 spin_lock_irq(&chip->reg_lock); 1031 } 1032 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1033 if (runtime->sample_bits > 16) 1034 cnt |= ICH_PCM_20BIT; 1035 } 1036 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1037 break; 1038 } 1039 } 1040 1041 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream) 1042 { 1043 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1044 snd_pcm_runtime_t *runtime = substream->runtime; 1045 ichdev_t *ichdev = get_ichdev(substream); 1046 1047 ichdev->physbuf = runtime->dma_addr; 1048 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1049 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1050 spin_lock_irq(&chip->reg_lock); 1051 if (ichdev->ichd == ICHD_PCMOUT) { 1052 snd_intel8x0_setup_pcm_out(chip, runtime); 1053 if (chip->device_type == DEVICE_INTEL_ICH4) { 1054 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1055 } 1056 } 1057 snd_intel8x0_setup_periods(chip, ichdev); 1058 spin_unlock_irq(&chip->reg_lock); 1059 return 0; 1060 } 1061 1062 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream) 1063 { 1064 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1065 ichdev_t *ichdev = get_ichdev(substream); 1066 size_t ptr1, ptr; 1067 int civ, timeout = 100; 1068 unsigned int position; 1069 1070 spin_lock(&chip->reg_lock); 1071 do { 1072 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1073 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1074 position = ichdev->position; 1075 if (ptr1 == 0) { 1076 udelay(10); 1077 continue; 1078 } 1079 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 1080 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1081 break; 1082 } while (timeout--); 1083 ptr1 <<= ichdev->pos_shift; 1084 ptr = ichdev->fragsize1 - ptr1; 1085 ptr += position; 1086 spin_unlock(&chip->reg_lock); 1087 if (ptr >= ichdev->size) 1088 return 0; 1089 return bytes_to_frames(substream->runtime, ptr); 1090 } 1091 1092 static snd_pcm_hardware_t snd_intel8x0_stream = 1093 { 1094 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1095 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1096 SNDRV_PCM_INFO_MMAP_VALID | 1097 SNDRV_PCM_INFO_PAUSE | 1098 SNDRV_PCM_INFO_RESUME), 1099 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1100 .rates = SNDRV_PCM_RATE_48000, 1101 .rate_min = 48000, 1102 .rate_max = 48000, 1103 .channels_min = 2, 1104 .channels_max = 2, 1105 .buffer_bytes_max = 128 * 1024, 1106 .period_bytes_min = 32, 1107 .period_bytes_max = 128 * 1024, 1108 .periods_min = 1, 1109 .periods_max = 1024, 1110 .fifo_size = 0, 1111 }; 1112 1113 static unsigned int channels4[] = { 1114 2, 4, 1115 }; 1116 1117 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = { 1118 .count = ARRAY_SIZE(channels4), 1119 .list = channels4, 1120 .mask = 0, 1121 }; 1122 1123 static unsigned int channels6[] = { 1124 2, 4, 6, 1125 }; 1126 1127 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = { 1128 .count = ARRAY_SIZE(channels6), 1129 .list = channels6, 1130 .mask = 0, 1131 }; 1132 1133 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev) 1134 { 1135 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1136 snd_pcm_runtime_t *runtime = substream->runtime; 1137 int err; 1138 1139 ichdev->substream = substream; 1140 runtime->hw = snd_intel8x0_stream; 1141 runtime->hw.rates = ichdev->pcm->rates; 1142 snd_pcm_limit_hw_rates(runtime); 1143 if (chip->device_type == DEVICE_SIS) { 1144 runtime->hw.buffer_bytes_max = 64*1024; 1145 runtime->hw.period_bytes_max = 64*1024; 1146 } 1147 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1148 return err; 1149 runtime->private_data = ichdev; 1150 return 0; 1151 } 1152 1153 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream) 1154 { 1155 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1156 snd_pcm_runtime_t *runtime = substream->runtime; 1157 int err; 1158 1159 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1160 if (err < 0) 1161 return err; 1162 1163 if (chip->multi6) { 1164 runtime->hw.channels_max = 6; 1165 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6); 1166 } else if (chip->multi4) { 1167 runtime->hw.channels_max = 4; 1168 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4); 1169 } 1170 if (chip->dra) { 1171 snd_ac97_pcm_double_rate_rules(runtime); 1172 } 1173 if (chip->smp20bit) { 1174 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1175 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1176 } 1177 return 0; 1178 } 1179 1180 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream) 1181 { 1182 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1183 1184 chip->ichd[ICHD_PCMOUT].substream = NULL; 1185 return 0; 1186 } 1187 1188 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream) 1189 { 1190 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1191 1192 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1193 } 1194 1195 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream) 1196 { 1197 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1198 1199 chip->ichd[ICHD_PCMIN].substream = NULL; 1200 return 0; 1201 } 1202 1203 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream) 1204 { 1205 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1206 1207 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1208 } 1209 1210 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream) 1211 { 1212 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1213 1214 chip->ichd[ICHD_MIC].substream = NULL; 1215 return 0; 1216 } 1217 1218 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream) 1219 { 1220 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1221 1222 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1223 } 1224 1225 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream) 1226 { 1227 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1228 1229 chip->ichd[ICHD_MIC2].substream = NULL; 1230 return 0; 1231 } 1232 1233 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream) 1234 { 1235 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1236 1237 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1238 } 1239 1240 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream) 1241 { 1242 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1243 1244 chip->ichd[ICHD_PCM2IN].substream = NULL; 1245 return 0; 1246 } 1247 1248 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream) 1249 { 1250 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1251 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1252 1253 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1254 } 1255 1256 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream) 1257 { 1258 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1259 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1260 1261 chip->ichd[idx].substream = NULL; 1262 return 0; 1263 } 1264 1265 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream) 1266 { 1267 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1268 unsigned int val; 1269 1270 spin_lock_irq(&chip->reg_lock); 1271 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1272 val |= ICH_ALI_IF_AC97SP; 1273 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1274 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1275 spin_unlock_irq(&chip->reg_lock); 1276 1277 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1278 } 1279 1280 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream) 1281 { 1282 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1283 unsigned int val; 1284 1285 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1286 spin_lock_irq(&chip->reg_lock); 1287 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1288 val &= ~ICH_ALI_IF_AC97SP; 1289 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1290 spin_unlock_irq(&chip->reg_lock); 1291 1292 return 0; 1293 } 1294 1295 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream) 1296 { 1297 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1298 1299 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1300 } 1301 1302 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream) 1303 { 1304 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1305 1306 chip->ichd[ALID_SPDIFIN].substream = NULL; 1307 return 0; 1308 } 1309 1310 #if 0 // NYI 1311 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream) 1312 { 1313 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1314 1315 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1316 } 1317 1318 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream) 1319 { 1320 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1321 1322 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1323 return 0; 1324 } 1325 #endif 1326 1327 static snd_pcm_ops_t snd_intel8x0_playback_ops = { 1328 .open = snd_intel8x0_playback_open, 1329 .close = snd_intel8x0_playback_close, 1330 .ioctl = snd_pcm_lib_ioctl, 1331 .hw_params = snd_intel8x0_hw_params, 1332 .hw_free = snd_intel8x0_hw_free, 1333 .prepare = snd_intel8x0_pcm_prepare, 1334 .trigger = snd_intel8x0_pcm_trigger, 1335 .pointer = snd_intel8x0_pcm_pointer, 1336 }; 1337 1338 static snd_pcm_ops_t snd_intel8x0_capture_ops = { 1339 .open = snd_intel8x0_capture_open, 1340 .close = snd_intel8x0_capture_close, 1341 .ioctl = snd_pcm_lib_ioctl, 1342 .hw_params = snd_intel8x0_hw_params, 1343 .hw_free = snd_intel8x0_hw_free, 1344 .prepare = snd_intel8x0_pcm_prepare, 1345 .trigger = snd_intel8x0_pcm_trigger, 1346 .pointer = snd_intel8x0_pcm_pointer, 1347 }; 1348 1349 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = { 1350 .open = snd_intel8x0_mic_open, 1351 .close = snd_intel8x0_mic_close, 1352 .ioctl = snd_pcm_lib_ioctl, 1353 .hw_params = snd_intel8x0_hw_params, 1354 .hw_free = snd_intel8x0_hw_free, 1355 .prepare = snd_intel8x0_pcm_prepare, 1356 .trigger = snd_intel8x0_pcm_trigger, 1357 .pointer = snd_intel8x0_pcm_pointer, 1358 }; 1359 1360 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = { 1361 .open = snd_intel8x0_mic2_open, 1362 .close = snd_intel8x0_mic2_close, 1363 .ioctl = snd_pcm_lib_ioctl, 1364 .hw_params = snd_intel8x0_hw_params, 1365 .hw_free = snd_intel8x0_hw_free, 1366 .prepare = snd_intel8x0_pcm_prepare, 1367 .trigger = snd_intel8x0_pcm_trigger, 1368 .pointer = snd_intel8x0_pcm_pointer, 1369 }; 1370 1371 static snd_pcm_ops_t snd_intel8x0_capture2_ops = { 1372 .open = snd_intel8x0_capture2_open, 1373 .close = snd_intel8x0_capture2_close, 1374 .ioctl = snd_pcm_lib_ioctl, 1375 .hw_params = snd_intel8x0_hw_params, 1376 .hw_free = snd_intel8x0_hw_free, 1377 .prepare = snd_intel8x0_pcm_prepare, 1378 .trigger = snd_intel8x0_pcm_trigger, 1379 .pointer = snd_intel8x0_pcm_pointer, 1380 }; 1381 1382 static snd_pcm_ops_t snd_intel8x0_spdif_ops = { 1383 .open = snd_intel8x0_spdif_open, 1384 .close = snd_intel8x0_spdif_close, 1385 .ioctl = snd_pcm_lib_ioctl, 1386 .hw_params = snd_intel8x0_hw_params, 1387 .hw_free = snd_intel8x0_hw_free, 1388 .prepare = snd_intel8x0_pcm_prepare, 1389 .trigger = snd_intel8x0_pcm_trigger, 1390 .pointer = snd_intel8x0_pcm_pointer, 1391 }; 1392 1393 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = { 1394 .open = snd_intel8x0_playback_open, 1395 .close = snd_intel8x0_playback_close, 1396 .ioctl = snd_pcm_lib_ioctl, 1397 .hw_params = snd_intel8x0_hw_params, 1398 .hw_free = snd_intel8x0_hw_free, 1399 .prepare = snd_intel8x0_pcm_prepare, 1400 .trigger = snd_intel8x0_ali_trigger, 1401 .pointer = snd_intel8x0_pcm_pointer, 1402 }; 1403 1404 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = { 1405 .open = snd_intel8x0_capture_open, 1406 .close = snd_intel8x0_capture_close, 1407 .ioctl = snd_pcm_lib_ioctl, 1408 .hw_params = snd_intel8x0_hw_params, 1409 .hw_free = snd_intel8x0_hw_free, 1410 .prepare = snd_intel8x0_pcm_prepare, 1411 .trigger = snd_intel8x0_ali_trigger, 1412 .pointer = snd_intel8x0_pcm_pointer, 1413 }; 1414 1415 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = { 1416 .open = snd_intel8x0_mic_open, 1417 .close = snd_intel8x0_mic_close, 1418 .ioctl = snd_pcm_lib_ioctl, 1419 .hw_params = snd_intel8x0_hw_params, 1420 .hw_free = snd_intel8x0_hw_free, 1421 .prepare = snd_intel8x0_pcm_prepare, 1422 .trigger = snd_intel8x0_ali_trigger, 1423 .pointer = snd_intel8x0_pcm_pointer, 1424 }; 1425 1426 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = { 1427 .open = snd_intel8x0_ali_ac97spdifout_open, 1428 .close = snd_intel8x0_ali_ac97spdifout_close, 1429 .ioctl = snd_pcm_lib_ioctl, 1430 .hw_params = snd_intel8x0_hw_params, 1431 .hw_free = snd_intel8x0_hw_free, 1432 .prepare = snd_intel8x0_pcm_prepare, 1433 .trigger = snd_intel8x0_ali_trigger, 1434 .pointer = snd_intel8x0_pcm_pointer, 1435 }; 1436 1437 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = { 1438 .open = snd_intel8x0_ali_spdifin_open, 1439 .close = snd_intel8x0_ali_spdifin_close, 1440 .ioctl = snd_pcm_lib_ioctl, 1441 .hw_params = snd_intel8x0_hw_params, 1442 .hw_free = snd_intel8x0_hw_free, 1443 .prepare = snd_intel8x0_pcm_prepare, 1444 .trigger = snd_intel8x0_pcm_trigger, 1445 .pointer = snd_intel8x0_pcm_pointer, 1446 }; 1447 1448 #if 0 // NYI 1449 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = { 1450 .open = snd_intel8x0_ali_spdifout_open, 1451 .close = snd_intel8x0_ali_spdifout_close, 1452 .ioctl = snd_pcm_lib_ioctl, 1453 .hw_params = snd_intel8x0_hw_params, 1454 .hw_free = snd_intel8x0_hw_free, 1455 .prepare = snd_intel8x0_pcm_prepare, 1456 .trigger = snd_intel8x0_pcm_trigger, 1457 .pointer = snd_intel8x0_pcm_pointer, 1458 }; 1459 #endif // NYI 1460 1461 struct ich_pcm_table { 1462 char *suffix; 1463 snd_pcm_ops_t *playback_ops; 1464 snd_pcm_ops_t *capture_ops; 1465 size_t prealloc_size; 1466 size_t prealloc_max_size; 1467 int ac97_idx; 1468 }; 1469 1470 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec) 1471 { 1472 snd_pcm_t *pcm; 1473 int err; 1474 char name[32]; 1475 1476 if (rec->suffix) 1477 sprintf(name, "Intel ICH - %s", rec->suffix); 1478 else 1479 strcpy(name, "Intel ICH"); 1480 err = snd_pcm_new(chip->card, name, device, 1481 rec->playback_ops ? 1 : 0, 1482 rec->capture_ops ? 1 : 0, &pcm); 1483 if (err < 0) 1484 return err; 1485 1486 if (rec->playback_ops) 1487 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1488 if (rec->capture_ops) 1489 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1490 1491 pcm->private_data = chip; 1492 pcm->info_flags = 0; 1493 if (rec->suffix) 1494 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1495 else 1496 strcpy(pcm->name, chip->card->shortname); 1497 chip->pcm[device] = pcm; 1498 1499 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1500 rec->prealloc_size, rec->prealloc_max_size); 1501 1502 return 0; 1503 } 1504 1505 static struct ich_pcm_table intel_pcms[] __devinitdata = { 1506 { 1507 .playback_ops = &snd_intel8x0_playback_ops, 1508 .capture_ops = &snd_intel8x0_capture_ops, 1509 .prealloc_size = 64 * 1024, 1510 .prealloc_max_size = 128 * 1024, 1511 }, 1512 { 1513 .suffix = "MIC ADC", 1514 .capture_ops = &snd_intel8x0_capture_mic_ops, 1515 .prealloc_size = 0, 1516 .prealloc_max_size = 128 * 1024, 1517 .ac97_idx = ICHD_MIC, 1518 }, 1519 { 1520 .suffix = "MIC2 ADC", 1521 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1522 .prealloc_size = 0, 1523 .prealloc_max_size = 128 * 1024, 1524 .ac97_idx = ICHD_MIC2, 1525 }, 1526 { 1527 .suffix = "ADC2", 1528 .capture_ops = &snd_intel8x0_capture2_ops, 1529 .prealloc_size = 0, 1530 .prealloc_max_size = 128 * 1024, 1531 .ac97_idx = ICHD_PCM2IN, 1532 }, 1533 { 1534 .suffix = "IEC958", 1535 .playback_ops = &snd_intel8x0_spdif_ops, 1536 .prealloc_size = 64 * 1024, 1537 .prealloc_max_size = 128 * 1024, 1538 .ac97_idx = ICHD_SPBAR, 1539 }, 1540 }; 1541 1542 static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1543 { 1544 .playback_ops = &snd_intel8x0_playback_ops, 1545 .capture_ops = &snd_intel8x0_capture_ops, 1546 .prealloc_size = 64 * 1024, 1547 .prealloc_max_size = 128 * 1024, 1548 }, 1549 { 1550 .suffix = "MIC ADC", 1551 .capture_ops = &snd_intel8x0_capture_mic_ops, 1552 .prealloc_size = 0, 1553 .prealloc_max_size = 128 * 1024, 1554 .ac97_idx = NVD_MIC, 1555 }, 1556 { 1557 .suffix = "IEC958", 1558 .playback_ops = &snd_intel8x0_spdif_ops, 1559 .prealloc_size = 64 * 1024, 1560 .prealloc_max_size = 128 * 1024, 1561 .ac97_idx = NVD_SPBAR, 1562 }, 1563 }; 1564 1565 static struct ich_pcm_table ali_pcms[] __devinitdata = { 1566 { 1567 .playback_ops = &snd_intel8x0_ali_playback_ops, 1568 .capture_ops = &snd_intel8x0_ali_capture_ops, 1569 .prealloc_size = 64 * 1024, 1570 .prealloc_max_size = 128 * 1024, 1571 }, 1572 { 1573 .suffix = "MIC ADC", 1574 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1575 .prealloc_size = 0, 1576 .prealloc_max_size = 128 * 1024, 1577 .ac97_idx = ALID_MIC, 1578 }, 1579 { 1580 .suffix = "IEC958", 1581 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1582 .capture_ops = &snd_intel8x0_ali_spdifin_ops, 1583 .prealloc_size = 64 * 1024, 1584 .prealloc_max_size = 128 * 1024, 1585 .ac97_idx = ALID_AC97SPDIFOUT, 1586 }, 1587 #if 0 // NYI 1588 { 1589 .suffix = "HW IEC958", 1590 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1591 .prealloc_size = 64 * 1024, 1592 .prealloc_max_size = 128 * 1024, 1593 }, 1594 #endif 1595 }; 1596 1597 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip) 1598 { 1599 int i, tblsize, device, err; 1600 struct ich_pcm_table *tbl, *rec; 1601 1602 switch (chip->device_type) { 1603 case DEVICE_INTEL_ICH4: 1604 tbl = intel_pcms; 1605 tblsize = ARRAY_SIZE(intel_pcms); 1606 break; 1607 case DEVICE_NFORCE: 1608 tbl = nforce_pcms; 1609 tblsize = ARRAY_SIZE(nforce_pcms); 1610 break; 1611 case DEVICE_ALI: 1612 tbl = ali_pcms; 1613 tblsize = ARRAY_SIZE(ali_pcms); 1614 break; 1615 default: 1616 tbl = intel_pcms; 1617 tblsize = 2; 1618 break; 1619 } 1620 1621 device = 0; 1622 for (i = 0; i < tblsize; i++) { 1623 rec = tbl + i; 1624 if (i > 0 && rec->ac97_idx) { 1625 /* activate PCM only when associated AC'97 codec */ 1626 if (! chip->ichd[rec->ac97_idx].pcm) 1627 continue; 1628 } 1629 err = snd_intel8x0_pcm1(chip, device, rec); 1630 if (err < 0) 1631 return err; 1632 device++; 1633 } 1634 1635 chip->pcm_devs = device; 1636 return 0; 1637 } 1638 1639 1640 /* 1641 * Mixer part 1642 */ 1643 1644 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus) 1645 { 1646 intel8x0_t *chip = bus->private_data; 1647 chip->ac97_bus = NULL; 1648 } 1649 1650 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97) 1651 { 1652 intel8x0_t *chip = ac97->private_data; 1653 chip->ac97[ac97->num] = NULL; 1654 } 1655 1656 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1657 /* front PCM */ 1658 { 1659 .exclusive = 1, 1660 .r = { { 1661 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1662 (1 << AC97_SLOT_PCM_RIGHT) | 1663 (1 << AC97_SLOT_PCM_CENTER) | 1664 (1 << AC97_SLOT_PCM_SLEFT) | 1665 (1 << AC97_SLOT_PCM_SRIGHT) | 1666 (1 << AC97_SLOT_LFE) 1667 }, 1668 { 1669 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1670 (1 << AC97_SLOT_PCM_RIGHT) | 1671 (1 << AC97_SLOT_PCM_LEFT_0) | 1672 (1 << AC97_SLOT_PCM_RIGHT_0) 1673 } 1674 } 1675 }, 1676 /* PCM IN #1 */ 1677 { 1678 .stream = 1, 1679 .exclusive = 1, 1680 .r = { { 1681 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1682 (1 << AC97_SLOT_PCM_RIGHT) 1683 } 1684 } 1685 }, 1686 /* MIC IN #1 */ 1687 { 1688 .stream = 1, 1689 .exclusive = 1, 1690 .r = { { 1691 .slots = (1 << AC97_SLOT_MIC) 1692 } 1693 } 1694 }, 1695 /* S/PDIF PCM */ 1696 { 1697 .exclusive = 1, 1698 .spdif = 1, 1699 .r = { { 1700 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1701 (1 << AC97_SLOT_SPDIF_RIGHT2) 1702 } 1703 } 1704 }, 1705 /* PCM IN #2 */ 1706 { 1707 .stream = 1, 1708 .exclusive = 1, 1709 .r = { { 1710 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1711 (1 << AC97_SLOT_PCM_RIGHT) 1712 } 1713 } 1714 }, 1715 /* MIC IN #2 */ 1716 { 1717 .stream = 1, 1718 .exclusive = 1, 1719 .r = { { 1720 .slots = (1 << AC97_SLOT_MIC) 1721 } 1722 } 1723 }, 1724 }; 1725 1726 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1727 { 1728 .subvendor = 0x0e11, 1729 .subdevice = 0x008a, 1730 .name = "Compaq Evo W4000", /* AD1885 */ 1731 .type = AC97_TUNE_HP_ONLY 1732 }, 1733 { 1734 .subvendor = 0x0e11, 1735 .subdevice = 0x00b8, 1736 .name = "Compaq Evo D510C", 1737 .type = AC97_TUNE_HP_ONLY 1738 }, 1739 { 1740 .subvendor = 0x0e11, 1741 .subdevice = 0x0860, 1742 .name = "HP/Compaq nx7010", 1743 .type = AC97_TUNE_MUTE_LED 1744 }, 1745 { 1746 .subvendor = 0x1014, 1747 .subdevice = 0x1f00, 1748 .name = "MS-9128", 1749 .type = AC97_TUNE_ALC_JACK 1750 }, 1751 { 1752 .subvendor = 0x1028, 1753 .subdevice = 0x00d8, 1754 .name = "Dell Precision 530", /* AD1885 */ 1755 .type = AC97_TUNE_HP_ONLY 1756 }, 1757 { 1758 .subvendor = 0x1028, 1759 .subdevice = 0x010d, 1760 .name = "Dell", /* which model? AD1885 */ 1761 .type = AC97_TUNE_HP_ONLY 1762 }, 1763 { 1764 .subvendor = 0x1028, 1765 .subdevice = 0x0126, 1766 .name = "Dell Optiplex GX260", /* AD1981A */ 1767 .type = AC97_TUNE_HP_ONLY 1768 }, 1769 { 1770 .subvendor = 0x1028, 1771 .subdevice = 0x012c, 1772 .name = "Dell Precision 650", /* AD1981A */ 1773 .type = AC97_TUNE_HP_ONLY 1774 }, 1775 { 1776 .subvendor = 0x1028, 1777 .subdevice = 0x012d, 1778 .name = "Dell Precision 450", /* AD1981B*/ 1779 .type = AC97_TUNE_HP_ONLY 1780 }, 1781 { 1782 .subvendor = 0x1028, 1783 .subdevice = 0x0147, 1784 .name = "Dell", /* which model? AD1981B*/ 1785 .type = AC97_TUNE_HP_ONLY 1786 }, 1787 { 1788 .subvendor = 0x1028, 1789 .subdevice = 0x0163, 1790 .name = "Dell Unknown", /* STAC9750/51 */ 1791 .type = AC97_TUNE_HP_ONLY 1792 }, 1793 { 1794 .subvendor = 0x103c, 1795 .subdevice = 0x006d, 1796 .name = "HP zv5000", 1797 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1798 }, 1799 { /* FIXME: which codec? */ 1800 .subvendor = 0x103c, 1801 .subdevice = 0x00c3, 1802 .name = "HP xw6000", 1803 .type = AC97_TUNE_HP_ONLY 1804 }, 1805 { 1806 .subvendor = 0x103c, 1807 .subdevice = 0x088c, 1808 .name = "HP nc8000", 1809 .type = AC97_TUNE_MUTE_LED 1810 }, 1811 { 1812 .subvendor = 0x103c, 1813 .subdevice = 0x0890, 1814 .name = "HP nc6000", 1815 .type = AC97_TUNE_MUTE_LED 1816 }, 1817 { 1818 .subvendor = 0x103c, 1819 .subdevice = 0x129d, 1820 .name = "HP xw8000", 1821 .type = AC97_TUNE_HP_ONLY 1822 }, 1823 { 1824 .subvendor = 0x103c, 1825 .subdevice = 0x12f1, 1826 .name = "HP xw8200", /* AD1981B*/ 1827 .type = AC97_TUNE_HP_ONLY 1828 }, 1829 { 1830 .subvendor = 0x103c, 1831 .subdevice = 0x12f2, 1832 .name = "HP xw6200", 1833 .type = AC97_TUNE_HP_ONLY 1834 }, 1835 { 1836 .subvendor = 0x103c, 1837 .subdevice = 0x3008, 1838 .name = "HP xw4200", /* AD1981B*/ 1839 .type = AC97_TUNE_HP_ONLY 1840 }, 1841 { 1842 .subvendor = 0x104d, 1843 .subdevice = 0x8197, 1844 .name = "Sony S1XP", 1845 .type = AC97_TUNE_INV_EAPD 1846 }, 1847 { 1848 .subvendor = 0x1043, 1849 .subdevice = 0x80f3, 1850 .name = "ASUS ICH5/AD1985", 1851 .type = AC97_TUNE_AD_SHARING 1852 }, 1853 { 1854 .subvendor = 0x10cf, 1855 .subdevice = 0x11c3, 1856 .name = "Fujitsu-Siemens E4010", 1857 .type = AC97_TUNE_HP_ONLY 1858 }, 1859 { 1860 .subvendor = 0x10cf, 1861 .subdevice = 0x1225, 1862 .name = "Fujitsu-Siemens T3010", 1863 .type = AC97_TUNE_HP_ONLY 1864 }, 1865 { 1866 .subvendor = 0x10cf, 1867 .subdevice = 0x1253, 1868 .name = "Fujitsu S6210", /* STAC9750/51 */ 1869 .type = AC97_TUNE_HP_ONLY 1870 }, 1871 { 1872 .subvendor = 0x10f1, 1873 .subdevice = 0x2665, 1874 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1875 .type = AC97_TUNE_HP_ONLY 1876 }, 1877 { 1878 .subvendor = 0x10f1, 1879 .subdevice = 0x2885, 1880 .name = "AMD64 Mobo", /* ALC650 */ 1881 .type = AC97_TUNE_HP_ONLY 1882 }, 1883 { 1884 .subvendor = 0x110a, 1885 .subdevice = 0x0056, 1886 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 1887 .type = AC97_TUNE_HP_ONLY 1888 }, 1889 { 1890 .subvendor = 0x11d4, 1891 .subdevice = 0x5375, 1892 .name = "ADI AD1985 (discrete)", 1893 .type = AC97_TUNE_HP_ONLY 1894 }, 1895 { 1896 .subvendor = 0x1462, 1897 .subdevice = 0x5470, 1898 .name = "MSI P4 ATX 645 Ultra", 1899 .type = AC97_TUNE_HP_ONLY 1900 }, 1901 { 1902 .subvendor = 0x1734, 1903 .subdevice = 0x0088, 1904 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 1905 .type = AC97_TUNE_HP_ONLY 1906 }, 1907 { 1908 .subvendor = 0x8086, 1909 .subdevice = 0x2000, 1910 .mask = 0xfff0, 1911 .name = "Intel ICH5/AD1985", 1912 .type = AC97_TUNE_AD_SHARING 1913 }, 1914 { 1915 .subvendor = 0x8086, 1916 .subdevice = 0x4000, 1917 .mask = 0xfff0, 1918 .name = "Intel ICH5/AD1985", 1919 .type = AC97_TUNE_AD_SHARING 1920 }, 1921 { 1922 .subvendor = 0x8086, 1923 .subdevice = 0x4856, 1924 .name = "Intel D845WN (82801BA)", 1925 .type = AC97_TUNE_SWAP_HP 1926 }, 1927 { 1928 .subvendor = 0x8086, 1929 .subdevice = 0x4d44, 1930 .name = "Intel D850EMV2", /* AD1885 */ 1931 .type = AC97_TUNE_HP_ONLY 1932 }, 1933 { 1934 .subvendor = 0x8086, 1935 .subdevice = 0x4d56, 1936 .name = "Intel ICH/AD1885", 1937 .type = AC97_TUNE_HP_ONLY 1938 }, 1939 { 1940 .subvendor = 0x8086, 1941 .subdevice = 0x6000, 1942 .mask = 0xfff0, 1943 .name = "Intel ICH5/AD1985", 1944 .type = AC97_TUNE_AD_SHARING 1945 }, 1946 { 1947 .subvendor = 0x8086, 1948 .subdevice = 0xe000, 1949 .mask = 0xfff0, 1950 .name = "Intel ICH5/AD1985", 1951 .type = AC97_TUNE_AD_SHARING 1952 }, 1953 #if 0 /* FIXME: this seems wrong on most boards */ 1954 { 1955 .subvendor = 0x8086, 1956 .subdevice = 0xa000, 1957 .mask = 0xfff0, 1958 .name = "Intel ICH5/AD1985", 1959 .type = AC97_TUNE_HP_ONLY 1960 }, 1961 #endif 1962 { } /* terminator */ 1963 }; 1964 1965 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override) 1966 { 1967 ac97_bus_t *pbus; 1968 ac97_template_t ac97; 1969 int err; 1970 unsigned int i, codecs; 1971 unsigned int glob_sta = 0; 1972 ac97_bus_ops_t *ops; 1973 static ac97_bus_ops_t standard_bus_ops = { 1974 .write = snd_intel8x0_codec_write, 1975 .read = snd_intel8x0_codec_read, 1976 }; 1977 static ac97_bus_ops_t ali_bus_ops = { 1978 .write = snd_intel8x0_ali_codec_write, 1979 .read = snd_intel8x0_ali_codec_read, 1980 }; 1981 1982 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 1983 switch (chip->device_type) { 1984 case DEVICE_NFORCE: 1985 chip->spdif_idx = NVD_SPBAR; 1986 break; 1987 case DEVICE_ALI: 1988 chip->spdif_idx = ALID_AC97SPDIFOUT; 1989 break; 1990 case DEVICE_INTEL_ICH4: 1991 chip->spdif_idx = ICHD_SPBAR; 1992 break; 1993 }; 1994 1995 chip->in_ac97_init = 1; 1996 1997 memset(&ac97, 0, sizeof(ac97)); 1998 ac97.private_data = chip; 1999 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2000 ac97.scaps = AC97_SCAP_SKIP_MODEM; 2001 if (chip->xbox) 2002 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2003 if (chip->device_type != DEVICE_ALI) { 2004 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2005 ops = &standard_bus_ops; 2006 if (chip->device_type == DEVICE_INTEL_ICH4) { 2007 codecs = 0; 2008 if (glob_sta & ICH_PCR) 2009 codecs++; 2010 if (glob_sta & ICH_SCR) 2011 codecs++; 2012 if (glob_sta & ICH_TCR) 2013 codecs++; 2014 chip->in_sdin_init = 1; 2015 for (i = 0; i < codecs; i++) { 2016 snd_intel8x0_codec_read_test(chip, i); 2017 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2018 } 2019 chip->in_sdin_init = 0; 2020 } else { 2021 codecs = glob_sta & ICH_SCR ? 2 : 1; 2022 } 2023 } else { 2024 ops = &ali_bus_ops; 2025 codecs = 1; 2026 /* detect the secondary codec */ 2027 for (i = 0; i < 100; i++) { 2028 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2029 if (reg & 0x40) { 2030 codecs = 2; 2031 break; 2032 } 2033 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2034 udelay(1); 2035 } 2036 } 2037 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2038 goto __err; 2039 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2040 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */ 2041 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2042 pbus->clock = ac97_clock; 2043 /* FIXME: my test board doesn't work well with VRA... */ 2044 if (chip->device_type == DEVICE_ALI) 2045 pbus->no_vra = 1; 2046 else 2047 pbus->dra = 1; 2048 chip->ac97_bus = pbus; 2049 2050 ac97.pci = chip->pci; 2051 for (i = 0; i < codecs; i++) { 2052 ac97.num = i; 2053 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2054 if (err != -EACCES) 2055 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2056 if (i == 0) 2057 goto __err; 2058 continue; 2059 } 2060 } 2061 /* tune up the primary codec */ 2062 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2063 /* enable separate SDINs for ICH4 */ 2064 if (chip->device_type == DEVICE_INTEL_ICH4) 2065 pbus->isdin = 1; 2066 /* find the available PCM streams */ 2067 i = ARRAY_SIZE(ac97_pcm_defs); 2068 if (chip->device_type != DEVICE_INTEL_ICH4) 2069 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2070 if (chip->spdif_idx < 0) 2071 i--; /* do not allocate S/PDIF */ 2072 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2073 if (err < 0) 2074 goto __err; 2075 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2076 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2077 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2078 if (chip->spdif_idx >= 0) 2079 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2080 if (chip->device_type == DEVICE_INTEL_ICH4) { 2081 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2082 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2083 } 2084 /* enable separate SDINs for ICH4 */ 2085 if (chip->device_type == DEVICE_INTEL_ICH4) { 2086 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2087 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2088 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2089 if (pcm) { 2090 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2091 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2092 for (i = 1; i < 4; i++) { 2093 if (pcm->r[0].codec[i]) { 2094 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2095 break; 2096 } 2097 } 2098 } else { 2099 tmp &= ~ICH_SE; /* steer disable */ 2100 } 2101 iputbyte(chip, ICHREG(SDM), tmp); 2102 } 2103 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2104 chip->multi4 = 1; 2105 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) 2106 chip->multi6 = 1; 2107 } 2108 if (pbus->pcms[0].r[1].rslots[0]) { 2109 chip->dra = 1; 2110 } 2111 if (chip->device_type == DEVICE_INTEL_ICH4) { 2112 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2113 chip->smp20bit = 1; 2114 } 2115 if (chip->device_type == DEVICE_NFORCE) { 2116 /* 48kHz only */ 2117 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2118 } 2119 if (chip->device_type == DEVICE_INTEL_ICH4) { 2120 /* use slot 10/11 for SPDIF */ 2121 u32 val; 2122 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2123 val |= ICH_PCM_SPDIF_1011; 2124 iputdword(chip, ICHREG(GLOB_CNT), val); 2125 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2126 } 2127 chip->in_ac97_init = 0; 2128 return 0; 2129 2130 __err: 2131 /* clear the cold-reset bit for the next chance */ 2132 if (chip->device_type != DEVICE_ALI) 2133 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2134 return err; 2135 } 2136 2137 2138 /* 2139 * 2140 */ 2141 2142 static void do_ali_reset(intel8x0_t *chip) 2143 { 2144 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2145 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2146 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2147 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2148 iputdword(chip, ICHREG(ALI_INTERFACECR), 2149 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2150 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2151 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2152 } 2153 2154 #define do_delay(chip) do {\ 2155 set_current_state(TASK_UNINTERRUPTIBLE);\ 2156 schedule_timeout(1);\ 2157 } while (0) 2158 2159 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing) 2160 { 2161 unsigned long end_time; 2162 unsigned int cnt, status, nstatus; 2163 2164 /* put logic to right state */ 2165 /* first clear status bits */ 2166 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2167 if (chip->device_type == DEVICE_NFORCE) 2168 status |= ICH_NVSPINT; 2169 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2170 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2171 2172 /* ACLink on, 2 channels */ 2173 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2174 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2175 /* finish cold or do warm reset */ 2176 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2177 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2178 end_time = (jiffies + (HZ / 4)) + 1; 2179 do { 2180 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2181 goto __ok; 2182 do_delay(chip); 2183 } while (time_after_eq(end_time, jiffies)); 2184 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT))); 2185 return -EIO; 2186 2187 __ok: 2188 if (probing) { 2189 /* wait for any codec ready status. 2190 * Once it becomes ready it should remain ready 2191 * as long as we do not disable the ac97 link. 2192 */ 2193 end_time = jiffies + HZ; 2194 do { 2195 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 2196 if (status) 2197 break; 2198 do_delay(chip); 2199 } while (time_after_eq(end_time, jiffies)); 2200 if (! status) { 2201 /* no codec is found */ 2202 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA))); 2203 return -EIO; 2204 } 2205 2206 if (chip->device_type == DEVICE_INTEL_ICH4) 2207 /* ICH4 can have three codecs */ 2208 nstatus = ICH_PCR | ICH_SCR | ICH_TCR; 2209 else 2210 /* others up to two codecs */ 2211 nstatus = ICH_PCR | ICH_SCR; 2212 2213 /* wait for other codecs ready status. */ 2214 end_time = jiffies + HZ / 4; 2215 while (status != nstatus && time_after_eq(end_time, jiffies)) { 2216 do_delay(chip); 2217 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 2218 } 2219 2220 } else { 2221 /* resume phase */ 2222 int i; 2223 status = 0; 2224 for (i = 0; i < 3; i++) 2225 if (chip->ac97[i]) 2226 status |= get_ich_codec_bit(chip, i); 2227 /* wait until all the probed codecs are ready */ 2228 end_time = jiffies + HZ; 2229 do { 2230 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 2231 if (status == nstatus) 2232 break; 2233 do_delay(chip); 2234 } while (time_after_eq(end_time, jiffies)); 2235 } 2236 2237 if (chip->device_type == DEVICE_SIS) { 2238 /* unmute the output on SIS7012 */ 2239 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2240 } 2241 if (chip->device_type == DEVICE_NFORCE) { 2242 /* enable SPDIF interrupt */ 2243 unsigned int val; 2244 pci_read_config_dword(chip->pci, 0x4c, &val); 2245 val |= 0x1000000; 2246 pci_write_config_dword(chip->pci, 0x4c, val); 2247 } 2248 return 0; 2249 } 2250 2251 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing) 2252 { 2253 u32 reg; 2254 int i = 0; 2255 2256 reg = igetdword(chip, ICHREG(ALI_SCR)); 2257 if ((reg & 2) == 0) /* Cold required */ 2258 reg |= 2; 2259 else 2260 reg |= 1; /* Warm */ 2261 reg &= ~0x80000000; /* ACLink on */ 2262 iputdword(chip, ICHREG(ALI_SCR), reg); 2263 2264 for (i = 0; i < HZ / 2; i++) { 2265 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2266 goto __ok; 2267 do_delay(chip); 2268 } 2269 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2270 if (probing) 2271 return -EIO; 2272 2273 __ok: 2274 for (i = 0; i < HZ / 2; i++) { 2275 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2276 if (reg & 0x80) /* primary codec */ 2277 break; 2278 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2279 do_delay(chip); 2280 } 2281 2282 do_ali_reset(chip); 2283 return 0; 2284 } 2285 2286 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing) 2287 { 2288 unsigned int i; 2289 int err; 2290 2291 if (chip->device_type != DEVICE_ALI) { 2292 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2293 return err; 2294 iagetword(chip, 0); /* clear semaphore flag */ 2295 } else { 2296 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2297 return err; 2298 } 2299 2300 /* disable interrupts */ 2301 for (i = 0; i < chip->bdbars_count; i++) 2302 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2303 /* reset channels */ 2304 for (i = 0; i < chip->bdbars_count; i++) 2305 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2306 /* initialize Buffer Descriptor Lists */ 2307 for (i = 0; i < chip->bdbars_count; i++) 2308 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 2309 return 0; 2310 } 2311 2312 static int snd_intel8x0_free(intel8x0_t *chip) 2313 { 2314 unsigned int i; 2315 2316 if (chip->irq < 0) 2317 goto __hw_end; 2318 /* disable interrupts */ 2319 for (i = 0; i < chip->bdbars_count; i++) 2320 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2321 /* reset channels */ 2322 for (i = 0; i < chip->bdbars_count; i++) 2323 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2324 if (chip->device_type == DEVICE_NFORCE) { 2325 /* stop the spdif interrupt */ 2326 unsigned int val; 2327 pci_read_config_dword(chip->pci, 0x4c, &val); 2328 val &= ~0x1000000; 2329 pci_write_config_dword(chip->pci, 0x4c, val); 2330 } 2331 /* --- */ 2332 synchronize_irq(chip->irq); 2333 __hw_end: 2334 if (chip->irq >= 0) 2335 free_irq(chip->irq, (void *)chip); 2336 if (chip->bdbars.area) { 2337 if (chip->fix_nocache) 2338 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2339 snd_dma_free_pages(&chip->bdbars); 2340 } 2341 if (chip->remap_addr) 2342 iounmap(chip->remap_addr); 2343 if (chip->remap_bmaddr) 2344 iounmap(chip->remap_bmaddr); 2345 pci_release_regions(chip->pci); 2346 pci_disable_device(chip->pci); 2347 kfree(chip); 2348 return 0; 2349 } 2350 2351 #ifdef CONFIG_PM 2352 /* 2353 * power management 2354 */ 2355 static int intel8x0_suspend(snd_card_t *card, pm_message_t state) 2356 { 2357 intel8x0_t *chip = card->pm_private_data; 2358 int i; 2359 2360 for (i = 0; i < chip->pcm_devs; i++) 2361 snd_pcm_suspend_all(chip->pcm[i]); 2362 /* clear nocache */ 2363 if (chip->fix_nocache) { 2364 for (i = 0; i < chip->bdbars_count; i++) { 2365 ichdev_t *ichdev = &chip->ichd[i]; 2366 if (ichdev->substream && ichdev->page_attr_changed) { 2367 snd_pcm_runtime_t *runtime = ichdev->substream->runtime; 2368 if (runtime->dma_area) 2369 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2370 } 2371 } 2372 } 2373 for (i = 0; i < 3; i++) 2374 if (chip->ac97[i]) 2375 snd_ac97_suspend(chip->ac97[i]); 2376 pci_disable_device(chip->pci); 2377 return 0; 2378 } 2379 2380 static int intel8x0_resume(snd_card_t *card) 2381 { 2382 intel8x0_t *chip = card->pm_private_data; 2383 int i; 2384 2385 pci_enable_device(chip->pci); 2386 pci_set_master(chip->pci); 2387 snd_intel8x0_chip_init(chip, 0); 2388 2389 /* refill nocache */ 2390 if (chip->fix_nocache) 2391 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2392 2393 for (i = 0; i < 3; i++) 2394 if (chip->ac97[i]) 2395 snd_ac97_resume(chip->ac97[i]); 2396 2397 /* refill nocache */ 2398 if (chip->fix_nocache) { 2399 for (i = 0; i < chip->bdbars_count; i++) { 2400 ichdev_t *ichdev = &chip->ichd[i]; 2401 if (ichdev->substream && ichdev->page_attr_changed) { 2402 snd_pcm_runtime_t *runtime = ichdev->substream->runtime; 2403 if (runtime->dma_area) 2404 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2405 } 2406 } 2407 } 2408 2409 return 0; 2410 } 2411 #endif /* CONFIG_PM */ 2412 2413 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2414 2415 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip) 2416 { 2417 snd_pcm_substream_t *subs; 2418 ichdev_t *ichdev; 2419 unsigned long port; 2420 unsigned long pos, t; 2421 struct timeval start_time, stop_time; 2422 2423 if (chip->ac97_bus->clock != 48000) 2424 return; /* specified in module option */ 2425 2426 subs = chip->pcm[0]->streams[0].substream; 2427 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2428 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n"); 2429 return; 2430 } 2431 ichdev = &chip->ichd[ICHD_PCMOUT]; 2432 ichdev->physbuf = subs->dma_buffer.addr; 2433 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE; 2434 ichdev->substream = NULL; /* don't process interrupts */ 2435 2436 /* set rate */ 2437 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2438 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2439 return; 2440 } 2441 snd_intel8x0_setup_periods(chip, ichdev); 2442 port = ichdev->reg_offset; 2443 spin_lock_irq(&chip->reg_lock); 2444 chip->in_measurement = 1; 2445 /* trigger */ 2446 if (chip->device_type != DEVICE_ALI) 2447 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2448 else { 2449 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2450 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2451 } 2452 do_gettimeofday(&start_time); 2453 spin_unlock_irq(&chip->reg_lock); 2454 set_current_state(TASK_UNINTERRUPTIBLE); 2455 schedule_timeout(HZ / 20); 2456 spin_lock_irq(&chip->reg_lock); 2457 /* check the position */ 2458 pos = ichdev->fragsize1; 2459 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift; 2460 pos += ichdev->position; 2461 chip->in_measurement = 0; 2462 do_gettimeofday(&stop_time); 2463 /* stop */ 2464 if (chip->device_type == DEVICE_ALI) { 2465 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8)); 2466 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2467 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2468 ; 2469 } else { 2470 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2471 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2472 ; 2473 } 2474 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2475 spin_unlock_irq(&chip->reg_lock); 2476 2477 t = stop_time.tv_sec - start_time.tv_sec; 2478 t *= 1000000; 2479 t += stop_time.tv_usec - start_time.tv_usec; 2480 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t); 2481 if (t == 0) { 2482 snd_printk(KERN_ERR "?? calculation error..\n"); 2483 return; 2484 } 2485 pos = (pos / 4) * 1000; 2486 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2487 if (pos < 40000 || pos >= 60000) 2488 /* abnormal value. hw problem? */ 2489 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2490 else if (pos < 47500 || pos > 48500) 2491 /* not 48000Hz, tuning the clock.. */ 2492 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2493 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2494 } 2495 2496 static void snd_intel8x0_proc_read(snd_info_entry_t * entry, 2497 snd_info_buffer_t * buffer) 2498 { 2499 intel8x0_t *chip = entry->private_data; 2500 unsigned int tmp; 2501 2502 snd_iprintf(buffer, "Intel8x0\n\n"); 2503 if (chip->device_type == DEVICE_ALI) 2504 return; 2505 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2506 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2507 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2508 if (chip->device_type == DEVICE_INTEL_ICH4) 2509 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2510 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 2511 tmp & ICH_PCR ? " primary" : "", 2512 tmp & ICH_SCR ? " secondary" : "", 2513 tmp & ICH_TCR ? " tertiary" : "", 2514 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 2515 if (chip->device_type == DEVICE_INTEL_ICH4) 2516 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2517 chip->ac97_sdin[0], 2518 chip->ac97_sdin[1], 2519 chip->ac97_sdin[2]); 2520 } 2521 2522 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip) 2523 { 2524 snd_info_entry_t *entry; 2525 2526 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2527 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read); 2528 } 2529 2530 static int snd_intel8x0_dev_free(snd_device_t *device) 2531 { 2532 intel8x0_t *chip = device->device_data; 2533 return snd_intel8x0_free(chip); 2534 } 2535 2536 struct ich_reg_info { 2537 unsigned int int_sta_mask; 2538 unsigned int offset; 2539 }; 2540 2541 static int __devinit snd_intel8x0_create(snd_card_t * card, 2542 struct pci_dev *pci, 2543 unsigned long device_type, 2544 intel8x0_t ** r_intel8x0) 2545 { 2546 intel8x0_t *chip; 2547 int err; 2548 unsigned int i; 2549 unsigned int int_sta_masks; 2550 ichdev_t *ichdev; 2551 static snd_device_ops_t ops = { 2552 .dev_free = snd_intel8x0_dev_free, 2553 }; 2554 2555 static unsigned int bdbars[] = { 2556 3, /* DEVICE_INTEL */ 2557 6, /* DEVICE_INTEL_ICH4 */ 2558 3, /* DEVICE_SIS */ 2559 6, /* DEVICE_ALI */ 2560 4, /* DEVICE_NFORCE */ 2561 }; 2562 static struct ich_reg_info intel_regs[6] = { 2563 { ICH_PIINT, 0 }, 2564 { ICH_POINT, 0x10 }, 2565 { ICH_MCINT, 0x20 }, 2566 { ICH_M2INT, 0x40 }, 2567 { ICH_P2INT, 0x50 }, 2568 { ICH_SPINT, 0x60 }, 2569 }; 2570 static struct ich_reg_info nforce_regs[4] = { 2571 { ICH_PIINT, 0 }, 2572 { ICH_POINT, 0x10 }, 2573 { ICH_MCINT, 0x20 }, 2574 { ICH_NVSPINT, 0x70 }, 2575 }; 2576 static struct ich_reg_info ali_regs[6] = { 2577 { ALI_INT_PCMIN, 0x40 }, 2578 { ALI_INT_PCMOUT, 0x50 }, 2579 { ALI_INT_MICIN, 0x60 }, 2580 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2581 { ALI_INT_SPDIFIN, 0xa0 }, 2582 { ALI_INT_SPDIFOUT, 0xb0 }, 2583 }; 2584 struct ich_reg_info *tbl; 2585 2586 *r_intel8x0 = NULL; 2587 2588 if ((err = pci_enable_device(pci)) < 0) 2589 return err; 2590 2591 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL); 2592 if (chip == NULL) { 2593 pci_disable_device(pci); 2594 return -ENOMEM; 2595 } 2596 spin_lock_init(&chip->reg_lock); 2597 chip->device_type = device_type; 2598 chip->card = card; 2599 chip->pci = pci; 2600 chip->irq = -1; 2601 2602 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2603 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2604 chip->fix_nocache = 1; /* enable workaround */ 2605 2606 /* some Nforce[2] and ICH boards have problems with IRQ handling. 2607 * Needs to return IRQ_HANDLED for unknown irqs. 2608 */ 2609 if (device_type == DEVICE_NFORCE) 2610 chip->buggy_irq = 1; 2611 2612 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2613 kfree(chip); 2614 pci_disable_device(pci); 2615 return err; 2616 } 2617 2618 if (device_type == DEVICE_ALI) { 2619 /* ALI5455 has no ac97 region */ 2620 chip->bmaddr = pci_resource_start(pci, 0); 2621 goto port_inited; 2622 } 2623 2624 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */ 2625 chip->mmio = 1; 2626 chip->addr = pci_resource_start(pci, 2); 2627 chip->remap_addr = ioremap_nocache(chip->addr, 2628 pci_resource_len(pci, 2)); 2629 if (chip->remap_addr == NULL) { 2630 snd_printk("AC'97 space ioremap problem\n"); 2631 snd_intel8x0_free(chip); 2632 return -EIO; 2633 } 2634 } else { 2635 chip->addr = pci_resource_start(pci, 0); 2636 } 2637 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */ 2638 chip->bm_mmio = 1; 2639 chip->bmaddr = pci_resource_start(pci, 3); 2640 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, 2641 pci_resource_len(pci, 3)); 2642 if (chip->remap_bmaddr == NULL) { 2643 snd_printk("Controller space ioremap problem\n"); 2644 snd_intel8x0_free(chip); 2645 return -EIO; 2646 } 2647 } else { 2648 chip->bmaddr = pci_resource_start(pci, 1); 2649 } 2650 2651 port_inited: 2652 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { 2653 snd_printk("unable to grab IRQ %d\n", pci->irq); 2654 snd_intel8x0_free(chip); 2655 return -EBUSY; 2656 } 2657 chip->irq = pci->irq; 2658 pci_set_master(pci); 2659 synchronize_irq(chip->irq); 2660 2661 chip->bdbars_count = bdbars[device_type]; 2662 2663 /* initialize offsets */ 2664 switch (device_type) { 2665 case DEVICE_NFORCE: 2666 tbl = nforce_regs; 2667 break; 2668 case DEVICE_ALI: 2669 tbl = ali_regs; 2670 break; 2671 default: 2672 tbl = intel_regs; 2673 break; 2674 } 2675 for (i = 0; i < chip->bdbars_count; i++) { 2676 ichdev = &chip->ichd[i]; 2677 ichdev->ichd = i; 2678 ichdev->reg_offset = tbl[i].offset; 2679 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2680 if (device_type == DEVICE_SIS) { 2681 /* SiS 7012 swaps the registers */ 2682 ichdev->roff_sr = ICH_REG_OFF_PICB; 2683 ichdev->roff_picb = ICH_REG_OFF_SR; 2684 } else { 2685 ichdev->roff_sr = ICH_REG_OFF_SR; 2686 ichdev->roff_picb = ICH_REG_OFF_PICB; 2687 } 2688 if (device_type == DEVICE_ALI) 2689 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 2690 /* SIS7012 handles the pcm data in bytes, others are in samples */ 2691 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 2692 } 2693 2694 /* allocate buffer descriptor lists */ 2695 /* the start of each lists must be aligned to 8 bytes */ 2696 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2697 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 2698 &chip->bdbars) < 0) { 2699 snd_intel8x0_free(chip); 2700 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 2701 return -ENOMEM; 2702 } 2703 /* tables must be aligned to 8 bytes here, but the kernel pages 2704 are much bigger, so we don't care (on i386) */ 2705 /* workaround for 440MX */ 2706 if (chip->fix_nocache) 2707 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2708 int_sta_masks = 0; 2709 for (i = 0; i < chip->bdbars_count; i++) { 2710 ichdev = &chip->ichd[i]; 2711 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 2712 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 2713 int_sta_masks |= ichdev->int_sta_mask; 2714 } 2715 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 2716 chip->int_sta_mask = int_sta_masks; 2717 2718 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 2719 snd_intel8x0_free(chip); 2720 return err; 2721 } 2722 2723 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip); 2724 2725 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2726 snd_intel8x0_free(chip); 2727 return err; 2728 } 2729 2730 snd_card_set_dev(card, &pci->dev); 2731 2732 *r_intel8x0 = chip; 2733 return 0; 2734 } 2735 2736 static struct shortname_table { 2737 unsigned int id; 2738 const char *s; 2739 } shortnames[] __devinitdata = { 2740 { PCI_DEVICE_ID_INTEL_82801, "Intel 82801AA-ICH" }, 2741 { PCI_DEVICE_ID_INTEL_82901, "Intel 82901AB-ICH0" }, 2742 { PCI_DEVICE_ID_INTEL_82801BA, "Intel 82801BA-ICH2" }, 2743 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 2744 { PCI_DEVICE_ID_INTEL_ICH3, "Intel 82801CA-ICH3" }, 2745 { PCI_DEVICE_ID_INTEL_ICH4, "Intel 82801DB-ICH4" }, 2746 { PCI_DEVICE_ID_INTEL_ICH5, "Intel ICH5" }, 2747 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 2748 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 2749 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 2750 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 2751 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 2752 { PCI_DEVICE_ID_NVIDIA_MCP_AUDIO, "NVidia nForce" }, 2753 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 2754 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 2755 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 2756 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 2757 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 2758 { 0x003a, "NVidia MCP04" }, 2759 { 0x746d, "AMD AMD8111" }, 2760 { 0x7445, "AMD AMD768" }, 2761 { 0x5455, "ALi M5455" }, 2762 { 0, NULL }, 2763 }; 2764 2765 static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 2766 const struct pci_device_id *pci_id) 2767 { 2768 static int dev; 2769 snd_card_t *card; 2770 intel8x0_t *chip; 2771 int err; 2772 struct shortname_table *name; 2773 2774 if (dev >= SNDRV_CARDS) 2775 return -ENODEV; 2776 if (!enable[dev]) { 2777 dev++; 2778 return -ENOENT; 2779 } 2780 2781 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2782 if (card == NULL) 2783 return -ENOMEM; 2784 2785 switch (pci_id->driver_data) { 2786 case DEVICE_NFORCE: 2787 strcpy(card->driver, "NFORCE"); 2788 break; 2789 case DEVICE_INTEL_ICH4: 2790 strcpy(card->driver, "ICH4"); 2791 break; 2792 default: 2793 strcpy(card->driver, "ICH"); 2794 break; 2795 } 2796 2797 strcpy(card->shortname, "Intel ICH"); 2798 for (name = shortnames; name->id; name++) { 2799 if (pci->device == name->id) { 2800 strcpy(card->shortname, name->s); 2801 break; 2802 } 2803 } 2804 2805 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, &chip)) < 0) { 2806 snd_card_free(card); 2807 return err; 2808 } 2809 if (buggy_irq[dev]) 2810 chip->buggy_irq = 1; 2811 if (xbox[dev]) 2812 chip->xbox = 1; 2813 2814 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) { 2815 snd_card_free(card); 2816 return err; 2817 } 2818 if ((err = snd_intel8x0_pcm(chip)) < 0) { 2819 snd_card_free(card); 2820 return err; 2821 } 2822 2823 snd_intel8x0_proc_init(chip); 2824 2825 snprintf(card->longname, sizeof(card->longname), 2826 "%s with %s at %#lx, irq %i", card->shortname, 2827 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq); 2828 2829 if (! ac97_clock[dev]) 2830 intel8x0_measure_ac97_clock(chip); 2831 2832 if ((err = snd_card_register(card)) < 0) { 2833 snd_card_free(card); 2834 return err; 2835 } 2836 pci_set_drvdata(pci, card); 2837 dev++; 2838 return 0; 2839 } 2840 2841 static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 2842 { 2843 snd_card_free(pci_get_drvdata(pci)); 2844 pci_set_drvdata(pci, NULL); 2845 } 2846 2847 static struct pci_driver driver = { 2848 .name = "Intel ICH", 2849 .id_table = snd_intel8x0_ids, 2850 .probe = snd_intel8x0_probe, 2851 .remove = __devexit_p(snd_intel8x0_remove), 2852 SND_PCI_PM_CALLBACKS 2853 }; 2854 2855 2856 static int __init alsa_card_intel8x0_init(void) 2857 { 2858 return pci_register_driver(&driver); 2859 } 2860 2861 static void __exit alsa_card_intel8x0_exit(void) 2862 { 2863 pci_unregister_driver(&driver); 2864 } 2865 2866 module_init(alsa_card_intel8x0_init) 2867 module_exit(alsa_card_intel8x0_exit) 2868