1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <sound/driver.h> 30 #include <asm/io.h> 31 #include <linux/delay.h> 32 #include <linux/interrupt.h> 33 #include <linux/init.h> 34 #include <linux/pci.h> 35 #include <linux/slab.h> 36 #include <linux/moduleparam.h> 37 #include <sound/core.h> 38 #include <sound/pcm.h> 39 #include <sound/ac97_codec.h> 40 #include <sound/info.h> 41 #include <sound/initval.h> 42 /* for 440MX workaround */ 43 #include <asm/pgtable.h> 44 #include <asm/cacheflush.h> 45 46 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>"); 47 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 50 "{Intel,82901AB-ICH0}," 51 "{Intel,82801BA-ICH2}," 52 "{Intel,82801CA-ICH3}," 53 "{Intel,82801DB-ICH4}," 54 "{Intel,ICH5}," 55 "{Intel,ICH6}," 56 "{Intel,ICH7}," 57 "{Intel,6300ESB}," 58 "{Intel,ESB2}," 59 "{Intel,MX440}," 60 "{SiS,SI7012}," 61 "{NVidia,nForce Audio}," 62 "{NVidia,nForce2 Audio}," 63 "{AMD,AMD768}," 64 "{AMD,AMD8111}," 65 "{ALI,M5455}}"); 66 67 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 68 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 69 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 70 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 0}; 71 static char *ac97_quirk[SNDRV_CARDS]; 72 static int buggy_semaphore[SNDRV_CARDS]; 73 static int buggy_irq[SNDRV_CARDS]; 74 static int xbox[SNDRV_CARDS]; 75 76 #ifdef SUPPORT_MIDI 77 static int mpu_port[SNDRV_CARDS]; /* disabled */ 78 #endif 79 80 module_param_array(index, int, NULL, 0444); 81 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 82 module_param_array(id, charp, NULL, 0444); 83 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 84 module_param_array(enable, bool, NULL, 0444); 85 MODULE_PARM_DESC(enable, "Enable Intel i8x0 soundcard."); 86 module_param_array(ac97_clock, int, NULL, 0444); 87 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 88 module_param_array(ac97_quirk, charp, NULL, 0444); 89 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 90 module_param_array(buggy_semaphore, bool, NULL, 0444); 91 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 92 module_param_array(buggy_irq, bool, NULL, 0444); 93 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 94 module_param_array(xbox, bool, NULL, 0444); 95 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 96 97 /* 98 * Direct registers 99 */ 100 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 101 102 #define ICHREG(x) ICH_REG_##x 103 104 #define DEFINE_REGSET(name,base) \ 105 enum { \ 106 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 107 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 108 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 109 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 110 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 111 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 112 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 113 }; 114 115 /* busmaster blocks */ 116 DEFINE_REGSET(OFF, 0); /* offset */ 117 DEFINE_REGSET(PI, 0x00); /* PCM in */ 118 DEFINE_REGSET(PO, 0x10); /* PCM out */ 119 DEFINE_REGSET(MC, 0x20); /* Mic in */ 120 121 /* ICH4 busmaster blocks */ 122 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 123 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 124 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 125 126 /* values for each busmaster block */ 127 128 /* LVI */ 129 #define ICH_REG_LVI_MASK 0x1f 130 131 /* SR */ 132 #define ICH_FIFOE 0x10 /* FIFO error */ 133 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 134 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 135 #define ICH_CELV 0x02 /* current equals last valid */ 136 #define ICH_DCH 0x01 /* DMA controller halted */ 137 138 /* PIV */ 139 #define ICH_REG_PIV_MASK 0x1f /* mask */ 140 141 /* CR */ 142 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 143 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 144 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 145 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 146 #define ICH_STARTBM 0x01 /* start busmaster operation */ 147 148 149 /* global block */ 150 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 151 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 152 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 153 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 154 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 155 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 156 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 157 #define ICH_PCM_246_MASK 0x00300000 /* 6 channels (not all chips) */ 158 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 159 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 160 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 161 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 162 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 163 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 164 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 165 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 166 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 167 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 168 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 169 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 170 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 171 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 172 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 173 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 174 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 175 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 176 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 177 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 178 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 179 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 180 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 181 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 182 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 183 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 184 #define ICH_RCS 0x00008000 /* read completion status */ 185 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 186 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 187 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 188 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 189 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 190 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 191 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 192 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 193 #define ICH_POINT 0x00000040 /* playback interrupt */ 194 #define ICH_PIINT 0x00000020 /* capture interrupt */ 195 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 196 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 197 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 198 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 199 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 200 #define ICH_CAS 0x01 /* codec access semaphore */ 201 #define ICH_REG_SDM 0x80 202 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 203 #define ICH_DI2L_SHIFT 6 204 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 205 #define ICH_DI1L_SHIFT 4 206 #define ICH_SE 0x00000008 /* steer enable */ 207 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 208 209 #define ICH_MAX_FRAGS 32 /* max hw frags */ 210 211 212 /* 213 * registers for Ali5455 214 */ 215 216 /* ALi 5455 busmaster blocks */ 217 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 218 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 219 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 220 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 221 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 222 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 223 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 224 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 225 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 226 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 227 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 228 229 enum { 230 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 231 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 232 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 233 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 234 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 235 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 236 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 237 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 238 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 239 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 240 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 241 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 242 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 243 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 244 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 245 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 246 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 247 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 248 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 249 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 250 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 251 }; 252 253 #define ALI_CAS_SEM_BUSY 0x80000000 254 #define ALI_CPR_ADDR_SECONDARY 0x100 255 #define ALI_CPR_ADDR_READ 0x80 256 #define ALI_CSPSR_CODEC_READY 0x08 257 #define ALI_CSPSR_READ_OK 0x02 258 #define ALI_CSPSR_WRITE_OK 0x01 259 260 /* interrupts for the whole chip by interrupt status register finish */ 261 262 #define ALI_INT_MICIN2 (1<<26) 263 #define ALI_INT_PCMIN2 (1<<25) 264 #define ALI_INT_I2SIN (1<<24) 265 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 266 #define ALI_INT_SPDIFIN (1<<22) 267 #define ALI_INT_LFEOUT (1<<21) 268 #define ALI_INT_CENTEROUT (1<<20) 269 #define ALI_INT_CODECSPDIFOUT (1<<19) 270 #define ALI_INT_MICIN (1<<18) 271 #define ALI_INT_PCMOUT (1<<17) 272 #define ALI_INT_PCMIN (1<<16) 273 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 274 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 275 #define ALI_INT_GPIO (1<<1) 276 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 277 278 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 279 #define ICH_ALI_SC_AC97_DBL (1<<30) 280 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 281 #define ICH_ALI_SC_IN_BITS (3<<18) 282 #define ICH_ALI_SC_OUT_BITS (3<<16) 283 #define ICH_ALI_SC_6CH_CFG (3<<14) 284 #define ICH_ALI_SC_PCM_4 (1<<8) 285 #define ICH_ALI_SC_PCM_6 (2<<8) 286 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 287 288 #define ICH_ALI_SS_SEC_ID (3<<5) 289 #define ICH_ALI_SS_PRI_ID (3<<3) 290 291 #define ICH_ALI_IF_AC97SP (1<<21) 292 #define ICH_ALI_IF_MC (1<<20) 293 #define ICH_ALI_IF_PI (1<<19) 294 #define ICH_ALI_IF_MC2 (1<<18) 295 #define ICH_ALI_IF_PI2 (1<<17) 296 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 297 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 298 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 299 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 300 #define ICH_ALI_IF_PO_SPDF (1<<3) 301 #define ICH_ALI_IF_PO (1<<1) 302 303 /* 304 * 305 */ 306 307 enum { ICHD_PCMIN, ICHD_PCMOUT, ICHD_MIC, ICHD_MIC2, ICHD_PCM2IN, ICHD_SPBAR, ICHD_LAST = ICHD_SPBAR }; 308 enum { NVD_PCMIN, NVD_PCMOUT, NVD_MIC, NVD_SPBAR, NVD_LAST = NVD_SPBAR }; 309 enum { ALID_PCMIN, ALID_PCMOUT, ALID_MIC, ALID_AC97SPDIFOUT, ALID_SPDIFIN, ALID_SPDIFOUT, ALID_LAST = ALID_SPDIFOUT }; 310 311 #define get_ichdev(substream) (ichdev_t *)(substream->runtime->private_data) 312 313 typedef struct { 314 unsigned int ichd; /* ich device number */ 315 unsigned long reg_offset; /* offset to bmaddr */ 316 u32 *bdbar; /* CPU address (32bit) */ 317 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 318 snd_pcm_substream_t *substream; 319 unsigned int physbuf; /* physical address (32bit) */ 320 unsigned int size; 321 unsigned int fragsize; 322 unsigned int fragsize1; 323 unsigned int position; 324 unsigned int pos_shift; 325 int frags; 326 int lvi; 327 int lvi_frag; 328 int civ; 329 int ack; 330 int ack_reload; 331 unsigned int ack_bit; 332 unsigned int roff_sr; 333 unsigned int roff_picb; 334 unsigned int int_sta_mask; /* interrupt status mask */ 335 unsigned int ali_slot; /* ALI DMA slot */ 336 struct ac97_pcm *pcm; 337 int pcm_open_flag; 338 unsigned int page_attr_changed: 1; 339 unsigned int suspended: 1; 340 } ichdev_t; 341 342 typedef struct _snd_intel8x0 intel8x0_t; 343 344 struct _snd_intel8x0 { 345 unsigned int device_type; 346 347 int irq; 348 349 unsigned int mmio; 350 unsigned long addr; 351 void __iomem *remap_addr; 352 unsigned int bm_mmio; 353 unsigned long bmaddr; 354 void __iomem *remap_bmaddr; 355 356 struct pci_dev *pci; 357 snd_card_t *card; 358 359 int pcm_devs; 360 snd_pcm_t *pcm[6]; 361 ichdev_t ichd[6]; 362 363 unsigned multi4: 1, 364 multi6: 1, 365 dra: 1, 366 smp20bit: 1; 367 unsigned in_ac97_init: 1, 368 in_sdin_init: 1; 369 unsigned in_measurement: 1; /* during ac97 clock measurement */ 370 unsigned fix_nocache: 1; /* workaround for 440MX */ 371 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 372 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 373 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 374 375 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 376 unsigned int sdm_saved; /* SDM reg value */ 377 378 ac97_bus_t *ac97_bus; 379 ac97_t *ac97[3]; 380 unsigned int ac97_sdin[3]; 381 382 spinlock_t reg_lock; 383 384 u32 bdbars_count; 385 struct snd_dma_buffer bdbars; 386 u32 int_sta_reg; /* interrupt status register */ 387 u32 int_sta_mask; /* interrupt status mask */ 388 }; 389 390 static struct pci_device_id snd_intel8x0_ids[] = { 391 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 392 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 393 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 394 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 395 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */ 396 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */ 397 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */ 398 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */ 399 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */ 400 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */ 401 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 402 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */ 403 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 404 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */ 405 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 406 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */ 407 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */ 408 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 409 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */ 410 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 411 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 412 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 413 { 0, } 414 }; 415 416 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 417 418 /* 419 * Lowlevel I/O - busmaster 420 */ 421 422 static u8 igetbyte(intel8x0_t *chip, u32 offset) 423 { 424 if (chip->bm_mmio) 425 return readb(chip->remap_bmaddr + offset); 426 else 427 return inb(chip->bmaddr + offset); 428 } 429 430 static u16 igetword(intel8x0_t *chip, u32 offset) 431 { 432 if (chip->bm_mmio) 433 return readw(chip->remap_bmaddr + offset); 434 else 435 return inw(chip->bmaddr + offset); 436 } 437 438 static u32 igetdword(intel8x0_t *chip, u32 offset) 439 { 440 if (chip->bm_mmio) 441 return readl(chip->remap_bmaddr + offset); 442 else 443 return inl(chip->bmaddr + offset); 444 } 445 446 static void iputbyte(intel8x0_t *chip, u32 offset, u8 val) 447 { 448 if (chip->bm_mmio) 449 writeb(val, chip->remap_bmaddr + offset); 450 else 451 outb(val, chip->bmaddr + offset); 452 } 453 454 static void iputword(intel8x0_t *chip, u32 offset, u16 val) 455 { 456 if (chip->bm_mmio) 457 writew(val, chip->remap_bmaddr + offset); 458 else 459 outw(val, chip->bmaddr + offset); 460 } 461 462 static void iputdword(intel8x0_t *chip, u32 offset, u32 val) 463 { 464 if (chip->bm_mmio) 465 writel(val, chip->remap_bmaddr + offset); 466 else 467 outl(val, chip->bmaddr + offset); 468 } 469 470 /* 471 * Lowlevel I/O - AC'97 registers 472 */ 473 474 static u16 iagetword(intel8x0_t *chip, u32 offset) 475 { 476 if (chip->mmio) 477 return readw(chip->remap_addr + offset); 478 else 479 return inw(chip->addr + offset); 480 } 481 482 static void iaputword(intel8x0_t *chip, u32 offset, u16 val) 483 { 484 if (chip->mmio) 485 writew(val, chip->remap_addr + offset); 486 else 487 outw(val, chip->addr + offset); 488 } 489 490 /* 491 * Basic I/O 492 */ 493 494 /* 495 * access to AC97 codec via normal i/o (for ICH and SIS7012) 496 */ 497 498 /* return the GLOB_STA bit for the corresponding codec */ 499 static unsigned int get_ich_codec_bit(intel8x0_t *chip, unsigned int codec) 500 { 501 static unsigned int codec_bit[3] = { 502 ICH_PCR, ICH_SCR, ICH_TCR 503 }; 504 snd_assert(codec < 3, return ICH_PCR); 505 if (chip->device_type == DEVICE_INTEL_ICH4) 506 codec = chip->ac97_sdin[codec]; 507 return codec_bit[codec]; 508 } 509 510 static int snd_intel8x0_codec_semaphore(intel8x0_t *chip, unsigned int codec) 511 { 512 int time; 513 514 if (codec > 2) 515 return -EIO; 516 if (chip->in_sdin_init) { 517 /* we don't know the ready bit assignment at the moment */ 518 /* so we check any */ 519 codec = ICH_PCR | ICH_SCR | ICH_TCR; 520 } else { 521 codec = get_ich_codec_bit(chip, codec); 522 } 523 524 /* codec ready ? */ 525 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 526 return -EIO; 527 528 if (chip->buggy_semaphore) 529 return 0; /* just ignore ... */ 530 531 /* Anyone holding a semaphore for 1 msec should be shot... */ 532 time = 100; 533 do { 534 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 535 return 0; 536 udelay(10); 537 } while (time--); 538 539 /* access to some forbidden (non existant) ac97 registers will not 540 * reset the semaphore. So even if you don't get the semaphore, still 541 * continue the access. We don't need the semaphore anyway. */ 542 snd_printk("codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 543 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 544 iagetword(chip, 0); /* clear semaphore flag */ 545 /* I don't care about the semaphore */ 546 return -EBUSY; 547 } 548 549 static void snd_intel8x0_codec_write(ac97_t *ac97, 550 unsigned short reg, 551 unsigned short val) 552 { 553 intel8x0_t *chip = ac97->private_data; 554 555 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 556 if (! chip->in_ac97_init) 557 snd_printk("codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 558 } 559 iaputword(chip, reg + ac97->num * 0x80, val); 560 } 561 562 static unsigned short snd_intel8x0_codec_read(ac97_t *ac97, 563 unsigned short reg) 564 { 565 intel8x0_t *chip = ac97->private_data; 566 unsigned short res; 567 unsigned int tmp; 568 569 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 570 if (! chip->in_ac97_init) 571 snd_printk("codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 572 res = 0xffff; 573 } else { 574 res = iagetword(chip, reg + ac97->num * 0x80); 575 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 576 /* reset RCS and preserve other R/WC bits */ 577 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 578 if (! chip->in_ac97_init) 579 snd_printk("codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 580 res = 0xffff; 581 } 582 } 583 return res; 584 } 585 586 static void snd_intel8x0_codec_read_test(intel8x0_t *chip, unsigned int codec) 587 { 588 unsigned int tmp; 589 590 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 591 iagetword(chip, codec * 0x80); 592 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 593 /* reset RCS and preserve other R/WC bits */ 594 iputdword(chip, ICHREG(GLOB_STA), tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 595 } 596 } 597 } 598 599 /* 600 * access to AC97 for Ali5455 601 */ 602 static int snd_intel8x0_ali_codec_ready(intel8x0_t *chip, int mask) 603 { 604 int count = 0; 605 for (count = 0; count < 0x7f; count++) { 606 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 607 if (val & mask) 608 return 0; 609 } 610 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 611 return -EBUSY; 612 } 613 614 static int snd_intel8x0_ali_codec_semaphore(intel8x0_t *chip) 615 { 616 int time = 100; 617 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 618 udelay(1); 619 if (! time) 620 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 621 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 622 } 623 624 static unsigned short snd_intel8x0_ali_codec_read(ac97_t *ac97, unsigned short reg) 625 { 626 intel8x0_t *chip = ac97->private_data; 627 unsigned short data = 0xffff; 628 629 if (snd_intel8x0_ali_codec_semaphore(chip)) 630 goto __err; 631 reg |= ALI_CPR_ADDR_READ; 632 if (ac97->num) 633 reg |= ALI_CPR_ADDR_SECONDARY; 634 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 635 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 636 goto __err; 637 data = igetword(chip, ICHREG(ALI_SPR)); 638 __err: 639 return data; 640 } 641 642 static void snd_intel8x0_ali_codec_write(ac97_t *ac97, unsigned short reg, unsigned short val) 643 { 644 intel8x0_t *chip = ac97->private_data; 645 646 if (snd_intel8x0_ali_codec_semaphore(chip)) 647 return; 648 iputword(chip, ICHREG(ALI_CPR), val); 649 if (ac97->num) 650 reg |= ALI_CPR_ADDR_SECONDARY; 651 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 652 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 653 } 654 655 656 /* 657 * DMA I/O 658 */ 659 static void snd_intel8x0_setup_periods(intel8x0_t *chip, ichdev_t *ichdev) 660 { 661 int idx; 662 u32 *bdbar = ichdev->bdbar; 663 unsigned long port = ichdev->reg_offset; 664 665 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 666 if (ichdev->size == ichdev->fragsize) { 667 ichdev->ack_reload = ichdev->ack = 2; 668 ichdev->fragsize1 = ichdev->fragsize >> 1; 669 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 670 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 671 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 672 ichdev->fragsize1 >> ichdev->pos_shift); 673 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 674 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 675 ichdev->fragsize1 >> ichdev->pos_shift); 676 } 677 ichdev->frags = 2; 678 } else { 679 ichdev->ack_reload = ichdev->ack = 1; 680 ichdev->fragsize1 = ichdev->fragsize; 681 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 682 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 683 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 684 ichdev->fragsize >> ichdev->pos_shift); 685 // printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 686 } 687 ichdev->frags = ichdev->size / ichdev->fragsize; 688 } 689 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 690 ichdev->civ = 0; 691 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 692 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 693 ichdev->position = 0; 694 #if 0 695 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 696 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 697 #endif 698 /* clear interrupts */ 699 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 700 } 701 702 #ifdef __i386__ 703 /* 704 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 705 * which aborts PCI busmaster for audio transfer. A workaround is to set 706 * the pages as non-cached. For details, see the errata in 707 * http://www.intel.com/design/chipsets/specupdt/245051.htm 708 */ 709 static void fill_nocache(void *buf, int size, int nocache) 710 { 711 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 712 change_page_attr(virt_to_page(buf), size, nocache ? PAGE_KERNEL_NOCACHE : PAGE_KERNEL); 713 global_flush_tlb(); 714 } 715 #else 716 #define fill_nocache(buf,size,nocache) 717 #endif 718 719 /* 720 * Interrupt handler 721 */ 722 723 static inline void snd_intel8x0_update(intel8x0_t *chip, ichdev_t *ichdev) 724 { 725 unsigned long port = ichdev->reg_offset; 726 int status, civ, i, step; 727 int ack = 0; 728 729 spin_lock(&chip->reg_lock); 730 status = igetbyte(chip, port + ichdev->roff_sr); 731 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 732 if (!(status & ICH_BCIS)) { 733 step = 0; 734 } else if (civ == ichdev->civ) { 735 // snd_printd("civ same %d\n", civ); 736 step = 1; 737 ichdev->civ++; 738 ichdev->civ &= ICH_REG_LVI_MASK; 739 } else { 740 step = civ - ichdev->civ; 741 if (step < 0) 742 step += ICH_REG_LVI_MASK + 1; 743 // if (step != 1) 744 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 745 ichdev->civ = civ; 746 } 747 748 ichdev->position += step * ichdev->fragsize1; 749 if (! chip->in_measurement) 750 ichdev->position %= ichdev->size; 751 ichdev->lvi += step; 752 ichdev->lvi &= ICH_REG_LVI_MASK; 753 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 754 for (i = 0; i < step; i++) { 755 ichdev->lvi_frag++; 756 ichdev->lvi_frag %= ichdev->frags; 757 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 758 // printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), inl(port + 4), inb(port + ICH_REG_OFF_CR)); 759 if (--ichdev->ack == 0) { 760 ichdev->ack = ichdev->ack_reload; 761 ack = 1; 762 } 763 } 764 spin_unlock(&chip->reg_lock); 765 if (ack && ichdev->substream) { 766 snd_pcm_period_elapsed(ichdev->substream); 767 } 768 iputbyte(chip, port + ichdev->roff_sr, 769 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 770 } 771 772 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id, struct pt_regs *regs) 773 { 774 intel8x0_t *chip = dev_id; 775 ichdev_t *ichdev; 776 unsigned int status; 777 unsigned int i; 778 779 status = igetdword(chip, chip->int_sta_reg); 780 if (status == 0xffffffff) /* we are not yet resumed */ 781 return IRQ_NONE; 782 783 if ((status & chip->int_sta_mask) == 0) { 784 if (status) { 785 /* ack */ 786 iputdword(chip, chip->int_sta_reg, status); 787 if (! chip->buggy_irq) 788 status = 0; 789 } 790 return IRQ_RETVAL(status); 791 } 792 793 for (i = 0; i < chip->bdbars_count; i++) { 794 ichdev = &chip->ichd[i]; 795 if (status & ichdev->int_sta_mask) 796 snd_intel8x0_update(chip, ichdev); 797 } 798 799 /* ack them */ 800 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 801 802 return IRQ_HANDLED; 803 } 804 805 /* 806 * PCM part 807 */ 808 809 static int snd_intel8x0_pcm_trigger(snd_pcm_substream_t *substream, int cmd) 810 { 811 intel8x0_t *chip = snd_pcm_substream_chip(substream); 812 ichdev_t *ichdev = get_ichdev(substream); 813 unsigned char val = 0; 814 unsigned long port = ichdev->reg_offset; 815 816 switch (cmd) { 817 case SNDRV_PCM_TRIGGER_RESUME: 818 ichdev->suspended = 0; 819 /* fallthru */ 820 case SNDRV_PCM_TRIGGER_START: 821 val = ICH_IOCE | ICH_STARTBM; 822 break; 823 case SNDRV_PCM_TRIGGER_SUSPEND: 824 ichdev->suspended = 1; 825 /* fallthru */ 826 case SNDRV_PCM_TRIGGER_STOP: 827 val = 0; 828 break; 829 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 830 val = ICH_IOCE; 831 break; 832 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 833 val = ICH_IOCE | ICH_STARTBM; 834 break; 835 default: 836 return -EINVAL; 837 } 838 iputbyte(chip, port + ICH_REG_OFF_CR, val); 839 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 840 /* wait until DMA stopped */ 841 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 842 /* reset whole DMA things */ 843 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 844 } 845 return 0; 846 } 847 848 static int snd_intel8x0_ali_trigger(snd_pcm_substream_t *substream, int cmd) 849 { 850 intel8x0_t *chip = snd_pcm_substream_chip(substream); 851 ichdev_t *ichdev = get_ichdev(substream); 852 unsigned long port = ichdev->reg_offset; 853 static int fiforeg[] = { ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) }; 854 unsigned int val, fifo; 855 856 val = igetdword(chip, ICHREG(ALI_DMACR)); 857 switch (cmd) { 858 case SNDRV_PCM_TRIGGER_RESUME: 859 ichdev->suspended = 0; 860 /* fallthru */ 861 case SNDRV_PCM_TRIGGER_START: 862 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 863 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 864 /* clear FIFO for synchronization of channels */ 865 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 866 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 867 fifo |= 0x83 << (ichdev->ali_slot % 4); 868 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 869 } 870 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 871 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 872 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); /* start DMA */ 873 break; 874 case SNDRV_PCM_TRIGGER_SUSPEND: 875 ichdev->suspended = 1; 876 /* fallthru */ 877 case SNDRV_PCM_TRIGGER_STOP: 878 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 879 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); /* pause */ 880 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 881 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 882 ; 883 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 884 break; 885 /* reset whole DMA things */ 886 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 887 /* clear interrupts */ 888 iputbyte(chip, port + ICH_REG_OFF_SR, igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 889 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 890 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 891 break; 892 default: 893 return -EINVAL; 894 } 895 return 0; 896 } 897 898 static int snd_intel8x0_hw_params(snd_pcm_substream_t * substream, 899 snd_pcm_hw_params_t * hw_params) 900 { 901 intel8x0_t *chip = snd_pcm_substream_chip(substream); 902 ichdev_t *ichdev = get_ichdev(substream); 903 snd_pcm_runtime_t *runtime = substream->runtime; 904 int dbl = params_rate(hw_params) > 48000; 905 int err; 906 907 if (chip->fix_nocache && ichdev->page_attr_changed) { 908 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 909 ichdev->page_attr_changed = 0; 910 } 911 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 912 if (err < 0) 913 return err; 914 if (chip->fix_nocache) { 915 if (runtime->dma_area && ! ichdev->page_attr_changed) { 916 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 917 ichdev->page_attr_changed = 1; 918 } 919 } 920 if (ichdev->pcm_open_flag) { 921 snd_ac97_pcm_close(ichdev->pcm); 922 ichdev->pcm_open_flag = 0; 923 } 924 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 925 params_channels(hw_params), 926 ichdev->pcm->r[dbl].slots); 927 if (err >= 0) { 928 ichdev->pcm_open_flag = 1; 929 /* Force SPDIF setting */ 930 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 931 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, params_rate(hw_params)); 932 } 933 return err; 934 } 935 936 static int snd_intel8x0_hw_free(snd_pcm_substream_t * substream) 937 { 938 intel8x0_t *chip = snd_pcm_substream_chip(substream); 939 ichdev_t *ichdev = get_ichdev(substream); 940 941 if (ichdev->pcm_open_flag) { 942 snd_ac97_pcm_close(ichdev->pcm); 943 ichdev->pcm_open_flag = 0; 944 } 945 if (chip->fix_nocache && ichdev->page_attr_changed) { 946 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 947 ichdev->page_attr_changed = 0; 948 } 949 return snd_pcm_lib_free_pages(substream); 950 } 951 952 static void snd_intel8x0_setup_pcm_out(intel8x0_t *chip, 953 snd_pcm_runtime_t *runtime) 954 { 955 unsigned int cnt; 956 int dbl = runtime->rate > 48000; 957 958 spin_lock_irq(&chip->reg_lock); 959 switch (chip->device_type) { 960 case DEVICE_ALI: 961 cnt = igetdword(chip, ICHREG(ALI_SCR)); 962 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 963 if (runtime->channels == 4 || dbl) 964 cnt |= ICH_ALI_SC_PCM_4; 965 else if (runtime->channels == 6) 966 cnt |= ICH_ALI_SC_PCM_6; 967 iputdword(chip, ICHREG(ALI_SCR), cnt); 968 break; 969 case DEVICE_SIS: 970 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 971 cnt &= ~ICH_SIS_PCM_246_MASK; 972 if (runtime->channels == 4 || dbl) 973 cnt |= ICH_SIS_PCM_4; 974 else if (runtime->channels == 6) 975 cnt |= ICH_SIS_PCM_6; 976 iputdword(chip, ICHREG(GLOB_CNT), cnt); 977 break; 978 default: 979 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 980 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 981 if (runtime->channels == 4 || dbl) 982 cnt |= ICH_PCM_4; 983 else if (runtime->channels == 6) 984 cnt |= ICH_PCM_6; 985 if (chip->device_type == DEVICE_NFORCE) { 986 /* reset to 2ch once to keep the 6 channel data in alignment, 987 * to start from Front Left always 988 */ 989 if (cnt & ICH_PCM_246_MASK) { 990 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 991 spin_unlock_irq(&chip->reg_lock); 992 msleep(50); /* grrr... */ 993 spin_lock_irq(&chip->reg_lock); 994 } 995 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 996 if (runtime->sample_bits > 16) 997 cnt |= ICH_PCM_20BIT; 998 } 999 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1000 break; 1001 } 1002 spin_unlock_irq(&chip->reg_lock); 1003 } 1004 1005 static int snd_intel8x0_pcm_prepare(snd_pcm_substream_t * substream) 1006 { 1007 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1008 snd_pcm_runtime_t *runtime = substream->runtime; 1009 ichdev_t *ichdev = get_ichdev(substream); 1010 1011 ichdev->physbuf = runtime->dma_addr; 1012 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1013 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1014 if (ichdev->ichd == ICHD_PCMOUT) { 1015 snd_intel8x0_setup_pcm_out(chip, runtime); 1016 if (chip->device_type == DEVICE_INTEL_ICH4) 1017 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1018 } 1019 snd_intel8x0_setup_periods(chip, ichdev); 1020 return 0; 1021 } 1022 1023 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(snd_pcm_substream_t * substream) 1024 { 1025 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1026 ichdev_t *ichdev = get_ichdev(substream); 1027 size_t ptr1, ptr; 1028 int civ, timeout = 100; 1029 unsigned int position; 1030 1031 spin_lock(&chip->reg_lock); 1032 do { 1033 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1034 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1035 position = ichdev->position; 1036 if (ptr1 == 0) { 1037 udelay(10); 1038 continue; 1039 } 1040 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 1041 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1042 break; 1043 } while (timeout--); 1044 ptr1 <<= ichdev->pos_shift; 1045 ptr = ichdev->fragsize1 - ptr1; 1046 ptr += position; 1047 spin_unlock(&chip->reg_lock); 1048 if (ptr >= ichdev->size) 1049 return 0; 1050 return bytes_to_frames(substream->runtime, ptr); 1051 } 1052 1053 static snd_pcm_hardware_t snd_intel8x0_stream = 1054 { 1055 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1056 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1057 SNDRV_PCM_INFO_MMAP_VALID | 1058 SNDRV_PCM_INFO_PAUSE | 1059 SNDRV_PCM_INFO_RESUME), 1060 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1061 .rates = SNDRV_PCM_RATE_48000, 1062 .rate_min = 48000, 1063 .rate_max = 48000, 1064 .channels_min = 2, 1065 .channels_max = 2, 1066 .buffer_bytes_max = 128 * 1024, 1067 .period_bytes_min = 32, 1068 .period_bytes_max = 128 * 1024, 1069 .periods_min = 1, 1070 .periods_max = 1024, 1071 .fifo_size = 0, 1072 }; 1073 1074 static unsigned int channels4[] = { 1075 2, 4, 1076 }; 1077 1078 static snd_pcm_hw_constraint_list_t hw_constraints_channels4 = { 1079 .count = ARRAY_SIZE(channels4), 1080 .list = channels4, 1081 .mask = 0, 1082 }; 1083 1084 static unsigned int channels6[] = { 1085 2, 4, 6, 1086 }; 1087 1088 static snd_pcm_hw_constraint_list_t hw_constraints_channels6 = { 1089 .count = ARRAY_SIZE(channels6), 1090 .list = channels6, 1091 .mask = 0, 1092 }; 1093 1094 static int snd_intel8x0_pcm_open(snd_pcm_substream_t * substream, ichdev_t *ichdev) 1095 { 1096 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1097 snd_pcm_runtime_t *runtime = substream->runtime; 1098 int err; 1099 1100 ichdev->substream = substream; 1101 runtime->hw = snd_intel8x0_stream; 1102 runtime->hw.rates = ichdev->pcm->rates; 1103 snd_pcm_limit_hw_rates(runtime); 1104 if (chip->device_type == DEVICE_SIS) { 1105 runtime->hw.buffer_bytes_max = 64*1024; 1106 runtime->hw.period_bytes_max = 64*1024; 1107 } 1108 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1109 return err; 1110 runtime->private_data = ichdev; 1111 return 0; 1112 } 1113 1114 static int snd_intel8x0_playback_open(snd_pcm_substream_t * substream) 1115 { 1116 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1117 snd_pcm_runtime_t *runtime = substream->runtime; 1118 int err; 1119 1120 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1121 if (err < 0) 1122 return err; 1123 1124 if (chip->multi6) { 1125 runtime->hw.channels_max = 6; 1126 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels6); 1127 } else if (chip->multi4) { 1128 runtime->hw.channels_max = 4; 1129 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, &hw_constraints_channels4); 1130 } 1131 if (chip->dra) { 1132 snd_ac97_pcm_double_rate_rules(runtime); 1133 } 1134 if (chip->smp20bit) { 1135 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1136 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1137 } 1138 return 0; 1139 } 1140 1141 static int snd_intel8x0_playback_close(snd_pcm_substream_t * substream) 1142 { 1143 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1144 1145 chip->ichd[ICHD_PCMOUT].substream = NULL; 1146 return 0; 1147 } 1148 1149 static int snd_intel8x0_capture_open(snd_pcm_substream_t * substream) 1150 { 1151 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1152 1153 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1154 } 1155 1156 static int snd_intel8x0_capture_close(snd_pcm_substream_t * substream) 1157 { 1158 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1159 1160 chip->ichd[ICHD_PCMIN].substream = NULL; 1161 return 0; 1162 } 1163 1164 static int snd_intel8x0_mic_open(snd_pcm_substream_t * substream) 1165 { 1166 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1167 1168 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1169 } 1170 1171 static int snd_intel8x0_mic_close(snd_pcm_substream_t * substream) 1172 { 1173 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1174 1175 chip->ichd[ICHD_MIC].substream = NULL; 1176 return 0; 1177 } 1178 1179 static int snd_intel8x0_mic2_open(snd_pcm_substream_t * substream) 1180 { 1181 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1182 1183 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1184 } 1185 1186 static int snd_intel8x0_mic2_close(snd_pcm_substream_t * substream) 1187 { 1188 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1189 1190 chip->ichd[ICHD_MIC2].substream = NULL; 1191 return 0; 1192 } 1193 1194 static int snd_intel8x0_capture2_open(snd_pcm_substream_t * substream) 1195 { 1196 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1197 1198 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1199 } 1200 1201 static int snd_intel8x0_capture2_close(snd_pcm_substream_t * substream) 1202 { 1203 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1204 1205 chip->ichd[ICHD_PCM2IN].substream = NULL; 1206 return 0; 1207 } 1208 1209 static int snd_intel8x0_spdif_open(snd_pcm_substream_t * substream) 1210 { 1211 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1212 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1213 1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1215 } 1216 1217 static int snd_intel8x0_spdif_close(snd_pcm_substream_t * substream) 1218 { 1219 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1220 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1221 1222 chip->ichd[idx].substream = NULL; 1223 return 0; 1224 } 1225 1226 static int snd_intel8x0_ali_ac97spdifout_open(snd_pcm_substream_t * substream) 1227 { 1228 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1229 unsigned int val; 1230 1231 spin_lock_irq(&chip->reg_lock); 1232 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1233 val |= ICH_ALI_IF_AC97SP; 1234 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1235 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1236 spin_unlock_irq(&chip->reg_lock); 1237 1238 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1239 } 1240 1241 static int snd_intel8x0_ali_ac97spdifout_close(snd_pcm_substream_t * substream) 1242 { 1243 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1244 unsigned int val; 1245 1246 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1247 spin_lock_irq(&chip->reg_lock); 1248 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1249 val &= ~ICH_ALI_IF_AC97SP; 1250 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1251 spin_unlock_irq(&chip->reg_lock); 1252 1253 return 0; 1254 } 1255 1256 static int snd_intel8x0_ali_spdifin_open(snd_pcm_substream_t * substream) 1257 { 1258 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1259 1260 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1261 } 1262 1263 static int snd_intel8x0_ali_spdifin_close(snd_pcm_substream_t * substream) 1264 { 1265 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1266 1267 chip->ichd[ALID_SPDIFIN].substream = NULL; 1268 return 0; 1269 } 1270 1271 #if 0 // NYI 1272 static int snd_intel8x0_ali_spdifout_open(snd_pcm_substream_t * substream) 1273 { 1274 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1275 1276 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1277 } 1278 1279 static int snd_intel8x0_ali_spdifout_close(snd_pcm_substream_t * substream) 1280 { 1281 intel8x0_t *chip = snd_pcm_substream_chip(substream); 1282 1283 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1284 return 0; 1285 } 1286 #endif 1287 1288 static snd_pcm_ops_t snd_intel8x0_playback_ops = { 1289 .open = snd_intel8x0_playback_open, 1290 .close = snd_intel8x0_playback_close, 1291 .ioctl = snd_pcm_lib_ioctl, 1292 .hw_params = snd_intel8x0_hw_params, 1293 .hw_free = snd_intel8x0_hw_free, 1294 .prepare = snd_intel8x0_pcm_prepare, 1295 .trigger = snd_intel8x0_pcm_trigger, 1296 .pointer = snd_intel8x0_pcm_pointer, 1297 }; 1298 1299 static snd_pcm_ops_t snd_intel8x0_capture_ops = { 1300 .open = snd_intel8x0_capture_open, 1301 .close = snd_intel8x0_capture_close, 1302 .ioctl = snd_pcm_lib_ioctl, 1303 .hw_params = snd_intel8x0_hw_params, 1304 .hw_free = snd_intel8x0_hw_free, 1305 .prepare = snd_intel8x0_pcm_prepare, 1306 .trigger = snd_intel8x0_pcm_trigger, 1307 .pointer = snd_intel8x0_pcm_pointer, 1308 }; 1309 1310 static snd_pcm_ops_t snd_intel8x0_capture_mic_ops = { 1311 .open = snd_intel8x0_mic_open, 1312 .close = snd_intel8x0_mic_close, 1313 .ioctl = snd_pcm_lib_ioctl, 1314 .hw_params = snd_intel8x0_hw_params, 1315 .hw_free = snd_intel8x0_hw_free, 1316 .prepare = snd_intel8x0_pcm_prepare, 1317 .trigger = snd_intel8x0_pcm_trigger, 1318 .pointer = snd_intel8x0_pcm_pointer, 1319 }; 1320 1321 static snd_pcm_ops_t snd_intel8x0_capture_mic2_ops = { 1322 .open = snd_intel8x0_mic2_open, 1323 .close = snd_intel8x0_mic2_close, 1324 .ioctl = snd_pcm_lib_ioctl, 1325 .hw_params = snd_intel8x0_hw_params, 1326 .hw_free = snd_intel8x0_hw_free, 1327 .prepare = snd_intel8x0_pcm_prepare, 1328 .trigger = snd_intel8x0_pcm_trigger, 1329 .pointer = snd_intel8x0_pcm_pointer, 1330 }; 1331 1332 static snd_pcm_ops_t snd_intel8x0_capture2_ops = { 1333 .open = snd_intel8x0_capture2_open, 1334 .close = snd_intel8x0_capture2_close, 1335 .ioctl = snd_pcm_lib_ioctl, 1336 .hw_params = snd_intel8x0_hw_params, 1337 .hw_free = snd_intel8x0_hw_free, 1338 .prepare = snd_intel8x0_pcm_prepare, 1339 .trigger = snd_intel8x0_pcm_trigger, 1340 .pointer = snd_intel8x0_pcm_pointer, 1341 }; 1342 1343 static snd_pcm_ops_t snd_intel8x0_spdif_ops = { 1344 .open = snd_intel8x0_spdif_open, 1345 .close = snd_intel8x0_spdif_close, 1346 .ioctl = snd_pcm_lib_ioctl, 1347 .hw_params = snd_intel8x0_hw_params, 1348 .hw_free = snd_intel8x0_hw_free, 1349 .prepare = snd_intel8x0_pcm_prepare, 1350 .trigger = snd_intel8x0_pcm_trigger, 1351 .pointer = snd_intel8x0_pcm_pointer, 1352 }; 1353 1354 static snd_pcm_ops_t snd_intel8x0_ali_playback_ops = { 1355 .open = snd_intel8x0_playback_open, 1356 .close = snd_intel8x0_playback_close, 1357 .ioctl = snd_pcm_lib_ioctl, 1358 .hw_params = snd_intel8x0_hw_params, 1359 .hw_free = snd_intel8x0_hw_free, 1360 .prepare = snd_intel8x0_pcm_prepare, 1361 .trigger = snd_intel8x0_ali_trigger, 1362 .pointer = snd_intel8x0_pcm_pointer, 1363 }; 1364 1365 static snd_pcm_ops_t snd_intel8x0_ali_capture_ops = { 1366 .open = snd_intel8x0_capture_open, 1367 .close = snd_intel8x0_capture_close, 1368 .ioctl = snd_pcm_lib_ioctl, 1369 .hw_params = snd_intel8x0_hw_params, 1370 .hw_free = snd_intel8x0_hw_free, 1371 .prepare = snd_intel8x0_pcm_prepare, 1372 .trigger = snd_intel8x0_ali_trigger, 1373 .pointer = snd_intel8x0_pcm_pointer, 1374 }; 1375 1376 static snd_pcm_ops_t snd_intel8x0_ali_capture_mic_ops = { 1377 .open = snd_intel8x0_mic_open, 1378 .close = snd_intel8x0_mic_close, 1379 .ioctl = snd_pcm_lib_ioctl, 1380 .hw_params = snd_intel8x0_hw_params, 1381 .hw_free = snd_intel8x0_hw_free, 1382 .prepare = snd_intel8x0_pcm_prepare, 1383 .trigger = snd_intel8x0_ali_trigger, 1384 .pointer = snd_intel8x0_pcm_pointer, 1385 }; 1386 1387 static snd_pcm_ops_t snd_intel8x0_ali_ac97spdifout_ops = { 1388 .open = snd_intel8x0_ali_ac97spdifout_open, 1389 .close = snd_intel8x0_ali_ac97spdifout_close, 1390 .ioctl = snd_pcm_lib_ioctl, 1391 .hw_params = snd_intel8x0_hw_params, 1392 .hw_free = snd_intel8x0_hw_free, 1393 .prepare = snd_intel8x0_pcm_prepare, 1394 .trigger = snd_intel8x0_ali_trigger, 1395 .pointer = snd_intel8x0_pcm_pointer, 1396 }; 1397 1398 static snd_pcm_ops_t snd_intel8x0_ali_spdifin_ops = { 1399 .open = snd_intel8x0_ali_spdifin_open, 1400 .close = snd_intel8x0_ali_spdifin_close, 1401 .ioctl = snd_pcm_lib_ioctl, 1402 .hw_params = snd_intel8x0_hw_params, 1403 .hw_free = snd_intel8x0_hw_free, 1404 .prepare = snd_intel8x0_pcm_prepare, 1405 .trigger = snd_intel8x0_pcm_trigger, 1406 .pointer = snd_intel8x0_pcm_pointer, 1407 }; 1408 1409 #if 0 // NYI 1410 static snd_pcm_ops_t snd_intel8x0_ali_spdifout_ops = { 1411 .open = snd_intel8x0_ali_spdifout_open, 1412 .close = snd_intel8x0_ali_spdifout_close, 1413 .ioctl = snd_pcm_lib_ioctl, 1414 .hw_params = snd_intel8x0_hw_params, 1415 .hw_free = snd_intel8x0_hw_free, 1416 .prepare = snd_intel8x0_pcm_prepare, 1417 .trigger = snd_intel8x0_pcm_trigger, 1418 .pointer = snd_intel8x0_pcm_pointer, 1419 }; 1420 #endif // NYI 1421 1422 struct ich_pcm_table { 1423 char *suffix; 1424 snd_pcm_ops_t *playback_ops; 1425 snd_pcm_ops_t *capture_ops; 1426 size_t prealloc_size; 1427 size_t prealloc_max_size; 1428 int ac97_idx; 1429 }; 1430 1431 static int __devinit snd_intel8x0_pcm1(intel8x0_t *chip, int device, struct ich_pcm_table *rec) 1432 { 1433 snd_pcm_t *pcm; 1434 int err; 1435 char name[32]; 1436 1437 if (rec->suffix) 1438 sprintf(name, "Intel ICH - %s", rec->suffix); 1439 else 1440 strcpy(name, "Intel ICH"); 1441 err = snd_pcm_new(chip->card, name, device, 1442 rec->playback_ops ? 1 : 0, 1443 rec->capture_ops ? 1 : 0, &pcm); 1444 if (err < 0) 1445 return err; 1446 1447 if (rec->playback_ops) 1448 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1449 if (rec->capture_ops) 1450 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1451 1452 pcm->private_data = chip; 1453 pcm->info_flags = 0; 1454 if (rec->suffix) 1455 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1456 else 1457 strcpy(pcm->name, chip->card->shortname); 1458 chip->pcm[device] = pcm; 1459 1460 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci), 1461 rec->prealloc_size, rec->prealloc_max_size); 1462 1463 return 0; 1464 } 1465 1466 static struct ich_pcm_table intel_pcms[] __devinitdata = { 1467 { 1468 .playback_ops = &snd_intel8x0_playback_ops, 1469 .capture_ops = &snd_intel8x0_capture_ops, 1470 .prealloc_size = 64 * 1024, 1471 .prealloc_max_size = 128 * 1024, 1472 }, 1473 { 1474 .suffix = "MIC ADC", 1475 .capture_ops = &snd_intel8x0_capture_mic_ops, 1476 .prealloc_size = 0, 1477 .prealloc_max_size = 128 * 1024, 1478 .ac97_idx = ICHD_MIC, 1479 }, 1480 { 1481 .suffix = "MIC2 ADC", 1482 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1483 .prealloc_size = 0, 1484 .prealloc_max_size = 128 * 1024, 1485 .ac97_idx = ICHD_MIC2, 1486 }, 1487 { 1488 .suffix = "ADC2", 1489 .capture_ops = &snd_intel8x0_capture2_ops, 1490 .prealloc_size = 0, 1491 .prealloc_max_size = 128 * 1024, 1492 .ac97_idx = ICHD_PCM2IN, 1493 }, 1494 { 1495 .suffix = "IEC958", 1496 .playback_ops = &snd_intel8x0_spdif_ops, 1497 .prealloc_size = 64 * 1024, 1498 .prealloc_max_size = 128 * 1024, 1499 .ac97_idx = ICHD_SPBAR, 1500 }, 1501 }; 1502 1503 static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1504 { 1505 .playback_ops = &snd_intel8x0_playback_ops, 1506 .capture_ops = &snd_intel8x0_capture_ops, 1507 .prealloc_size = 64 * 1024, 1508 .prealloc_max_size = 128 * 1024, 1509 }, 1510 { 1511 .suffix = "MIC ADC", 1512 .capture_ops = &snd_intel8x0_capture_mic_ops, 1513 .prealloc_size = 0, 1514 .prealloc_max_size = 128 * 1024, 1515 .ac97_idx = NVD_MIC, 1516 }, 1517 { 1518 .suffix = "IEC958", 1519 .playback_ops = &snd_intel8x0_spdif_ops, 1520 .prealloc_size = 64 * 1024, 1521 .prealloc_max_size = 128 * 1024, 1522 .ac97_idx = NVD_SPBAR, 1523 }, 1524 }; 1525 1526 static struct ich_pcm_table ali_pcms[] __devinitdata = { 1527 { 1528 .playback_ops = &snd_intel8x0_ali_playback_ops, 1529 .capture_ops = &snd_intel8x0_ali_capture_ops, 1530 .prealloc_size = 64 * 1024, 1531 .prealloc_max_size = 128 * 1024, 1532 }, 1533 { 1534 .suffix = "MIC ADC", 1535 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1536 .prealloc_size = 0, 1537 .prealloc_max_size = 128 * 1024, 1538 .ac97_idx = ALID_MIC, 1539 }, 1540 { 1541 .suffix = "IEC958", 1542 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1543 .capture_ops = &snd_intel8x0_ali_spdifin_ops, 1544 .prealloc_size = 64 * 1024, 1545 .prealloc_max_size = 128 * 1024, 1546 .ac97_idx = ALID_AC97SPDIFOUT, 1547 }, 1548 #if 0 // NYI 1549 { 1550 .suffix = "HW IEC958", 1551 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1552 .prealloc_size = 64 * 1024, 1553 .prealloc_max_size = 128 * 1024, 1554 }, 1555 #endif 1556 }; 1557 1558 static int __devinit snd_intel8x0_pcm(intel8x0_t *chip) 1559 { 1560 int i, tblsize, device, err; 1561 struct ich_pcm_table *tbl, *rec; 1562 1563 switch (chip->device_type) { 1564 case DEVICE_INTEL_ICH4: 1565 tbl = intel_pcms; 1566 tblsize = ARRAY_SIZE(intel_pcms); 1567 break; 1568 case DEVICE_NFORCE: 1569 tbl = nforce_pcms; 1570 tblsize = ARRAY_SIZE(nforce_pcms); 1571 break; 1572 case DEVICE_ALI: 1573 tbl = ali_pcms; 1574 tblsize = ARRAY_SIZE(ali_pcms); 1575 break; 1576 default: 1577 tbl = intel_pcms; 1578 tblsize = 2; 1579 break; 1580 } 1581 1582 device = 0; 1583 for (i = 0; i < tblsize; i++) { 1584 rec = tbl + i; 1585 if (i > 0 && rec->ac97_idx) { 1586 /* activate PCM only when associated AC'97 codec */ 1587 if (! chip->ichd[rec->ac97_idx].pcm) 1588 continue; 1589 } 1590 err = snd_intel8x0_pcm1(chip, device, rec); 1591 if (err < 0) 1592 return err; 1593 device++; 1594 } 1595 1596 chip->pcm_devs = device; 1597 return 0; 1598 } 1599 1600 1601 /* 1602 * Mixer part 1603 */ 1604 1605 static void snd_intel8x0_mixer_free_ac97_bus(ac97_bus_t *bus) 1606 { 1607 intel8x0_t *chip = bus->private_data; 1608 chip->ac97_bus = NULL; 1609 } 1610 1611 static void snd_intel8x0_mixer_free_ac97(ac97_t *ac97) 1612 { 1613 intel8x0_t *chip = ac97->private_data; 1614 chip->ac97[ac97->num] = NULL; 1615 } 1616 1617 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1618 /* front PCM */ 1619 { 1620 .exclusive = 1, 1621 .r = { { 1622 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1623 (1 << AC97_SLOT_PCM_RIGHT) | 1624 (1 << AC97_SLOT_PCM_CENTER) | 1625 (1 << AC97_SLOT_PCM_SLEFT) | 1626 (1 << AC97_SLOT_PCM_SRIGHT) | 1627 (1 << AC97_SLOT_LFE) 1628 }, 1629 { 1630 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1631 (1 << AC97_SLOT_PCM_RIGHT) | 1632 (1 << AC97_SLOT_PCM_LEFT_0) | 1633 (1 << AC97_SLOT_PCM_RIGHT_0) 1634 } 1635 } 1636 }, 1637 /* PCM IN #1 */ 1638 { 1639 .stream = 1, 1640 .exclusive = 1, 1641 .r = { { 1642 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1643 (1 << AC97_SLOT_PCM_RIGHT) 1644 } 1645 } 1646 }, 1647 /* MIC IN #1 */ 1648 { 1649 .stream = 1, 1650 .exclusive = 1, 1651 .r = { { 1652 .slots = (1 << AC97_SLOT_MIC) 1653 } 1654 } 1655 }, 1656 /* S/PDIF PCM */ 1657 { 1658 .exclusive = 1, 1659 .spdif = 1, 1660 .r = { { 1661 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1662 (1 << AC97_SLOT_SPDIF_RIGHT2) 1663 } 1664 } 1665 }, 1666 /* PCM IN #2 */ 1667 { 1668 .stream = 1, 1669 .exclusive = 1, 1670 .r = { { 1671 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1672 (1 << AC97_SLOT_PCM_RIGHT) 1673 } 1674 } 1675 }, 1676 /* MIC IN #2 */ 1677 { 1678 .stream = 1, 1679 .exclusive = 1, 1680 .r = { { 1681 .slots = (1 << AC97_SLOT_MIC) 1682 } 1683 } 1684 }, 1685 }; 1686 1687 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1688 { 1689 .subvendor = 0x0e11, 1690 .subdevice = 0x008a, 1691 .name = "Compaq Evo W4000", /* AD1885 */ 1692 .type = AC97_TUNE_HP_ONLY 1693 }, 1694 { 1695 .subvendor = 0x0e11, 1696 .subdevice = 0x00b8, 1697 .name = "Compaq Evo D510C", 1698 .type = AC97_TUNE_HP_ONLY 1699 }, 1700 { 1701 .subvendor = 0x0e11, 1702 .subdevice = 0x0860, 1703 .name = "HP/Compaq nx7010", 1704 .type = AC97_TUNE_MUTE_LED 1705 }, 1706 { 1707 .subvendor = 0x1014, 1708 .subdevice = 0x1f00, 1709 .name = "MS-9128", 1710 .type = AC97_TUNE_ALC_JACK 1711 }, 1712 { 1713 .subvendor = 0x1014, 1714 .subdevice = 0x0267, 1715 .name = "IBM NetVista A30p", /* AD1981B */ 1716 .type = AC97_TUNE_HP_ONLY 1717 }, 1718 { 1719 .subvendor = 0x1028, 1720 .subdevice = 0x00d8, 1721 .name = "Dell Precision 530", /* AD1885 */ 1722 .type = AC97_TUNE_HP_ONLY 1723 }, 1724 { 1725 .subvendor = 0x1028, 1726 .subdevice = 0x010d, 1727 .name = "Dell", /* which model? AD1885 */ 1728 .type = AC97_TUNE_HP_ONLY 1729 }, 1730 { 1731 .subvendor = 0x1028, 1732 .subdevice = 0x0126, 1733 .name = "Dell Optiplex GX260", /* AD1981A */ 1734 .type = AC97_TUNE_HP_ONLY 1735 }, 1736 { 1737 .subvendor = 0x1028, 1738 .subdevice = 0x012c, 1739 .name = "Dell Precision 650", /* AD1981A */ 1740 .type = AC97_TUNE_HP_ONLY 1741 }, 1742 { 1743 .subvendor = 0x1028, 1744 .subdevice = 0x012d, 1745 .name = "Dell Precision 450", /* AD1981B*/ 1746 .type = AC97_TUNE_HP_ONLY 1747 }, 1748 { 1749 .subvendor = 0x1028, 1750 .subdevice = 0x0147, 1751 .name = "Dell", /* which model? AD1981B*/ 1752 .type = AC97_TUNE_HP_ONLY 1753 }, 1754 { 1755 .subvendor = 0x1028, 1756 .subdevice = 0x0163, 1757 .name = "Dell Unknown", /* STAC9750/51 */ 1758 .type = AC97_TUNE_HP_ONLY 1759 }, 1760 { 1761 .subvendor = 0x103c, 1762 .subdevice = 0x006d, 1763 .name = "HP zv5000", 1764 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1765 }, 1766 { /* FIXME: which codec? */ 1767 .subvendor = 0x103c, 1768 .subdevice = 0x00c3, 1769 .name = "HP xw6000", 1770 .type = AC97_TUNE_HP_ONLY 1771 }, 1772 { 1773 .subvendor = 0x103c, 1774 .subdevice = 0x088c, 1775 .name = "HP nc8000", 1776 .type = AC97_TUNE_MUTE_LED 1777 }, 1778 { 1779 .subvendor = 0x103c, 1780 .subdevice = 0x0890, 1781 .name = "HP nc6000", 1782 .type = AC97_TUNE_MUTE_LED 1783 }, 1784 { 1785 .subvendor = 0x103c, 1786 .subdevice = 0x0934, 1787 .name = "HP nx8220", 1788 .type = AC97_TUNE_MUTE_LED 1789 }, 1790 { 1791 .subvendor = 0x103c, 1792 .subdevice = 0x099c, 1793 .name = "HP nx6110", /* AD1981B */ 1794 .type = AC97_TUNE_HP_ONLY 1795 }, 1796 { 1797 .subvendor = 0x103c, 1798 .subdevice = 0x129d, 1799 .name = "HP xw8000", 1800 .type = AC97_TUNE_HP_ONLY 1801 }, 1802 { 1803 .subvendor = 0x103c, 1804 .subdevice = 0x12f1, 1805 .name = "HP xw8200", /* AD1981B*/ 1806 .type = AC97_TUNE_HP_ONLY 1807 }, 1808 { 1809 .subvendor = 0x103c, 1810 .subdevice = 0x12f2, 1811 .name = "HP xw6200", 1812 .type = AC97_TUNE_HP_ONLY 1813 }, 1814 { 1815 .subvendor = 0x103c, 1816 .subdevice = 0x3008, 1817 .name = "HP xw4200", /* AD1981B*/ 1818 .type = AC97_TUNE_HP_ONLY 1819 }, 1820 { 1821 .subvendor = 0x104d, 1822 .subdevice = 0x8197, 1823 .name = "Sony S1XP", 1824 .type = AC97_TUNE_INV_EAPD 1825 }, 1826 { 1827 .subvendor = 0x1043, 1828 .subdevice = 0x80f3, 1829 .name = "ASUS ICH5/AD1985", 1830 .type = AC97_TUNE_AD_SHARING 1831 }, 1832 { 1833 .subvendor = 0x10cf, 1834 .subdevice = 0x11c3, 1835 .name = "Fujitsu-Siemens E4010", 1836 .type = AC97_TUNE_HP_ONLY 1837 }, 1838 { 1839 .subvendor = 0x10cf, 1840 .subdevice = 0x1225, 1841 .name = "Fujitsu-Siemens T3010", 1842 .type = AC97_TUNE_HP_ONLY 1843 }, 1844 { 1845 .subvendor = 0x10cf, 1846 .subdevice = 0x1253, 1847 .name = "Fujitsu S6210", /* STAC9750/51 */ 1848 .type = AC97_TUNE_HP_ONLY 1849 }, 1850 { 1851 .subvendor = 0x10cf, 1852 .subdevice = 0x12ec, 1853 .name = "Fujitsu-Siemens 4010", 1854 .type = AC97_TUNE_HP_ONLY 1855 }, 1856 { 1857 .subvendor = 0x10f1, 1858 .subdevice = 0x2665, 1859 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1860 .type = AC97_TUNE_HP_ONLY 1861 }, 1862 { 1863 .subvendor = 0x10f1, 1864 .subdevice = 0x2885, 1865 .name = "AMD64 Mobo", /* ALC650 */ 1866 .type = AC97_TUNE_HP_ONLY 1867 }, 1868 { 1869 .subvendor = 0x110a, 1870 .subdevice = 0x0056, 1871 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 1872 .type = AC97_TUNE_HP_ONLY 1873 }, 1874 { 1875 .subvendor = 0x11d4, 1876 .subdevice = 0x5375, 1877 .name = "ADI AD1985 (discrete)", 1878 .type = AC97_TUNE_HP_ONLY 1879 }, 1880 { 1881 .subvendor = 0x1462, 1882 .subdevice = 0x5470, 1883 .name = "MSI P4 ATX 645 Ultra", 1884 .type = AC97_TUNE_HP_ONLY 1885 }, 1886 { 1887 .subvendor = 0x1734, 1888 .subdevice = 0x0088, 1889 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 1890 .type = AC97_TUNE_HP_ONLY 1891 }, 1892 { 1893 .subvendor = 0x8086, 1894 .subdevice = 0x2000, 1895 .mask = 0xfff0, 1896 .name = "Intel ICH5/AD1985", 1897 .type = AC97_TUNE_AD_SHARING 1898 }, 1899 { 1900 .subvendor = 0x8086, 1901 .subdevice = 0x4000, 1902 .mask = 0xfff0, 1903 .name = "Intel ICH5/AD1985", 1904 .type = AC97_TUNE_AD_SHARING 1905 }, 1906 { 1907 .subvendor = 0x8086, 1908 .subdevice = 0x4856, 1909 .name = "Intel D845WN (82801BA)", 1910 .type = AC97_TUNE_SWAP_HP 1911 }, 1912 { 1913 .subvendor = 0x8086, 1914 .subdevice = 0x4d44, 1915 .name = "Intel D850EMV2", /* AD1885 */ 1916 .type = AC97_TUNE_HP_ONLY 1917 }, 1918 { 1919 .subvendor = 0x8086, 1920 .subdevice = 0x4d56, 1921 .name = "Intel ICH/AD1885", 1922 .type = AC97_TUNE_HP_ONLY 1923 }, 1924 { 1925 .subvendor = 0x8086, 1926 .subdevice = 0x6000, 1927 .mask = 0xfff0, 1928 .name = "Intel ICH5/AD1985", 1929 .type = AC97_TUNE_AD_SHARING 1930 }, 1931 { 1932 .subvendor = 0x8086, 1933 .subdevice = 0xe000, 1934 .mask = 0xfff0, 1935 .name = "Intel ICH5/AD1985", 1936 .type = AC97_TUNE_AD_SHARING 1937 }, 1938 #if 0 /* FIXME: this seems wrong on most boards */ 1939 { 1940 .subvendor = 0x8086, 1941 .subdevice = 0xa000, 1942 .mask = 0xfff0, 1943 .name = "Intel ICH5/AD1985", 1944 .type = AC97_TUNE_HP_ONLY 1945 }, 1946 #endif 1947 { } /* terminator */ 1948 }; 1949 1950 static int __devinit snd_intel8x0_mixer(intel8x0_t *chip, int ac97_clock, const char *quirk_override) 1951 { 1952 ac97_bus_t *pbus; 1953 ac97_template_t ac97; 1954 int err; 1955 unsigned int i, codecs; 1956 unsigned int glob_sta = 0; 1957 ac97_bus_ops_t *ops; 1958 static ac97_bus_ops_t standard_bus_ops = { 1959 .write = snd_intel8x0_codec_write, 1960 .read = snd_intel8x0_codec_read, 1961 }; 1962 static ac97_bus_ops_t ali_bus_ops = { 1963 .write = snd_intel8x0_ali_codec_write, 1964 .read = snd_intel8x0_ali_codec_read, 1965 }; 1966 1967 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 1968 switch (chip->device_type) { 1969 case DEVICE_NFORCE: 1970 chip->spdif_idx = NVD_SPBAR; 1971 break; 1972 case DEVICE_ALI: 1973 chip->spdif_idx = ALID_AC97SPDIFOUT; 1974 break; 1975 case DEVICE_INTEL_ICH4: 1976 chip->spdif_idx = ICHD_SPBAR; 1977 break; 1978 }; 1979 1980 chip->in_ac97_init = 1; 1981 1982 memset(&ac97, 0, sizeof(ac97)); 1983 ac97.private_data = chip; 1984 ac97.private_free = snd_intel8x0_mixer_free_ac97; 1985 ac97.scaps = AC97_SCAP_SKIP_MODEM; 1986 if (chip->xbox) 1987 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 1988 if (chip->device_type != DEVICE_ALI) { 1989 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 1990 ops = &standard_bus_ops; 1991 if (chip->device_type == DEVICE_INTEL_ICH4) { 1992 codecs = 0; 1993 if (glob_sta & ICH_PCR) 1994 codecs++; 1995 if (glob_sta & ICH_SCR) 1996 codecs++; 1997 if (glob_sta & ICH_TCR) 1998 codecs++; 1999 chip->in_sdin_init = 1; 2000 for (i = 0; i < codecs; i++) { 2001 snd_intel8x0_codec_read_test(chip, i); 2002 chip->ac97_sdin[i] = igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2003 } 2004 chip->in_sdin_init = 0; 2005 } else { 2006 codecs = glob_sta & ICH_SCR ? 2 : 1; 2007 } 2008 } else { 2009 ops = &ali_bus_ops; 2010 codecs = 1; 2011 /* detect the secondary codec */ 2012 for (i = 0; i < 100; i++) { 2013 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2014 if (reg & 0x40) { 2015 codecs = 2; 2016 break; 2017 } 2018 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2019 udelay(1); 2020 } 2021 } 2022 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2023 goto __err; 2024 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2025 pbus->shared_type = AC97_SHARED_TYPE_ICH; /* shared with modem driver */ 2026 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2027 pbus->clock = ac97_clock; 2028 /* FIXME: my test board doesn't work well with VRA... */ 2029 if (chip->device_type == DEVICE_ALI) 2030 pbus->no_vra = 1; 2031 else 2032 pbus->dra = 1; 2033 chip->ac97_bus = pbus; 2034 2035 ac97.pci = chip->pci; 2036 for (i = 0; i < codecs; i++) { 2037 ac97.num = i; 2038 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2039 if (err != -EACCES) 2040 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2041 if (i == 0) 2042 goto __err; 2043 continue; 2044 } 2045 } 2046 /* tune up the primary codec */ 2047 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2048 /* enable separate SDINs for ICH4 */ 2049 if (chip->device_type == DEVICE_INTEL_ICH4) 2050 pbus->isdin = 1; 2051 /* find the available PCM streams */ 2052 i = ARRAY_SIZE(ac97_pcm_defs); 2053 if (chip->device_type != DEVICE_INTEL_ICH4) 2054 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2055 if (chip->spdif_idx < 0) 2056 i--; /* do not allocate S/PDIF */ 2057 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2058 if (err < 0) 2059 goto __err; 2060 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2061 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2062 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2063 if (chip->spdif_idx >= 0) 2064 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2065 if (chip->device_type == DEVICE_INTEL_ICH4) { 2066 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2067 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2068 } 2069 /* enable separate SDINs for ICH4 */ 2070 if (chip->device_type == DEVICE_INTEL_ICH4) { 2071 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2072 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2073 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2074 if (pcm) { 2075 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2076 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2077 for (i = 1; i < 4; i++) { 2078 if (pcm->r[0].codec[i]) { 2079 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2080 break; 2081 } 2082 } 2083 } else { 2084 tmp &= ~ICH_SE; /* steer disable */ 2085 } 2086 iputbyte(chip, ICHREG(SDM), tmp); 2087 } 2088 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2089 chip->multi4 = 1; 2090 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) 2091 chip->multi6 = 1; 2092 } 2093 if (pbus->pcms[0].r[1].rslots[0]) { 2094 chip->dra = 1; 2095 } 2096 if (chip->device_type == DEVICE_INTEL_ICH4) { 2097 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2098 chip->smp20bit = 1; 2099 } 2100 if (chip->device_type == DEVICE_NFORCE) { 2101 /* 48kHz only */ 2102 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2103 } 2104 if (chip->device_type == DEVICE_INTEL_ICH4) { 2105 /* use slot 10/11 for SPDIF */ 2106 u32 val; 2107 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2108 val |= ICH_PCM_SPDIF_1011; 2109 iputdword(chip, ICHREG(GLOB_CNT), val); 2110 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2111 } 2112 chip->in_ac97_init = 0; 2113 return 0; 2114 2115 __err: 2116 /* clear the cold-reset bit for the next chance */ 2117 if (chip->device_type != DEVICE_ALI) 2118 iputdword(chip, ICHREG(GLOB_CNT), igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2119 return err; 2120 } 2121 2122 2123 /* 2124 * 2125 */ 2126 2127 static void do_ali_reset(intel8x0_t *chip) 2128 { 2129 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2130 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2131 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2132 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2133 iputdword(chip, ICHREG(ALI_INTERFACECR), 2134 ICH_ALI_IF_MC|ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2135 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2136 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2137 } 2138 2139 #define do_delay(chip) do {\ 2140 set_current_state(TASK_UNINTERRUPTIBLE);\ 2141 schedule_timeout(1);\ 2142 } while (0) 2143 2144 static int snd_intel8x0_ich_chip_init(intel8x0_t *chip, int probing) 2145 { 2146 unsigned long end_time; 2147 unsigned int cnt, status, nstatus; 2148 2149 /* put logic to right state */ 2150 /* first clear status bits */ 2151 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2152 if (chip->device_type == DEVICE_NFORCE) 2153 status |= ICH_NVSPINT; 2154 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2155 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2156 2157 /* ACLink on, 2 channels */ 2158 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2159 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2160 /* finish cold or do warm reset */ 2161 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2162 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2163 end_time = (jiffies + (HZ / 4)) + 1; 2164 do { 2165 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2166 goto __ok; 2167 do_delay(chip); 2168 } while (time_after_eq(end_time, jiffies)); 2169 snd_printk("AC'97 warm reset still in progress? [0x%x]\n", igetdword(chip, ICHREG(GLOB_CNT))); 2170 return -EIO; 2171 2172 __ok: 2173 if (probing) { 2174 /* wait for any codec ready status. 2175 * Once it becomes ready it should remain ready 2176 * as long as we do not disable the ac97 link. 2177 */ 2178 end_time = jiffies + HZ; 2179 do { 2180 status = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 2181 if (status) 2182 break; 2183 do_delay(chip); 2184 } while (time_after_eq(end_time, jiffies)); 2185 if (! status) { 2186 /* no codec is found */ 2187 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", igetdword(chip, ICHREG(GLOB_STA))); 2188 return -EIO; 2189 } 2190 2191 if (chip->device_type == DEVICE_INTEL_ICH4) 2192 /* ICH4 can have three codecs */ 2193 nstatus = ICH_PCR | ICH_SCR | ICH_TCR; 2194 else 2195 /* others up to two codecs */ 2196 nstatus = ICH_PCR | ICH_SCR; 2197 2198 /* wait for other codecs ready status. */ 2199 end_time = jiffies + HZ / 4; 2200 while (status != nstatus && time_after_eq(end_time, jiffies)) { 2201 do_delay(chip); 2202 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 2203 } 2204 2205 } else { 2206 /* resume phase */ 2207 int i; 2208 status = 0; 2209 for (i = 0; i < 3; i++) 2210 if (chip->ac97[i]) 2211 status |= get_ich_codec_bit(chip, i); 2212 /* wait until all the probed codecs are ready */ 2213 end_time = jiffies + HZ; 2214 do { 2215 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & (ICH_PCR | ICH_SCR | ICH_TCR); 2216 if (status == nstatus) 2217 break; 2218 do_delay(chip); 2219 } while (time_after_eq(end_time, jiffies)); 2220 } 2221 2222 if (chip->device_type == DEVICE_SIS) { 2223 /* unmute the output on SIS7012 */ 2224 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2225 } 2226 if (chip->device_type == DEVICE_NFORCE) { 2227 /* enable SPDIF interrupt */ 2228 unsigned int val; 2229 pci_read_config_dword(chip->pci, 0x4c, &val); 2230 val |= 0x1000000; 2231 pci_write_config_dword(chip->pci, 0x4c, val); 2232 } 2233 return 0; 2234 } 2235 2236 static int snd_intel8x0_ali_chip_init(intel8x0_t *chip, int probing) 2237 { 2238 u32 reg; 2239 int i = 0; 2240 2241 reg = igetdword(chip, ICHREG(ALI_SCR)); 2242 if ((reg & 2) == 0) /* Cold required */ 2243 reg |= 2; 2244 else 2245 reg |= 1; /* Warm */ 2246 reg &= ~0x80000000; /* ACLink on */ 2247 iputdword(chip, ICHREG(ALI_SCR), reg); 2248 2249 for (i = 0; i < HZ / 2; i++) { 2250 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2251 goto __ok; 2252 do_delay(chip); 2253 } 2254 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2255 if (probing) 2256 return -EIO; 2257 2258 __ok: 2259 for (i = 0; i < HZ / 2; i++) { 2260 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2261 if (reg & 0x80) /* primary codec */ 2262 break; 2263 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2264 do_delay(chip); 2265 } 2266 2267 do_ali_reset(chip); 2268 return 0; 2269 } 2270 2271 static int snd_intel8x0_chip_init(intel8x0_t *chip, int probing) 2272 { 2273 unsigned int i; 2274 int err; 2275 2276 if (chip->device_type != DEVICE_ALI) { 2277 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2278 return err; 2279 iagetword(chip, 0); /* clear semaphore flag */ 2280 } else { 2281 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2282 return err; 2283 } 2284 2285 /* disable interrupts */ 2286 for (i = 0; i < chip->bdbars_count; i++) 2287 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2288 /* reset channels */ 2289 for (i = 0; i < chip->bdbars_count; i++) 2290 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2291 /* initialize Buffer Descriptor Lists */ 2292 for (i = 0; i < chip->bdbars_count; i++) 2293 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 2294 return 0; 2295 } 2296 2297 static int snd_intel8x0_free(intel8x0_t *chip) 2298 { 2299 unsigned int i; 2300 2301 if (chip->irq < 0) 2302 goto __hw_end; 2303 /* disable interrupts */ 2304 for (i = 0; i < chip->bdbars_count; i++) 2305 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2306 /* reset channels */ 2307 for (i = 0; i < chip->bdbars_count; i++) 2308 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2309 if (chip->device_type == DEVICE_NFORCE) { 2310 /* stop the spdif interrupt */ 2311 unsigned int val; 2312 pci_read_config_dword(chip->pci, 0x4c, &val); 2313 val &= ~0x1000000; 2314 pci_write_config_dword(chip->pci, 0x4c, val); 2315 } 2316 /* --- */ 2317 synchronize_irq(chip->irq); 2318 __hw_end: 2319 if (chip->irq >= 0) 2320 free_irq(chip->irq, (void *)chip); 2321 if (chip->bdbars.area) { 2322 if (chip->fix_nocache) 2323 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2324 snd_dma_free_pages(&chip->bdbars); 2325 } 2326 if (chip->remap_addr) 2327 iounmap(chip->remap_addr); 2328 if (chip->remap_bmaddr) 2329 iounmap(chip->remap_bmaddr); 2330 pci_release_regions(chip->pci); 2331 pci_disable_device(chip->pci); 2332 kfree(chip); 2333 return 0; 2334 } 2335 2336 #ifdef CONFIG_PM 2337 /* 2338 * power management 2339 */ 2340 static int intel8x0_suspend(snd_card_t *card, pm_message_t state) 2341 { 2342 intel8x0_t *chip = card->pm_private_data; 2343 int i; 2344 2345 for (i = 0; i < chip->pcm_devs; i++) 2346 snd_pcm_suspend_all(chip->pcm[i]); 2347 /* clear nocache */ 2348 if (chip->fix_nocache) { 2349 for (i = 0; i < chip->bdbars_count; i++) { 2350 ichdev_t *ichdev = &chip->ichd[i]; 2351 if (ichdev->substream && ichdev->page_attr_changed) { 2352 snd_pcm_runtime_t *runtime = ichdev->substream->runtime; 2353 if (runtime->dma_area) 2354 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2355 } 2356 } 2357 } 2358 for (i = 0; i < 3; i++) 2359 if (chip->ac97[i]) 2360 snd_ac97_suspend(chip->ac97[i]); 2361 if (chip->device_type == DEVICE_INTEL_ICH4) 2362 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2363 2364 if (chip->irq >= 0) 2365 free_irq(chip->irq, (void *)chip); 2366 pci_disable_device(chip->pci); 2367 return 0; 2368 } 2369 2370 static int intel8x0_resume(snd_card_t *card) 2371 { 2372 intel8x0_t *chip = card->pm_private_data; 2373 int i; 2374 2375 pci_enable_device(chip->pci); 2376 pci_set_master(chip->pci); 2377 request_irq(chip->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip); 2378 synchronize_irq(chip->irq); 2379 snd_intel8x0_chip_init(chip, 1); 2380 2381 /* re-initialize mixer stuff */ 2382 if (chip->device_type == DEVICE_INTEL_ICH4) { 2383 /* enable separate SDINs for ICH4 */ 2384 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2385 /* use slot 10/11 for SPDIF */ 2386 iputdword(chip, ICHREG(GLOB_CNT), 2387 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2388 ICH_PCM_SPDIF_1011); 2389 } 2390 2391 /* refill nocache */ 2392 if (chip->fix_nocache) 2393 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2394 2395 for (i = 0; i < 3; i++) 2396 if (chip->ac97[i]) 2397 snd_ac97_resume(chip->ac97[i]); 2398 2399 /* refill nocache */ 2400 if (chip->fix_nocache) { 2401 for (i = 0; i < chip->bdbars_count; i++) { 2402 ichdev_t *ichdev = &chip->ichd[i]; 2403 if (ichdev->substream && ichdev->page_attr_changed) { 2404 snd_pcm_runtime_t *runtime = ichdev->substream->runtime; 2405 if (runtime->dma_area) 2406 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2407 } 2408 } 2409 } 2410 2411 /* resume status */ 2412 for (i = 0; i < chip->bdbars_count; i++) { 2413 ichdev_t *ichdev = &chip->ichd[i]; 2414 unsigned long port = ichdev->reg_offset; 2415 if (! ichdev->substream || ! ichdev->suspended) 2416 continue; 2417 if (ichdev->ichd == ICHD_PCMOUT) 2418 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2419 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2420 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2421 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2422 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2423 } 2424 2425 return 0; 2426 } 2427 #endif /* CONFIG_PM */ 2428 2429 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2430 2431 static void __devinit intel8x0_measure_ac97_clock(intel8x0_t *chip) 2432 { 2433 snd_pcm_substream_t *subs; 2434 ichdev_t *ichdev; 2435 unsigned long port; 2436 unsigned long pos, t; 2437 struct timeval start_time, stop_time; 2438 2439 if (chip->ac97_bus->clock != 48000) 2440 return; /* specified in module option */ 2441 2442 subs = chip->pcm[0]->streams[0].substream; 2443 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2444 snd_printk("no playback buffer allocated - aborting measure ac97 clock\n"); 2445 return; 2446 } 2447 ichdev = &chip->ichd[ICHD_PCMOUT]; 2448 ichdev->physbuf = subs->dma_buffer.addr; 2449 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE; 2450 ichdev->substream = NULL; /* don't process interrupts */ 2451 2452 /* set rate */ 2453 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2454 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2455 return; 2456 } 2457 snd_intel8x0_setup_periods(chip, ichdev); 2458 port = ichdev->reg_offset; 2459 spin_lock_irq(&chip->reg_lock); 2460 chip->in_measurement = 1; 2461 /* trigger */ 2462 if (chip->device_type != DEVICE_ALI) 2463 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2464 else { 2465 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2466 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2467 } 2468 do_gettimeofday(&start_time); 2469 spin_unlock_irq(&chip->reg_lock); 2470 msleep(50); 2471 spin_lock_irq(&chip->reg_lock); 2472 /* check the position */ 2473 pos = ichdev->fragsize1; 2474 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift; 2475 pos += ichdev->position; 2476 chip->in_measurement = 0; 2477 do_gettimeofday(&stop_time); 2478 /* stop */ 2479 if (chip->device_type == DEVICE_ALI) { 2480 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 8)); 2481 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2482 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2483 ; 2484 } else { 2485 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2486 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2487 ; 2488 } 2489 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2490 spin_unlock_irq(&chip->reg_lock); 2491 2492 t = stop_time.tv_sec - start_time.tv_sec; 2493 t *= 1000000; 2494 t += stop_time.tv_usec - start_time.tv_usec; 2495 printk(KERN_INFO "%s: measured %lu usecs\n", __FUNCTION__, t); 2496 if (t == 0) { 2497 snd_printk(KERN_ERR "?? calculation error..\n"); 2498 return; 2499 } 2500 pos = (pos / 4) * 1000; 2501 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2502 if (pos < 40000 || pos >= 60000) 2503 /* abnormal value. hw problem? */ 2504 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2505 else if (pos < 47500 || pos > 48500) 2506 /* not 48000Hz, tuning the clock.. */ 2507 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2508 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2509 } 2510 2511 static void snd_intel8x0_proc_read(snd_info_entry_t * entry, 2512 snd_info_buffer_t * buffer) 2513 { 2514 intel8x0_t *chip = entry->private_data; 2515 unsigned int tmp; 2516 2517 snd_iprintf(buffer, "Intel8x0\n\n"); 2518 if (chip->device_type == DEVICE_ALI) 2519 return; 2520 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2521 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2522 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2523 if (chip->device_type == DEVICE_INTEL_ICH4) 2524 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2525 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 2526 tmp & ICH_PCR ? " primary" : "", 2527 tmp & ICH_SCR ? " secondary" : "", 2528 tmp & ICH_TCR ? " tertiary" : "", 2529 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 2530 if (chip->device_type == DEVICE_INTEL_ICH4) 2531 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2532 chip->ac97_sdin[0], 2533 chip->ac97_sdin[1], 2534 chip->ac97_sdin[2]); 2535 } 2536 2537 static void __devinit snd_intel8x0_proc_init(intel8x0_t * chip) 2538 { 2539 snd_info_entry_t *entry; 2540 2541 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2542 snd_info_set_text_ops(entry, chip, 1024, snd_intel8x0_proc_read); 2543 } 2544 2545 static int snd_intel8x0_dev_free(snd_device_t *device) 2546 { 2547 intel8x0_t *chip = device->device_data; 2548 return snd_intel8x0_free(chip); 2549 } 2550 2551 struct ich_reg_info { 2552 unsigned int int_sta_mask; 2553 unsigned int offset; 2554 }; 2555 2556 static int __devinit snd_intel8x0_create(snd_card_t * card, 2557 struct pci_dev *pci, 2558 unsigned long device_type, 2559 int buggy_sem, 2560 intel8x0_t ** r_intel8x0) 2561 { 2562 intel8x0_t *chip; 2563 int err; 2564 unsigned int i; 2565 unsigned int int_sta_masks; 2566 ichdev_t *ichdev; 2567 static snd_device_ops_t ops = { 2568 .dev_free = snd_intel8x0_dev_free, 2569 }; 2570 2571 static unsigned int bdbars[] = { 2572 3, /* DEVICE_INTEL */ 2573 6, /* DEVICE_INTEL_ICH4 */ 2574 3, /* DEVICE_SIS */ 2575 6, /* DEVICE_ALI */ 2576 4, /* DEVICE_NFORCE */ 2577 }; 2578 static struct ich_reg_info intel_regs[6] = { 2579 { ICH_PIINT, 0 }, 2580 { ICH_POINT, 0x10 }, 2581 { ICH_MCINT, 0x20 }, 2582 { ICH_M2INT, 0x40 }, 2583 { ICH_P2INT, 0x50 }, 2584 { ICH_SPINT, 0x60 }, 2585 }; 2586 static struct ich_reg_info nforce_regs[4] = { 2587 { ICH_PIINT, 0 }, 2588 { ICH_POINT, 0x10 }, 2589 { ICH_MCINT, 0x20 }, 2590 { ICH_NVSPINT, 0x70 }, 2591 }; 2592 static struct ich_reg_info ali_regs[6] = { 2593 { ALI_INT_PCMIN, 0x40 }, 2594 { ALI_INT_PCMOUT, 0x50 }, 2595 { ALI_INT_MICIN, 0x60 }, 2596 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2597 { ALI_INT_SPDIFIN, 0xa0 }, 2598 { ALI_INT_SPDIFOUT, 0xb0 }, 2599 }; 2600 struct ich_reg_info *tbl; 2601 2602 *r_intel8x0 = NULL; 2603 2604 if ((err = pci_enable_device(pci)) < 0) 2605 return err; 2606 2607 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2608 if (chip == NULL) { 2609 pci_disable_device(pci); 2610 return -ENOMEM; 2611 } 2612 spin_lock_init(&chip->reg_lock); 2613 chip->device_type = device_type; 2614 chip->card = card; 2615 chip->pci = pci; 2616 chip->irq = -1; 2617 chip->buggy_semaphore = buggy_sem; 2618 2619 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2620 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2621 chip->fix_nocache = 1; /* enable workaround */ 2622 2623 /* some Nforce[2] and ICH boards have problems with IRQ handling. 2624 * Needs to return IRQ_HANDLED for unknown irqs. 2625 */ 2626 if (device_type == DEVICE_NFORCE) 2627 chip->buggy_irq = 1; 2628 2629 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2630 kfree(chip); 2631 pci_disable_device(pci); 2632 return err; 2633 } 2634 2635 if (device_type == DEVICE_ALI) { 2636 /* ALI5455 has no ac97 region */ 2637 chip->bmaddr = pci_resource_start(pci, 0); 2638 goto port_inited; 2639 } 2640 2641 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) { /* ICH4 and Nforce */ 2642 chip->mmio = 1; 2643 chip->addr = pci_resource_start(pci, 2); 2644 chip->remap_addr = ioremap_nocache(chip->addr, 2645 pci_resource_len(pci, 2)); 2646 if (chip->remap_addr == NULL) { 2647 snd_printk("AC'97 space ioremap problem\n"); 2648 snd_intel8x0_free(chip); 2649 return -EIO; 2650 } 2651 } else { 2652 chip->addr = pci_resource_start(pci, 0); 2653 } 2654 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) { /* ICH4 */ 2655 chip->bm_mmio = 1; 2656 chip->bmaddr = pci_resource_start(pci, 3); 2657 chip->remap_bmaddr = ioremap_nocache(chip->bmaddr, 2658 pci_resource_len(pci, 3)); 2659 if (chip->remap_bmaddr == NULL) { 2660 snd_printk("Controller space ioremap problem\n"); 2661 snd_intel8x0_free(chip); 2662 return -EIO; 2663 } 2664 } else { 2665 chip->bmaddr = pci_resource_start(pci, 1); 2666 } 2667 2668 port_inited: 2669 if (request_irq(pci->irq, snd_intel8x0_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) { 2670 snd_printk("unable to grab IRQ %d\n", pci->irq); 2671 snd_intel8x0_free(chip); 2672 return -EBUSY; 2673 } 2674 chip->irq = pci->irq; 2675 pci_set_master(pci); 2676 synchronize_irq(chip->irq); 2677 2678 chip->bdbars_count = bdbars[device_type]; 2679 2680 /* initialize offsets */ 2681 switch (device_type) { 2682 case DEVICE_NFORCE: 2683 tbl = nforce_regs; 2684 break; 2685 case DEVICE_ALI: 2686 tbl = ali_regs; 2687 break; 2688 default: 2689 tbl = intel_regs; 2690 break; 2691 } 2692 for (i = 0; i < chip->bdbars_count; i++) { 2693 ichdev = &chip->ichd[i]; 2694 ichdev->ichd = i; 2695 ichdev->reg_offset = tbl[i].offset; 2696 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2697 if (device_type == DEVICE_SIS) { 2698 /* SiS 7012 swaps the registers */ 2699 ichdev->roff_sr = ICH_REG_OFF_PICB; 2700 ichdev->roff_picb = ICH_REG_OFF_SR; 2701 } else { 2702 ichdev->roff_sr = ICH_REG_OFF_SR; 2703 ichdev->roff_picb = ICH_REG_OFF_PICB; 2704 } 2705 if (device_type == DEVICE_ALI) 2706 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 2707 /* SIS7012 handles the pcm data in bytes, others are in samples */ 2708 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 2709 } 2710 2711 /* allocate buffer descriptor lists */ 2712 /* the start of each lists must be aligned to 8 bytes */ 2713 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2714 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 2715 &chip->bdbars) < 0) { 2716 snd_intel8x0_free(chip); 2717 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 2718 return -ENOMEM; 2719 } 2720 /* tables must be aligned to 8 bytes here, but the kernel pages 2721 are much bigger, so we don't care (on i386) */ 2722 /* workaround for 440MX */ 2723 if (chip->fix_nocache) 2724 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2725 int_sta_masks = 0; 2726 for (i = 0; i < chip->bdbars_count; i++) { 2727 ichdev = &chip->ichd[i]; 2728 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 2729 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 2730 int_sta_masks |= ichdev->int_sta_mask; 2731 } 2732 chip->int_sta_reg = device_type == DEVICE_ALI ? ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 2733 chip->int_sta_mask = int_sta_masks; 2734 2735 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 2736 snd_intel8x0_free(chip); 2737 return err; 2738 } 2739 2740 snd_card_set_pm_callback(card, intel8x0_suspend, intel8x0_resume, chip); 2741 2742 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2743 snd_intel8x0_free(chip); 2744 return err; 2745 } 2746 2747 snd_card_set_dev(card, &pci->dev); 2748 2749 *r_intel8x0 = chip; 2750 return 0; 2751 } 2752 2753 static struct shortname_table { 2754 unsigned int id; 2755 const char *s; 2756 } shortnames[] __devinitdata = { 2757 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 2758 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 2759 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 2760 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 2761 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 2762 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 2763 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 2764 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 2765 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 2766 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 2767 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 2768 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 2769 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 2770 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 2771 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 2772 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 2773 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 2774 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 2775 { 0x003a, "NVidia MCP04" }, 2776 { 0x746d, "AMD AMD8111" }, 2777 { 0x7445, "AMD AMD768" }, 2778 { 0x5455, "ALi M5455" }, 2779 { 0, NULL }, 2780 }; 2781 2782 static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 2783 const struct pci_device_id *pci_id) 2784 { 2785 static int dev; 2786 snd_card_t *card; 2787 intel8x0_t *chip; 2788 int err; 2789 struct shortname_table *name; 2790 2791 if (dev >= SNDRV_CARDS) 2792 return -ENODEV; 2793 if (!enable[dev]) { 2794 dev++; 2795 return -ENOENT; 2796 } 2797 2798 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0); 2799 if (card == NULL) 2800 return -ENOMEM; 2801 2802 switch (pci_id->driver_data) { 2803 case DEVICE_NFORCE: 2804 strcpy(card->driver, "NFORCE"); 2805 break; 2806 case DEVICE_INTEL_ICH4: 2807 strcpy(card->driver, "ICH4"); 2808 break; 2809 default: 2810 strcpy(card->driver, "ICH"); 2811 break; 2812 } 2813 2814 strcpy(card->shortname, "Intel ICH"); 2815 for (name = shortnames; name->id; name++) { 2816 if (pci->device == name->id) { 2817 strcpy(card->shortname, name->s); 2818 break; 2819 } 2820 } 2821 2822 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 2823 buggy_semaphore[dev], &chip)) < 0) { 2824 snd_card_free(card); 2825 return err; 2826 } 2827 if (buggy_irq[dev]) 2828 chip->buggy_irq = 1; 2829 if (xbox[dev]) 2830 chip->xbox = 1; 2831 2832 if ((err = snd_intel8x0_mixer(chip, ac97_clock[dev], ac97_quirk[dev])) < 0) { 2833 snd_card_free(card); 2834 return err; 2835 } 2836 if ((err = snd_intel8x0_pcm(chip)) < 0) { 2837 snd_card_free(card); 2838 return err; 2839 } 2840 2841 snd_intel8x0_proc_init(chip); 2842 2843 snprintf(card->longname, sizeof(card->longname), 2844 "%s with %s at %#lx, irq %i", card->shortname, 2845 snd_ac97_get_short_name(chip->ac97[0]), chip->addr, chip->irq); 2846 2847 if (! ac97_clock[dev]) 2848 intel8x0_measure_ac97_clock(chip); 2849 2850 if ((err = snd_card_register(card)) < 0) { 2851 snd_card_free(card); 2852 return err; 2853 } 2854 pci_set_drvdata(pci, card); 2855 dev++; 2856 return 0; 2857 } 2858 2859 static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 2860 { 2861 snd_card_free(pci_get_drvdata(pci)); 2862 pci_set_drvdata(pci, NULL); 2863 } 2864 2865 static struct pci_driver driver = { 2866 .name = "Intel ICH", 2867 .owner = THIS_MODULE, 2868 .id_table = snd_intel8x0_ids, 2869 .probe = snd_intel8x0_probe, 2870 .remove = __devexit_p(snd_intel8x0_remove), 2871 SND_PCI_PM_CALLBACKS 2872 }; 2873 2874 2875 static int __init alsa_card_intel8x0_init(void) 2876 { 2877 return pci_register_driver(&driver); 2878 } 2879 2880 static void __exit alsa_card_intel8x0_exit(void) 2881 { 2882 pci_unregister_driver(&driver); 2883 } 2884 2885 module_init(alsa_card_intel8x0_init) 2886 module_exit(alsa_card_intel8x0_exit) 2887