18c70461bSLucas Tanure // SPDX-License-Identifier: GPL-2.0-or-later 28c70461bSLucas Tanure /* 38c70461bSLucas Tanure * HD audio interface patch for Cirrus Logic CS8409 HDA bridge chip 48c70461bSLucas Tanure * 58c70461bSLucas Tanure * Copyright (C) 2021 Cirrus Logic, Inc. and 68c70461bSLucas Tanure * Cirrus Logic International Semiconductor Ltd. 78c70461bSLucas Tanure */ 88c70461bSLucas Tanure 98c70461bSLucas Tanure #include <linux/init.h> 108c70461bSLucas Tanure #include <linux/slab.h> 118c70461bSLucas Tanure #include <linux/module.h> 128c70461bSLucas Tanure #include <sound/core.h> 138c70461bSLucas Tanure #include <linux/mutex.h> 144ff2ae3aSStefan Binding #include <linux/iopoll.h> 158c70461bSLucas Tanure 168c70461bSLucas Tanure #include "patch_cs8409.h" 178c70461bSLucas Tanure 18636eb9d2SLucas Tanure /****************************************************************************** 19636eb9d2SLucas Tanure * CS8409 Specific Functions 20636eb9d2SLucas Tanure ******************************************************************************/ 21636eb9d2SLucas Tanure 228c70461bSLucas Tanure static int cs8409_parse_auto_config(struct hda_codec *codec) 238c70461bSLucas Tanure { 248c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 258c70461bSLucas Tanure int err; 268c70461bSLucas Tanure int i; 278c70461bSLucas Tanure 288c70461bSLucas Tanure err = snd_hda_parse_pin_defcfg(codec, &spec->gen.autocfg, NULL, 0); 298c70461bSLucas Tanure if (err < 0) 308c70461bSLucas Tanure return err; 318c70461bSLucas Tanure 328c70461bSLucas Tanure err = snd_hda_gen_parse_auto_config(codec, &spec->gen.autocfg); 338c70461bSLucas Tanure if (err < 0) 348c70461bSLucas Tanure return err; 358c70461bSLucas Tanure 368c70461bSLucas Tanure /* keep the ADCs powered up when it's dynamically switchable */ 378c70461bSLucas Tanure if (spec->gen.dyn_adc_switch) { 388c70461bSLucas Tanure unsigned int done = 0; 398c70461bSLucas Tanure 408c70461bSLucas Tanure for (i = 0; i < spec->gen.input_mux.num_items; i++) { 418c70461bSLucas Tanure int idx = spec->gen.dyn_adc_idx[i]; 428c70461bSLucas Tanure 438c70461bSLucas Tanure if (done & (1 << idx)) 448c70461bSLucas Tanure continue; 458c70461bSLucas Tanure snd_hda_gen_fix_pin_power(codec, spec->gen.adc_nids[idx]); 468c70461bSLucas Tanure done |= 1 << idx; 478c70461bSLucas Tanure } 488c70461bSLucas Tanure } 498c70461bSLucas Tanure 508c70461bSLucas Tanure return 0; 518c70461bSLucas Tanure } 528c70461bSLucas Tanure 53647d50a0SLucas Tanure static void cs8409_disable_i2c_clock_worker(struct work_struct *work); 54647d50a0SLucas Tanure 558c70461bSLucas Tanure static struct cs8409_spec *cs8409_alloc_spec(struct hda_codec *codec) 568c70461bSLucas Tanure { 578c70461bSLucas Tanure struct cs8409_spec *spec; 588c70461bSLucas Tanure 598c70461bSLucas Tanure spec = kzalloc(sizeof(*spec), GFP_KERNEL); 608c70461bSLucas Tanure if (!spec) 618c70461bSLucas Tanure return NULL; 628c70461bSLucas Tanure codec->spec = spec; 63647d50a0SLucas Tanure spec->codec = codec; 648c70461bSLucas Tanure codec->power_save_node = 1; 65636eb9d2SLucas Tanure mutex_init(&spec->i2c_mux); 66647d50a0SLucas Tanure INIT_DELAYED_WORK(&spec->i2c_clk_work, cs8409_disable_i2c_clock_worker); 678c70461bSLucas Tanure snd_hda_gen_spec_init(&spec->gen); 688c70461bSLucas Tanure 698c70461bSLucas Tanure return spec; 708c70461bSLucas Tanure } 718c70461bSLucas Tanure 728c70461bSLucas Tanure static inline int cs8409_vendor_coef_get(struct hda_codec *codec, unsigned int idx) 738c70461bSLucas Tanure { 74ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); 75ccff0064SStefan Binding return snd_hda_codec_read(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_GET_PROC_COEF, 0); 768c70461bSLucas Tanure } 778c70461bSLucas Tanure 788c70461bSLucas Tanure static inline void cs8409_vendor_coef_set(struct hda_codec *codec, unsigned int idx, 798c70461bSLucas Tanure unsigned int coef) 808c70461bSLucas Tanure { 81ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_COEF_INDEX, idx); 82ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_VENDOR_WIDGET, 0, AC_VERB_SET_PROC_COEF, coef); 838c70461bSLucas Tanure } 848c70461bSLucas Tanure 85647d50a0SLucas Tanure /* 86647d50a0SLucas Tanure * cs8409_enable_i2c_clock - Disable I2C clocks 87647d50a0SLucas Tanure * @codec: the codec instance 88647d50a0SLucas Tanure * Disable I2C clocks. 89647d50a0SLucas Tanure * This must be called when the i2c mutex is unlocked. 90647d50a0SLucas Tanure */ 91647d50a0SLucas Tanure static void cs8409_disable_i2c_clock(struct hda_codec *codec) 92647d50a0SLucas Tanure { 93647d50a0SLucas Tanure struct cs8409_spec *spec = codec->spec; 94647d50a0SLucas Tanure 95165b81c4SLucas Tanure mutex_lock(&spec->i2c_mux); 96647d50a0SLucas Tanure if (spec->i2c_clck_enabled) { 97647d50a0SLucas Tanure cs8409_vendor_coef_set(spec->codec, 0x0, 98647d50a0SLucas Tanure cs8409_vendor_coef_get(spec->codec, 0x0) & 0xfffffff7); 99647d50a0SLucas Tanure spec->i2c_clck_enabled = 0; 100647d50a0SLucas Tanure } 101165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 102647d50a0SLucas Tanure } 103647d50a0SLucas Tanure 104647d50a0SLucas Tanure /* 105647d50a0SLucas Tanure * cs8409_disable_i2c_clock_worker - Worker that disable the I2C Clock after 25ms without use 106647d50a0SLucas Tanure */ 107647d50a0SLucas Tanure static void cs8409_disable_i2c_clock_worker(struct work_struct *work) 108647d50a0SLucas Tanure { 109647d50a0SLucas Tanure struct cs8409_spec *spec = container_of(work, struct cs8409_spec, i2c_clk_work.work); 110647d50a0SLucas Tanure 111647d50a0SLucas Tanure cs8409_disable_i2c_clock(spec->codec); 112647d50a0SLucas Tanure } 113647d50a0SLucas Tanure 114647d50a0SLucas Tanure /* 1158c70461bSLucas Tanure * cs8409_enable_i2c_clock - Enable I2C clocks 1168c70461bSLucas Tanure * @codec: the codec instance 117647d50a0SLucas Tanure * Enable I2C clocks. 118647d50a0SLucas Tanure * This must be called when the i2c mutex is locked. 1198c70461bSLucas Tanure */ 120647d50a0SLucas Tanure static void cs8409_enable_i2c_clock(struct hda_codec *codec) 1218c70461bSLucas Tanure { 122647d50a0SLucas Tanure struct cs8409_spec *spec = codec->spec; 1238c70461bSLucas Tanure 124647d50a0SLucas Tanure /* Cancel the disable timer, but do not wait for any running disable functions to finish. 125647d50a0SLucas Tanure * If the disable timer runs out before cancel, the delayed work thread will be blocked, 126647d50a0SLucas Tanure * waiting for the mutex to become unlocked. This mutex will be locked for the duration of 127647d50a0SLucas Tanure * any i2c transaction, so the disable function will run to completion immediately 128647d50a0SLucas Tanure * afterwards in the scenario. The next enable call will re-enable the clock, regardless. 129647d50a0SLucas Tanure */ 130647d50a0SLucas Tanure cancel_delayed_work(&spec->i2c_clk_work); 131647d50a0SLucas Tanure 132647d50a0SLucas Tanure if (!spec->i2c_clck_enabled) { 133647d50a0SLucas Tanure cs8409_vendor_coef_set(codec, 0x0, cs8409_vendor_coef_get(codec, 0x0) | 0x8); 134647d50a0SLucas Tanure spec->i2c_clck_enabled = 1; 135647d50a0SLucas Tanure } 136647d50a0SLucas Tanure queue_delayed_work(system_power_efficient_wq, &spec->i2c_clk_work, msecs_to_jiffies(25)); 1378c70461bSLucas Tanure } 1388c70461bSLucas Tanure 1398c70461bSLucas Tanure /** 1408c70461bSLucas Tanure * cs8409_i2c_wait_complete - Wait for I2C transaction 1418c70461bSLucas Tanure * @codec: the codec instance 1428c70461bSLucas Tanure * 1438c70461bSLucas Tanure * Wait for I2C transaction to complete. 144928adf0eSStefan Binding * Return -ETIMEDOUT if transaction wait times out. 1458c70461bSLucas Tanure */ 1468c70461bSLucas Tanure static int cs8409_i2c_wait_complete(struct hda_codec *codec) 1478c70461bSLucas Tanure { 1488c70461bSLucas Tanure unsigned int retval; 1498c70461bSLucas Tanure 150928adf0eSStefan Binding return read_poll_timeout(cs8409_vendor_coef_get, retval, retval & 0x18, 151928adf0eSStefan Binding CS42L42_I2C_SLEEP_US, CS42L42_I2C_TIMEOUT_US, false, codec, CS8409_I2C_STS); 1528c70461bSLucas Tanure } 1538c70461bSLucas Tanure 1548c70461bSLucas Tanure /** 155d395fd78SLucas Tanure * cs8409_set_i2c_dev_addr - Set i2c address for transaction 156d395fd78SLucas Tanure * @codec: the codec instance 157d395fd78SLucas Tanure * @addr: I2C Address 158d395fd78SLucas Tanure */ 159d395fd78SLucas Tanure static void cs8409_set_i2c_dev_addr(struct hda_codec *codec, unsigned int addr) 160d395fd78SLucas Tanure { 161d395fd78SLucas Tanure struct cs8409_spec *spec = codec->spec; 162d395fd78SLucas Tanure 163d395fd78SLucas Tanure if (spec->dev_addr != addr) { 164d395fd78SLucas Tanure cs8409_vendor_coef_set(codec, CS8409_I2C_ADDR, addr); 165d395fd78SLucas Tanure spec->dev_addr = addr; 166d395fd78SLucas Tanure } 167d395fd78SLucas Tanure } 168d395fd78SLucas Tanure 169d395fd78SLucas Tanure /** 1708de4e5a6SLucas Tanure * cs8409_i2c_set_page - CS8409 I2C set page register. 17124f7ac3dSLucas Tanure * @scodec: the codec instance 1728de4e5a6SLucas Tanure * @i2c_reg: Page register 1738de4e5a6SLucas Tanure * 1748de4e5a6SLucas Tanure * Returns negative on error. 1758de4e5a6SLucas Tanure */ 17624f7ac3dSLucas Tanure static int cs8409_i2c_set_page(struct sub_codec *scodec, unsigned int i2c_reg) 1778de4e5a6SLucas Tanure { 17824f7ac3dSLucas Tanure struct hda_codec *codec = scodec->codec; 1798de4e5a6SLucas Tanure 18024f7ac3dSLucas Tanure if (scodec->paged && (scodec->last_page != (i2c_reg >> 8))) { 1818de4e5a6SLucas Tanure cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg >> 8); 1828de4e5a6SLucas Tanure if (cs8409_i2c_wait_complete(codec) < 0) 1838de4e5a6SLucas Tanure return -EIO; 18424f7ac3dSLucas Tanure scodec->last_page = i2c_reg >> 8; 1858de4e5a6SLucas Tanure } 1868de4e5a6SLucas Tanure 1878de4e5a6SLucas Tanure return 0; 1888de4e5a6SLucas Tanure } 1898de4e5a6SLucas Tanure 1908de4e5a6SLucas Tanure /** 1918c70461bSLucas Tanure * cs8409_i2c_read - CS8409 I2C Read. 19224f7ac3dSLucas Tanure * @scodec: the codec instance 193165b81c4SLucas Tanure * @addr: Register to read 1948c70461bSLucas Tanure * 1958c70461bSLucas Tanure * Returns negative on error, otherwise returns read value in bits 0-7. 1968c70461bSLucas Tanure */ 19724f7ac3dSLucas Tanure static int cs8409_i2c_read(struct sub_codec *scodec, unsigned int addr) 1988c70461bSLucas Tanure { 19924f7ac3dSLucas Tanure struct hda_codec *codec = scodec->codec; 200a1a6c7dfSLucas Tanure struct cs8409_spec *spec = codec->spec; 2018c70461bSLucas Tanure unsigned int i2c_reg_data; 2028c70461bSLucas Tanure unsigned int read_data; 2038c70461bSLucas Tanure 20424f7ac3dSLucas Tanure if (scodec->suspended) 205a1a6c7dfSLucas Tanure return -EPERM; 206a1a6c7dfSLucas Tanure 207165b81c4SLucas Tanure mutex_lock(&spec->i2c_mux); 208647d50a0SLucas Tanure cs8409_enable_i2c_clock(codec); 20924f7ac3dSLucas Tanure cs8409_set_i2c_dev_addr(codec, scodec->addr); 2108c70461bSLucas Tanure 21124f7ac3dSLucas Tanure if (cs8409_i2c_set_page(scodec, addr)) 21224f7ac3dSLucas Tanure goto error; 2138c70461bSLucas Tanure 214165b81c4SLucas Tanure i2c_reg_data = (addr << 8) & 0x0ffff; 215ccff0064SStefan Binding cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); 216165b81c4SLucas Tanure if (cs8409_i2c_wait_complete(codec) < 0) 217165b81c4SLucas Tanure goto error; 2188c70461bSLucas Tanure 2198c70461bSLucas Tanure /* Register in bits 15-8 and the data in 7-0 */ 220ccff0064SStefan Binding read_data = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD); 2218c70461bSLucas Tanure 222165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 2234ff2ae3aSStefan Binding 2248c70461bSLucas Tanure return read_data & 0x0ff; 225165b81c4SLucas Tanure 226165b81c4SLucas Tanure error: 227165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 22824f7ac3dSLucas Tanure codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); 229165b81c4SLucas Tanure return -EIO; 230165b81c4SLucas Tanure } 231165b81c4SLucas Tanure 232165b81c4SLucas Tanure /** 233165b81c4SLucas Tanure * cs8409_i2c_bulk_read - CS8409 I2C Read Sequence. 23424f7ac3dSLucas Tanure * @scodec: the codec instance 235165b81c4SLucas Tanure * @seq: Register Sequence to read 236165b81c4SLucas Tanure * @count: Number of registeres to read 237165b81c4SLucas Tanure * 238165b81c4SLucas Tanure * Returns negative on error, values are read into value element of cs8409_i2c_param sequence. 239165b81c4SLucas Tanure */ 24024f7ac3dSLucas Tanure static int cs8409_i2c_bulk_read(struct sub_codec *scodec, struct cs8409_i2c_param *seq, int count) 241165b81c4SLucas Tanure { 24224f7ac3dSLucas Tanure struct hda_codec *codec = scodec->codec; 243165b81c4SLucas Tanure struct cs8409_spec *spec = codec->spec; 244165b81c4SLucas Tanure unsigned int i2c_reg_data; 245165b81c4SLucas Tanure int i; 246165b81c4SLucas Tanure 24724f7ac3dSLucas Tanure if (scodec->suspended) 248165b81c4SLucas Tanure return -EPERM; 249165b81c4SLucas Tanure 250165b81c4SLucas Tanure mutex_lock(&spec->i2c_mux); 25124f7ac3dSLucas Tanure cs8409_set_i2c_dev_addr(codec, scodec->addr); 252165b81c4SLucas Tanure 253165b81c4SLucas Tanure for (i = 0; i < count; i++) { 254165b81c4SLucas Tanure cs8409_enable_i2c_clock(codec); 25524f7ac3dSLucas Tanure if (cs8409_i2c_set_page(scodec, seq[i].addr)) 256165b81c4SLucas Tanure goto error; 257165b81c4SLucas Tanure 258165b81c4SLucas Tanure i2c_reg_data = (seq[i].addr << 8) & 0x0ffff; 259165b81c4SLucas Tanure cs8409_vendor_coef_set(codec, CS8409_I2C_QREAD, i2c_reg_data); 260165b81c4SLucas Tanure 261165b81c4SLucas Tanure if (cs8409_i2c_wait_complete(codec) < 0) 262165b81c4SLucas Tanure goto error; 263165b81c4SLucas Tanure 264165b81c4SLucas Tanure seq[i].value = cs8409_vendor_coef_get(codec, CS8409_I2C_QREAD) & 0xff; 265165b81c4SLucas Tanure } 266165b81c4SLucas Tanure 267165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 268165b81c4SLucas Tanure 269165b81c4SLucas Tanure return 0; 270165b81c4SLucas Tanure 271165b81c4SLucas Tanure error: 272165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 27324f7ac3dSLucas Tanure codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr); 274165b81c4SLucas Tanure return -EIO; 2758c70461bSLucas Tanure } 2768c70461bSLucas Tanure 2778c70461bSLucas Tanure /** 2788c70461bSLucas Tanure * cs8409_i2c_write - CS8409 I2C Write. 27924f7ac3dSLucas Tanure * @scodec: the codec instance 280165b81c4SLucas Tanure * @addr: Register to write to 281165b81c4SLucas Tanure * @value: Data to write 2828c70461bSLucas Tanure * 2838c70461bSLucas Tanure * Returns negative on error, otherwise returns 0. 2848c70461bSLucas Tanure */ 28524f7ac3dSLucas Tanure static int cs8409_i2c_write(struct sub_codec *scodec, unsigned int addr, unsigned int value) 2868c70461bSLucas Tanure { 28724f7ac3dSLucas Tanure struct hda_codec *codec = scodec->codec; 288a1a6c7dfSLucas Tanure struct cs8409_spec *spec = codec->spec; 2898c70461bSLucas Tanure unsigned int i2c_reg_data; 2908c70461bSLucas Tanure 29124f7ac3dSLucas Tanure if (scodec->suspended) 292a1a6c7dfSLucas Tanure return -EPERM; 293a1a6c7dfSLucas Tanure 294165b81c4SLucas Tanure mutex_lock(&spec->i2c_mux); 295165b81c4SLucas Tanure 296647d50a0SLucas Tanure cs8409_enable_i2c_clock(codec); 29724f7ac3dSLucas Tanure cs8409_set_i2c_dev_addr(codec, scodec->addr); 2988c70461bSLucas Tanure 29924f7ac3dSLucas Tanure if (cs8409_i2c_set_page(scodec, addr)) 30024f7ac3dSLucas Tanure goto error; 3018c70461bSLucas Tanure 302165b81c4SLucas Tanure i2c_reg_data = ((addr << 8) & 0x0ff00) | (value & 0x0ff); 303ccff0064SStefan Binding cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); 3048c70461bSLucas Tanure 305165b81c4SLucas Tanure if (cs8409_i2c_wait_complete(codec) < 0) 306165b81c4SLucas Tanure goto error; 307165b81c4SLucas Tanure 308165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 309165b81c4SLucas Tanure return 0; 310165b81c4SLucas Tanure 311165b81c4SLucas Tanure error: 312165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 31324f7ac3dSLucas Tanure codec_err(codec, "%s() Failed 0x%02x : 0x%04x\n", __func__, scodec->addr, addr); 3148c70461bSLucas Tanure return -EIO; 3158c70461bSLucas Tanure } 3168c70461bSLucas Tanure 317165b81c4SLucas Tanure /** 318165b81c4SLucas Tanure * cs8409_i2c_bulk_write - CS8409 I2C Write Sequence. 31924f7ac3dSLucas Tanure * @scodec: the codec instance 320165b81c4SLucas Tanure * @seq: Register Sequence to write 321165b81c4SLucas Tanure * @count: Number of registeres to write 322165b81c4SLucas Tanure * 323165b81c4SLucas Tanure * Returns negative on error. 324165b81c4SLucas Tanure */ 32524f7ac3dSLucas Tanure static int cs8409_i2c_bulk_write(struct sub_codec *scodec, const struct cs8409_i2c_param *seq, 32624f7ac3dSLucas Tanure int count) 327165b81c4SLucas Tanure { 32824f7ac3dSLucas Tanure struct hda_codec *codec = scodec->codec; 329165b81c4SLucas Tanure struct cs8409_spec *spec = codec->spec; 330165b81c4SLucas Tanure unsigned int i2c_reg_data; 331165b81c4SLucas Tanure int i; 332165b81c4SLucas Tanure 33324f7ac3dSLucas Tanure if (scodec->suspended) 334165b81c4SLucas Tanure return -EPERM; 335165b81c4SLucas Tanure 336165b81c4SLucas Tanure mutex_lock(&spec->i2c_mux); 33724f7ac3dSLucas Tanure cs8409_set_i2c_dev_addr(codec, scodec->addr); 338165b81c4SLucas Tanure 339165b81c4SLucas Tanure for (i = 0; i < count; i++) { 340165b81c4SLucas Tanure cs8409_enable_i2c_clock(codec); 34124f7ac3dSLucas Tanure if (cs8409_i2c_set_page(scodec, seq[i].addr)) 342165b81c4SLucas Tanure goto error; 343165b81c4SLucas Tanure 344165b81c4SLucas Tanure i2c_reg_data = ((seq[i].addr << 8) & 0x0ff00) | (seq[i].value & 0x0ff); 345165b81c4SLucas Tanure cs8409_vendor_coef_set(codec, CS8409_I2C_QWRITE, i2c_reg_data); 346165b81c4SLucas Tanure 347165b81c4SLucas Tanure if (cs8409_i2c_wait_complete(codec) < 0) 348165b81c4SLucas Tanure goto error; 349165b81c4SLucas Tanure } 350165b81c4SLucas Tanure 351165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 352165b81c4SLucas Tanure 3538c70461bSLucas Tanure return 0; 354165b81c4SLucas Tanure 355165b81c4SLucas Tanure error: 356165b81c4SLucas Tanure mutex_unlock(&spec->i2c_mux); 35724f7ac3dSLucas Tanure codec_err(codec, "I2C Bulk Write Failed 0x%02x\n", scodec->addr); 358165b81c4SLucas Tanure return -EIO; 3598c70461bSLucas Tanure } 3608c70461bSLucas Tanure 361636eb9d2SLucas Tanure static int cs8409_init(struct hda_codec *codec) 362636eb9d2SLucas Tanure { 363636eb9d2SLucas Tanure int ret = snd_hda_gen_init(codec); 364636eb9d2SLucas Tanure 365636eb9d2SLucas Tanure if (!ret) 366636eb9d2SLucas Tanure snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_INIT); 367636eb9d2SLucas Tanure 368636eb9d2SLucas Tanure return ret; 369636eb9d2SLucas Tanure } 370636eb9d2SLucas Tanure 371636eb9d2SLucas Tanure static int cs8409_build_controls(struct hda_codec *codec) 372636eb9d2SLucas Tanure { 373636eb9d2SLucas Tanure int err; 374636eb9d2SLucas Tanure 375636eb9d2SLucas Tanure err = snd_hda_gen_build_controls(codec); 376636eb9d2SLucas Tanure if (err < 0) 377636eb9d2SLucas Tanure return err; 378636eb9d2SLucas Tanure snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_BUILD); 379636eb9d2SLucas Tanure 380636eb9d2SLucas Tanure return 0; 381636eb9d2SLucas Tanure } 382636eb9d2SLucas Tanure 383c076e201SStefan Binding /* Enable/Disable Unsolicited Response */ 384636eb9d2SLucas Tanure static void cs8409_enable_ur(struct hda_codec *codec, int flag) 385636eb9d2SLucas Tanure { 386c076e201SStefan Binding struct cs8409_spec *spec = codec->spec; 387c076e201SStefan Binding unsigned int ur_gpios = 0; 388c076e201SStefan Binding int i; 389c076e201SStefan Binding 390c076e201SStefan Binding for (i = 0; i < spec->num_scodecs; i++) 391c076e201SStefan Binding ur_gpios |= spec->scodecs[i]->irq_mask; 392c076e201SStefan Binding 393636eb9d2SLucas Tanure snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK, 394c076e201SStefan Binding flag ? ur_gpios : 0); 395636eb9d2SLucas Tanure 396636eb9d2SLucas Tanure snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_UNSOLICITED_ENABLE, 397636eb9d2SLucas Tanure flag ? AC_UNSOL_ENABLED : 0); 398636eb9d2SLucas Tanure } 399636eb9d2SLucas Tanure 400636eb9d2SLucas Tanure static void cs8409_fix_caps(struct hda_codec *codec, unsigned int nid) 401636eb9d2SLucas Tanure { 402636eb9d2SLucas Tanure int caps; 403636eb9d2SLucas Tanure 404636eb9d2SLucas Tanure /* CS8409 is simple HDA bridge and intended to be used with a remote 405636eb9d2SLucas Tanure * companion codec. Most of input/output PIN(s) have only basic 406636eb9d2SLucas Tanure * capabilities. Receive and Transmit NID(s) have only OUTC and INC 407636eb9d2SLucas Tanure * capabilities and no presence detect capable (PDC) and call to 408636eb9d2SLucas Tanure * snd_hda_gen_build_controls() will mark them as non detectable 409636eb9d2SLucas Tanure * phantom jacks. However, a companion codec may be 410636eb9d2SLucas Tanure * connected to these pins which supports jack detect 411636eb9d2SLucas Tanure * capabilities. We have to override pin capabilities, 412636eb9d2SLucas Tanure * otherwise they will not be created as input devices. 413636eb9d2SLucas Tanure */ 414636eb9d2SLucas Tanure caps = snd_hdac_read_parm(&codec->core, nid, AC_PAR_PIN_CAP); 415636eb9d2SLucas Tanure if (caps >= 0) 416636eb9d2SLucas Tanure snd_hdac_override_parm(&codec->core, nid, AC_PAR_PIN_CAP, 417636eb9d2SLucas Tanure (caps | (AC_PINCAP_IMP_SENSE | AC_PINCAP_PRES_DETECT))); 418636eb9d2SLucas Tanure 419636eb9d2SLucas Tanure snd_hda_override_wcaps(codec, nid, (get_wcaps(codec, nid) | AC_WCAP_UNSOL_CAP)); 420636eb9d2SLucas Tanure } 421636eb9d2SLucas Tanure 422f129f26fSStefan Binding static int cs8409_spk_sw_gpio_get(struct snd_kcontrol *kcontrol, 423f129f26fSStefan Binding struct snd_ctl_elem_value *ucontrol) 424f129f26fSStefan Binding { 425f129f26fSStefan Binding struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 426f129f26fSStefan Binding struct cs8409_spec *spec = codec->spec; 427f129f26fSStefan Binding 428f129f26fSStefan Binding ucontrol->value.integer.value[0] = !!(spec->gpio_data & spec->speaker_pdn_gpio); 429f129f26fSStefan Binding return 0; 430f129f26fSStefan Binding } 431f129f26fSStefan Binding 432f129f26fSStefan Binding static int cs8409_spk_sw_gpio_put(struct snd_kcontrol *kcontrol, 433f129f26fSStefan Binding struct snd_ctl_elem_value *ucontrol) 434f129f26fSStefan Binding { 435f129f26fSStefan Binding struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 436f129f26fSStefan Binding struct cs8409_spec *spec = codec->spec; 437f129f26fSStefan Binding unsigned int gpio_data; 438f129f26fSStefan Binding 439f129f26fSStefan Binding gpio_data = (spec->gpio_data & ~spec->speaker_pdn_gpio) | 440f129f26fSStefan Binding (ucontrol->value.integer.value[0] ? spec->speaker_pdn_gpio : 0); 441f129f26fSStefan Binding if (gpio_data == spec->gpio_data) 442f129f26fSStefan Binding return 0; 443f129f26fSStefan Binding spec->gpio_data = gpio_data; 444f129f26fSStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 445f129f26fSStefan Binding return 1; 446f129f26fSStefan Binding } 447f129f26fSStefan Binding 448f129f26fSStefan Binding static const struct snd_kcontrol_new cs8409_spk_sw_ctrl = { 449f129f26fSStefan Binding .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 450f129f26fSStefan Binding .info = snd_ctl_boolean_mono_info, 451f129f26fSStefan Binding .get = cs8409_spk_sw_gpio_get, 452f129f26fSStefan Binding .put = cs8409_spk_sw_gpio_put, 453f129f26fSStefan Binding }; 454f129f26fSStefan Binding 455636eb9d2SLucas Tanure /****************************************************************************** 456636eb9d2SLucas Tanure * CS42L42 Specific Functions 457636eb9d2SLucas Tanure ******************************************************************************/ 458636eb9d2SLucas Tanure 459636eb9d2SLucas Tanure int cs42l42_volume_info(struct snd_kcontrol *kctrl, struct snd_ctl_elem_info *uinfo) 4608c70461bSLucas Tanure { 461b2a88774SLucas Tanure unsigned int ofs = get_amp_offset(kctrl); 4628c70461bSLucas Tanure u8 chs = get_amp_channels(kctrl); 4638c70461bSLucas Tanure 4648c70461bSLucas Tanure uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 465b2a88774SLucas Tanure uinfo->value.integer.step = 1; 4668c70461bSLucas Tanure uinfo->count = chs == 3 ? 2 : 1; 467b2a88774SLucas Tanure 468b2a88774SLucas Tanure switch (ofs) { 469b2a88774SLucas Tanure case CS42L42_VOL_DAC: 470636eb9d2SLucas Tanure uinfo->value.integer.min = CS42L42_HP_VOL_REAL_MIN; 471636eb9d2SLucas Tanure uinfo->value.integer.max = CS42L42_HP_VOL_REAL_MAX; 4728c70461bSLucas Tanure break; 473b2a88774SLucas Tanure case CS42L42_VOL_ADC: 474636eb9d2SLucas Tanure uinfo->value.integer.min = CS42L42_AMIC_VOL_REAL_MIN; 475636eb9d2SLucas Tanure uinfo->value.integer.max = CS42L42_AMIC_VOL_REAL_MAX; 4768c70461bSLucas Tanure break; 4778c70461bSLucas Tanure default: 4788c70461bSLucas Tanure break; 4798c70461bSLucas Tanure } 480b2a88774SLucas Tanure 4818c70461bSLucas Tanure return 0; 4828c70461bSLucas Tanure } 4838c70461bSLucas Tanure 484636eb9d2SLucas Tanure int cs42l42_volume_get(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) 4858c70461bSLucas Tanure { 4868c70461bSLucas Tanure struct hda_codec *codec = snd_kcontrol_chip(kctrl); 4878c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 48824f7ac3dSLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; 4898c70461bSLucas Tanure int chs = get_amp_channels(kctrl); 490b2a88774SLucas Tanure unsigned int ofs = get_amp_offset(kctrl); 4918c70461bSLucas Tanure long *valp = uctrl->value.integer.value; 4928c70461bSLucas Tanure 493b2a88774SLucas Tanure switch (ofs) { 494b2a88774SLucas Tanure case CS42L42_VOL_DAC: 4958c70461bSLucas Tanure if (chs & BIT(0)) 49624f7ac3dSLucas Tanure *valp++ = cs42l42->vol[ofs]; 4978c70461bSLucas Tanure if (chs & BIT(1)) 49824f7ac3dSLucas Tanure *valp = cs42l42->vol[ofs+1]; 4998c70461bSLucas Tanure break; 500b2a88774SLucas Tanure case CS42L42_VOL_ADC: 5018c70461bSLucas Tanure if (chs & BIT(0)) 50224f7ac3dSLucas Tanure *valp = cs42l42->vol[ofs]; 5038c70461bSLucas Tanure break; 5048c70461bSLucas Tanure default: 5058c70461bSLucas Tanure break; 5068c70461bSLucas Tanure } 507b2a88774SLucas Tanure 5088c70461bSLucas Tanure return 0; 5098c70461bSLucas Tanure } 5108c70461bSLucas Tanure 5117482ec71SStefan Binding static void cs42l42_mute(struct sub_codec *cs42l42, int vol_type, 5127482ec71SStefan Binding unsigned int chs, bool mute) 5137482ec71SStefan Binding { 5147482ec71SStefan Binding if (mute) { 5157482ec71SStefan Binding if (vol_type == CS42L42_VOL_DAC) { 5167482ec71SStefan Binding if (chs & BIT(0)) 5179cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 0x3f); 5187482ec71SStefan Binding if (chs & BIT(1)) 5199cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 0x3f); 5207482ec71SStefan Binding } else if (vol_type == CS42L42_VOL_ADC) { 5217482ec71SStefan Binding if (chs & BIT(0)) 5229cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 0x9f); 5237482ec71SStefan Binding } 5247482ec71SStefan Binding } else { 5257482ec71SStefan Binding if (vol_type == CS42L42_VOL_DAC) { 5267482ec71SStefan Binding if (chs & BIT(0)) 5279cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHA_VOL, 5287482ec71SStefan Binding -(cs42l42->vol[CS42L42_DAC_CH0_VOL_OFFSET]) 5299cd82738SStefan Binding & CS42L42_MIXER_CH_VOL_MASK); 5307482ec71SStefan Binding if (chs & BIT(1)) 5319cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_MIXER_CHB_VOL, 5327482ec71SStefan Binding -(cs42l42->vol[CS42L42_DAC_CH1_VOL_OFFSET]) 5339cd82738SStefan Binding & CS42L42_MIXER_CH_VOL_MASK); 5347482ec71SStefan Binding } else if (vol_type == CS42L42_VOL_ADC) { 5357482ec71SStefan Binding if (chs & BIT(0)) 5369cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_ADC_VOLUME, 5377482ec71SStefan Binding cs42l42->vol[CS42L42_ADC_VOL_OFFSET] 5387482ec71SStefan Binding & CS42L42_REG_AMIC_VOL_MASK); 5397482ec71SStefan Binding } 5407482ec71SStefan Binding } 5417482ec71SStefan Binding } 5427482ec71SStefan Binding 543636eb9d2SLucas Tanure int cs42l42_volume_put(struct snd_kcontrol *kctrl, struct snd_ctl_elem_value *uctrl) 5448c70461bSLucas Tanure { 5458c70461bSLucas Tanure struct hda_codec *codec = snd_kcontrol_chip(kctrl); 5468c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 54724f7ac3dSLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[get_amp_index(kctrl)]; 5488c70461bSLucas Tanure int chs = get_amp_channels(kctrl); 549b2a88774SLucas Tanure unsigned int ofs = get_amp_offset(kctrl); 5508c70461bSLucas Tanure long *valp = uctrl->value.integer.value; 5518c70461bSLucas Tanure 552b2a88774SLucas Tanure switch (ofs) { 553b2a88774SLucas Tanure case CS42L42_VOL_DAC: 5547482ec71SStefan Binding if (chs & BIT(0)) 55524f7ac3dSLucas Tanure cs42l42->vol[ofs] = *valp; 5568c70461bSLucas Tanure if (chs & BIT(1)) { 557b2a88774SLucas Tanure valp++; 5587482ec71SStefan Binding cs42l42->vol[ofs + 1] = *valp; 5598c70461bSLucas Tanure } 5607482ec71SStefan Binding if (spec->playback_started) 5617482ec71SStefan Binding cs42l42_mute(cs42l42, CS42L42_VOL_DAC, chs, false); 5628c70461bSLucas Tanure break; 563b2a88774SLucas Tanure case CS42L42_VOL_ADC: 5647482ec71SStefan Binding if (chs & BIT(0)) 56524f7ac3dSLucas Tanure cs42l42->vol[ofs] = *valp; 5667482ec71SStefan Binding if (spec->capture_started) 5677482ec71SStefan Binding cs42l42_mute(cs42l42, CS42L42_VOL_ADC, chs, false); 5688c70461bSLucas Tanure break; 5698c70461bSLucas Tanure default: 5708c70461bSLucas Tanure break; 5718c70461bSLucas Tanure } 572b2a88774SLucas Tanure 573b2a88774SLucas Tanure return 0; 5748c70461bSLucas Tanure } 5758c70461bSLucas Tanure 5767482ec71SStefan Binding static void cs42l42_playback_pcm_hook(struct hda_pcm_stream *hinfo, 5777482ec71SStefan Binding struct hda_codec *codec, 5787482ec71SStefan Binding struct snd_pcm_substream *substream, 5797482ec71SStefan Binding int action) 5807482ec71SStefan Binding { 5817482ec71SStefan Binding struct cs8409_spec *spec = codec->spec; 5827482ec71SStefan Binding struct sub_codec *cs42l42; 5837482ec71SStefan Binding int i; 5847482ec71SStefan Binding bool mute; 5857482ec71SStefan Binding 5867482ec71SStefan Binding switch (action) { 5877482ec71SStefan Binding case HDA_GEN_PCM_ACT_PREPARE: 5887482ec71SStefan Binding mute = false; 5897482ec71SStefan Binding spec->playback_started = 1; 5907482ec71SStefan Binding break; 5917482ec71SStefan Binding case HDA_GEN_PCM_ACT_CLEANUP: 5927482ec71SStefan Binding mute = true; 5937482ec71SStefan Binding spec->playback_started = 0; 5947482ec71SStefan Binding break; 5957482ec71SStefan Binding default: 5967482ec71SStefan Binding return; 5977482ec71SStefan Binding } 5987482ec71SStefan Binding 5997482ec71SStefan Binding for (i = 0; i < spec->num_scodecs; i++) { 6007482ec71SStefan Binding cs42l42 = spec->scodecs[i]; 6017482ec71SStefan Binding cs42l42_mute(cs42l42, CS42L42_VOL_DAC, 0x3, mute); 6027482ec71SStefan Binding } 6037482ec71SStefan Binding } 6047482ec71SStefan Binding 6057482ec71SStefan Binding static void cs42l42_capture_pcm_hook(struct hda_pcm_stream *hinfo, 6067482ec71SStefan Binding struct hda_codec *codec, 6077482ec71SStefan Binding struct snd_pcm_substream *substream, 6087482ec71SStefan Binding int action) 6097482ec71SStefan Binding { 6107482ec71SStefan Binding struct cs8409_spec *spec = codec->spec; 6117482ec71SStefan Binding struct sub_codec *cs42l42; 6127482ec71SStefan Binding int i; 6137482ec71SStefan Binding bool mute; 6147482ec71SStefan Binding 6157482ec71SStefan Binding switch (action) { 6167482ec71SStefan Binding case HDA_GEN_PCM_ACT_PREPARE: 6177482ec71SStefan Binding mute = false; 6187482ec71SStefan Binding spec->capture_started = 1; 6197482ec71SStefan Binding break; 6207482ec71SStefan Binding case HDA_GEN_PCM_ACT_CLEANUP: 6217482ec71SStefan Binding mute = true; 6227482ec71SStefan Binding spec->capture_started = 0; 6237482ec71SStefan Binding break; 6247482ec71SStefan Binding default: 6257482ec71SStefan Binding return; 6267482ec71SStefan Binding } 6277482ec71SStefan Binding 6287482ec71SStefan Binding for (i = 0; i < spec->num_scodecs; i++) { 6297482ec71SStefan Binding cs42l42 = spec->scodecs[i]; 6307482ec71SStefan Binding cs42l42_mute(cs42l42, CS42L42_VOL_ADC, 0x3, mute); 6317482ec71SStefan Binding } 6327482ec71SStefan Binding } 6337482ec71SStefan Binding 6348c70461bSLucas Tanure /* Configure CS42L42 slave codec for jack autodetect */ 63524f7ac3dSLucas Tanure static void cs42l42_enable_jack_detect(struct sub_codec *cs42l42) 6368c70461bSLucas Tanure { 6379cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSBIAS_SC_AUTOCTL, cs42l42->hsbias_hiz); 6388c70461bSLucas Tanure /* Clear WAKE# */ 6399cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C1); 6408c70461bSLucas Tanure /* Wait ~2.5ms */ 6418c70461bSLucas Tanure usleep_range(2500, 3000); 6428c70461bSLucas Tanure /* Set mode WAKE# output follows the combination logic directly */ 6439cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_WAKE_CTL, 0x00C0); 6448c70461bSLucas Tanure /* Clear interrupts status */ 6459cd82738SStefan Binding cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 6468c70461bSLucas Tanure /* Enable interrupt */ 6479cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); 6488c70461bSLucas Tanure } 6498c70461bSLucas Tanure 6508c70461bSLucas Tanure /* Enable and run CS42L42 slave codec jack auto detect */ 65124f7ac3dSLucas Tanure static void cs42l42_run_jack_detect(struct sub_codec *cs42l42) 6528c70461bSLucas Tanure { 6538c70461bSLucas Tanure /* Clear interrupts */ 6549cd82738SStefan Binding cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); 6559cd82738SStefan Binding cs8409_i2c_read(cs42l42, CS42L42_DET_STATUS1); 6569cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xFF); 6579cd82738SStefan Binding cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 6588c70461bSLucas Tanure 6599cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x87); 6609cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x86); 6619cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_MISC_DET_CTL, 0x07); 6629cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFD); 6639cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); 6648cd07657SChristian A. Ehrhardt /* Wait ~20ms*/ 6658cd07657SChristian A. Ehrhardt usleep_range(20000, 25000); 6669cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 0x77); 6679cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0xc0); 6688c70461bSLucas Tanure } 6698c70461bSLucas Tanure 670ec6a8aaaSStefan Binding static int cs42l42_manual_hs_det(struct sub_codec *cs42l42) 671ec6a8aaaSStefan Binding { 672ec6a8aaaSStefan Binding unsigned int hs_det_status; 673ec6a8aaaSStefan Binding unsigned int hs_det_comp1; 674ec6a8aaaSStefan Binding unsigned int hs_det_comp2; 675ec6a8aaaSStefan Binding unsigned int hs_det_sw; 676ec6a8aaaSStefan Binding unsigned int hs_type; 677ec6a8aaaSStefan Binding 678ec6a8aaaSStefan Binding /* Set hs detect to manual, active mode */ 679ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 680ec6a8aaaSStefan Binding (1 << CS42L42_HSDET_CTRL_SHIFT) | 681ec6a8aaaSStefan Binding (0 << CS42L42_HSDET_SET_SHIFT) | 682ec6a8aaaSStefan Binding (0 << CS42L42_HSBIAS_REF_SHIFT) | 683ec6a8aaaSStefan Binding (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 684ec6a8aaaSStefan Binding 685ec6a8aaaSStefan Binding /* Configure HS DET comparator reference levels. */ 686ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 687ec6a8aaaSStefan Binding (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) | 688ec6a8aaaSStefan Binding (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT)); 689ec6a8aaaSStefan Binding 690ec6a8aaaSStefan Binding /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */ 691ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1); 692ec6a8aaaSStefan Binding 693ec6a8aaaSStefan Binding msleep(100); 694ec6a8aaaSStefan Binding 695ec6a8aaaSStefan Binding hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 696ec6a8aaaSStefan Binding 697ec6a8aaaSStefan Binding hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 698ec6a8aaaSStefan Binding CS42L42_HSDET_COMP1_OUT_SHIFT; 699ec6a8aaaSStefan Binding hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 700ec6a8aaaSStefan Binding CS42L42_HSDET_COMP2_OUT_SHIFT; 701ec6a8aaaSStefan Binding 702ec6a8aaaSStefan Binding /* Close the SW_HSB_HS3 switch for a Type 2 headset. */ 703ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2); 704ec6a8aaaSStefan Binding 705ec6a8aaaSStefan Binding msleep(100); 706ec6a8aaaSStefan Binding 707ec6a8aaaSStefan Binding hs_det_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 708ec6a8aaaSStefan Binding 709ec6a8aaaSStefan Binding hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >> 710ec6a8aaaSStefan Binding CS42L42_HSDET_COMP1_OUT_SHIFT) << 1; 711ec6a8aaaSStefan Binding hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >> 712ec6a8aaaSStefan Binding CS42L42_HSDET_COMP2_OUT_SHIFT) << 1; 713ec6a8aaaSStefan Binding 714ec6a8aaaSStefan Binding /* Use Comparator 1 with 1.25V Threshold. */ 715ec6a8aaaSStefan Binding switch (hs_det_comp1) { 716ec6a8aaaSStefan Binding case CS42L42_HSDET_COMP_TYPE1: 717ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_CTIA; 718ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE1; 719ec6a8aaaSStefan Binding break; 720ec6a8aaaSStefan Binding case CS42L42_HSDET_COMP_TYPE2: 721ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_OMTP; 722ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE2; 723ec6a8aaaSStefan Binding break; 724ec6a8aaaSStefan Binding default: 725ec6a8aaaSStefan Binding /* Fallback to Comparator 2 with 1.75V Threshold. */ 726ec6a8aaaSStefan Binding switch (hs_det_comp2) { 727ec6a8aaaSStefan Binding case CS42L42_HSDET_COMP_TYPE1: 728ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_CTIA; 729ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE1; 730ec6a8aaaSStefan Binding break; 731ec6a8aaaSStefan Binding case CS42L42_HSDET_COMP_TYPE2: 732ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_OMTP; 733ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE2; 734ec6a8aaaSStefan Binding break; 735ec6a8aaaSStefan Binding case CS42L42_HSDET_COMP_TYPE3: 736ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_HEADPHONE; 737ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE3; 738ec6a8aaaSStefan Binding break; 739ec6a8aaaSStefan Binding default: 740ec6a8aaaSStefan Binding hs_type = CS42L42_PLUG_INVALID; 741ec6a8aaaSStefan Binding hs_det_sw = CS42L42_HSDET_SW_TYPE4; 742ec6a8aaaSStefan Binding break; 743ec6a8aaaSStefan Binding } 744ec6a8aaaSStefan Binding } 745ec6a8aaaSStefan Binding 746ec6a8aaaSStefan Binding /* Set Switches */ 747ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HS_SWITCH_CTL, hs_det_sw); 748ec6a8aaaSStefan Binding 749ec6a8aaaSStefan Binding /* Set HSDET mode to Manual—Disabled */ 750ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 751ec6a8aaaSStefan Binding (0 << CS42L42_HSDET_CTRL_SHIFT) | 752ec6a8aaaSStefan Binding (0 << CS42L42_HSDET_SET_SHIFT) | 753ec6a8aaaSStefan Binding (0 << CS42L42_HSBIAS_REF_SHIFT) | 754ec6a8aaaSStefan Binding (0 << CS42L42_HSDET_AUTO_TIME_SHIFT)); 755ec6a8aaaSStefan Binding 756ec6a8aaaSStefan Binding /* Configure HS DET comparator reference levels. */ 757ec6a8aaaSStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL1, 758ec6a8aaaSStefan Binding (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) | 759ec6a8aaaSStefan Binding (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT)); 760ec6a8aaaSStefan Binding 761ec6a8aaaSStefan Binding return hs_type; 762ec6a8aaaSStefan Binding } 763ec6a8aaaSStefan Binding 764404e770aSStefan Binding static int cs42l42_handle_tip_sense(struct sub_codec *cs42l42, unsigned int reg_ts_status) 765404e770aSStefan Binding { 766ec6a8aaaSStefan Binding int status_changed = 0; 767404e770aSStefan Binding 768404e770aSStefan Binding /* TIP_SENSE INSERT/REMOVE */ 769404e770aSStefan Binding switch (reg_ts_status) { 7709cd82738SStefan Binding case CS42L42_TS_PLUG: 771404e770aSStefan Binding if (cs42l42->no_type_dect) { 772404e770aSStefan Binding status_changed = 1; 773404e770aSStefan Binding cs42l42->hp_jack_in = 1; 774404e770aSStefan Binding cs42l42->mic_jack_in = 0; 775404e770aSStefan Binding } else { 776404e770aSStefan Binding cs42l42_run_jack_detect(cs42l42); 777404e770aSStefan Binding } 778404e770aSStefan Binding break; 779404e770aSStefan Binding 7809cd82738SStefan Binding case CS42L42_TS_UNPLUG: 781404e770aSStefan Binding status_changed = 1; 782404e770aSStefan Binding cs42l42->hp_jack_in = 0; 783404e770aSStefan Binding cs42l42->mic_jack_in = 0; 784404e770aSStefan Binding break; 785404e770aSStefan Binding default: 786404e770aSStefan Binding /* jack in transition */ 787404e770aSStefan Binding break; 788404e770aSStefan Binding } 789404e770aSStefan Binding 790ec6a8aaaSStefan Binding codec_dbg(cs42l42->codec, "Tip Sense Detection: (%d)\n", reg_ts_status); 791ec6a8aaaSStefan Binding 792404e770aSStefan Binding return status_changed; 793404e770aSStefan Binding } 794404e770aSStefan Binding 79524f7ac3dSLucas Tanure static int cs42l42_jack_unsol_event(struct sub_codec *cs42l42) 7968c70461bSLucas Tanure { 7979cd82738SStefan Binding int current_plug_status; 7988c70461bSLucas Tanure int status_changed = 0; 7998c70461bSLucas Tanure int reg_cdc_status; 8008c70461bSLucas Tanure int reg_hs_status; 8018c70461bSLucas Tanure int reg_ts_status; 8028c70461bSLucas Tanure int type; 8038c70461bSLucas Tanure 8048c70461bSLucas Tanure /* Read jack detect status registers */ 8059cd82738SStefan Binding reg_cdc_status = cs8409_i2c_read(cs42l42, CS42L42_CODEC_STATUS); 8069cd82738SStefan Binding reg_hs_status = cs8409_i2c_read(cs42l42, CS42L42_HS_DET_STATUS); 8079cd82738SStefan Binding reg_ts_status = cs8409_i2c_read(cs42l42, CS42L42_TSRS_PLUG_STATUS); 8088c70461bSLucas Tanure 8098c70461bSLucas Tanure /* If status values are < 0, read error has occurred. */ 8108c70461bSLucas Tanure if (reg_cdc_status < 0 || reg_hs_status < 0 || reg_ts_status < 0) 811636eb9d2SLucas Tanure return -EIO; 8128c70461bSLucas Tanure 8139cd82738SStefan Binding current_plug_status = (reg_ts_status & (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) 8149cd82738SStefan Binding >> CS42L42_TS_PLUG_SHIFT; 8159cd82738SStefan Binding 8168c70461bSLucas Tanure /* HSDET_AUTO_DONE */ 8179cd82738SStefan Binding if (reg_cdc_status & CS42L42_HSDET_AUTO_DONE_MASK) { 8188c70461bSLucas Tanure 819db0ae848SStefan Binding /* Disable HSDET_AUTO_DONE */ 8209cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_CODEC_INT_MASK, 0xFF); 821db0ae848SStefan Binding 8229cd82738SStefan Binding type = (reg_hs_status & CS42L42_HSDET_TYPE_MASK) >> CS42L42_HSDET_TYPE_SHIFT; 823404e770aSStefan Binding 8241a048301SStefan Binding /* Configure the HSDET mode. */ 8259cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HSDET_CTL2, 0x80); 826ec6a8aaaSStefan Binding 827ec6a8aaaSStefan Binding if (cs42l42->no_type_dect) { 828ec6a8aaaSStefan Binding status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); 829ec6a8aaaSStefan Binding } else { 830ec6a8aaaSStefan Binding if (type == CS42L42_PLUG_INVALID || type == CS42L42_PLUG_HEADPHONE) { 831ec6a8aaaSStefan Binding codec_dbg(cs42l42->codec, 832ec6a8aaaSStefan Binding "Auto detect value not valid (%d), running manual det\n", 833ec6a8aaaSStefan Binding type); 834ec6a8aaaSStefan Binding type = cs42l42_manual_hs_det(cs42l42); 835ec6a8aaaSStefan Binding } 836ec6a8aaaSStefan Binding 837ec6a8aaaSStefan Binding switch (type) { 838ec6a8aaaSStefan Binding case CS42L42_PLUG_CTIA: 839ec6a8aaaSStefan Binding case CS42L42_PLUG_OMTP: 840ec6a8aaaSStefan Binding status_changed = 1; 841ec6a8aaaSStefan Binding cs42l42->hp_jack_in = 1; 842ec6a8aaaSStefan Binding cs42l42->mic_jack_in = 1; 843ec6a8aaaSStefan Binding break; 844ec6a8aaaSStefan Binding case CS42L42_PLUG_HEADPHONE: 845ec6a8aaaSStefan Binding status_changed = 1; 846ec6a8aaaSStefan Binding cs42l42->hp_jack_in = 1; 847ec6a8aaaSStefan Binding cs42l42->mic_jack_in = 0; 848ec6a8aaaSStefan Binding break; 849ec6a8aaaSStefan Binding default: 850ec6a8aaaSStefan Binding status_changed = 1; 851ec6a8aaaSStefan Binding cs42l42->hp_jack_in = 0; 852ec6a8aaaSStefan Binding cs42l42->mic_jack_in = 0; 853ec6a8aaaSStefan Binding break; 854ec6a8aaaSStefan Binding } 855ec6a8aaaSStefan Binding codec_dbg(cs42l42->codec, "Detection done (%d)\n", type); 856ec6a8aaaSStefan Binding } 857ec6a8aaaSStefan Binding 8581a048301SStefan Binding /* Enable the HPOUT ground clamp and configure the HP pull-down */ 8599cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_DAC_CTL2, 0x02); 860db0ae848SStefan Binding /* Re-Enable Tip Sense Interrupt */ 8619cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_TSRS_PLUG_INT_MASK, 0xF3); 8628c70461bSLucas Tanure } else { 8639cd82738SStefan Binding status_changed = cs42l42_handle_tip_sense(cs42l42, current_plug_status); 8648c70461bSLucas Tanure } 8658c70461bSLucas Tanure 866636eb9d2SLucas Tanure return status_changed; 867636eb9d2SLucas Tanure } 8688c70461bSLucas Tanure 86924f7ac3dSLucas Tanure static void cs42l42_resume(struct sub_codec *cs42l42) 870636eb9d2SLucas Tanure { 871c076e201SStefan Binding struct hda_codec *codec = cs42l42->codec; 872f129f26fSStefan Binding struct cs8409_spec *spec = codec->spec; 873636eb9d2SLucas Tanure struct cs8409_i2c_param irq_regs[] = { 8749cd82738SStefan Binding { CS42L42_CODEC_STATUS, 0x00 }, 8759cd82738SStefan Binding { CS42L42_DET_INT_STATUS1, 0x00 }, 8769cd82738SStefan Binding { CS42L42_DET_INT_STATUS2, 0x00 }, 8779cd82738SStefan Binding { CS42L42_TSRS_PLUG_STATUS, 0x00 }, 878636eb9d2SLucas Tanure }; 879342b6b61SStefan Binding int fsv_old, fsv_new; 880636eb9d2SLucas Tanure 881c076e201SStefan Binding /* Bring CS42L42 out of Reset */ 882f129f26fSStefan Binding spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); 883f129f26fSStefan Binding spec->gpio_data |= cs42l42->reset_gpio; 884f129f26fSStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 885c076e201SStefan Binding usleep_range(10000, 15000); 886c076e201SStefan Binding 88724f7ac3dSLucas Tanure cs42l42->suspended = 0; 888636eb9d2SLucas Tanure 88924f7ac3dSLucas Tanure /* Initialize CS42L42 companion codec */ 89024f7ac3dSLucas Tanure cs8409_i2c_bulk_write(cs42l42, cs42l42->init_seq, cs42l42->init_seq_num); 89199bf5b0bSVitaly Rodionov msleep(CS42L42_INIT_TIMEOUT_MS); 892636eb9d2SLucas Tanure 893636eb9d2SLucas Tanure /* Clear interrupts, by reading interrupt status registers */ 89424f7ac3dSLucas Tanure cs8409_i2c_bulk_read(cs42l42, irq_regs, ARRAY_SIZE(irq_regs)); 89524f7ac3dSLucas Tanure 8969cd82738SStefan Binding fsv_old = cs8409_i2c_read(cs42l42, CS42L42_HP_CTL); 897342b6b61SStefan Binding if (cs42l42->full_scale_vol == CS42L42_FULL_SCALE_VOL_0DB) 898342b6b61SStefan Binding fsv_new = fsv_old & ~CS42L42_FULL_SCALE_VOL_MASK; 899342b6b61SStefan Binding else 900342b6b61SStefan Binding fsv_new = fsv_old & CS42L42_FULL_SCALE_VOL_MASK; 901342b6b61SStefan Binding if (fsv_new != fsv_old) 9029cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_HP_CTL, fsv_new); 90324f7ac3dSLucas Tanure 90465cc4ad6SStefan Binding /* we have to explicitly allow unsol event handling even during the 90565cc4ad6SStefan Binding * resume phase so that the jack event is processed properly 90665cc4ad6SStefan Binding */ 90765cc4ad6SStefan Binding snd_hda_codec_allow_unsol_events(cs42l42->codec); 90865cc4ad6SStefan Binding 90924f7ac3dSLucas Tanure cs42l42_enable_jack_detect(cs42l42); 910636eb9d2SLucas Tanure } 911636eb9d2SLucas Tanure 912636eb9d2SLucas Tanure #ifdef CONFIG_PM 91324f7ac3dSLucas Tanure static void cs42l42_suspend(struct sub_codec *cs42l42) 914636eb9d2SLucas Tanure { 915c076e201SStefan Binding struct hda_codec *codec = cs42l42->codec; 916f129f26fSStefan Binding struct cs8409_spec *spec = codec->spec; 9174ff2ae3aSStefan Binding int reg_cdc_status = 0; 9184ff2ae3aSStefan Binding const struct cs8409_i2c_param cs42l42_pwr_down_seq[] = { 9199cd82738SStefan Binding { CS42L42_DAC_CTL2, 0x02 }, 9209cd82738SStefan Binding { CS42L42_HS_CLAMP_DISABLE, 0x00 }, 9219cd82738SStefan Binding { CS42L42_MIXER_CHA_VOL, 0x3F }, 9229cd82738SStefan Binding { CS42L42_MIXER_ADC_VOL, 0x3F }, 9239cd82738SStefan Binding { CS42L42_MIXER_CHB_VOL, 0x3F }, 9249cd82738SStefan Binding { CS42L42_HP_CTL, 0x0F }, 9259cd82738SStefan Binding { CS42L42_ASP_RX_DAI0_EN, 0x00 }, 9269cd82738SStefan Binding { CS42L42_ASP_CLK_CFG, 0x00 }, 9279cd82738SStefan Binding { CS42L42_PWR_CTL1, 0xFE }, 9289cd82738SStefan Binding { CS42L42_PWR_CTL2, 0x8C }, 9299cd82738SStefan Binding { CS42L42_PWR_CTL1, 0xFF }, 9304ff2ae3aSStefan Binding }; 9314ff2ae3aSStefan Binding 9324ff2ae3aSStefan Binding cs8409_i2c_bulk_write(cs42l42, cs42l42_pwr_down_seq, ARRAY_SIZE(cs42l42_pwr_down_seq)); 9334ff2ae3aSStefan Binding 9344ff2ae3aSStefan Binding if (read_poll_timeout(cs8409_i2c_read, reg_cdc_status, 9354ff2ae3aSStefan Binding (reg_cdc_status & 0x1), CS42L42_PDN_SLEEP_US, CS42L42_PDN_TIMEOUT_US, 9369cd82738SStefan Binding true, cs42l42, CS42L42_CODEC_STATUS) < 0) 9374ff2ae3aSStefan Binding codec_warn(codec, "Timeout waiting for PDN_DONE for CS42L42\n"); 938c076e201SStefan Binding 939636eb9d2SLucas Tanure /* Power down CS42L42 ASP/EQ/MIX/HP */ 9409cd82738SStefan Binding cs8409_i2c_write(cs42l42, CS42L42_PWR_CTL2, 0x9C); 94124f7ac3dSLucas Tanure cs42l42->suspended = 1; 94224f7ac3dSLucas Tanure cs42l42->last_page = 0; 943424e531bSStefan Binding cs42l42->hp_jack_in = 0; 944424e531bSStefan Binding cs42l42->mic_jack_in = 0; 945c076e201SStefan Binding 946c076e201SStefan Binding /* Put CS42L42 into Reset */ 947f129f26fSStefan Binding spec->gpio_data = snd_hda_codec_read(codec, CS8409_PIN_AFG, 0, AC_VERB_GET_GPIO_DATA, 0); 948f129f26fSStefan Binding spec->gpio_data &= ~cs42l42->reset_gpio; 949f129f26fSStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, spec->gpio_data); 950636eb9d2SLucas Tanure } 951636eb9d2SLucas Tanure #endif 952636eb9d2SLucas Tanure 953636eb9d2SLucas Tanure static void cs8409_free(struct hda_codec *codec) 954636eb9d2SLucas Tanure { 955636eb9d2SLucas Tanure struct cs8409_spec *spec = codec->spec; 956636eb9d2SLucas Tanure 957636eb9d2SLucas Tanure /* Cancel i2c clock disable timer, and disable clock if left enabled */ 958636eb9d2SLucas Tanure cancel_delayed_work_sync(&spec->i2c_clk_work); 959636eb9d2SLucas Tanure cs8409_disable_i2c_clock(codec); 960636eb9d2SLucas Tanure 961636eb9d2SLucas Tanure snd_hda_gen_free(codec); 962636eb9d2SLucas Tanure } 963636eb9d2SLucas Tanure 964636eb9d2SLucas Tanure /****************************************************************************** 965636eb9d2SLucas Tanure * BULLSEYE / WARLOCK / CYBORG Specific Functions 966636eb9d2SLucas Tanure * CS8409/CS42L42 967636eb9d2SLucas Tanure ******************************************************************************/ 968636eb9d2SLucas Tanure 969636eb9d2SLucas Tanure /* 970636eb9d2SLucas Tanure * In the case of CS8409 we do not have unsolicited events from NID's 0x24 971636eb9d2SLucas Tanure * and 0x34 where hs mic and hp are connected. Companion codec CS42L42 will 972636eb9d2SLucas Tanure * generate interrupt via gpio 4 to notify jack events. We have to overwrite 973636eb9d2SLucas Tanure * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers 974636eb9d2SLucas Tanure * and then notify status via generic snd_hda_jack_unsol_event() call. 975636eb9d2SLucas Tanure */ 97624f7ac3dSLucas Tanure static void cs8409_cs42l42_jack_unsol_event(struct hda_codec *codec, unsigned int res) 977636eb9d2SLucas Tanure { 978636eb9d2SLucas Tanure struct cs8409_spec *spec = codec->spec; 97924f7ac3dSLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 980636eb9d2SLucas Tanure struct hda_jack_tbl *jk; 981636eb9d2SLucas Tanure 982636eb9d2SLucas Tanure /* jack_unsol_event() will be called every time gpio line changing state. 983636eb9d2SLucas Tanure * In this case gpio4 line goes up as a result of reading interrupt status 984636eb9d2SLucas Tanure * registers in previous cs8409_jack_unsol_event() call. 985636eb9d2SLucas Tanure * We don't need to handle this event, ignoring... 986636eb9d2SLucas Tanure */ 98724f7ac3dSLucas Tanure if (res & cs42l42->irq_mask) 988636eb9d2SLucas Tanure return; 989636eb9d2SLucas Tanure 99024f7ac3dSLucas Tanure if (cs42l42_jack_unsol_event(cs42l42)) { 9918c70461bSLucas Tanure snd_hda_set_pin_ctl(codec, CS8409_CS42L42_SPK_PIN_NID, 99224f7ac3dSLucas Tanure cs42l42->hp_jack_in ? 0 : PIN_OUT); 9938c70461bSLucas Tanure /* Report jack*/ 9948c70461bSLucas Tanure jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_HP_PIN_NID, 0); 995636eb9d2SLucas Tanure if (jk) 9968c70461bSLucas Tanure snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 9978c70461bSLucas Tanure AC_UNSOL_RES_TAG); 9988c70461bSLucas Tanure /* Report jack*/ 9998c70461bSLucas Tanure jk = snd_hda_jack_tbl_get_mst(codec, CS8409_CS42L42_AMIC_PIN_NID, 0); 1000636eb9d2SLucas Tanure if (jk) 10018c70461bSLucas Tanure snd_hda_jack_unsol_event(codec, (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 10028c70461bSLucas Tanure AC_UNSOL_RES_TAG); 10038c70461bSLucas Tanure } 10048c70461bSLucas Tanure } 1005cc7df162SStefan Binding 10068c70461bSLucas Tanure #ifdef CONFIG_PM 10078c70461bSLucas Tanure /* Manage PDREF, when transition to D3hot */ 1008636eb9d2SLucas Tanure static int cs8409_cs42l42_suspend(struct hda_codec *codec) 10098c70461bSLucas Tanure { 10108c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 1011c076e201SStefan Binding int i; 10128c70461bSLucas Tanure 1013424e531bSStefan Binding spec->init_done = 0; 1014424e531bSStefan Binding 1015cc7df162SStefan Binding cs8409_enable_ur(codec, 0); 1016cc7df162SStefan Binding 1017c076e201SStefan Binding for (i = 0; i < spec->num_scodecs; i++) 1018c076e201SStefan Binding cs42l42_suspend(spec->scodecs[i]); 10198c70461bSLucas Tanure 1020647d50a0SLucas Tanure /* Cancel i2c clock disable timer, and disable clock if left enabled */ 1021647d50a0SLucas Tanure cancel_delayed_work_sync(&spec->i2c_clk_work); 1022647d50a0SLucas Tanure cs8409_disable_i2c_clock(codec); 1023647d50a0SLucas Tanure 10248c70461bSLucas Tanure snd_hda_shutup_pins(codec); 10258c70461bSLucas Tanure 10268c70461bSLucas Tanure return 0; 10278c70461bSLucas Tanure } 10288c70461bSLucas Tanure #endif 10298c70461bSLucas Tanure 10308c70461bSLucas Tanure /* Vendor specific HW configuration 10318c70461bSLucas Tanure * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... 10328c70461bSLucas Tanure */ 10338c70461bSLucas Tanure static void cs8409_cs42l42_hw_init(struct hda_codec *codec) 10348c70461bSLucas Tanure { 10358c70461bSLucas Tanure const struct cs8409_cir_param *seq = cs8409_cs42l42_hw_cfg; 10368c70461bSLucas Tanure const struct cs8409_cir_param *seq_bullseye = cs8409_cs42l42_bullseye_atn; 10378c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 103824f7ac3dSLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 10398c70461bSLucas Tanure 10408c70461bSLucas Tanure if (spec->gpio_mask) { 1041ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK, 1042ccff0064SStefan Binding spec->gpio_mask); 1043ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION, 1044ccff0064SStefan Binding spec->gpio_dir); 1045ccff0064SStefan Binding snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, 1046ccff0064SStefan Binding spec->gpio_data); 10478c70461bSLucas Tanure } 10488c70461bSLucas Tanure 10498c70461bSLucas Tanure for (; seq->nid; seq++) 10508c70461bSLucas Tanure cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); 10518c70461bSLucas Tanure 105224f7ac3dSLucas Tanure if (codec->fixup_id == CS8409_BULLSEYE) { 10538c70461bSLucas Tanure for (; seq_bullseye->nid; seq_bullseye++) 10548c70461bSLucas Tanure cs8409_vendor_coef_set(codec, seq_bullseye->cir, seq_bullseye->coeff); 10558c70461bSLucas Tanure } 10568c70461bSLucas Tanure 10576581a045SStefan Binding switch (codec->fixup_id) { 10586581a045SStefan Binding case CS8409_CYBORG: 10596581a045SStefan Binding case CS8409_WARLOCK_MLK_DUAL_MIC: 106024f7ac3dSLucas Tanure /* DMIC1_MO=00b, DMIC1/2_SR=1 */ 10618a772453SStefan Binding cs8409_vendor_coef_set(codec, CS8409_DMIC_CFG, 0x0003); 10626581a045SStefan Binding break; 106322bb8226SStefan Binding case CS8409_ODIN: 106422bb8226SStefan Binding /* ASP1/2_xxx_EN=1, ASP1/2_MCLK_EN=0, DMIC1_SCL_EN=0 */ 106522bb8226SStefan Binding cs8409_vendor_coef_set(codec, CS8409_PAD_CFG_SLW_RATE_CTRL, 0xfc00); 106622bb8226SStefan Binding break; 10676581a045SStefan Binding default: 10686581a045SStefan Binding break; 10696581a045SStefan Binding } 10708c70461bSLucas Tanure 107124f7ac3dSLucas Tanure cs42l42_resume(cs42l42); 10728c70461bSLucas Tanure 10738c70461bSLucas Tanure /* Enable Unsolicited Response */ 10748c70461bSLucas Tanure cs8409_enable_ur(codec, 1); 10758c70461bSLucas Tanure } 10768c70461bSLucas Tanure 10778c70461bSLucas Tanure static const struct hda_codec_ops cs8409_cs42l42_patch_ops = { 10788c70461bSLucas Tanure .build_controls = cs8409_build_controls, 10798c70461bSLucas Tanure .build_pcms = snd_hda_gen_build_pcms, 1080636eb9d2SLucas Tanure .init = cs8409_init, 1081647d50a0SLucas Tanure .free = cs8409_free, 108224f7ac3dSLucas Tanure .unsol_event = cs8409_cs42l42_jack_unsol_event, 10838c70461bSLucas Tanure #ifdef CONFIG_PM 1084636eb9d2SLucas Tanure .suspend = cs8409_cs42l42_suspend, 10858c70461bSLucas Tanure #endif 10868c70461bSLucas Tanure }; 10878c70461bSLucas Tanure 10888c70461bSLucas Tanure static int cs8409_cs42l42_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 10898c70461bSLucas Tanure unsigned int *res) 10908c70461bSLucas Tanure { 10918c70461bSLucas Tanure struct hda_codec *codec = container_of(dev, struct hda_codec, core); 10928c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 109324f7ac3dSLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 10948c70461bSLucas Tanure 10958c70461bSLucas Tanure unsigned int nid = ((cmd >> 20) & 0x07f); 10968c70461bSLucas Tanure unsigned int verb = ((cmd >> 8) & 0x0fff); 10978c70461bSLucas Tanure 10988c70461bSLucas Tanure /* CS8409 pins have no AC_PINSENSE_PRESENCE 10998c70461bSLucas Tanure * capabilities. We have to intercept 2 calls for pins 0x24 and 0x34 11008c70461bSLucas Tanure * and return correct pin sense values for read_pin_sense() call from 11018c70461bSLucas Tanure * hda_jack based on CS42L42 jack detect status. 11028c70461bSLucas Tanure */ 11038c70461bSLucas Tanure switch (nid) { 11048c70461bSLucas Tanure case CS8409_CS42L42_HP_PIN_NID: 11058c70461bSLucas Tanure if (verb == AC_VERB_GET_PIN_SENSE) { 110624f7ac3dSLucas Tanure *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; 11078c70461bSLucas Tanure return 0; 11088c70461bSLucas Tanure } 11098c70461bSLucas Tanure break; 11108c70461bSLucas Tanure case CS8409_CS42L42_AMIC_PIN_NID: 11118c70461bSLucas Tanure if (verb == AC_VERB_GET_PIN_SENSE) { 111224f7ac3dSLucas Tanure *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; 11138c70461bSLucas Tanure return 0; 11148c70461bSLucas Tanure } 11158c70461bSLucas Tanure break; 11168c70461bSLucas Tanure default: 11178c70461bSLucas Tanure break; 11188c70461bSLucas Tanure } 11198c70461bSLucas Tanure 11208c70461bSLucas Tanure return spec->exec_verb(dev, cmd, flags, res); 11218c70461bSLucas Tanure } 11228c70461bSLucas Tanure 11239e7647b5SLucas Tanure void cs8409_cs42l42_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) 11248c70461bSLucas Tanure { 11258c70461bSLucas Tanure struct cs8409_spec *spec = codec->spec; 11268c70461bSLucas Tanure 11278c70461bSLucas Tanure switch (action) { 11288c70461bSLucas Tanure case HDA_FIXUP_ACT_PRE_PROBE: 11298c70461bSLucas Tanure snd_hda_add_verbs(codec, cs8409_cs42l42_init_verbs); 11308c70461bSLucas Tanure /* verb exec op override */ 11318c70461bSLucas Tanure spec->exec_verb = codec->core.exec_verb; 11328c70461bSLucas Tanure codec->core.exec_verb = cs8409_cs42l42_exec_verb; 11338c70461bSLucas Tanure 113424f7ac3dSLucas Tanure spec->scodecs[CS8409_CODEC0] = &cs8409_cs42l42_codec; 113524f7ac3dSLucas Tanure spec->num_scodecs = 1; 113624f7ac3dSLucas Tanure spec->scodecs[CS8409_CODEC0]->codec = codec; 11378c70461bSLucas Tanure codec->patch_ops = cs8409_cs42l42_patch_ops; 11388c70461bSLucas Tanure 11398c70461bSLucas Tanure spec->gen.suppress_auto_mute = 1; 11408c70461bSLucas Tanure spec->gen.no_primary_hp = 1; 11418c70461bSLucas Tanure spec->gen.suppress_vmaster = 1; 11428c70461bSLucas Tanure 1143f129f26fSStefan Binding spec->speaker_pdn_gpio = 0; 1144f129f26fSStefan Binding 11458c70461bSLucas Tanure /* GPIO 5 out, 3,4 in */ 114624f7ac3dSLucas Tanure spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio; 11478c70461bSLucas Tanure spec->gpio_data = 0; 11488c70461bSLucas Tanure spec->gpio_mask = 0x03f; 11498c70461bSLucas Tanure 11508c70461bSLucas Tanure /* Basic initial sequence for specific hw configuration */ 11518c70461bSLucas Tanure snd_hda_sequence_write(codec, cs8409_cs42l42_init_verbs); 11528c70461bSLucas Tanure 1153636eb9d2SLucas Tanure cs8409_fix_caps(codec, CS8409_CS42L42_HP_PIN_NID); 1154636eb9d2SLucas Tanure cs8409_fix_caps(codec, CS8409_CS42L42_AMIC_PIN_NID); 11558c70461bSLucas Tanure 1156f129f26fSStefan Binding spec->scodecs[CS8409_CODEC0]->hsbias_hiz = 0x0020; 1157f129f26fSStefan Binding 115824f7ac3dSLucas Tanure switch (codec->fixup_id) { 1159f129f26fSStefan Binding case CS8409_CYBORG: 1160f129f26fSStefan Binding spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1161f129f26fSStefan Binding CS42L42_FULL_SCALE_VOL_MINUS6DB; 1162f129f26fSStefan Binding spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; 1163f129f26fSStefan Binding break; 116422bb8226SStefan Binding case CS8409_ODIN: 1165f129f26fSStefan Binding spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; 1166f129f26fSStefan Binding spec->speaker_pdn_gpio = CS8409_CYBORG_SPEAKER_PDN; 1167f129f26fSStefan Binding break; 11686581a045SStefan Binding case CS8409_WARLOCK_MLK: 11696581a045SStefan Binding case CS8409_WARLOCK_MLK_DUAL_MIC: 11706581a045SStefan Binding spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_0DB; 11716e7cf670SStefan Binding spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; 11726581a045SStefan Binding break; 117324f7ac3dSLucas Tanure default: 1174342b6b61SStefan Binding spec->scodecs[CS8409_CODEC0]->full_scale_vol = 1175342b6b61SStefan Binding CS42L42_FULL_SCALE_VOL_MINUS6DB; 11766e7cf670SStefan Binding spec->speaker_pdn_gpio = CS8409_WARLOCK_SPEAKER_PDN; 117724f7ac3dSLucas Tanure break; 117824f7ac3dSLucas Tanure } 117924f7ac3dSLucas Tanure 1180f129f26fSStefan Binding if (spec->speaker_pdn_gpio > 0) { 1181f129f26fSStefan Binding spec->gpio_dir |= spec->speaker_pdn_gpio; 1182f129f26fSStefan Binding spec->gpio_data |= spec->speaker_pdn_gpio; 1183f129f26fSStefan Binding } 1184f129f26fSStefan Binding 11858c70461bSLucas Tanure break; 11868c70461bSLucas Tanure case HDA_FIXUP_ACT_PROBE: 1187fed0aacaSStefan Binding /* Fix Sample Rate to 48kHz */ 1188fed0aacaSStefan Binding spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; 1189fed0aacaSStefan Binding spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; 11907482ec71SStefan Binding /* add hooks */ 11917482ec71SStefan Binding spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; 11927482ec71SStefan Binding spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; 119322bb8226SStefan Binding if (codec->fixup_id != CS8409_ODIN) 11948c70461bSLucas Tanure /* Set initial DMIC volume to -26 dB */ 11958c70461bSLucas Tanure snd_hda_codec_amp_init_stereo(codec, CS8409_CS42L42_DMIC_ADC_PIN_NID, 11968c70461bSLucas Tanure HDA_INPUT, 0, 0xff, 0x19); 1197b2a88774SLucas Tanure snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", 1198b2a88774SLucas Tanure &cs42l42_dac_volume_mixer); 1199b2a88774SLucas Tanure snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", 1200b2a88774SLucas Tanure &cs42l42_adc_volume_mixer); 1201f129f26fSStefan Binding if (spec->speaker_pdn_gpio > 0) 1202f129f26fSStefan Binding snd_hda_gen_add_kctl(&spec->gen, "Speaker Playback Switch", 1203f129f26fSStefan Binding &cs8409_spk_sw_ctrl); 1204134ae782SLucas Tanure /* Disable Unsolicited Response during boot */ 1205134ae782SLucas Tanure cs8409_enable_ur(codec, 0); 12068c70461bSLucas Tanure snd_hda_codec_set_name(codec, "CS8409/CS42L42"); 12078c70461bSLucas Tanure break; 12088c70461bSLucas Tanure case HDA_FIXUP_ACT_INIT: 12098c70461bSLucas Tanure cs8409_cs42l42_hw_init(codec); 1210424e531bSStefan Binding spec->init_done = 1; 1211424e531bSStefan Binding if (spec->init_done && spec->build_ctrl_done 1212424e531bSStefan Binding && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) 1213424e531bSStefan Binding cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); 1214424e531bSStefan Binding break; 12158c70461bSLucas Tanure case HDA_FIXUP_ACT_BUILD: 1216424e531bSStefan Binding spec->build_ctrl_done = 1; 12178c70461bSLucas Tanure /* Run jack auto detect first time on boot 12188c70461bSLucas Tanure * after controls have been added, to check if jack has 12198c70461bSLucas Tanure * been already plugged in. 12208c70461bSLucas Tanure * Run immediately after init. 12218c70461bSLucas Tanure */ 1222424e531bSStefan Binding if (spec->init_done && spec->build_ctrl_done 1223424e531bSStefan Binding && !spec->scodecs[CS8409_CODEC0]->hp_jack_in) 122424f7ac3dSLucas Tanure cs42l42_run_jack_detect(spec->scodecs[CS8409_CODEC0]); 12258c70461bSLucas Tanure break; 12268c70461bSLucas Tanure default: 12278c70461bSLucas Tanure break; 12288c70461bSLucas Tanure } 12298c70461bSLucas Tanure } 12308c70461bSLucas Tanure 123120e50772SLucas Tanure /****************************************************************************** 123220e50772SLucas Tanure * Dolphin Specific Functions 123320e50772SLucas Tanure * CS8409/ 2 X CS42L42 123420e50772SLucas Tanure ******************************************************************************/ 123520e50772SLucas Tanure 123620e50772SLucas Tanure /* 123720e50772SLucas Tanure * In the case of CS8409 we do not have unsolicited events when 123820e50772SLucas Tanure * hs mic and hp are connected. Companion codec CS42L42 will 123920e50772SLucas Tanure * generate interrupt via irq_mask to notify jack events. We have to overwrite 124020e50772SLucas Tanure * generic snd_hda_jack_unsol_event(), read CS42L42 jack detect status registers 124120e50772SLucas Tanure * and then notify status via generic snd_hda_jack_unsol_event() call. 124220e50772SLucas Tanure */ 124320e50772SLucas Tanure static void dolphin_jack_unsol_event(struct hda_codec *codec, unsigned int res) 124420e50772SLucas Tanure { 124520e50772SLucas Tanure struct cs8409_spec *spec = codec->spec; 124620e50772SLucas Tanure struct sub_codec *cs42l42; 124720e50772SLucas Tanure struct hda_jack_tbl *jk; 124820e50772SLucas Tanure 124920e50772SLucas Tanure cs42l42 = spec->scodecs[CS8409_CODEC0]; 125020e50772SLucas Tanure if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && 125120e50772SLucas Tanure cs42l42_jack_unsol_event(cs42l42)) { 125220e50772SLucas Tanure jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_HP_PIN_NID, 0); 125320e50772SLucas Tanure if (jk) 125420e50772SLucas Tanure snd_hda_jack_unsol_event(codec, 125520e50772SLucas Tanure (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 125620e50772SLucas Tanure AC_UNSOL_RES_TAG); 125720e50772SLucas Tanure 125820e50772SLucas Tanure jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_AMIC_PIN_NID, 0); 125920e50772SLucas Tanure if (jk) 126020e50772SLucas Tanure snd_hda_jack_unsol_event(codec, 126120e50772SLucas Tanure (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 126220e50772SLucas Tanure AC_UNSOL_RES_TAG); 126320e50772SLucas Tanure } 126420e50772SLucas Tanure 126520e50772SLucas Tanure cs42l42 = spec->scodecs[CS8409_CODEC1]; 126620e50772SLucas Tanure if (!cs42l42->suspended && (~res & cs42l42->irq_mask) && 126720e50772SLucas Tanure cs42l42_jack_unsol_event(cs42l42)) { 126820e50772SLucas Tanure jk = snd_hda_jack_tbl_get_mst(codec, DOLPHIN_LO_PIN_NID, 0); 126920e50772SLucas Tanure if (jk) 127020e50772SLucas Tanure snd_hda_jack_unsol_event(codec, 127120e50772SLucas Tanure (jk->tag << AC_UNSOL_RES_TAG_SHIFT) & 127220e50772SLucas Tanure AC_UNSOL_RES_TAG); 127320e50772SLucas Tanure } 127420e50772SLucas Tanure } 127520e50772SLucas Tanure 127620e50772SLucas Tanure /* Vendor specific HW configuration 127720e50772SLucas Tanure * PLL, ASP, I2C, SPI, GPIOs, DMIC etc... 127820e50772SLucas Tanure */ 127920e50772SLucas Tanure static void dolphin_hw_init(struct hda_codec *codec) 128020e50772SLucas Tanure { 128120e50772SLucas Tanure const struct cs8409_cir_param *seq = dolphin_hw_cfg; 128220e50772SLucas Tanure struct cs8409_spec *spec = codec->spec; 128320e50772SLucas Tanure struct sub_codec *cs42l42; 128420e50772SLucas Tanure int i; 128520e50772SLucas Tanure 128620e50772SLucas Tanure if (spec->gpio_mask) { 128720e50772SLucas Tanure snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_MASK, 128820e50772SLucas Tanure spec->gpio_mask); 128920e50772SLucas Tanure snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DIRECTION, 129020e50772SLucas Tanure spec->gpio_dir); 129120e50772SLucas Tanure snd_hda_codec_write(codec, CS8409_PIN_AFG, 0, AC_VERB_SET_GPIO_DATA, 129220e50772SLucas Tanure spec->gpio_data); 129320e50772SLucas Tanure } 129420e50772SLucas Tanure 129520e50772SLucas Tanure for (; seq->nid; seq++) 129620e50772SLucas Tanure cs8409_vendor_coef_set(codec, seq->cir, seq->coeff); 129720e50772SLucas Tanure 129820e50772SLucas Tanure for (i = 0; i < spec->num_scodecs; i++) { 129920e50772SLucas Tanure cs42l42 = spec->scodecs[i]; 130020e50772SLucas Tanure cs42l42_resume(cs42l42); 130120e50772SLucas Tanure } 130220e50772SLucas Tanure 130320e50772SLucas Tanure /* Enable Unsolicited Response */ 130420e50772SLucas Tanure cs8409_enable_ur(codec, 1); 130520e50772SLucas Tanure } 130620e50772SLucas Tanure 130720e50772SLucas Tanure static const struct hda_codec_ops cs8409_dolphin_patch_ops = { 130820e50772SLucas Tanure .build_controls = cs8409_build_controls, 130920e50772SLucas Tanure .build_pcms = snd_hda_gen_build_pcms, 131020e50772SLucas Tanure .init = cs8409_init, 131120e50772SLucas Tanure .free = cs8409_free, 131220e50772SLucas Tanure .unsol_event = dolphin_jack_unsol_event, 131320e50772SLucas Tanure #ifdef CONFIG_PM 131420e50772SLucas Tanure .suspend = cs8409_cs42l42_suspend, 131520e50772SLucas Tanure #endif 131620e50772SLucas Tanure }; 131720e50772SLucas Tanure 131820e50772SLucas Tanure static int dolphin_exec_verb(struct hdac_device *dev, unsigned int cmd, unsigned int flags, 131920e50772SLucas Tanure unsigned int *res) 132020e50772SLucas Tanure { 132120e50772SLucas Tanure struct hda_codec *codec = container_of(dev, struct hda_codec, core); 132220e50772SLucas Tanure struct cs8409_spec *spec = codec->spec; 132320e50772SLucas Tanure struct sub_codec *cs42l42 = spec->scodecs[CS8409_CODEC0]; 132420e50772SLucas Tanure 132520e50772SLucas Tanure unsigned int nid = ((cmd >> 20) & 0x07f); 132620e50772SLucas Tanure unsigned int verb = ((cmd >> 8) & 0x0fff); 132720e50772SLucas Tanure 132820e50772SLucas Tanure /* CS8409 pins have no AC_PINSENSE_PRESENCE 132920e50772SLucas Tanure * capabilities. We have to intercept calls for CS42L42 pins 133020e50772SLucas Tanure * and return correct pin sense values for read_pin_sense() call from 133120e50772SLucas Tanure * hda_jack based on CS42L42 jack detect status. 133220e50772SLucas Tanure */ 133320e50772SLucas Tanure switch (nid) { 133420e50772SLucas Tanure case DOLPHIN_HP_PIN_NID: 133520e50772SLucas Tanure case DOLPHIN_LO_PIN_NID: 133620e50772SLucas Tanure if (nid == DOLPHIN_LO_PIN_NID) 133720e50772SLucas Tanure cs42l42 = spec->scodecs[CS8409_CODEC1]; 133820e50772SLucas Tanure if (verb == AC_VERB_GET_PIN_SENSE) { 133920e50772SLucas Tanure *res = (cs42l42->hp_jack_in) ? AC_PINSENSE_PRESENCE : 0; 134020e50772SLucas Tanure return 0; 134120e50772SLucas Tanure } 134220e50772SLucas Tanure break; 134320e50772SLucas Tanure case DOLPHIN_AMIC_PIN_NID: 134420e50772SLucas Tanure if (verb == AC_VERB_GET_PIN_SENSE) { 134520e50772SLucas Tanure *res = (cs42l42->mic_jack_in) ? AC_PINSENSE_PRESENCE : 0; 134620e50772SLucas Tanure return 0; 134720e50772SLucas Tanure } 134820e50772SLucas Tanure break; 134920e50772SLucas Tanure default: 135020e50772SLucas Tanure break; 135120e50772SLucas Tanure } 135220e50772SLucas Tanure 135320e50772SLucas Tanure return spec->exec_verb(dev, cmd, flags, res); 135420e50772SLucas Tanure } 135520e50772SLucas Tanure 135620e50772SLucas Tanure void dolphin_fixups(struct hda_codec *codec, const struct hda_fixup *fix, int action) 135720e50772SLucas Tanure { 135820e50772SLucas Tanure struct cs8409_spec *spec = codec->spec; 135920e50772SLucas Tanure struct snd_kcontrol_new *kctrl; 136020e50772SLucas Tanure int i; 136120e50772SLucas Tanure 136220e50772SLucas Tanure switch (action) { 136320e50772SLucas Tanure case HDA_FIXUP_ACT_PRE_PROBE: 136420e50772SLucas Tanure snd_hda_add_verbs(codec, dolphin_init_verbs); 136520e50772SLucas Tanure /* verb exec op override */ 136620e50772SLucas Tanure spec->exec_verb = codec->core.exec_verb; 136720e50772SLucas Tanure codec->core.exec_verb = dolphin_exec_verb; 136820e50772SLucas Tanure 136920e50772SLucas Tanure spec->scodecs[CS8409_CODEC0] = &dolphin_cs42l42_0; 137020e50772SLucas Tanure spec->scodecs[CS8409_CODEC0]->codec = codec; 137120e50772SLucas Tanure spec->scodecs[CS8409_CODEC1] = &dolphin_cs42l42_1; 137220e50772SLucas Tanure spec->scodecs[CS8409_CODEC1]->codec = codec; 137320e50772SLucas Tanure spec->num_scodecs = 2; 1374*a2ed0a44SVitaly Rodionov spec->gen.suppress_vmaster = 1; 137520e50772SLucas Tanure 137620e50772SLucas Tanure codec->patch_ops = cs8409_dolphin_patch_ops; 137720e50772SLucas Tanure 137820e50772SLucas Tanure /* GPIO 1,5 out, 0,4 in */ 137920e50772SLucas Tanure spec->gpio_dir = spec->scodecs[CS8409_CODEC0]->reset_gpio | 138020e50772SLucas Tanure spec->scodecs[CS8409_CODEC1]->reset_gpio; 138120e50772SLucas Tanure spec->gpio_data = 0; 138220e50772SLucas Tanure spec->gpio_mask = 0x03f; 138320e50772SLucas Tanure 138420e50772SLucas Tanure /* Basic initial sequence for specific hw configuration */ 138520e50772SLucas Tanure snd_hda_sequence_write(codec, dolphin_init_verbs); 138620e50772SLucas Tanure 138720e50772SLucas Tanure snd_hda_jack_add_kctl(codec, DOLPHIN_LO_PIN_NID, "Line Out", true, 138820e50772SLucas Tanure SND_JACK_HEADPHONE, NULL); 138920e50772SLucas Tanure 139094d508faSStefan Binding snd_hda_jack_add_kctl(codec, DOLPHIN_AMIC_PIN_NID, "Microphone", true, 139194d508faSStefan Binding SND_JACK_MICROPHONE, NULL); 139294d508faSStefan Binding 139320e50772SLucas Tanure cs8409_fix_caps(codec, DOLPHIN_HP_PIN_NID); 139420e50772SLucas Tanure cs8409_fix_caps(codec, DOLPHIN_LO_PIN_NID); 139520e50772SLucas Tanure cs8409_fix_caps(codec, DOLPHIN_AMIC_PIN_NID); 139620e50772SLucas Tanure 1397342b6b61SStefan Binding spec->scodecs[CS8409_CODEC0]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; 1398342b6b61SStefan Binding spec->scodecs[CS8409_CODEC1]->full_scale_vol = CS42L42_FULL_SCALE_VOL_MINUS6DB; 1399342b6b61SStefan Binding 140020e50772SLucas Tanure break; 140120e50772SLucas Tanure case HDA_FIXUP_ACT_PROBE: 1402fed0aacaSStefan Binding /* Fix Sample Rate to 48kHz */ 1403fed0aacaSStefan Binding spec->gen.stream_analog_playback = &cs42l42_48k_pcm_analog_playback; 1404fed0aacaSStefan Binding spec->gen.stream_analog_capture = &cs42l42_48k_pcm_analog_capture; 14057482ec71SStefan Binding /* add hooks */ 14067482ec71SStefan Binding spec->gen.pcm_playback_hook = cs42l42_playback_pcm_hook; 14077482ec71SStefan Binding spec->gen.pcm_capture_hook = cs42l42_capture_pcm_hook; 140820e50772SLucas Tanure snd_hda_gen_add_kctl(&spec->gen, "Headphone Playback Volume", 140920e50772SLucas Tanure &cs42l42_dac_volume_mixer); 141020e50772SLucas Tanure snd_hda_gen_add_kctl(&spec->gen, "Mic Capture Volume", &cs42l42_adc_volume_mixer); 141120e50772SLucas Tanure kctrl = snd_hda_gen_add_kctl(&spec->gen, "Line Out Playback Volume", 141220e50772SLucas Tanure &cs42l42_dac_volume_mixer); 141320e50772SLucas Tanure /* Update Line Out kcontrol template */ 141420e50772SLucas Tanure kctrl->private_value = HDA_COMPOSE_AMP_VAL_OFS(DOLPHIN_HP_PIN_NID, 3, CS8409_CODEC1, 141520e50772SLucas Tanure HDA_OUTPUT, CS42L42_VOL_DAC) | HDA_AMP_VAL_MIN_MUTE; 141620e50772SLucas Tanure cs8409_enable_ur(codec, 0); 141720e50772SLucas Tanure snd_hda_codec_set_name(codec, "CS8409/CS42L42"); 141820e50772SLucas Tanure break; 141920e50772SLucas Tanure case HDA_FIXUP_ACT_INIT: 142020e50772SLucas Tanure dolphin_hw_init(codec); 1421424e531bSStefan Binding spec->init_done = 1; 1422424e531bSStefan Binding if (spec->init_done && spec->build_ctrl_done) { 1423424e531bSStefan Binding for (i = 0; i < spec->num_scodecs; i++) { 1424424e531bSStefan Binding if (!spec->scodecs[i]->hp_jack_in) 1425424e531bSStefan Binding cs42l42_run_jack_detect(spec->scodecs[i]); 1426424e531bSStefan Binding } 1427424e531bSStefan Binding } 1428424e531bSStefan Binding break; 142920e50772SLucas Tanure case HDA_FIXUP_ACT_BUILD: 1430424e531bSStefan Binding spec->build_ctrl_done = 1; 143120e50772SLucas Tanure /* Run jack auto detect first time on boot 143220e50772SLucas Tanure * after controls have been added, to check if jack has 143320e50772SLucas Tanure * been already plugged in. 143420e50772SLucas Tanure * Run immediately after init. 143520e50772SLucas Tanure */ 1436424e531bSStefan Binding if (spec->init_done && spec->build_ctrl_done) { 1437424e531bSStefan Binding for (i = 0; i < spec->num_scodecs; i++) { 1438424e531bSStefan Binding if (!spec->scodecs[i]->hp_jack_in) 143920e50772SLucas Tanure cs42l42_run_jack_detect(spec->scodecs[i]); 1440424e531bSStefan Binding } 1441424e531bSStefan Binding } 144220e50772SLucas Tanure break; 144320e50772SLucas Tanure default: 144420e50772SLucas Tanure break; 144520e50772SLucas Tanure } 144620e50772SLucas Tanure } 144720e50772SLucas Tanure 14488c70461bSLucas Tanure static int patch_cs8409(struct hda_codec *codec) 14498c70461bSLucas Tanure { 14508c70461bSLucas Tanure int err; 14518c70461bSLucas Tanure 14528c70461bSLucas Tanure if (!cs8409_alloc_spec(codec)) 14538c70461bSLucas Tanure return -ENOMEM; 14548c70461bSLucas Tanure 14558c70461bSLucas Tanure snd_hda_pick_fixup(codec, cs8409_models, cs8409_fixup_tbl, cs8409_fixups); 14568c70461bSLucas Tanure 14578c70461bSLucas Tanure codec_dbg(codec, "Picked ID=%d, VID=%08x, DEV=%08x\n", codec->fixup_id, 14588c70461bSLucas Tanure codec->bus->pci->subsystem_vendor, 14598c70461bSLucas Tanure codec->bus->pci->subsystem_device); 14608c70461bSLucas Tanure 14618c70461bSLucas Tanure snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PRE_PROBE); 14628c70461bSLucas Tanure 14638c70461bSLucas Tanure err = cs8409_parse_auto_config(codec); 14648c70461bSLucas Tanure if (err < 0) { 1465647d50a0SLucas Tanure cs8409_free(codec); 14668c70461bSLucas Tanure return err; 14678c70461bSLucas Tanure } 14688c70461bSLucas Tanure 14698c70461bSLucas Tanure snd_hda_apply_fixup(codec, HDA_FIXUP_ACT_PROBE); 14708c70461bSLucas Tanure return 0; 14718c70461bSLucas Tanure } 14728c70461bSLucas Tanure 14738c70461bSLucas Tanure static const struct hda_device_id snd_hda_id_cs8409[] = { 14748c70461bSLucas Tanure HDA_CODEC_ENTRY(0x10138409, "CS8409", patch_cs8409), 14758c70461bSLucas Tanure {} /* terminator */ 14768c70461bSLucas Tanure }; 14778c70461bSLucas Tanure MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_cs8409); 14788c70461bSLucas Tanure 14798c70461bSLucas Tanure static struct hda_codec_driver cs8409_driver = { 14808c70461bSLucas Tanure .id = snd_hda_id_cs8409, 14818c70461bSLucas Tanure }; 14828c70461bSLucas Tanure module_hda_codec_driver(cs8409_driver); 14838c70461bSLucas Tanure 14848c70461bSLucas Tanure MODULE_LICENSE("GPL"); 14858c70461bSLucas Tanure MODULE_DESCRIPTION("Cirrus Logic HDA bridge"); 1486