1 /* 2 * HD audio interface patch for Creative CA0132 chip 3 * 4 * Copyright (c) 2011, Creative Technology Ltd. 5 * 6 * Based on patch_ca0110.c 7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de> 8 * 9 * This driver is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This driver is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/slab.h> 27 #include <linux/mutex.h> 28 #include <linux/module.h> 29 #include <linux/firmware.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/io.h> 33 #include <linux/pci.h> 34 #include <asm/io.h> 35 #include <sound/core.h> 36 #include <sound/hda_codec.h> 37 #include "hda_local.h" 38 #include "hda_auto_parser.h" 39 #include "hda_jack.h" 40 41 #include "ca0132_regs.h" 42 43 /* Enable this to see controls for tuning purpose. */ 44 /*#define ENABLE_TUNING_CONTROLS*/ 45 46 #ifdef ENABLE_TUNING_CONTROLS 47 #include <sound/tlv.h> 48 #endif 49 50 #define FLOAT_ZERO 0x00000000 51 #define FLOAT_ONE 0x3f800000 52 #define FLOAT_TWO 0x40000000 53 #define FLOAT_THREE 0x40400000 54 #define FLOAT_EIGHT 0x41000000 55 #define FLOAT_MINUS_5 0xc0a00000 56 57 #define UNSOL_TAG_DSP 0x16 58 59 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18) 60 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15) 61 62 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8 63 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32 64 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2 65 66 #define MASTERCONTROL 0x80 67 #define MASTERCONTROL_ALLOC_DMA_CHAN 10 68 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60 69 70 #define WIDGET_CHIP_CTRL 0x15 71 #define WIDGET_DSP_CTRL 0x16 72 73 #define MEM_CONNID_MICIN1 3 74 #define MEM_CONNID_MICIN2 5 75 #define MEM_CONNID_MICOUT1 12 76 #define MEM_CONNID_MICOUT2 14 77 #define MEM_CONNID_WUH 10 78 #define MEM_CONNID_DSP 16 79 #define MEM_CONNID_DMIC 100 80 81 #define SCP_SET 0 82 #define SCP_GET 1 83 84 #define EFX_FILE "ctefx.bin" 85 #define DESKTOP_EFX_FILE "ctefx-desktop.bin" 86 #define R3DI_EFX_FILE "ctefx-r3di.bin" 87 88 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 89 MODULE_FIRMWARE(EFX_FILE); 90 MODULE_FIRMWARE(DESKTOP_EFX_FILE); 91 MODULE_FIRMWARE(R3DI_EFX_FILE); 92 #endif 93 94 static const char *const dirstr[2] = { "Playback", "Capture" }; 95 96 #define NUM_OF_OUTPUTS 3 97 enum { 98 SPEAKER_OUT, 99 HEADPHONE_OUT, 100 SURROUND_OUT 101 }; 102 103 enum { 104 DIGITAL_MIC, 105 LINE_MIC_IN 106 }; 107 108 /* Strings for Input Source Enum Control */ 109 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" }; 110 #define IN_SRC_NUM_OF_INPUTS 3 111 enum { 112 REAR_MIC, 113 REAR_LINE_IN, 114 FRONT_MIC, 115 }; 116 117 enum { 118 #define VNODE_START_NID 0x80 119 VNID_SPK = VNODE_START_NID, /* Speaker vnid */ 120 VNID_MIC, 121 VNID_HP_SEL, 122 VNID_AMIC1_SEL, 123 VNID_HP_ASEL, 124 VNID_AMIC1_ASEL, 125 VNODE_END_NID, 126 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID) 127 128 #define EFFECT_START_NID 0x90 129 #define OUT_EFFECT_START_NID EFFECT_START_NID 130 SURROUND = OUT_EFFECT_START_NID, 131 CRYSTALIZER, 132 DIALOG_PLUS, 133 SMART_VOLUME, 134 X_BASS, 135 EQUALIZER, 136 OUT_EFFECT_END_NID, 137 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID) 138 139 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID 140 ECHO_CANCELLATION = IN_EFFECT_START_NID, 141 VOICE_FOCUS, 142 MIC_SVM, 143 NOISE_REDUCTION, 144 IN_EFFECT_END_NID, 145 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID) 146 147 VOICEFX = IN_EFFECT_END_NID, 148 PLAY_ENHANCEMENT, 149 CRYSTAL_VOICE, 150 EFFECT_END_NID, 151 OUTPUT_SOURCE_ENUM, 152 INPUT_SOURCE_ENUM, 153 XBASS_XOVER, 154 EQ_PRESET_ENUM, 155 SMART_VOLUME_ENUM, 156 MIC_BOOST_ENUM, 157 AE5_HEADPHONE_GAIN_ENUM, 158 AE5_SOUND_FILTER_ENUM, 159 ZXR_HEADPHONE_GAIN 160 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID) 161 }; 162 163 /* Effects values size*/ 164 #define EFFECT_VALS_MAX_COUNT 12 165 166 /* 167 * Default values for the effect slider controls, they are in order of their 168 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then 169 * X-bass. 170 */ 171 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50}; 172 /* Amount of effect level sliders for ca0132_alt controls. */ 173 #define EFFECT_LEVEL_SLIDERS 5 174 175 /* Latency introduced by DSP blocks in milliseconds. */ 176 #define DSP_CAPTURE_INIT_LATENCY 0 177 #define DSP_CRYSTAL_VOICE_LATENCY 124 178 #define DSP_PLAYBACK_INIT_LATENCY 13 179 #define DSP_PLAY_ENHANCEMENT_LATENCY 30 180 #define DSP_SPEAKER_OUT_LATENCY 7 181 182 struct ct_effect { 183 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 184 hda_nid_t nid; 185 int mid; /*effect module ID*/ 186 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/ 187 int direct; /* 0:output; 1:input*/ 188 int params; /* number of default non-on/off params */ 189 /*effect default values, 1st is on/off. */ 190 unsigned int def_vals[EFFECT_VALS_MAX_COUNT]; 191 }; 192 193 #define EFX_DIR_OUT 0 194 #define EFX_DIR_IN 1 195 196 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = { 197 { .name = "Surround", 198 .nid = SURROUND, 199 .mid = 0x96, 200 .reqs = {0, 1}, 201 .direct = EFX_DIR_OUT, 202 .params = 1, 203 .def_vals = {0x3F800000, 0x3F2B851F} 204 }, 205 { .name = "Crystalizer", 206 .nid = CRYSTALIZER, 207 .mid = 0x96, 208 .reqs = {7, 8}, 209 .direct = EFX_DIR_OUT, 210 .params = 1, 211 .def_vals = {0x3F800000, 0x3F266666} 212 }, 213 { .name = "Dialog Plus", 214 .nid = DIALOG_PLUS, 215 .mid = 0x96, 216 .reqs = {2, 3}, 217 .direct = EFX_DIR_OUT, 218 .params = 1, 219 .def_vals = {0x00000000, 0x3F000000} 220 }, 221 { .name = "Smart Volume", 222 .nid = SMART_VOLUME, 223 .mid = 0x96, 224 .reqs = {4, 5, 6}, 225 .direct = EFX_DIR_OUT, 226 .params = 2, 227 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000} 228 }, 229 { .name = "X-Bass", 230 .nid = X_BASS, 231 .mid = 0x96, 232 .reqs = {24, 23, 25}, 233 .direct = EFX_DIR_OUT, 234 .params = 2, 235 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000} 236 }, 237 { .name = "Equalizer", 238 .nid = EQUALIZER, 239 .mid = 0x96, 240 .reqs = {9, 10, 11, 12, 13, 14, 241 15, 16, 17, 18, 19, 20}, 242 .direct = EFX_DIR_OUT, 243 .params = 11, 244 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000, 245 0x00000000, 0x00000000, 0x00000000, 0x00000000, 246 0x00000000, 0x00000000, 0x00000000, 0x00000000} 247 }, 248 { .name = "Echo Cancellation", 249 .nid = ECHO_CANCELLATION, 250 .mid = 0x95, 251 .reqs = {0, 1, 2, 3}, 252 .direct = EFX_DIR_IN, 253 .params = 3, 254 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000} 255 }, 256 { .name = "Voice Focus", 257 .nid = VOICE_FOCUS, 258 .mid = 0x95, 259 .reqs = {6, 7, 8, 9}, 260 .direct = EFX_DIR_IN, 261 .params = 3, 262 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000} 263 }, 264 { .name = "Mic SVM", 265 .nid = MIC_SVM, 266 .mid = 0x95, 267 .reqs = {44, 45}, 268 .direct = EFX_DIR_IN, 269 .params = 1, 270 .def_vals = {0x00000000, 0x3F3D70A4} 271 }, 272 { .name = "Noise Reduction", 273 .nid = NOISE_REDUCTION, 274 .mid = 0x95, 275 .reqs = {4, 5}, 276 .direct = EFX_DIR_IN, 277 .params = 1, 278 .def_vals = {0x3F800000, 0x3F000000} 279 }, 280 { .name = "VoiceFX", 281 .nid = VOICEFX, 282 .mid = 0x95, 283 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}, 284 .direct = EFX_DIR_IN, 285 .params = 8, 286 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000, 287 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000, 288 0x00000000} 289 } 290 }; 291 292 /* Tuning controls */ 293 #ifdef ENABLE_TUNING_CONTROLS 294 295 enum { 296 #define TUNING_CTL_START_NID 0xC0 297 WEDGE_ANGLE = TUNING_CTL_START_NID, 298 SVM_LEVEL, 299 EQUALIZER_BAND_0, 300 EQUALIZER_BAND_1, 301 EQUALIZER_BAND_2, 302 EQUALIZER_BAND_3, 303 EQUALIZER_BAND_4, 304 EQUALIZER_BAND_5, 305 EQUALIZER_BAND_6, 306 EQUALIZER_BAND_7, 307 EQUALIZER_BAND_8, 308 EQUALIZER_BAND_9, 309 TUNING_CTL_END_NID 310 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID) 311 }; 312 313 struct ct_tuning_ctl { 314 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 315 hda_nid_t parent_nid; 316 hda_nid_t nid; 317 int mid; /*effect module ID*/ 318 int req; /*effect module request*/ 319 int direct; /* 0:output; 1:input*/ 320 unsigned int def_val;/*effect default values*/ 321 }; 322 323 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = { 324 { .name = "Wedge Angle", 325 .parent_nid = VOICE_FOCUS, 326 .nid = WEDGE_ANGLE, 327 .mid = 0x95, 328 .req = 8, 329 .direct = EFX_DIR_IN, 330 .def_val = 0x41F00000 331 }, 332 { .name = "SVM Level", 333 .parent_nid = MIC_SVM, 334 .nid = SVM_LEVEL, 335 .mid = 0x95, 336 .req = 45, 337 .direct = EFX_DIR_IN, 338 .def_val = 0x3F3D70A4 339 }, 340 { .name = "EQ Band0", 341 .parent_nid = EQUALIZER, 342 .nid = EQUALIZER_BAND_0, 343 .mid = 0x96, 344 .req = 11, 345 .direct = EFX_DIR_OUT, 346 .def_val = 0x00000000 347 }, 348 { .name = "EQ Band1", 349 .parent_nid = EQUALIZER, 350 .nid = EQUALIZER_BAND_1, 351 .mid = 0x96, 352 .req = 12, 353 .direct = EFX_DIR_OUT, 354 .def_val = 0x00000000 355 }, 356 { .name = "EQ Band2", 357 .parent_nid = EQUALIZER, 358 .nid = EQUALIZER_BAND_2, 359 .mid = 0x96, 360 .req = 13, 361 .direct = EFX_DIR_OUT, 362 .def_val = 0x00000000 363 }, 364 { .name = "EQ Band3", 365 .parent_nid = EQUALIZER, 366 .nid = EQUALIZER_BAND_3, 367 .mid = 0x96, 368 .req = 14, 369 .direct = EFX_DIR_OUT, 370 .def_val = 0x00000000 371 }, 372 { .name = "EQ Band4", 373 .parent_nid = EQUALIZER, 374 .nid = EQUALIZER_BAND_4, 375 .mid = 0x96, 376 .req = 15, 377 .direct = EFX_DIR_OUT, 378 .def_val = 0x00000000 379 }, 380 { .name = "EQ Band5", 381 .parent_nid = EQUALIZER, 382 .nid = EQUALIZER_BAND_5, 383 .mid = 0x96, 384 .req = 16, 385 .direct = EFX_DIR_OUT, 386 .def_val = 0x00000000 387 }, 388 { .name = "EQ Band6", 389 .parent_nid = EQUALIZER, 390 .nid = EQUALIZER_BAND_6, 391 .mid = 0x96, 392 .req = 17, 393 .direct = EFX_DIR_OUT, 394 .def_val = 0x00000000 395 }, 396 { .name = "EQ Band7", 397 .parent_nid = EQUALIZER, 398 .nid = EQUALIZER_BAND_7, 399 .mid = 0x96, 400 .req = 18, 401 .direct = EFX_DIR_OUT, 402 .def_val = 0x00000000 403 }, 404 { .name = "EQ Band8", 405 .parent_nid = EQUALIZER, 406 .nid = EQUALIZER_BAND_8, 407 .mid = 0x96, 408 .req = 19, 409 .direct = EFX_DIR_OUT, 410 .def_val = 0x00000000 411 }, 412 { .name = "EQ Band9", 413 .parent_nid = EQUALIZER, 414 .nid = EQUALIZER_BAND_9, 415 .mid = 0x96, 416 .req = 20, 417 .direct = EFX_DIR_OUT, 418 .def_val = 0x00000000 419 } 420 }; 421 #endif 422 423 /* Voice FX Presets */ 424 #define VOICEFX_MAX_PARAM_COUNT 9 425 426 struct ct_voicefx { 427 char *name; 428 hda_nid_t nid; 429 int mid; 430 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/ 431 }; 432 433 struct ct_voicefx_preset { 434 char *name; /*preset name*/ 435 unsigned int vals[VOICEFX_MAX_PARAM_COUNT]; 436 }; 437 438 static const struct ct_voicefx ca0132_voicefx = { 439 .name = "VoiceFX Capture Switch", 440 .nid = VOICEFX, 441 .mid = 0x95, 442 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18} 443 }; 444 445 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = { 446 { .name = "Neutral", 447 .vals = { 0x00000000, 0x43C80000, 0x44AF0000, 448 0x44FA0000, 0x3F800000, 0x3F800000, 449 0x3F800000, 0x00000000, 0x00000000 } 450 }, 451 { .name = "Female2Male", 452 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 453 0x44FA0000, 0x3F19999A, 0x3F866666, 454 0x3F800000, 0x00000000, 0x00000000 } 455 }, 456 { .name = "Male2Female", 457 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 458 0x450AC000, 0x4017AE14, 0x3F6B851F, 459 0x3F800000, 0x00000000, 0x00000000 } 460 }, 461 { .name = "ScrappyKid", 462 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 463 0x44FA0000, 0x40400000, 0x3F28F5C3, 464 0x3F800000, 0x00000000, 0x00000000 } 465 }, 466 { .name = "Elderly", 467 .vals = { 0x3F800000, 0x44324000, 0x44BB8000, 468 0x44E10000, 0x3FB33333, 0x3FB9999A, 469 0x3F800000, 0x3E3A2E43, 0x00000000 } 470 }, 471 { .name = "Orc", 472 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000, 473 0x45098000, 0x3F266666, 0x3FC00000, 474 0x3F800000, 0x00000000, 0x00000000 } 475 }, 476 { .name = "Elf", 477 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000, 478 0x45193000, 0x3F8E147B, 0x3F75C28F, 479 0x3F800000, 0x00000000, 0x00000000 } 480 }, 481 { .name = "Dwarf", 482 .vals = { 0x3F800000, 0x43930000, 0x44BEE000, 483 0x45007000, 0x3F451EB8, 0x3F7851EC, 484 0x3F800000, 0x00000000, 0x00000000 } 485 }, 486 { .name = "AlienBrute", 487 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF, 488 0x451F6000, 0x3F266666, 0x3FA7D945, 489 0x3F800000, 0x3CF5C28F, 0x00000000 } 490 }, 491 { .name = "Robot", 492 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 493 0x44FA0000, 0x3FB2718B, 0x3F800000, 494 0xBC07010E, 0x00000000, 0x00000000 } 495 }, 496 { .name = "Marine", 497 .vals = { 0x3F800000, 0x43C20000, 0x44906000, 498 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71, 499 0x3F0A3D71, 0x00000000, 0x00000000 } 500 }, 501 { .name = "Emo", 502 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 503 0x44FA0000, 0x3F800000, 0x3F800000, 504 0x3E4CCCCD, 0x00000000, 0x00000000 } 505 }, 506 { .name = "DeepVoice", 507 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF, 508 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA, 509 0x3F800000, 0x00000000, 0x00000000 } 510 }, 511 { .name = "Munchkin", 512 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000, 513 0x44FA0000, 0x3F800000, 0x3F1A043C, 514 0x3F800000, 0x00000000, 0x00000000 } 515 } 516 }; 517 518 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */ 519 520 #define EQ_PRESET_MAX_PARAM_COUNT 11 521 522 struct ct_eq { 523 char *name; 524 hda_nid_t nid; 525 int mid; 526 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/ 527 }; 528 529 struct ct_eq_preset { 530 char *name; /*preset name*/ 531 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT]; 532 }; 533 534 static const struct ct_eq ca0132_alt_eq_enum = { 535 .name = "FX: Equalizer Preset Switch", 536 .nid = EQ_PRESET_ENUM, 537 .mid = 0x96, 538 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20} 539 }; 540 541 542 static const struct ct_eq_preset ca0132_alt_eq_presets[] = { 543 { .name = "Flat", 544 .vals = { 0x00000000, 0x00000000, 0x00000000, 545 0x00000000, 0x00000000, 0x00000000, 546 0x00000000, 0x00000000, 0x00000000, 547 0x00000000, 0x00000000 } 548 }, 549 { .name = "Acoustic", 550 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD, 551 0x40000000, 0x00000000, 0x00000000, 552 0x00000000, 0x00000000, 0x40000000, 553 0x40000000, 0x40000000 } 554 }, 555 { .name = "Classical", 556 .vals = { 0x00000000, 0x00000000, 0x40C00000, 557 0x40C00000, 0x40466666, 0x00000000, 558 0x00000000, 0x00000000, 0x00000000, 559 0x40466666, 0x40466666 } 560 }, 561 { .name = "Country", 562 .vals = { 0x00000000, 0xBF99999A, 0x00000000, 563 0x3FA66666, 0x3FA66666, 0x3F8CCCCD, 564 0x00000000, 0x00000000, 0x40000000, 565 0x40466666, 0x40800000 } 566 }, 567 { .name = "Dance", 568 .vals = { 0x00000000, 0xBF99999A, 0x40000000, 569 0x40466666, 0x40866666, 0xBF99999A, 570 0xBF99999A, 0x00000000, 0x00000000, 571 0x40800000, 0x40800000 } 572 }, 573 { .name = "Jazz", 574 .vals = { 0x00000000, 0x00000000, 0x00000000, 575 0x3F8CCCCD, 0x40800000, 0x40800000, 576 0x40800000, 0x00000000, 0x3F8CCCCD, 577 0x40466666, 0x40466666 } 578 }, 579 { .name = "New Age", 580 .vals = { 0x00000000, 0x00000000, 0x40000000, 581 0x40000000, 0x00000000, 0x00000000, 582 0x00000000, 0x3F8CCCCD, 0x40000000, 583 0x40000000, 0x40000000 } 584 }, 585 { .name = "Pop", 586 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000, 587 0x40000000, 0x40000000, 0x00000000, 588 0xBF99999A, 0xBF99999A, 0x00000000, 589 0x40466666, 0x40C00000 } 590 }, 591 { .name = "Rock", 592 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A, 593 0x3F8CCCCD, 0x40000000, 0xBF99999A, 594 0xBF99999A, 0x00000000, 0x00000000, 595 0x40800000, 0x40800000 } 596 }, 597 { .name = "Vocal", 598 .vals = { 0x00000000, 0xC0000000, 0xBF99999A, 599 0xBF99999A, 0x00000000, 0x40466666, 600 0x40800000, 0x40466666, 0x00000000, 601 0x00000000, 0x3F8CCCCD } 602 } 603 }; 604 605 /* DSP command sequences for ca0132_alt_select_out */ 606 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */ 607 struct ca0132_alt_out_set { 608 char *name; /*preset name*/ 609 unsigned char commands; 610 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS]; 611 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS]; 612 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS]; 613 }; 614 615 static const struct ca0132_alt_out_set alt_out_presets[] = { 616 { .name = "Line Out", 617 .commands = 7, 618 .mids = { 0x96, 0x96, 0x96, 0x8F, 619 0x96, 0x96, 0x96 }, 620 .reqs = { 0x19, 0x17, 0x18, 0x01, 621 0x1F, 0x15, 0x3A }, 622 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 623 0x00000000, 0x00000000, 0x00000000, 624 0x00000000 } 625 }, 626 { .name = "Headphone", 627 .commands = 7, 628 .mids = { 0x96, 0x96, 0x96, 0x8F, 629 0x96, 0x96, 0x96 }, 630 .reqs = { 0x19, 0x17, 0x18, 0x01, 631 0x1F, 0x15, 0x3A }, 632 .vals = { 0x3F000000, 0x42A00000, 0x00000000, 633 0x00000000, 0x00000000, 0x00000000, 634 0x00000000 } 635 }, 636 { .name = "Surround", 637 .commands = 8, 638 .mids = { 0x96, 0x8F, 0x96, 0x96, 639 0x96, 0x96, 0x96, 0x96 }, 640 .reqs = { 0x18, 0x01, 0x1F, 0x15, 641 0x3A, 0x1A, 0x1B, 0x1C }, 642 .vals = { 0x00000000, 0x00000000, 0x00000000, 643 0x00000000, 0x00000000, 0x00000000, 644 0x00000000, 0x00000000 } 645 } 646 }; 647 648 /* 649 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume, 650 * and I don't know what the third req is, but it's always zero. I assume it's 651 * some sort of update or set command to tell the DSP there's new volume info. 652 */ 653 #define DSP_VOL_OUT 0 654 #define DSP_VOL_IN 1 655 656 struct ct_dsp_volume_ctl { 657 hda_nid_t vnid; 658 int mid; /* module ID*/ 659 unsigned int reqs[3]; /* scp req ID */ 660 }; 661 662 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = { 663 { .vnid = VNID_SPK, 664 .mid = 0x32, 665 .reqs = {3, 4, 2} 666 }, 667 { .vnid = VNID_MIC, 668 .mid = 0x37, 669 .reqs = {2, 3, 1} 670 } 671 }; 672 673 /* Values for ca0113_mmio_command_set for selecting output. */ 674 #define AE5_CA0113_OUT_SET_COMMANDS 6 675 struct ae5_ca0113_output_set { 676 unsigned int group[AE5_CA0113_OUT_SET_COMMANDS]; 677 unsigned int target[AE5_CA0113_OUT_SET_COMMANDS]; 678 unsigned int vals[AE5_CA0113_OUT_SET_COMMANDS]; 679 }; 680 681 static const struct ae5_ca0113_output_set ae5_ca0113_output_presets[] = { 682 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 683 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 684 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 685 }, 686 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 687 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 688 .vals = { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } 689 }, 690 { .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 }, 691 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 }, 692 .vals = { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f } 693 } 694 }; 695 696 /* ae5 ca0113 command sequences to set headphone gain levels. */ 697 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4 698 struct ae5_headphone_gain_set { 699 char *name; 700 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS]; 701 }; 702 703 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = { 704 { .name = "Low (16-31", 705 .vals = { 0xff, 0x2c, 0xf5, 0x32 } 706 }, 707 { .name = "Medium (32-149", 708 .vals = { 0x38, 0xa8, 0x3e, 0x4c } 709 }, 710 { .name = "High (150-600", 711 .vals = { 0xff, 0xff, 0xff, 0x7f } 712 } 713 }; 714 715 struct ae5_filter_set { 716 char *name; 717 unsigned int val; 718 }; 719 720 static const struct ae5_filter_set ae5_filter_presets[] = { 721 { .name = "Slow Roll Off", 722 .val = 0xa0 723 }, 724 { .name = "Minimum Phase", 725 .val = 0xc0 726 }, 727 { .name = "Fast Roll Off", 728 .val = 0x80 729 } 730 }; 731 732 enum hda_cmd_vendor_io { 733 /* for DspIO node */ 734 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000, 735 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100, 736 737 VENDOR_DSPIO_STATUS = 0xF01, 738 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702, 739 VENDOR_DSPIO_SCP_READ_DATA = 0xF02, 740 VENDOR_DSPIO_DSP_INIT = 0x703, 741 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704, 742 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04, 743 744 /* for ChipIO node */ 745 VENDOR_CHIPIO_ADDRESS_LOW = 0x000, 746 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100, 747 VENDOR_CHIPIO_STREAM_FORMAT = 0x200, 748 VENDOR_CHIPIO_DATA_LOW = 0x300, 749 VENDOR_CHIPIO_DATA_HIGH = 0x400, 750 751 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500, 752 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00, 753 754 VENDOR_CHIPIO_GET_PARAMETER = 0xF00, 755 VENDOR_CHIPIO_STATUS = 0xF01, 756 VENDOR_CHIPIO_HIC_POST_READ = 0x702, 757 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03, 758 759 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707, 760 VENDOR_CHIPIO_8051_DATA_READ = 0xF07, 761 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08, 762 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709, 763 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09, 764 765 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A, 766 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A, 767 768 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C, 769 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C, 770 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D, 771 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E, 772 VENDOR_CHIPIO_FLAG_SET = 0x70F, 773 VENDOR_CHIPIO_FLAGS_GET = 0xF0F, 774 VENDOR_CHIPIO_PARAM_SET = 0x710, 775 VENDOR_CHIPIO_PARAM_GET = 0xF10, 776 777 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711, 778 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712, 779 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12, 780 VENDOR_CHIPIO_PORT_FREE_SET = 0x713, 781 782 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17, 783 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717, 784 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18, 785 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718, 786 787 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788, 788 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88, 789 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789, 790 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89, 791 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A, 792 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A, 793 794 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D 795 }; 796 797 /* 798 * Control flag IDs 799 */ 800 enum control_flag_id { 801 /* Connection manager stream setup is bypassed/enabled */ 802 CONTROL_FLAG_C_MGR = 0, 803 /* DSP DMA is bypassed/enabled */ 804 CONTROL_FLAG_DMA = 1, 805 /* 8051 'idle' mode is disabled/enabled */ 806 CONTROL_FLAG_IDLE_ENABLE = 2, 807 /* Tracker for the SPDIF-in path is bypassed/enabled */ 808 CONTROL_FLAG_TRACKER = 3, 809 /* DigitalOut to Spdif2Out connection is disabled/enabled */ 810 CONTROL_FLAG_SPDIF2OUT = 4, 811 /* Digital Microphone is disabled/enabled */ 812 CONTROL_FLAG_DMIC = 5, 813 /* ADC_B rate is 48 kHz/96 kHz */ 814 CONTROL_FLAG_ADC_B_96KHZ = 6, 815 /* ADC_C rate is 48 kHz/96 kHz */ 816 CONTROL_FLAG_ADC_C_96KHZ = 7, 817 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */ 818 CONTROL_FLAG_DAC_96KHZ = 8, 819 /* DSP rate is 48 kHz/96 kHz */ 820 CONTROL_FLAG_DSP_96KHZ = 9, 821 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */ 822 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10, 823 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */ 824 CONTROL_FLAG_SRC_RATE_96KHZ = 11, 825 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */ 826 CONTROL_FLAG_DECODE_LOOP = 12, 827 /* De-emphasis filter on DAC-1 disabled/enabled */ 828 CONTROL_FLAG_DAC1_DEEMPHASIS = 13, 829 /* De-emphasis filter on DAC-2 disabled/enabled */ 830 CONTROL_FLAG_DAC2_DEEMPHASIS = 14, 831 /* De-emphasis filter on DAC-3 disabled/enabled */ 832 CONTROL_FLAG_DAC3_DEEMPHASIS = 15, 833 /* High-pass filter on ADC_B disabled/enabled */ 834 CONTROL_FLAG_ADC_B_HIGH_PASS = 16, 835 /* High-pass filter on ADC_C disabled/enabled */ 836 CONTROL_FLAG_ADC_C_HIGH_PASS = 17, 837 /* Common mode on Port_A disabled/enabled */ 838 CONTROL_FLAG_PORT_A_COMMON_MODE = 18, 839 /* Common mode on Port_D disabled/enabled */ 840 CONTROL_FLAG_PORT_D_COMMON_MODE = 19, 841 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */ 842 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20, 843 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */ 844 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21, 845 /* ASI rate is 48kHz/96kHz */ 846 CONTROL_FLAG_ASI_96KHZ = 22, 847 /* DAC power settings able to control attached ports no/yes */ 848 CONTROL_FLAG_DACS_CONTROL_PORTS = 23, 849 /* Clock Stop OK reporting is disabled/enabled */ 850 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24, 851 /* Number of control flags */ 852 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1) 853 }; 854 855 /* 856 * Control parameter IDs 857 */ 858 enum control_param_id { 859 /* 0: None, 1: Mic1In*/ 860 CONTROL_PARAM_VIP_SOURCE = 1, 861 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */ 862 CONTROL_PARAM_SPDIF1_SOURCE = 2, 863 /* Port A output stage gain setting to use when 16 Ohm output 864 * impedance is selected*/ 865 CONTROL_PARAM_PORTA_160OHM_GAIN = 8, 866 /* Port D output stage gain setting to use when 16 Ohm output 867 * impedance is selected*/ 868 CONTROL_PARAM_PORTD_160OHM_GAIN = 10, 869 870 /* 871 * This control param name was found in the 8051 memory, and makes 872 * sense given the fact the AE-5 uses it and has the ASI flag set. 873 */ 874 CONTROL_PARAM_ASI = 23, 875 876 /* Stream Control */ 877 878 /* Select stream with the given ID */ 879 CONTROL_PARAM_STREAM_ID = 24, 880 /* Source connection point for the selected stream */ 881 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25, 882 /* Destination connection point for the selected stream */ 883 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26, 884 /* Number of audio channels in the selected stream */ 885 CONTROL_PARAM_STREAMS_CHANNELS = 27, 886 /*Enable control for the selected stream */ 887 CONTROL_PARAM_STREAM_CONTROL = 28, 888 889 /* Connection Point Control */ 890 891 /* Select connection point with the given ID */ 892 CONTROL_PARAM_CONN_POINT_ID = 29, 893 /* Connection point sample rate */ 894 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30, 895 896 /* Node Control */ 897 898 /* Select HDA node with the given ID */ 899 CONTROL_PARAM_NODE_ID = 31 900 }; 901 902 /* 903 * Dsp Io Status codes 904 */ 905 enum hda_vendor_status_dspio { 906 /* Success */ 907 VENDOR_STATUS_DSPIO_OK = 0x00, 908 /* Busy, unable to accept new command, the host must retry */ 909 VENDOR_STATUS_DSPIO_BUSY = 0x01, 910 /* SCP command queue is full */ 911 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02, 912 /* SCP response queue is empty */ 913 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03 914 }; 915 916 /* 917 * Chip Io Status codes 918 */ 919 enum hda_vendor_status_chipio { 920 /* Success */ 921 VENDOR_STATUS_CHIPIO_OK = 0x00, 922 /* Busy, unable to accept new command, the host must retry */ 923 VENDOR_STATUS_CHIPIO_BUSY = 0x01 924 }; 925 926 /* 927 * CA0132 sample rate 928 */ 929 enum ca0132_sample_rate { 930 SR_6_000 = 0x00, 931 SR_8_000 = 0x01, 932 SR_9_600 = 0x02, 933 SR_11_025 = 0x03, 934 SR_16_000 = 0x04, 935 SR_22_050 = 0x05, 936 SR_24_000 = 0x06, 937 SR_32_000 = 0x07, 938 SR_44_100 = 0x08, 939 SR_48_000 = 0x09, 940 SR_88_200 = 0x0A, 941 SR_96_000 = 0x0B, 942 SR_144_000 = 0x0C, 943 SR_176_400 = 0x0D, 944 SR_192_000 = 0x0E, 945 SR_384_000 = 0x0F, 946 947 SR_COUNT = 0x10, 948 949 SR_RATE_UNKNOWN = 0x1F 950 }; 951 952 enum dsp_download_state { 953 DSP_DOWNLOAD_FAILED = -1, 954 DSP_DOWNLOAD_INIT = 0, 955 DSP_DOWNLOADING = 1, 956 DSP_DOWNLOADED = 2 957 }; 958 959 /* retrieve parameters from hda format */ 960 #define get_hdafmt_chs(fmt) (fmt & 0xf) 961 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7) 962 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f) 963 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1) 964 965 /* 966 * CA0132 specific 967 */ 968 969 struct ca0132_spec { 970 const struct snd_kcontrol_new *mixers[5]; 971 unsigned int num_mixers; 972 const struct hda_verb *base_init_verbs; 973 const struct hda_verb *base_exit_verbs; 974 const struct hda_verb *chip_init_verbs; 975 const struct hda_verb *desktop_init_verbs; 976 struct hda_verb *spec_init_verbs; 977 struct auto_pin_cfg autocfg; 978 979 /* Nodes configurations */ 980 struct hda_multi_out multiout; 981 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS]; 982 hda_nid_t dacs[AUTO_CFG_MAX_OUTS]; 983 unsigned int num_outputs; 984 hda_nid_t input_pins[AUTO_PIN_LAST]; 985 hda_nid_t adcs[AUTO_PIN_LAST]; 986 hda_nid_t dig_out; 987 hda_nid_t dig_in; 988 unsigned int num_inputs; 989 hda_nid_t shared_mic_nid; 990 hda_nid_t shared_out_nid; 991 hda_nid_t unsol_tag_hp; 992 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */ 993 hda_nid_t unsol_tag_amic1; 994 995 /* chip access */ 996 struct mutex chipio_mutex; /* chip access mutex */ 997 u32 curr_chip_addx; 998 999 /* DSP download related */ 1000 enum dsp_download_state dsp_state; 1001 unsigned int dsp_stream_id; 1002 unsigned int wait_scp; 1003 unsigned int wait_scp_header; 1004 unsigned int wait_num_data; 1005 unsigned int scp_resp_header; 1006 unsigned int scp_resp_data[4]; 1007 unsigned int scp_resp_count; 1008 bool alt_firmware_present; 1009 bool startup_check_entered; 1010 bool dsp_reload; 1011 1012 /* mixer and effects related */ 1013 unsigned char dmic_ctl; 1014 int cur_out_type; 1015 int cur_mic_type; 1016 long vnode_lvol[VNODES_COUNT]; 1017 long vnode_rvol[VNODES_COUNT]; 1018 long vnode_lswitch[VNODES_COUNT]; 1019 long vnode_rswitch[VNODES_COUNT]; 1020 long effects_switch[EFFECTS_COUNT]; 1021 long voicefx_val; 1022 long cur_mic_boost; 1023 /* ca0132_alt control related values */ 1024 unsigned char in_enum_val; 1025 unsigned char out_enum_val; 1026 unsigned char mic_boost_enum_val; 1027 unsigned char smart_volume_setting; 1028 long fx_ctl_val[EFFECT_LEVEL_SLIDERS]; 1029 long xbass_xover_freq; 1030 long eq_preset_val; 1031 unsigned int tlv[4]; 1032 struct hda_vmaster_mute_hook vmaster_mute; 1033 /* AE-5 Control values */ 1034 unsigned char ae5_headphone_gain_val; 1035 unsigned char ae5_filter_val; 1036 /* ZxR Control Values */ 1037 unsigned char zxr_gain_set; 1038 1039 struct hda_codec *codec; 1040 struct delayed_work unsol_hp_work; 1041 int quirk; 1042 1043 #ifdef ENABLE_TUNING_CONTROLS 1044 long cur_ctl_vals[TUNING_CTLS_COUNT]; 1045 #endif 1046 /* 1047 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster 1048 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown 1049 * things. 1050 */ 1051 bool use_pci_mmio; 1052 void __iomem *mem_base; 1053 1054 /* 1055 * Whether or not to use the alt functions like alt_select_out, 1056 * alt_select_in, etc. Only used on desktop codecs for now, because of 1057 * surround sound support. 1058 */ 1059 bool use_alt_functions; 1060 1061 /* 1062 * Whether or not to use alt controls: volume effect sliders, EQ 1063 * presets, smart volume presets, and new control names with FX prefix. 1064 * Renames PlayEnhancement and CrystalVoice too. 1065 */ 1066 bool use_alt_controls; 1067 }; 1068 1069 /* 1070 * CA0132 quirks table 1071 */ 1072 enum { 1073 QUIRK_NONE, 1074 QUIRK_ALIENWARE, 1075 QUIRK_ALIENWARE_M17XR4, 1076 QUIRK_SBZ, 1077 QUIRK_ZXR, 1078 QUIRK_ZXR_DBPRO, 1079 QUIRK_R3DI, 1080 QUIRK_R3D, 1081 QUIRK_AE5, 1082 }; 1083 1084 #ifdef CONFIG_PCI 1085 #define ca0132_quirk(spec) ((spec)->quirk) 1086 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio) 1087 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions) 1088 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls) 1089 #else 1090 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; }) 1091 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; }) 1092 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; }) 1093 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; }) 1094 #endif 1095 1096 static const struct hda_pintbl alienware_pincfgs[] = { 1097 { 0x0b, 0x90170110 }, /* Builtin Speaker */ 1098 { 0x0c, 0x411111f0 }, /* N/A */ 1099 { 0x0d, 0x411111f0 }, /* N/A */ 1100 { 0x0e, 0x411111f0 }, /* N/A */ 1101 { 0x0f, 0x0321101f }, /* HP */ 1102 { 0x10, 0x411111f0 }, /* Headset? disabled for now */ 1103 { 0x11, 0x03a11021 }, /* Mic */ 1104 { 0x12, 0xd5a30140 }, /* Builtin Mic */ 1105 { 0x13, 0x411111f0 }, /* N/A */ 1106 { 0x18, 0x411111f0 }, /* N/A */ 1107 {} 1108 }; 1109 1110 /* Sound Blaster Z pin configs taken from Windows Driver */ 1111 static const struct hda_pintbl sbz_pincfgs[] = { 1112 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1113 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1114 { 0x0d, 0x014510f0 }, /* Digital Out */ 1115 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1116 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */ 1117 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1118 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1119 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1120 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1121 { 0x18, 0x50d000f0 }, /* N/A */ 1122 {} 1123 }; 1124 1125 /* Sound Blaster ZxR pin configs taken from Windows Driver */ 1126 static const struct hda_pintbl zxr_pincfgs[] = { 1127 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */ 1128 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/ 1129 { 0x0d, 0x014510f0 }, /* Digital Out */ 1130 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/ 1131 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */ 1132 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */ 1133 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */ 1134 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */ 1135 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1136 { 0x18, 0x50d000f0 }, /* N/A */ 1137 {} 1138 }; 1139 1140 /* Recon3D pin configs taken from Windows Driver */ 1141 static const struct hda_pintbl r3d_pincfgs[] = { 1142 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1143 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1144 { 0x0d, 0x014510f0 }, /* Digital Out */ 1145 { 0x0e, 0x01c520f0 }, /* SPDIF In */ 1146 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1147 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1148 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1149 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1150 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1151 { 0x18, 0x50d000f0 }, /* N/A */ 1152 {} 1153 }; 1154 1155 /* Sound Blaster AE-5 pin configs taken from Windows Driver */ 1156 static const struct hda_pintbl ae5_pincfgs[] = { 1157 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */ 1158 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1159 { 0x0d, 0x014510f0 }, /* Digital Out */ 1160 { 0x0e, 0x01c510f0 }, /* SPDIF In */ 1161 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */ 1162 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */ 1163 { 0x11, 0x01a170ff }, /* Port B -- LineMicIn2 / Rear Headphone */ 1164 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */ 1165 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1166 { 0x18, 0x50d000f0 }, /* N/A */ 1167 {} 1168 }; 1169 1170 /* Recon3D integrated pin configs taken from Windows Driver */ 1171 static const struct hda_pintbl r3di_pincfgs[] = { 1172 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */ 1173 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */ 1174 { 0x0d, 0x014510f0 }, /* Digital Out */ 1175 { 0x0e, 0x41c520f0 }, /* SPDIF In */ 1176 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */ 1177 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */ 1178 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */ 1179 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */ 1180 { 0x13, 0x908700f0 }, /* What U Hear In*/ 1181 { 0x18, 0x500000f0 }, /* N/A */ 1182 {} 1183 }; 1184 1185 static const struct snd_pci_quirk ca0132_quirks[] = { 1186 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4), 1187 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE), 1188 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE), 1189 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE), 1190 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ), 1191 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ), 1192 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ), 1193 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI), 1194 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), 1195 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), 1196 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), 1197 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5), 1198 {} 1199 }; 1200 1201 /* 1202 * CA0132 codec access 1203 */ 1204 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid, 1205 unsigned int verb, unsigned int parm, unsigned int *res) 1206 { 1207 unsigned int response; 1208 response = snd_hda_codec_read(codec, nid, 0, verb, parm); 1209 *res = response; 1210 1211 return ((response == -1) ? -1 : 0); 1212 } 1213 1214 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid, 1215 unsigned short converter_format, unsigned int *res) 1216 { 1217 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT, 1218 converter_format & 0xffff, res); 1219 } 1220 1221 static int codec_set_converter_stream_channel(struct hda_codec *codec, 1222 hda_nid_t nid, unsigned char stream, 1223 unsigned char channel, unsigned int *res) 1224 { 1225 unsigned char converter_stream_channel = 0; 1226 1227 converter_stream_channel = (stream << 4) | (channel & 0x0f); 1228 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID, 1229 converter_stream_channel, res); 1230 } 1231 1232 /* Chip access helper function */ 1233 static int chipio_send(struct hda_codec *codec, 1234 unsigned int reg, 1235 unsigned int data) 1236 { 1237 unsigned int res; 1238 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1239 1240 /* send bits of data specified by reg */ 1241 do { 1242 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1243 reg, data); 1244 if (res == VENDOR_STATUS_CHIPIO_OK) 1245 return 0; 1246 msleep(20); 1247 } while (time_before(jiffies, timeout)); 1248 1249 return -EIO; 1250 } 1251 1252 /* 1253 * Write chip address through the vendor widget -- NOT protected by the Mutex! 1254 */ 1255 static int chipio_write_address(struct hda_codec *codec, 1256 unsigned int chip_addx) 1257 { 1258 struct ca0132_spec *spec = codec->spec; 1259 int res; 1260 1261 if (spec->curr_chip_addx == chip_addx) 1262 return 0; 1263 1264 /* send low 16 bits of the address */ 1265 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW, 1266 chip_addx & 0xffff); 1267 1268 if (res != -EIO) { 1269 /* send high 16 bits of the address */ 1270 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH, 1271 chip_addx >> 16); 1272 } 1273 1274 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx; 1275 1276 return res; 1277 } 1278 1279 /* 1280 * Write data through the vendor widget -- NOT protected by the Mutex! 1281 */ 1282 static int chipio_write_data(struct hda_codec *codec, unsigned int data) 1283 { 1284 struct ca0132_spec *spec = codec->spec; 1285 int res; 1286 1287 /* send low 16 bits of the data */ 1288 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff); 1289 1290 if (res != -EIO) { 1291 /* send high 16 bits of the data */ 1292 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH, 1293 data >> 16); 1294 } 1295 1296 /*If no error encountered, automatically increment the address 1297 as per chip behaviour*/ 1298 spec->curr_chip_addx = (res != -EIO) ? 1299 (spec->curr_chip_addx + 4) : ~0U; 1300 return res; 1301 } 1302 1303 /* 1304 * Write multiple data through the vendor widget -- NOT protected by the Mutex! 1305 */ 1306 static int chipio_write_data_multiple(struct hda_codec *codec, 1307 const u32 *data, 1308 unsigned int count) 1309 { 1310 int status = 0; 1311 1312 if (data == NULL) { 1313 codec_dbg(codec, "chipio_write_data null ptr\n"); 1314 return -EINVAL; 1315 } 1316 1317 while ((count-- != 0) && (status == 0)) 1318 status = chipio_write_data(codec, *data++); 1319 1320 return status; 1321 } 1322 1323 1324 /* 1325 * Read data through the vendor widget -- NOT protected by the Mutex! 1326 */ 1327 static int chipio_read_data(struct hda_codec *codec, unsigned int *data) 1328 { 1329 struct ca0132_spec *spec = codec->spec; 1330 int res; 1331 1332 /* post read */ 1333 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0); 1334 1335 if (res != -EIO) { 1336 /* read status */ 1337 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 1338 } 1339 1340 if (res != -EIO) { 1341 /* read data */ 1342 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 1343 VENDOR_CHIPIO_HIC_READ_DATA, 1344 0); 1345 } 1346 1347 /*If no error encountered, automatically increment the address 1348 as per chip behaviour*/ 1349 spec->curr_chip_addx = (res != -EIO) ? 1350 (spec->curr_chip_addx + 4) : ~0U; 1351 return res; 1352 } 1353 1354 /* 1355 * Write given value to the given address through the chip I/O widget. 1356 * protected by the Mutex 1357 */ 1358 static int chipio_write(struct hda_codec *codec, 1359 unsigned int chip_addx, const unsigned int data) 1360 { 1361 struct ca0132_spec *spec = codec->spec; 1362 int err; 1363 1364 mutex_lock(&spec->chipio_mutex); 1365 1366 /* write the address, and if successful proceed to write data */ 1367 err = chipio_write_address(codec, chip_addx); 1368 if (err < 0) 1369 goto exit; 1370 1371 err = chipio_write_data(codec, data); 1372 if (err < 0) 1373 goto exit; 1374 1375 exit: 1376 mutex_unlock(&spec->chipio_mutex); 1377 return err; 1378 } 1379 1380 /* 1381 * Write given value to the given address through the chip I/O widget. 1382 * not protected by the Mutex 1383 */ 1384 static int chipio_write_no_mutex(struct hda_codec *codec, 1385 unsigned int chip_addx, const unsigned int data) 1386 { 1387 int err; 1388 1389 1390 /* write the address, and if successful proceed to write data */ 1391 err = chipio_write_address(codec, chip_addx); 1392 if (err < 0) 1393 goto exit; 1394 1395 err = chipio_write_data(codec, data); 1396 if (err < 0) 1397 goto exit; 1398 1399 exit: 1400 return err; 1401 } 1402 1403 /* 1404 * Write multiple values to the given address through the chip I/O widget. 1405 * protected by the Mutex 1406 */ 1407 static int chipio_write_multiple(struct hda_codec *codec, 1408 u32 chip_addx, 1409 const u32 *data, 1410 unsigned int count) 1411 { 1412 struct ca0132_spec *spec = codec->spec; 1413 int status; 1414 1415 mutex_lock(&spec->chipio_mutex); 1416 status = chipio_write_address(codec, chip_addx); 1417 if (status < 0) 1418 goto error; 1419 1420 status = chipio_write_data_multiple(codec, data, count); 1421 error: 1422 mutex_unlock(&spec->chipio_mutex); 1423 1424 return status; 1425 } 1426 1427 /* 1428 * Read the given address through the chip I/O widget 1429 * protected by the Mutex 1430 */ 1431 static int chipio_read(struct hda_codec *codec, 1432 unsigned int chip_addx, unsigned int *data) 1433 { 1434 struct ca0132_spec *spec = codec->spec; 1435 int err; 1436 1437 mutex_lock(&spec->chipio_mutex); 1438 1439 /* write the address, and if successful proceed to write data */ 1440 err = chipio_write_address(codec, chip_addx); 1441 if (err < 0) 1442 goto exit; 1443 1444 err = chipio_read_data(codec, data); 1445 if (err < 0) 1446 goto exit; 1447 1448 exit: 1449 mutex_unlock(&spec->chipio_mutex); 1450 return err; 1451 } 1452 1453 /* 1454 * Set chip control flags through the chip I/O widget. 1455 */ 1456 static void chipio_set_control_flag(struct hda_codec *codec, 1457 enum control_flag_id flag_id, 1458 bool flag_state) 1459 { 1460 unsigned int val; 1461 unsigned int flag_bit; 1462 1463 flag_bit = (flag_state ? 1 : 0); 1464 val = (flag_bit << 7) | (flag_id); 1465 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1466 VENDOR_CHIPIO_FLAG_SET, val); 1467 } 1468 1469 /* 1470 * Set chip parameters through the chip I/O widget. 1471 */ 1472 static void chipio_set_control_param(struct hda_codec *codec, 1473 enum control_param_id param_id, int param_val) 1474 { 1475 struct ca0132_spec *spec = codec->spec; 1476 int val; 1477 1478 if ((param_id < 32) && (param_val < 8)) { 1479 val = (param_val << 5) | (param_id); 1480 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1481 VENDOR_CHIPIO_PARAM_SET, val); 1482 } else { 1483 mutex_lock(&spec->chipio_mutex); 1484 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1485 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1486 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1487 param_id); 1488 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1489 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1490 param_val); 1491 } 1492 mutex_unlock(&spec->chipio_mutex); 1493 } 1494 } 1495 1496 /* 1497 * Set chip parameters through the chip I/O widget. NO MUTEX. 1498 */ 1499 static void chipio_set_control_param_no_mutex(struct hda_codec *codec, 1500 enum control_param_id param_id, int param_val) 1501 { 1502 int val; 1503 1504 if ((param_id < 32) && (param_val < 8)) { 1505 val = (param_val << 5) | (param_id); 1506 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1507 VENDOR_CHIPIO_PARAM_SET, val); 1508 } else { 1509 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) { 1510 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1511 VENDOR_CHIPIO_PARAM_EX_ID_SET, 1512 param_id); 1513 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1514 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 1515 param_val); 1516 } 1517 } 1518 } 1519 /* 1520 * Connect stream to a source point, and then connect 1521 * that source point to a destination point. 1522 */ 1523 static void chipio_set_stream_source_dest(struct hda_codec *codec, 1524 int streamid, int source_point, int dest_point) 1525 { 1526 chipio_set_control_param_no_mutex(codec, 1527 CONTROL_PARAM_STREAM_ID, streamid); 1528 chipio_set_control_param_no_mutex(codec, 1529 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point); 1530 chipio_set_control_param_no_mutex(codec, 1531 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point); 1532 } 1533 1534 /* 1535 * Set number of channels in the selected stream. 1536 */ 1537 static void chipio_set_stream_channels(struct hda_codec *codec, 1538 int streamid, unsigned int channels) 1539 { 1540 chipio_set_control_param_no_mutex(codec, 1541 CONTROL_PARAM_STREAM_ID, streamid); 1542 chipio_set_control_param_no_mutex(codec, 1543 CONTROL_PARAM_STREAMS_CHANNELS, channels); 1544 } 1545 1546 /* 1547 * Enable/Disable audio stream. 1548 */ 1549 static void chipio_set_stream_control(struct hda_codec *codec, 1550 int streamid, int enable) 1551 { 1552 chipio_set_control_param_no_mutex(codec, 1553 CONTROL_PARAM_STREAM_ID, streamid); 1554 chipio_set_control_param_no_mutex(codec, 1555 CONTROL_PARAM_STREAM_CONTROL, enable); 1556 } 1557 1558 1559 /* 1560 * Set sampling rate of the connection point. NO MUTEX. 1561 */ 1562 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec, 1563 int connid, enum ca0132_sample_rate rate) 1564 { 1565 chipio_set_control_param_no_mutex(codec, 1566 CONTROL_PARAM_CONN_POINT_ID, connid); 1567 chipio_set_control_param_no_mutex(codec, 1568 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate); 1569 } 1570 1571 /* 1572 * Set sampling rate of the connection point. 1573 */ 1574 static void chipio_set_conn_rate(struct hda_codec *codec, 1575 int connid, enum ca0132_sample_rate rate) 1576 { 1577 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid); 1578 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, 1579 rate); 1580 } 1581 1582 /* 1583 * Writes to the 8051's internal address space directly instead of indirectly, 1584 * giving access to the special function registers located at addresses 1585 * 0x80-0xFF. 1586 */ 1587 static void chipio_8051_write_direct(struct hda_codec *codec, 1588 unsigned int addr, unsigned int data) 1589 { 1590 unsigned int verb; 1591 1592 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data; 1593 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr); 1594 } 1595 1596 /* 1597 * Enable clocks. 1598 */ 1599 static void chipio_enable_clocks(struct hda_codec *codec) 1600 { 1601 struct ca0132_spec *spec = codec->spec; 1602 1603 mutex_lock(&spec->chipio_mutex); 1604 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1605 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0); 1606 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1607 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1608 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1609 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5); 1610 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1611 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b); 1612 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1613 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6); 1614 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 1615 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff); 1616 mutex_unlock(&spec->chipio_mutex); 1617 } 1618 1619 /* 1620 * CA0132 DSP IO stuffs 1621 */ 1622 static int dspio_send(struct hda_codec *codec, unsigned int reg, 1623 unsigned int data) 1624 { 1625 int res; 1626 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1627 1628 /* send bits of data specified by reg to dsp */ 1629 do { 1630 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data); 1631 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY)) 1632 return res; 1633 msleep(20); 1634 } while (time_before(jiffies, timeout)); 1635 1636 return -EIO; 1637 } 1638 1639 /* 1640 * Wait for DSP to be ready for commands 1641 */ 1642 static void dspio_write_wait(struct hda_codec *codec) 1643 { 1644 int status; 1645 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1646 1647 do { 1648 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1649 VENDOR_DSPIO_STATUS, 0); 1650 if ((status == VENDOR_STATUS_DSPIO_OK) || 1651 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)) 1652 break; 1653 msleep(1); 1654 } while (time_before(jiffies, timeout)); 1655 } 1656 1657 /* 1658 * Write SCP data to DSP 1659 */ 1660 static int dspio_write(struct hda_codec *codec, unsigned int scp_data) 1661 { 1662 struct ca0132_spec *spec = codec->spec; 1663 int status; 1664 1665 dspio_write_wait(codec); 1666 1667 mutex_lock(&spec->chipio_mutex); 1668 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW, 1669 scp_data & 0xffff); 1670 if (status < 0) 1671 goto error; 1672 1673 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH, 1674 scp_data >> 16); 1675 if (status < 0) 1676 goto error; 1677 1678 /* OK, now check if the write itself has executed*/ 1679 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1680 VENDOR_DSPIO_STATUS, 0); 1681 error: 1682 mutex_unlock(&spec->chipio_mutex); 1683 1684 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ? 1685 -EIO : 0; 1686 } 1687 1688 /* 1689 * Write multiple SCP data to DSP 1690 */ 1691 static int dspio_write_multiple(struct hda_codec *codec, 1692 unsigned int *buffer, unsigned int size) 1693 { 1694 int status = 0; 1695 unsigned int count; 1696 1697 if (buffer == NULL) 1698 return -EINVAL; 1699 1700 count = 0; 1701 while (count < size) { 1702 status = dspio_write(codec, *buffer++); 1703 if (status != 0) 1704 break; 1705 count++; 1706 } 1707 1708 return status; 1709 } 1710 1711 static int dspio_read(struct hda_codec *codec, unsigned int *data) 1712 { 1713 int status; 1714 1715 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0); 1716 if (status == -EIO) 1717 return status; 1718 1719 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0); 1720 if (status == -EIO || 1721 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY) 1722 return -EIO; 1723 1724 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, 1725 VENDOR_DSPIO_SCP_READ_DATA, 0); 1726 1727 return 0; 1728 } 1729 1730 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer, 1731 unsigned int *buf_size, unsigned int size_count) 1732 { 1733 int status = 0; 1734 unsigned int size = *buf_size; 1735 unsigned int count; 1736 unsigned int skip_count; 1737 unsigned int dummy; 1738 1739 if (buffer == NULL) 1740 return -1; 1741 1742 count = 0; 1743 while (count < size && count < size_count) { 1744 status = dspio_read(codec, buffer++); 1745 if (status != 0) 1746 break; 1747 count++; 1748 } 1749 1750 skip_count = count; 1751 if (status == 0) { 1752 while (skip_count < size) { 1753 status = dspio_read(codec, &dummy); 1754 if (status != 0) 1755 break; 1756 skip_count++; 1757 } 1758 } 1759 *buf_size = count; 1760 1761 return status; 1762 } 1763 1764 /* 1765 * Construct the SCP header using corresponding fields 1766 */ 1767 static inline unsigned int 1768 make_scp_header(unsigned int target_id, unsigned int source_id, 1769 unsigned int get_flag, unsigned int req, 1770 unsigned int device_flag, unsigned int resp_flag, 1771 unsigned int error_flag, unsigned int data_size) 1772 { 1773 unsigned int header = 0; 1774 1775 header = (data_size & 0x1f) << 27; 1776 header |= (error_flag & 0x01) << 26; 1777 header |= (resp_flag & 0x01) << 25; 1778 header |= (device_flag & 0x01) << 24; 1779 header |= (req & 0x7f) << 17; 1780 header |= (get_flag & 0x01) << 16; 1781 header |= (source_id & 0xff) << 8; 1782 header |= target_id & 0xff; 1783 1784 return header; 1785 } 1786 1787 /* 1788 * Extract corresponding fields from SCP header 1789 */ 1790 static inline void 1791 extract_scp_header(unsigned int header, 1792 unsigned int *target_id, unsigned int *source_id, 1793 unsigned int *get_flag, unsigned int *req, 1794 unsigned int *device_flag, unsigned int *resp_flag, 1795 unsigned int *error_flag, unsigned int *data_size) 1796 { 1797 if (data_size) 1798 *data_size = (header >> 27) & 0x1f; 1799 if (error_flag) 1800 *error_flag = (header >> 26) & 0x01; 1801 if (resp_flag) 1802 *resp_flag = (header >> 25) & 0x01; 1803 if (device_flag) 1804 *device_flag = (header >> 24) & 0x01; 1805 if (req) 1806 *req = (header >> 17) & 0x7f; 1807 if (get_flag) 1808 *get_flag = (header >> 16) & 0x01; 1809 if (source_id) 1810 *source_id = (header >> 8) & 0xff; 1811 if (target_id) 1812 *target_id = header & 0xff; 1813 } 1814 1815 #define SCP_MAX_DATA_WORDS (16) 1816 1817 /* Structure to contain any SCP message */ 1818 struct scp_msg { 1819 unsigned int hdr; 1820 unsigned int data[SCP_MAX_DATA_WORDS]; 1821 }; 1822 1823 static void dspio_clear_response_queue(struct hda_codec *codec) 1824 { 1825 unsigned int dummy = 0; 1826 int status = -1; 1827 1828 /* clear all from the response queue */ 1829 do { 1830 status = dspio_read(codec, &dummy); 1831 } while (status == 0); 1832 } 1833 1834 static int dspio_get_response_data(struct hda_codec *codec) 1835 { 1836 struct ca0132_spec *spec = codec->spec; 1837 unsigned int data = 0; 1838 unsigned int count; 1839 1840 if (dspio_read(codec, &data) < 0) 1841 return -EIO; 1842 1843 if ((data & 0x00ffffff) == spec->wait_scp_header) { 1844 spec->scp_resp_header = data; 1845 spec->scp_resp_count = data >> 27; 1846 count = spec->wait_num_data; 1847 dspio_read_multiple(codec, spec->scp_resp_data, 1848 &spec->scp_resp_count, count); 1849 return 0; 1850 } 1851 1852 return -EIO; 1853 } 1854 1855 /* 1856 * Send SCP message to DSP 1857 */ 1858 static int dspio_send_scp_message(struct hda_codec *codec, 1859 unsigned char *send_buf, 1860 unsigned int send_buf_size, 1861 unsigned char *return_buf, 1862 unsigned int return_buf_size, 1863 unsigned int *bytes_returned) 1864 { 1865 struct ca0132_spec *spec = codec->spec; 1866 int status = -1; 1867 unsigned int scp_send_size = 0; 1868 unsigned int total_size; 1869 bool waiting_for_resp = false; 1870 unsigned int header; 1871 struct scp_msg *ret_msg; 1872 unsigned int resp_src_id, resp_target_id; 1873 unsigned int data_size, src_id, target_id, get_flag, device_flag; 1874 1875 if (bytes_returned) 1876 *bytes_returned = 0; 1877 1878 /* get scp header from buffer */ 1879 header = *((unsigned int *)send_buf); 1880 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL, 1881 &device_flag, NULL, NULL, &data_size); 1882 scp_send_size = data_size + 1; 1883 total_size = (scp_send_size * 4); 1884 1885 if (send_buf_size < total_size) 1886 return -EINVAL; 1887 1888 if (get_flag || device_flag) { 1889 if (!return_buf || return_buf_size < 4 || !bytes_returned) 1890 return -EINVAL; 1891 1892 spec->wait_scp_header = *((unsigned int *)send_buf); 1893 1894 /* swap source id with target id */ 1895 resp_target_id = src_id; 1896 resp_src_id = target_id; 1897 spec->wait_scp_header &= 0xffff0000; 1898 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id); 1899 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1; 1900 spec->wait_scp = 1; 1901 waiting_for_resp = true; 1902 } 1903 1904 status = dspio_write_multiple(codec, (unsigned int *)send_buf, 1905 scp_send_size); 1906 if (status < 0) { 1907 spec->wait_scp = 0; 1908 return status; 1909 } 1910 1911 if (waiting_for_resp) { 1912 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 1913 memset(return_buf, 0, return_buf_size); 1914 do { 1915 msleep(20); 1916 } while (spec->wait_scp && time_before(jiffies, timeout)); 1917 waiting_for_resp = false; 1918 if (!spec->wait_scp) { 1919 ret_msg = (struct scp_msg *)return_buf; 1920 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4); 1921 memcpy(&ret_msg->data, spec->scp_resp_data, 1922 spec->wait_num_data); 1923 *bytes_returned = (spec->scp_resp_count + 1) * 4; 1924 status = 0; 1925 } else { 1926 status = -EIO; 1927 } 1928 spec->wait_scp = 0; 1929 } 1930 1931 return status; 1932 } 1933 1934 /** 1935 * Prepare and send the SCP message to DSP 1936 * @codec: the HDA codec 1937 * @mod_id: ID of the DSP module to send the command 1938 * @req: ID of request to send to the DSP module 1939 * @dir: SET or GET 1940 * @data: pointer to the data to send with the request, request specific 1941 * @len: length of the data, in bytes 1942 * @reply: point to the buffer to hold data returned for a reply 1943 * @reply_len: length of the reply buffer returned from GET 1944 * 1945 * Returns zero or a negative error code. 1946 */ 1947 static int dspio_scp(struct hda_codec *codec, 1948 int mod_id, int src_id, int req, int dir, const void *data, 1949 unsigned int len, void *reply, unsigned int *reply_len) 1950 { 1951 int status = 0; 1952 struct scp_msg scp_send, scp_reply; 1953 unsigned int ret_bytes, send_size, ret_size; 1954 unsigned int send_get_flag, reply_resp_flag, reply_error_flag; 1955 unsigned int reply_data_size; 1956 1957 memset(&scp_send, 0, sizeof(scp_send)); 1958 memset(&scp_reply, 0, sizeof(scp_reply)); 1959 1960 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS)) 1961 return -EINVAL; 1962 1963 if (dir == SCP_GET && reply == NULL) { 1964 codec_dbg(codec, "dspio_scp get but has no buffer\n"); 1965 return -EINVAL; 1966 } 1967 1968 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) { 1969 codec_dbg(codec, "dspio_scp bad resp buf len parms\n"); 1970 return -EINVAL; 1971 } 1972 1973 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req, 1974 0, 0, 0, len/sizeof(unsigned int)); 1975 if (data != NULL && len > 0) { 1976 len = min((unsigned int)(sizeof(scp_send.data)), len); 1977 memcpy(scp_send.data, data, len); 1978 } 1979 1980 ret_bytes = 0; 1981 send_size = sizeof(unsigned int) + len; 1982 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send, 1983 send_size, (unsigned char *)&scp_reply, 1984 sizeof(scp_reply), &ret_bytes); 1985 1986 if (status < 0) { 1987 codec_dbg(codec, "dspio_scp: send scp msg failed\n"); 1988 return status; 1989 } 1990 1991 /* extract send and reply headers members */ 1992 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag, 1993 NULL, NULL, NULL, NULL, NULL); 1994 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL, 1995 &reply_resp_flag, &reply_error_flag, 1996 &reply_data_size); 1997 1998 if (!send_get_flag) 1999 return 0; 2000 2001 if (reply_resp_flag && !reply_error_flag) { 2002 ret_size = (ret_bytes - sizeof(scp_reply.hdr)) 2003 / sizeof(unsigned int); 2004 2005 if (*reply_len < ret_size*sizeof(unsigned int)) { 2006 codec_dbg(codec, "reply too long for buf\n"); 2007 return -EINVAL; 2008 } else if (ret_size != reply_data_size) { 2009 codec_dbg(codec, "RetLen and HdrLen .NE.\n"); 2010 return -EINVAL; 2011 } else if (!reply) { 2012 codec_dbg(codec, "NULL reply\n"); 2013 return -EINVAL; 2014 } else { 2015 *reply_len = ret_size*sizeof(unsigned int); 2016 memcpy(reply, scp_reply.data, *reply_len); 2017 } 2018 } else { 2019 codec_dbg(codec, "reply ill-formed or errflag set\n"); 2020 return -EIO; 2021 } 2022 2023 return status; 2024 } 2025 2026 /* 2027 * Set DSP parameters 2028 */ 2029 static int dspio_set_param(struct hda_codec *codec, int mod_id, 2030 int src_id, int req, const void *data, unsigned int len) 2031 { 2032 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL, 2033 NULL); 2034 } 2035 2036 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id, 2037 int req, const unsigned int data) 2038 { 2039 return dspio_set_param(codec, mod_id, 0x20, req, &data, 2040 sizeof(unsigned int)); 2041 } 2042 2043 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, 2044 int req, const unsigned int data) 2045 { 2046 return dspio_set_param(codec, mod_id, 0x00, req, &data, 2047 sizeof(unsigned int)); 2048 } 2049 2050 /* 2051 * Allocate a DSP DMA channel via an SCP message 2052 */ 2053 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) 2054 { 2055 int status = 0; 2056 unsigned int size = sizeof(dma_chan); 2057 2058 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); 2059 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2060 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0, 2061 dma_chan, &size); 2062 2063 if (status < 0) { 2064 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n"); 2065 return status; 2066 } 2067 2068 if ((*dma_chan + 1) == 0) { 2069 codec_dbg(codec, "no free dma channels to allocate\n"); 2070 return -EBUSY; 2071 } 2072 2073 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan); 2074 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n"); 2075 2076 return status; 2077 } 2078 2079 /* 2080 * Free a DSP DMA via an SCP message 2081 */ 2082 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan) 2083 { 2084 int status = 0; 2085 unsigned int dummy = 0; 2086 2087 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n"); 2088 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan); 2089 2090 status = dspio_scp(codec, MASTERCONTROL, 0x20, 2091 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan, 2092 sizeof(dma_chan), NULL, &dummy); 2093 2094 if (status < 0) { 2095 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n"); 2096 return status; 2097 } 2098 2099 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n"); 2100 2101 return status; 2102 } 2103 2104 /* 2105 * (Re)start the DSP 2106 */ 2107 static int dsp_set_run_state(struct hda_codec *codec) 2108 { 2109 unsigned int dbg_ctrl_reg; 2110 unsigned int halt_state; 2111 int err; 2112 2113 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg); 2114 if (err < 0) 2115 return err; 2116 2117 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >> 2118 DSP_DBGCNTL_STATE_LOBIT; 2119 2120 if (halt_state != 0) { 2121 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) & 2122 DSP_DBGCNTL_SS_MASK); 2123 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2124 dbg_ctrl_reg); 2125 if (err < 0) 2126 return err; 2127 2128 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) & 2129 DSP_DBGCNTL_EXEC_MASK; 2130 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET, 2131 dbg_ctrl_reg); 2132 if (err < 0) 2133 return err; 2134 } 2135 2136 return 0; 2137 } 2138 2139 /* 2140 * Reset the DSP 2141 */ 2142 static int dsp_reset(struct hda_codec *codec) 2143 { 2144 unsigned int res; 2145 int retry = 20; 2146 2147 codec_dbg(codec, "dsp_reset\n"); 2148 do { 2149 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0); 2150 retry--; 2151 } while (res == -EIO && retry); 2152 2153 if (!retry) { 2154 codec_dbg(codec, "dsp_reset timeout\n"); 2155 return -EIO; 2156 } 2157 2158 return 0; 2159 } 2160 2161 /* 2162 * Convert chip address to DSP address 2163 */ 2164 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx, 2165 bool *code, bool *yram) 2166 { 2167 *code = *yram = false; 2168 2169 if (UC_RANGE(chip_addx, 1)) { 2170 *code = true; 2171 return UC_OFF(chip_addx); 2172 } else if (X_RANGE_ALL(chip_addx, 1)) { 2173 return X_OFF(chip_addx); 2174 } else if (Y_RANGE_ALL(chip_addx, 1)) { 2175 *yram = true; 2176 return Y_OFF(chip_addx); 2177 } 2178 2179 return INVALID_CHIP_ADDRESS; 2180 } 2181 2182 /* 2183 * Check if the DSP DMA is active 2184 */ 2185 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan) 2186 { 2187 unsigned int dma_chnlstart_reg; 2188 2189 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg); 2190 2191 return ((dma_chnlstart_reg & (1 << 2192 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0); 2193 } 2194 2195 static int dsp_dma_setup_common(struct hda_codec *codec, 2196 unsigned int chip_addx, 2197 unsigned int dma_chan, 2198 unsigned int port_map_mask, 2199 bool ovly) 2200 { 2201 int status = 0; 2202 unsigned int chnl_prop; 2203 unsigned int dsp_addx; 2204 unsigned int active; 2205 bool code, yram; 2206 2207 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n"); 2208 2209 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) { 2210 codec_dbg(codec, "dma chan num invalid\n"); 2211 return -EINVAL; 2212 } 2213 2214 if (dsp_is_dma_active(codec, dma_chan)) { 2215 codec_dbg(codec, "dma already active\n"); 2216 return -EBUSY; 2217 } 2218 2219 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2220 2221 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2222 codec_dbg(codec, "invalid chip addr\n"); 2223 return -ENXIO; 2224 } 2225 2226 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK; 2227 active = 0; 2228 2229 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n"); 2230 2231 if (ovly) { 2232 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET, 2233 &chnl_prop); 2234 2235 if (status < 0) { 2236 codec_dbg(codec, "read CHNLPROP Reg fail\n"); 2237 return status; 2238 } 2239 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n"); 2240 } 2241 2242 if (!code) 2243 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2244 else 2245 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan)); 2246 2247 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan)); 2248 2249 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop); 2250 if (status < 0) { 2251 codec_dbg(codec, "write CHNLPROP Reg fail\n"); 2252 return status; 2253 } 2254 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n"); 2255 2256 if (ovly) { 2257 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET, 2258 &active); 2259 2260 if (status < 0) { 2261 codec_dbg(codec, "read ACTIVE Reg fail\n"); 2262 return status; 2263 } 2264 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n"); 2265 } 2266 2267 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) & 2268 DSPDMAC_ACTIVE_AAR_MASK; 2269 2270 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active); 2271 if (status < 0) { 2272 codec_dbg(codec, "write ACTIVE Reg fail\n"); 2273 return status; 2274 } 2275 2276 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n"); 2277 2278 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan), 2279 port_map_mask); 2280 if (status < 0) { 2281 codec_dbg(codec, "write AUDCHSEL Reg fail\n"); 2282 return status; 2283 } 2284 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n"); 2285 2286 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan), 2287 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK); 2288 if (status < 0) { 2289 codec_dbg(codec, "write IRQCNT Reg fail\n"); 2290 return status; 2291 } 2292 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n"); 2293 2294 codec_dbg(codec, 2295 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, " 2296 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n", 2297 chip_addx, dsp_addx, dma_chan, 2298 port_map_mask, chnl_prop, active); 2299 2300 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n"); 2301 2302 return 0; 2303 } 2304 2305 /* 2306 * Setup the DSP DMA per-transfer-specific registers 2307 */ 2308 static int dsp_dma_setup(struct hda_codec *codec, 2309 unsigned int chip_addx, 2310 unsigned int count, 2311 unsigned int dma_chan) 2312 { 2313 int status = 0; 2314 bool code, yram; 2315 unsigned int dsp_addx; 2316 unsigned int addr_field; 2317 unsigned int incr_field; 2318 unsigned int base_cnt; 2319 unsigned int cur_cnt; 2320 unsigned int dma_cfg = 0; 2321 unsigned int adr_ofs = 0; 2322 unsigned int xfr_cnt = 0; 2323 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT - 2324 DSPDMAC_XFRCNT_BCNT_LOBIT + 1); 2325 2326 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n"); 2327 2328 if (count > max_dma_count) { 2329 codec_dbg(codec, "count too big\n"); 2330 return -EINVAL; 2331 } 2332 2333 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram); 2334 if (dsp_addx == INVALID_CHIP_ADDRESS) { 2335 codec_dbg(codec, "invalid chip addr\n"); 2336 return -ENXIO; 2337 } 2338 2339 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n"); 2340 2341 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT; 2342 incr_field = 0; 2343 2344 if (!code) { 2345 addr_field <<= 1; 2346 if (yram) 2347 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT); 2348 2349 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT); 2350 } 2351 2352 dma_cfg = addr_field + incr_field; 2353 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan), 2354 dma_cfg); 2355 if (status < 0) { 2356 codec_dbg(codec, "write DMACFG Reg fail\n"); 2357 return status; 2358 } 2359 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n"); 2360 2361 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT + 2362 (code ? 0 : 1)); 2363 2364 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan), 2365 adr_ofs); 2366 if (status < 0) { 2367 codec_dbg(codec, "write DSPADROFS Reg fail\n"); 2368 return status; 2369 } 2370 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n"); 2371 2372 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT; 2373 2374 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT; 2375 2376 xfr_cnt = base_cnt | cur_cnt; 2377 2378 status = chipio_write(codec, 2379 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt); 2380 if (status < 0) { 2381 codec_dbg(codec, "write XFRCNT Reg fail\n"); 2382 return status; 2383 } 2384 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n"); 2385 2386 codec_dbg(codec, 2387 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, " 2388 "ADROFS=0x%x, XFRCNT=0x%x\n", 2389 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt); 2390 2391 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n"); 2392 2393 return 0; 2394 } 2395 2396 /* 2397 * Start the DSP DMA 2398 */ 2399 static int dsp_dma_start(struct hda_codec *codec, 2400 unsigned int dma_chan, bool ovly) 2401 { 2402 unsigned int reg = 0; 2403 int status = 0; 2404 2405 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n"); 2406 2407 if (ovly) { 2408 status = chipio_read(codec, 2409 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2410 2411 if (status < 0) { 2412 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2413 return status; 2414 } 2415 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n"); 2416 2417 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2418 DSPDMAC_CHNLSTART_DIS_MASK); 2419 } 2420 2421 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2422 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT))); 2423 if (status < 0) { 2424 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2425 return status; 2426 } 2427 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n"); 2428 2429 return status; 2430 } 2431 2432 /* 2433 * Stop the DSP DMA 2434 */ 2435 static int dsp_dma_stop(struct hda_codec *codec, 2436 unsigned int dma_chan, bool ovly) 2437 { 2438 unsigned int reg = 0; 2439 int status = 0; 2440 2441 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n"); 2442 2443 if (ovly) { 2444 status = chipio_read(codec, 2445 DSPDMAC_CHNLSTART_INST_OFFSET, ®); 2446 2447 if (status < 0) { 2448 codec_dbg(codec, "read CHNLSTART reg fail\n"); 2449 return status; 2450 } 2451 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n"); 2452 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK | 2453 DSPDMAC_CHNLSTART_DIS_MASK); 2454 } 2455 2456 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET, 2457 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT))); 2458 if (status < 0) { 2459 codec_dbg(codec, "write CHNLSTART reg fail\n"); 2460 return status; 2461 } 2462 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n"); 2463 2464 return status; 2465 } 2466 2467 /** 2468 * Allocate router ports 2469 * 2470 * @codec: the HDA codec 2471 * @num_chans: number of channels in the stream 2472 * @ports_per_channel: number of ports per channel 2473 * @start_device: start device 2474 * @port_map: pointer to the port list to hold the allocated ports 2475 * 2476 * Returns zero or a negative error code. 2477 */ 2478 static int dsp_allocate_router_ports(struct hda_codec *codec, 2479 unsigned int num_chans, 2480 unsigned int ports_per_channel, 2481 unsigned int start_device, 2482 unsigned int *port_map) 2483 { 2484 int status = 0; 2485 int res; 2486 u8 val; 2487 2488 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2489 if (status < 0) 2490 return status; 2491 2492 val = start_device << 6; 2493 val |= (ports_per_channel - 1) << 4; 2494 val |= num_chans - 1; 2495 2496 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2497 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET, 2498 val); 2499 2500 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2501 VENDOR_CHIPIO_PORT_ALLOC_SET, 2502 MEM_CONNID_DSP); 2503 2504 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2505 if (status < 0) 2506 return status; 2507 2508 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0, 2509 VENDOR_CHIPIO_PORT_ALLOC_GET, 0); 2510 2511 *port_map = res; 2512 2513 return (res < 0) ? res : 0; 2514 } 2515 2516 /* 2517 * Free router ports 2518 */ 2519 static int dsp_free_router_ports(struct hda_codec *codec) 2520 { 2521 int status = 0; 2522 2523 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2524 if (status < 0) 2525 return status; 2526 2527 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 2528 VENDOR_CHIPIO_PORT_FREE_SET, 2529 MEM_CONNID_DSP); 2530 2531 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0); 2532 2533 return status; 2534 } 2535 2536 /* 2537 * Allocate DSP ports for the download stream 2538 */ 2539 static int dsp_allocate_ports(struct hda_codec *codec, 2540 unsigned int num_chans, 2541 unsigned int rate_multi, unsigned int *port_map) 2542 { 2543 int status; 2544 2545 codec_dbg(codec, " dsp_allocate_ports() -- begin\n"); 2546 2547 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2548 codec_dbg(codec, "bad rate multiple\n"); 2549 return -EINVAL; 2550 } 2551 2552 status = dsp_allocate_router_ports(codec, num_chans, 2553 rate_multi, 0, port_map); 2554 2555 codec_dbg(codec, " dsp_allocate_ports() -- complete\n"); 2556 2557 return status; 2558 } 2559 2560 static int dsp_allocate_ports_format(struct hda_codec *codec, 2561 const unsigned short fmt, 2562 unsigned int *port_map) 2563 { 2564 int status; 2565 unsigned int num_chans; 2566 2567 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1; 2568 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1; 2569 unsigned int rate_multi = sample_rate_mul / sample_rate_div; 2570 2571 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) { 2572 codec_dbg(codec, "bad rate multiple\n"); 2573 return -EINVAL; 2574 } 2575 2576 num_chans = get_hdafmt_chs(fmt) + 1; 2577 2578 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map); 2579 2580 return status; 2581 } 2582 2583 /* 2584 * free DSP ports 2585 */ 2586 static int dsp_free_ports(struct hda_codec *codec) 2587 { 2588 int status; 2589 2590 codec_dbg(codec, " dsp_free_ports() -- begin\n"); 2591 2592 status = dsp_free_router_ports(codec); 2593 if (status < 0) { 2594 codec_dbg(codec, "free router ports fail\n"); 2595 return status; 2596 } 2597 codec_dbg(codec, " dsp_free_ports() -- complete\n"); 2598 2599 return status; 2600 } 2601 2602 /* 2603 * HDA DMA engine stuffs for DSP code download 2604 */ 2605 struct dma_engine { 2606 struct hda_codec *codec; 2607 unsigned short m_converter_format; 2608 struct snd_dma_buffer *dmab; 2609 unsigned int buf_size; 2610 }; 2611 2612 2613 enum dma_state { 2614 DMA_STATE_STOP = 0, 2615 DMA_STATE_RUN = 1 2616 }; 2617 2618 static int dma_convert_to_hda_format(struct hda_codec *codec, 2619 unsigned int sample_rate, 2620 unsigned short channels, 2621 unsigned short *hda_format) 2622 { 2623 unsigned int format_val; 2624 2625 format_val = snd_hdac_calc_stream_format(sample_rate, 2626 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0); 2627 2628 if (hda_format) 2629 *hda_format = (unsigned short)format_val; 2630 2631 return 0; 2632 } 2633 2634 /* 2635 * Reset DMA for DSP download 2636 */ 2637 static int dma_reset(struct dma_engine *dma) 2638 { 2639 struct hda_codec *codec = dma->codec; 2640 struct ca0132_spec *spec = codec->spec; 2641 int status; 2642 2643 if (dma->dmab->area) 2644 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab); 2645 2646 status = snd_hda_codec_load_dsp_prepare(codec, 2647 dma->m_converter_format, 2648 dma->buf_size, 2649 dma->dmab); 2650 if (status < 0) 2651 return status; 2652 spec->dsp_stream_id = status; 2653 return 0; 2654 } 2655 2656 static int dma_set_state(struct dma_engine *dma, enum dma_state state) 2657 { 2658 bool cmd; 2659 2660 switch (state) { 2661 case DMA_STATE_STOP: 2662 cmd = false; 2663 break; 2664 case DMA_STATE_RUN: 2665 cmd = true; 2666 break; 2667 default: 2668 return 0; 2669 } 2670 2671 snd_hda_codec_load_dsp_trigger(dma->codec, cmd); 2672 return 0; 2673 } 2674 2675 static unsigned int dma_get_buffer_size(struct dma_engine *dma) 2676 { 2677 return dma->dmab->bytes; 2678 } 2679 2680 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma) 2681 { 2682 return dma->dmab->area; 2683 } 2684 2685 static int dma_xfer(struct dma_engine *dma, 2686 const unsigned int *data, 2687 unsigned int count) 2688 { 2689 memcpy(dma->dmab->area, data, count); 2690 return 0; 2691 } 2692 2693 static void dma_get_converter_format( 2694 struct dma_engine *dma, 2695 unsigned short *format) 2696 { 2697 if (format) 2698 *format = dma->m_converter_format; 2699 } 2700 2701 static unsigned int dma_get_stream_id(struct dma_engine *dma) 2702 { 2703 struct ca0132_spec *spec = dma->codec->spec; 2704 2705 return spec->dsp_stream_id; 2706 } 2707 2708 struct dsp_image_seg { 2709 u32 magic; 2710 u32 chip_addr; 2711 u32 count; 2712 u32 data[0]; 2713 }; 2714 2715 static const u32 g_magic_value = 0x4c46584d; 2716 static const u32 g_chip_addr_magic_value = 0xFFFFFF01; 2717 2718 static bool is_valid(const struct dsp_image_seg *p) 2719 { 2720 return p->magic == g_magic_value; 2721 } 2722 2723 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p) 2724 { 2725 return g_chip_addr_magic_value == p->chip_addr; 2726 } 2727 2728 static bool is_last(const struct dsp_image_seg *p) 2729 { 2730 return p->count == 0; 2731 } 2732 2733 static size_t dsp_sizeof(const struct dsp_image_seg *p) 2734 { 2735 return sizeof(*p) + p->count*sizeof(u32); 2736 } 2737 2738 static const struct dsp_image_seg *get_next_seg_ptr( 2739 const struct dsp_image_seg *p) 2740 { 2741 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p)); 2742 } 2743 2744 /* 2745 * CA0132 chip DSP transfer stuffs. For DSP download. 2746 */ 2747 #define INVALID_DMA_CHANNEL (~0U) 2748 2749 /* 2750 * Program a list of address/data pairs via the ChipIO widget. 2751 * The segment data is in the format of successive pairs of words. 2752 * These are repeated as indicated by the segment's count field. 2753 */ 2754 static int dspxfr_hci_write(struct hda_codec *codec, 2755 const struct dsp_image_seg *fls) 2756 { 2757 int status; 2758 const u32 *data; 2759 unsigned int count; 2760 2761 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) { 2762 codec_dbg(codec, "hci_write invalid params\n"); 2763 return -EINVAL; 2764 } 2765 2766 count = fls->count; 2767 data = (u32 *)(fls->data); 2768 while (count >= 2) { 2769 status = chipio_write(codec, data[0], data[1]); 2770 if (status < 0) { 2771 codec_dbg(codec, "hci_write chipio failed\n"); 2772 return status; 2773 } 2774 count -= 2; 2775 data += 2; 2776 } 2777 return 0; 2778 } 2779 2780 /** 2781 * Write a block of data into DSP code or data RAM using pre-allocated 2782 * DMA engine. 2783 * 2784 * @codec: the HDA codec 2785 * @fls: pointer to a fast load image 2786 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2787 * no relocation 2788 * @dma_engine: pointer to DMA engine to be used for DSP download 2789 * @dma_chan: The number of DMA channels used for DSP download 2790 * @port_map_mask: port mapping 2791 * @ovly: TRUE if overlay format is required 2792 * 2793 * Returns zero or a negative error code. 2794 */ 2795 static int dspxfr_one_seg(struct hda_codec *codec, 2796 const struct dsp_image_seg *fls, 2797 unsigned int reloc, 2798 struct dma_engine *dma_engine, 2799 unsigned int dma_chan, 2800 unsigned int port_map_mask, 2801 bool ovly) 2802 { 2803 int status = 0; 2804 bool comm_dma_setup_done = false; 2805 const unsigned int *data; 2806 unsigned int chip_addx; 2807 unsigned int words_to_write; 2808 unsigned int buffer_size_words; 2809 unsigned char *buffer_addx; 2810 unsigned short hda_format; 2811 unsigned int sample_rate_div; 2812 unsigned int sample_rate_mul; 2813 unsigned int num_chans; 2814 unsigned int hda_frame_size_words; 2815 unsigned int remainder_words; 2816 const u32 *data_remainder; 2817 u32 chip_addx_remainder; 2818 unsigned int run_size_words; 2819 const struct dsp_image_seg *hci_write = NULL; 2820 unsigned long timeout; 2821 bool dma_active; 2822 2823 if (fls == NULL) 2824 return -EINVAL; 2825 if (is_hci_prog_list_seg(fls)) { 2826 hci_write = fls; 2827 fls = get_next_seg_ptr(fls); 2828 } 2829 2830 if (hci_write && (!fls || is_last(fls))) { 2831 codec_dbg(codec, "hci_write\n"); 2832 return dspxfr_hci_write(codec, hci_write); 2833 } 2834 2835 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) { 2836 codec_dbg(codec, "Invalid Params\n"); 2837 return -EINVAL; 2838 } 2839 2840 data = fls->data; 2841 chip_addx = fls->chip_addr, 2842 words_to_write = fls->count; 2843 2844 if (!words_to_write) 2845 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0; 2846 if (reloc) 2847 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2); 2848 2849 if (!UC_RANGE(chip_addx, words_to_write) && 2850 !X_RANGE_ALL(chip_addx, words_to_write) && 2851 !Y_RANGE_ALL(chip_addx, words_to_write)) { 2852 codec_dbg(codec, "Invalid chip_addx Params\n"); 2853 return -EINVAL; 2854 } 2855 2856 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) / 2857 sizeof(u32); 2858 2859 buffer_addx = dma_get_buffer_addr(dma_engine); 2860 2861 if (buffer_addx == NULL) { 2862 codec_dbg(codec, "dma_engine buffer NULL\n"); 2863 return -EINVAL; 2864 } 2865 2866 dma_get_converter_format(dma_engine, &hda_format); 2867 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1; 2868 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1; 2869 num_chans = get_hdafmt_chs(hda_format) + 1; 2870 2871 hda_frame_size_words = ((sample_rate_div == 0) ? 0 : 2872 (num_chans * sample_rate_mul / sample_rate_div)); 2873 2874 if (hda_frame_size_words == 0) { 2875 codec_dbg(codec, "frmsz zero\n"); 2876 return -EINVAL; 2877 } 2878 2879 buffer_size_words = min(buffer_size_words, 2880 (unsigned int)(UC_RANGE(chip_addx, 1) ? 2881 65536 : 32768)); 2882 buffer_size_words -= buffer_size_words % hda_frame_size_words; 2883 codec_dbg(codec, 2884 "chpadr=0x%08x frmsz=%u nchan=%u " 2885 "rate_mul=%u div=%u bufsz=%u\n", 2886 chip_addx, hda_frame_size_words, num_chans, 2887 sample_rate_mul, sample_rate_div, buffer_size_words); 2888 2889 if (buffer_size_words < hda_frame_size_words) { 2890 codec_dbg(codec, "dspxfr_one_seg:failed\n"); 2891 return -EINVAL; 2892 } 2893 2894 remainder_words = words_to_write % hda_frame_size_words; 2895 data_remainder = data; 2896 chip_addx_remainder = chip_addx; 2897 2898 data += remainder_words; 2899 chip_addx += remainder_words*sizeof(u32); 2900 words_to_write -= remainder_words; 2901 2902 while (words_to_write != 0) { 2903 run_size_words = min(buffer_size_words, words_to_write); 2904 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n", 2905 words_to_write, run_size_words, remainder_words); 2906 dma_xfer(dma_engine, data, run_size_words*sizeof(u32)); 2907 if (!comm_dma_setup_done) { 2908 status = dsp_dma_stop(codec, dma_chan, ovly); 2909 if (status < 0) 2910 return status; 2911 status = dsp_dma_setup_common(codec, chip_addx, 2912 dma_chan, port_map_mask, ovly); 2913 if (status < 0) 2914 return status; 2915 comm_dma_setup_done = true; 2916 } 2917 2918 status = dsp_dma_setup(codec, chip_addx, 2919 run_size_words, dma_chan); 2920 if (status < 0) 2921 return status; 2922 status = dsp_dma_start(codec, dma_chan, ovly); 2923 if (status < 0) 2924 return status; 2925 if (!dsp_is_dma_active(codec, dma_chan)) { 2926 codec_dbg(codec, "dspxfr:DMA did not start\n"); 2927 return -EIO; 2928 } 2929 status = dma_set_state(dma_engine, DMA_STATE_RUN); 2930 if (status < 0) 2931 return status; 2932 if (remainder_words != 0) { 2933 status = chipio_write_multiple(codec, 2934 chip_addx_remainder, 2935 data_remainder, 2936 remainder_words); 2937 if (status < 0) 2938 return status; 2939 remainder_words = 0; 2940 } 2941 if (hci_write) { 2942 status = dspxfr_hci_write(codec, hci_write); 2943 if (status < 0) 2944 return status; 2945 hci_write = NULL; 2946 } 2947 2948 timeout = jiffies + msecs_to_jiffies(2000); 2949 do { 2950 dma_active = dsp_is_dma_active(codec, dma_chan); 2951 if (!dma_active) 2952 break; 2953 msleep(20); 2954 } while (time_before(jiffies, timeout)); 2955 if (dma_active) 2956 break; 2957 2958 codec_dbg(codec, "+++++ DMA complete\n"); 2959 dma_set_state(dma_engine, DMA_STATE_STOP); 2960 status = dma_reset(dma_engine); 2961 2962 if (status < 0) 2963 return status; 2964 2965 data += run_size_words; 2966 chip_addx += run_size_words*sizeof(u32); 2967 words_to_write -= run_size_words; 2968 } 2969 2970 if (remainder_words != 0) { 2971 status = chipio_write_multiple(codec, chip_addx_remainder, 2972 data_remainder, remainder_words); 2973 } 2974 2975 return status; 2976 } 2977 2978 /** 2979 * Write the entire DSP image of a DSP code/data overlay to DSP memories 2980 * 2981 * @codec: the HDA codec 2982 * @fls_data: pointer to a fast load image 2983 * @reloc: Relocation address for loading single-segment overlays, or 0 for 2984 * no relocation 2985 * @sample_rate: sampling rate of the stream used for DSP download 2986 * @channels: channels of the stream used for DSP download 2987 * @ovly: TRUE if overlay format is required 2988 * 2989 * Returns zero or a negative error code. 2990 */ 2991 static int dspxfr_image(struct hda_codec *codec, 2992 const struct dsp_image_seg *fls_data, 2993 unsigned int reloc, 2994 unsigned int sample_rate, 2995 unsigned short channels, 2996 bool ovly) 2997 { 2998 struct ca0132_spec *spec = codec->spec; 2999 int status; 3000 unsigned short hda_format = 0; 3001 unsigned int response; 3002 unsigned char stream_id = 0; 3003 struct dma_engine *dma_engine; 3004 unsigned int dma_chan; 3005 unsigned int port_map_mask; 3006 3007 if (fls_data == NULL) 3008 return -EINVAL; 3009 3010 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL); 3011 if (!dma_engine) 3012 return -ENOMEM; 3013 3014 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL); 3015 if (!dma_engine->dmab) { 3016 kfree(dma_engine); 3017 return -ENOMEM; 3018 } 3019 3020 dma_engine->codec = codec; 3021 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format); 3022 dma_engine->m_converter_format = hda_format; 3023 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY : 3024 DSP_DMA_WRITE_BUFLEN_INIT) * 2; 3025 3026 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0; 3027 3028 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL, 3029 hda_format, &response); 3030 3031 if (status < 0) { 3032 codec_dbg(codec, "set converter format fail\n"); 3033 goto exit; 3034 } 3035 3036 status = snd_hda_codec_load_dsp_prepare(codec, 3037 dma_engine->m_converter_format, 3038 dma_engine->buf_size, 3039 dma_engine->dmab); 3040 if (status < 0) 3041 goto exit; 3042 spec->dsp_stream_id = status; 3043 3044 if (ovly) { 3045 status = dspio_alloc_dma_chan(codec, &dma_chan); 3046 if (status < 0) { 3047 codec_dbg(codec, "alloc dmachan fail\n"); 3048 dma_chan = INVALID_DMA_CHANNEL; 3049 goto exit; 3050 } 3051 } 3052 3053 port_map_mask = 0; 3054 status = dsp_allocate_ports_format(codec, hda_format, 3055 &port_map_mask); 3056 if (status < 0) { 3057 codec_dbg(codec, "alloc ports fail\n"); 3058 goto exit; 3059 } 3060 3061 stream_id = dma_get_stream_id(dma_engine); 3062 status = codec_set_converter_stream_channel(codec, 3063 WIDGET_CHIP_CTRL, stream_id, 0, &response); 3064 if (status < 0) { 3065 codec_dbg(codec, "set stream chan fail\n"); 3066 goto exit; 3067 } 3068 3069 while ((fls_data != NULL) && !is_last(fls_data)) { 3070 if (!is_valid(fls_data)) { 3071 codec_dbg(codec, "FLS check fail\n"); 3072 status = -EINVAL; 3073 goto exit; 3074 } 3075 status = dspxfr_one_seg(codec, fls_data, reloc, 3076 dma_engine, dma_chan, 3077 port_map_mask, ovly); 3078 if (status < 0) 3079 break; 3080 3081 if (is_hci_prog_list_seg(fls_data)) 3082 fls_data = get_next_seg_ptr(fls_data); 3083 3084 if ((fls_data != NULL) && !is_last(fls_data)) 3085 fls_data = get_next_seg_ptr(fls_data); 3086 } 3087 3088 if (port_map_mask != 0) 3089 status = dsp_free_ports(codec); 3090 3091 if (status < 0) 3092 goto exit; 3093 3094 status = codec_set_converter_stream_channel(codec, 3095 WIDGET_CHIP_CTRL, 0, 0, &response); 3096 3097 exit: 3098 if (ovly && (dma_chan != INVALID_DMA_CHANNEL)) 3099 dspio_free_dma_chan(codec, dma_chan); 3100 3101 if (dma_engine->dmab->area) 3102 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab); 3103 kfree(dma_engine->dmab); 3104 kfree(dma_engine); 3105 3106 return status; 3107 } 3108 3109 /* 3110 * CA0132 DSP download stuffs. 3111 */ 3112 static void dspload_post_setup(struct hda_codec *codec) 3113 { 3114 struct ca0132_spec *spec = codec->spec; 3115 codec_dbg(codec, "---- dspload_post_setup ------\n"); 3116 if (!ca0132_use_alt_functions(spec)) { 3117 /*set DSP speaker to 2.0 configuration*/ 3118 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080); 3119 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000); 3120 3121 /*update write pointer*/ 3122 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002); 3123 } 3124 } 3125 3126 /** 3127 * dspload_image - Download DSP from a DSP Image Fast Load structure. 3128 * 3129 * @codec: the HDA codec 3130 * @fls: pointer to a fast load image 3131 * @ovly: TRUE if overlay format is required 3132 * @reloc: Relocation address for loading single-segment overlays, or 0 for 3133 * no relocation 3134 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE 3135 * @router_chans: number of audio router channels to be allocated (0 means use 3136 * internal defaults; max is 32) 3137 * 3138 * Download DSP from a DSP Image Fast Load structure. This structure is a 3139 * linear, non-constant sized element array of structures, each of which 3140 * contain the count of the data to be loaded, the data itself, and the 3141 * corresponding starting chip address of the starting data location. 3142 * Returns zero or a negative error code. 3143 */ 3144 static int dspload_image(struct hda_codec *codec, 3145 const struct dsp_image_seg *fls, 3146 bool ovly, 3147 unsigned int reloc, 3148 bool autostart, 3149 int router_chans) 3150 { 3151 int status = 0; 3152 unsigned int sample_rate; 3153 unsigned short channels; 3154 3155 codec_dbg(codec, "---- dspload_image begin ------\n"); 3156 if (router_chans == 0) { 3157 if (!ovly) 3158 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS; 3159 else 3160 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS; 3161 } 3162 3163 sample_rate = 48000; 3164 channels = (unsigned short)router_chans; 3165 3166 while (channels > 16) { 3167 sample_rate *= 2; 3168 channels /= 2; 3169 } 3170 3171 do { 3172 codec_dbg(codec, "Ready to program DMA\n"); 3173 if (!ovly) 3174 status = dsp_reset(codec); 3175 3176 if (status < 0) 3177 break; 3178 3179 codec_dbg(codec, "dsp_reset() complete\n"); 3180 status = dspxfr_image(codec, fls, reloc, sample_rate, channels, 3181 ovly); 3182 3183 if (status < 0) 3184 break; 3185 3186 codec_dbg(codec, "dspxfr_image() complete\n"); 3187 if (autostart && !ovly) { 3188 dspload_post_setup(codec); 3189 status = dsp_set_run_state(codec); 3190 } 3191 3192 codec_dbg(codec, "LOAD FINISHED\n"); 3193 } while (0); 3194 3195 return status; 3196 } 3197 3198 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP 3199 static bool dspload_is_loaded(struct hda_codec *codec) 3200 { 3201 unsigned int data = 0; 3202 int status = 0; 3203 3204 status = chipio_read(codec, 0x40004, &data); 3205 if ((status < 0) || (data != 1)) 3206 return false; 3207 3208 return true; 3209 } 3210 #else 3211 #define dspload_is_loaded(codec) false 3212 #endif 3213 3214 static bool dspload_wait_loaded(struct hda_codec *codec) 3215 { 3216 unsigned long timeout = jiffies + msecs_to_jiffies(2000); 3217 3218 do { 3219 if (dspload_is_loaded(codec)) { 3220 codec_info(codec, "ca0132 DSP downloaded and running\n"); 3221 return true; 3222 } 3223 msleep(20); 3224 } while (time_before(jiffies, timeout)); 3225 3226 codec_err(codec, "ca0132 failed to download DSP\n"); 3227 return false; 3228 } 3229 3230 /* 3231 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e 3232 * based cards, and has a second mmio region, region2, that's used for special 3233 * commands. 3234 */ 3235 3236 /* 3237 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5) 3238 * the mmio address 0x320 is used to set GPIO pins. The format for the data 3239 * The first eight bits are just the number of the pin. So far, I've only seen 3240 * this number go to 7. 3241 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value 3242 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and 3243 * then off to send that bit. 3244 */ 3245 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin, 3246 bool enable) 3247 { 3248 struct ca0132_spec *spec = codec->spec; 3249 unsigned short gpio_data; 3250 3251 gpio_data = gpio_pin & 0xF; 3252 gpio_data |= ((enable << 8) & 0x100); 3253 3254 writew(gpio_data, spec->mem_base + 0x320); 3255 } 3256 3257 /* 3258 * Special pci region2 commands that are only used by the AE-5. They follow 3259 * a set format, and require reads at certain points to seemingly 'clear' 3260 * the response data. My first tests didn't do these reads, and would cause 3261 * the card to get locked up until the memory was read. These commands 3262 * seem to work with three distinct values that I've taken to calling group, 3263 * target-id, and value. 3264 */ 3265 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group, 3266 unsigned int target, unsigned int value) 3267 { 3268 struct ca0132_spec *spec = codec->spec; 3269 unsigned int write_val; 3270 3271 writel(0x0000007e, spec->mem_base + 0x210); 3272 readl(spec->mem_base + 0x210); 3273 writel(0x0000005a, spec->mem_base + 0x210); 3274 readl(spec->mem_base + 0x210); 3275 readl(spec->mem_base + 0x210); 3276 3277 writel(0x00800005, spec->mem_base + 0x20c); 3278 writel(group, spec->mem_base + 0x804); 3279 3280 writel(0x00800005, spec->mem_base + 0x20c); 3281 write_val = (target & 0xff); 3282 write_val |= (value << 8); 3283 3284 3285 writel(write_val, spec->mem_base + 0x204); 3286 /* 3287 * Need delay here or else it goes too fast and works inconsistently. 3288 */ 3289 msleep(20); 3290 3291 readl(spec->mem_base + 0x860); 3292 readl(spec->mem_base + 0x854); 3293 readl(spec->mem_base + 0x840); 3294 3295 writel(0x00800004, spec->mem_base + 0x20c); 3296 writel(0x00000000, spec->mem_base + 0x210); 3297 readl(spec->mem_base + 0x210); 3298 readl(spec->mem_base + 0x210); 3299 } 3300 3301 /* 3302 * This second type of command is used for setting the sound filter type. 3303 */ 3304 static void ca0113_mmio_command_set_type2(struct hda_codec *codec, 3305 unsigned int group, unsigned int target, unsigned int value) 3306 { 3307 struct ca0132_spec *spec = codec->spec; 3308 unsigned int write_val; 3309 3310 writel(0x0000007e, spec->mem_base + 0x210); 3311 readl(spec->mem_base + 0x210); 3312 writel(0x0000005a, spec->mem_base + 0x210); 3313 readl(spec->mem_base + 0x210); 3314 readl(spec->mem_base + 0x210); 3315 3316 writel(0x00800003, spec->mem_base + 0x20c); 3317 writel(group, spec->mem_base + 0x804); 3318 3319 writel(0x00800005, spec->mem_base + 0x20c); 3320 write_val = (target & 0xff); 3321 write_val |= (value << 8); 3322 3323 3324 writel(write_val, spec->mem_base + 0x204); 3325 msleep(20); 3326 readl(spec->mem_base + 0x860); 3327 readl(spec->mem_base + 0x854); 3328 readl(spec->mem_base + 0x840); 3329 3330 writel(0x00800004, spec->mem_base + 0x20c); 3331 writel(0x00000000, spec->mem_base + 0x210); 3332 readl(spec->mem_base + 0x210); 3333 readl(spec->mem_base + 0x210); 3334 } 3335 3336 /* 3337 * Setup GPIO for the other variants of Core3D. 3338 */ 3339 3340 /* 3341 * Sets up the GPIO pins so that they are discoverable. If this isn't done, 3342 * the card shows as having no GPIO pins. 3343 */ 3344 static void ca0132_gpio_init(struct hda_codec *codec) 3345 { 3346 struct ca0132_spec *spec = codec->spec; 3347 3348 switch (ca0132_quirk(spec)) { 3349 case QUIRK_SBZ: 3350 case QUIRK_AE5: 3351 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3352 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 3353 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23); 3354 break; 3355 case QUIRK_R3DI: 3356 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 3357 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B); 3358 break; 3359 default: 3360 break; 3361 } 3362 3363 } 3364 3365 /* Sets the GPIO for audio output. */ 3366 static void ca0132_gpio_setup(struct hda_codec *codec) 3367 { 3368 struct ca0132_spec *spec = codec->spec; 3369 3370 switch (ca0132_quirk(spec)) { 3371 case QUIRK_SBZ: 3372 snd_hda_codec_write(codec, 0x01, 0, 3373 AC_VERB_SET_GPIO_DIRECTION, 0x07); 3374 snd_hda_codec_write(codec, 0x01, 0, 3375 AC_VERB_SET_GPIO_MASK, 0x07); 3376 snd_hda_codec_write(codec, 0x01, 0, 3377 AC_VERB_SET_GPIO_DATA, 0x04); 3378 snd_hda_codec_write(codec, 0x01, 0, 3379 AC_VERB_SET_GPIO_DATA, 0x06); 3380 break; 3381 case QUIRK_R3DI: 3382 snd_hda_codec_write(codec, 0x01, 0, 3383 AC_VERB_SET_GPIO_DIRECTION, 0x1E); 3384 snd_hda_codec_write(codec, 0x01, 0, 3385 AC_VERB_SET_GPIO_MASK, 0x1F); 3386 snd_hda_codec_write(codec, 0x01, 0, 3387 AC_VERB_SET_GPIO_DATA, 0x0C); 3388 break; 3389 default: 3390 break; 3391 } 3392 } 3393 3394 /* 3395 * GPIO control functions for the Recon3D integrated. 3396 */ 3397 3398 enum r3di_gpio_bit { 3399 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */ 3400 R3DI_MIC_SELECT_BIT = 1, 3401 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */ 3402 R3DI_OUT_SELECT_BIT = 2, 3403 /* 3404 * I dunno what this actually does, but it stays on until the dsp 3405 * is downloaded. 3406 */ 3407 R3DI_GPIO_DSP_DOWNLOADING = 3, 3408 /* 3409 * Same as above, no clue what it does, but it comes on after the dsp 3410 * is downloaded. 3411 */ 3412 R3DI_GPIO_DSP_DOWNLOADED = 4 3413 }; 3414 3415 enum r3di_mic_select { 3416 /* Set GPIO bit 1 to 0 for rear mic */ 3417 R3DI_REAR_MIC = 0, 3418 /* Set GPIO bit 1 to 1 for front microphone*/ 3419 R3DI_FRONT_MIC = 1 3420 }; 3421 3422 enum r3di_out_select { 3423 /* Set GPIO bit 2 to 0 for headphone */ 3424 R3DI_HEADPHONE_OUT = 0, 3425 /* Set GPIO bit 2 to 1 for speaker */ 3426 R3DI_LINE_OUT = 1 3427 }; 3428 enum r3di_dsp_status { 3429 /* Set GPIO bit 3 to 1 until DSP is downloaded */ 3430 R3DI_DSP_DOWNLOADING = 0, 3431 /* Set GPIO bit 4 to 1 once DSP is downloaded */ 3432 R3DI_DSP_DOWNLOADED = 1 3433 }; 3434 3435 3436 static void r3di_gpio_mic_set(struct hda_codec *codec, 3437 enum r3di_mic_select cur_mic) 3438 { 3439 unsigned int cur_gpio; 3440 3441 /* Get the current GPIO Data setup */ 3442 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3443 3444 switch (cur_mic) { 3445 case R3DI_REAR_MIC: 3446 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT); 3447 break; 3448 case R3DI_FRONT_MIC: 3449 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT); 3450 break; 3451 } 3452 snd_hda_codec_write(codec, codec->core.afg, 0, 3453 AC_VERB_SET_GPIO_DATA, cur_gpio); 3454 } 3455 3456 static void r3di_gpio_out_set(struct hda_codec *codec, 3457 enum r3di_out_select cur_out) 3458 { 3459 unsigned int cur_gpio; 3460 3461 /* Get the current GPIO Data setup */ 3462 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3463 3464 switch (cur_out) { 3465 case R3DI_HEADPHONE_OUT: 3466 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT); 3467 break; 3468 case R3DI_LINE_OUT: 3469 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT); 3470 break; 3471 } 3472 snd_hda_codec_write(codec, codec->core.afg, 0, 3473 AC_VERB_SET_GPIO_DATA, cur_gpio); 3474 } 3475 3476 static void r3di_gpio_dsp_status_set(struct hda_codec *codec, 3477 enum r3di_dsp_status dsp_status) 3478 { 3479 unsigned int cur_gpio; 3480 3481 /* Get the current GPIO Data setup */ 3482 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0); 3483 3484 switch (dsp_status) { 3485 case R3DI_DSP_DOWNLOADING: 3486 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING); 3487 snd_hda_codec_write(codec, codec->core.afg, 0, 3488 AC_VERB_SET_GPIO_DATA, cur_gpio); 3489 break; 3490 case R3DI_DSP_DOWNLOADED: 3491 /* Set DOWNLOADING bit to 0. */ 3492 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING); 3493 3494 snd_hda_codec_write(codec, codec->core.afg, 0, 3495 AC_VERB_SET_GPIO_DATA, cur_gpio); 3496 3497 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED); 3498 break; 3499 } 3500 3501 snd_hda_codec_write(codec, codec->core.afg, 0, 3502 AC_VERB_SET_GPIO_DATA, cur_gpio); 3503 } 3504 3505 /* 3506 * PCM callbacks 3507 */ 3508 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3509 struct hda_codec *codec, 3510 unsigned int stream_tag, 3511 unsigned int format, 3512 struct snd_pcm_substream *substream) 3513 { 3514 struct ca0132_spec *spec = codec->spec; 3515 3516 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format); 3517 3518 return 0; 3519 } 3520 3521 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3522 struct hda_codec *codec, 3523 struct snd_pcm_substream *substream) 3524 { 3525 struct ca0132_spec *spec = codec->spec; 3526 3527 if (spec->dsp_state == DSP_DOWNLOADING) 3528 return 0; 3529 3530 /*If Playback effects are on, allow stream some time to flush 3531 *effects tail*/ 3532 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 3533 msleep(50); 3534 3535 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 3536 3537 return 0; 3538 } 3539 3540 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info, 3541 struct hda_codec *codec, 3542 struct snd_pcm_substream *substream) 3543 { 3544 struct ca0132_spec *spec = codec->spec; 3545 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY; 3546 struct snd_pcm_runtime *runtime = substream->runtime; 3547 3548 if (spec->dsp_state != DSP_DOWNLOADED) 3549 return 0; 3550 3551 /* Add latency if playback enhancement and either effect is enabled. */ 3552 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) { 3553 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) || 3554 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID])) 3555 latency += DSP_PLAY_ENHANCEMENT_LATENCY; 3556 } 3557 3558 /* Applying Speaker EQ adds latency as well. */ 3559 if (spec->cur_out_type == SPEAKER_OUT) 3560 latency += DSP_SPEAKER_OUT_LATENCY; 3561 3562 return (latency * runtime->rate) / 1000; 3563 } 3564 3565 /* 3566 * Digital out 3567 */ 3568 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo, 3569 struct hda_codec *codec, 3570 struct snd_pcm_substream *substream) 3571 { 3572 struct ca0132_spec *spec = codec->spec; 3573 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3574 } 3575 3576 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3577 struct hda_codec *codec, 3578 unsigned int stream_tag, 3579 unsigned int format, 3580 struct snd_pcm_substream *substream) 3581 { 3582 struct ca0132_spec *spec = codec->spec; 3583 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3584 stream_tag, format, substream); 3585 } 3586 3587 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 3588 struct hda_codec *codec, 3589 struct snd_pcm_substream *substream) 3590 { 3591 struct ca0132_spec *spec = codec->spec; 3592 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout); 3593 } 3594 3595 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo, 3596 struct hda_codec *codec, 3597 struct snd_pcm_substream *substream) 3598 { 3599 struct ca0132_spec *spec = codec->spec; 3600 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3601 } 3602 3603 /* 3604 * Analog capture 3605 */ 3606 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo, 3607 struct hda_codec *codec, 3608 unsigned int stream_tag, 3609 unsigned int format, 3610 struct snd_pcm_substream *substream) 3611 { 3612 snd_hda_codec_setup_stream(codec, hinfo->nid, 3613 stream_tag, 0, format); 3614 3615 return 0; 3616 } 3617 3618 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo, 3619 struct hda_codec *codec, 3620 struct snd_pcm_substream *substream) 3621 { 3622 struct ca0132_spec *spec = codec->spec; 3623 3624 if (spec->dsp_state == DSP_DOWNLOADING) 3625 return 0; 3626 3627 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 3628 return 0; 3629 } 3630 3631 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info, 3632 struct hda_codec *codec, 3633 struct snd_pcm_substream *substream) 3634 { 3635 struct ca0132_spec *spec = codec->spec; 3636 unsigned int latency = DSP_CAPTURE_INIT_LATENCY; 3637 struct snd_pcm_runtime *runtime = substream->runtime; 3638 3639 if (spec->dsp_state != DSP_DOWNLOADED) 3640 return 0; 3641 3642 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 3643 latency += DSP_CRYSTAL_VOICE_LATENCY; 3644 3645 return (latency * runtime->rate) / 1000; 3646 } 3647 3648 /* 3649 * Controls stuffs. 3650 */ 3651 3652 /* 3653 * Mixer controls helpers. 3654 */ 3655 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3656 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3657 .name = xname, \ 3658 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3659 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3660 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3661 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3662 .info = ca0132_volume_info, \ 3663 .get = ca0132_volume_get, \ 3664 .put = ca0132_volume_put, \ 3665 .tlv = { .c = ca0132_volume_tlv }, \ 3666 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3667 3668 /* 3669 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the 3670 * volume put, which is used for setting the DSP volume. This was done because 3671 * the ca0132 functions were taking too much time and causing lag. 3672 */ 3673 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \ 3674 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3675 .name = xname, \ 3676 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3677 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3678 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ 3679 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ 3680 .info = snd_hda_mixer_amp_volume_info, \ 3681 .get = snd_hda_mixer_amp_volume_get, \ 3682 .put = ca0132_alt_volume_put, \ 3683 .tlv = { .c = snd_hda_mixer_amp_tlv }, \ 3684 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3685 3686 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \ 3687 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3688 .name = xname, \ 3689 .subdevice = HDA_SUBDEV_AMP_FLAG, \ 3690 .info = snd_hda_mixer_amp_switch_info, \ 3691 .get = ca0132_switch_get, \ 3692 .put = ca0132_switch_put, \ 3693 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) } 3694 3695 /* stereo */ 3696 #define CA0132_CODEC_VOL(xname, nid, dir) \ 3697 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir) 3698 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \ 3699 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir) 3700 #define CA0132_CODEC_MUTE(xname, nid, dir) \ 3701 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir) 3702 3703 /* lookup tables */ 3704 /* 3705 * Lookup table with decibel values for the DSP. When volume is changed in 3706 * Windows, the DSP is also sent the dB value in floating point. In Windows, 3707 * these values have decimal points, probably because the Windows driver 3708 * actually uses floating point. We can't here, so I made a lookup table of 3709 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the 3710 * DAC's, and 9 is the maximum. 3711 */ 3712 static const unsigned int float_vol_db_lookup[] = { 3713 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000, 3714 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000, 3715 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000, 3716 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000, 3717 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000, 3718 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000, 3719 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000, 3720 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000, 3721 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000, 3722 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000, 3723 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000, 3724 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3725 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3726 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3727 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3728 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3729 0x40C00000, 0x40E00000, 0x41000000, 0x41100000 3730 }; 3731 3732 /* 3733 * This table counts from float 0 to 1 in increments of .01, which is 3734 * useful for a few different sliders. 3735 */ 3736 static const unsigned int float_zero_to_one_lookup[] = { 3737 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3738 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3739 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3740 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3741 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3742 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3743 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3744 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3745 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3746 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3747 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3748 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3749 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3750 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3751 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3752 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3753 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3754 }; 3755 3756 /* 3757 * This table counts from float 10 to 1000, which is the range of the x-bass 3758 * crossover slider in Windows. 3759 */ 3760 static const unsigned int float_xbass_xover_lookup[] = { 3761 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000, 3762 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000, 3763 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000, 3764 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000, 3765 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000, 3766 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000, 3767 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000, 3768 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000, 3769 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000, 3770 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000, 3771 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000, 3772 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000, 3773 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000, 3774 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000, 3775 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000, 3776 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000, 3777 0x44728000, 0x44750000, 0x44778000, 0x447A0000 3778 }; 3779 3780 /* The following are for tuning of products */ 3781 #ifdef ENABLE_TUNING_CONTROLS 3782 3783 static unsigned int voice_focus_vals_lookup[] = { 3784 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000, 3785 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000, 3786 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000, 3787 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000, 3788 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000, 3789 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000, 3790 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000, 3791 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000, 3792 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000, 3793 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000, 3794 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000, 3795 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000, 3796 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000, 3797 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000, 3798 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000, 3799 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000, 3800 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000, 3801 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000, 3802 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000, 3803 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000, 3804 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000, 3805 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000, 3806 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000, 3807 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000, 3808 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000, 3809 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000, 3810 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000 3811 }; 3812 3813 static unsigned int mic_svm_vals_lookup[] = { 3814 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD, 3815 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE, 3816 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B, 3817 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F, 3818 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1, 3819 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333, 3820 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85, 3821 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7, 3822 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14, 3823 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D, 3824 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666, 3825 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F, 3826 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8, 3827 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1, 3828 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A, 3829 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333, 3830 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000 3831 }; 3832 3833 static unsigned int equalizer_vals_lookup[] = { 3834 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000, 3835 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000, 3836 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000, 3837 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000, 3838 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000, 3839 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000, 3840 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000, 3841 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 3842 0x41C00000 3843 }; 3844 3845 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, 3846 unsigned int *lookup, int idx) 3847 { 3848 int i = 0; 3849 3850 for (i = 0; i < TUNING_CTLS_COUNT; i++) 3851 if (nid == ca0132_tuning_ctls[i].nid) 3852 break; 3853 3854 snd_hda_power_up(codec); 3855 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, 3856 ca0132_tuning_ctls[i].req, 3857 &(lookup[idx]), sizeof(unsigned int)); 3858 snd_hda_power_down(codec); 3859 3860 return 1; 3861 } 3862 3863 static int tuning_ctl_get(struct snd_kcontrol *kcontrol, 3864 struct snd_ctl_elem_value *ucontrol) 3865 { 3866 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3867 struct ca0132_spec *spec = codec->spec; 3868 hda_nid_t nid = get_amp_nid(kcontrol); 3869 long *valp = ucontrol->value.integer.value; 3870 int idx = nid - TUNING_CTL_START_NID; 3871 3872 *valp = spec->cur_ctl_vals[idx]; 3873 return 0; 3874 } 3875 3876 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol, 3877 struct snd_ctl_elem_info *uinfo) 3878 { 3879 int chs = get_amp_channels(kcontrol); 3880 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3881 uinfo->count = chs == 3 ? 2 : 1; 3882 uinfo->value.integer.min = 20; 3883 uinfo->value.integer.max = 180; 3884 uinfo->value.integer.step = 1; 3885 3886 return 0; 3887 } 3888 3889 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol, 3890 struct snd_ctl_elem_value *ucontrol) 3891 { 3892 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3893 struct ca0132_spec *spec = codec->spec; 3894 hda_nid_t nid = get_amp_nid(kcontrol); 3895 long *valp = ucontrol->value.integer.value; 3896 int idx; 3897 3898 idx = nid - TUNING_CTL_START_NID; 3899 /* any change? */ 3900 if (spec->cur_ctl_vals[idx] == *valp) 3901 return 0; 3902 3903 spec->cur_ctl_vals[idx] = *valp; 3904 3905 idx = *valp - 20; 3906 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx); 3907 3908 return 1; 3909 } 3910 3911 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol, 3912 struct snd_ctl_elem_info *uinfo) 3913 { 3914 int chs = get_amp_channels(kcontrol); 3915 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3916 uinfo->count = chs == 3 ? 2 : 1; 3917 uinfo->value.integer.min = 0; 3918 uinfo->value.integer.max = 100; 3919 uinfo->value.integer.step = 1; 3920 3921 return 0; 3922 } 3923 3924 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol, 3925 struct snd_ctl_elem_value *ucontrol) 3926 { 3927 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3928 struct ca0132_spec *spec = codec->spec; 3929 hda_nid_t nid = get_amp_nid(kcontrol); 3930 long *valp = ucontrol->value.integer.value; 3931 int idx; 3932 3933 idx = nid - TUNING_CTL_START_NID; 3934 /* any change? */ 3935 if (spec->cur_ctl_vals[idx] == *valp) 3936 return 0; 3937 3938 spec->cur_ctl_vals[idx] = *valp; 3939 3940 idx = *valp; 3941 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx); 3942 3943 return 0; 3944 } 3945 3946 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol, 3947 struct snd_ctl_elem_info *uinfo) 3948 { 3949 int chs = get_amp_channels(kcontrol); 3950 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3951 uinfo->count = chs == 3 ? 2 : 1; 3952 uinfo->value.integer.min = 0; 3953 uinfo->value.integer.max = 48; 3954 uinfo->value.integer.step = 1; 3955 3956 return 0; 3957 } 3958 3959 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol, 3960 struct snd_ctl_elem_value *ucontrol) 3961 { 3962 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 3963 struct ca0132_spec *spec = codec->spec; 3964 hda_nid_t nid = get_amp_nid(kcontrol); 3965 long *valp = ucontrol->value.integer.value; 3966 int idx; 3967 3968 idx = nid - TUNING_CTL_START_NID; 3969 /* any change? */ 3970 if (spec->cur_ctl_vals[idx] == *valp) 3971 return 0; 3972 3973 spec->cur_ctl_vals[idx] = *valp; 3974 3975 idx = *valp; 3976 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx); 3977 3978 return 1; 3979 } 3980 3981 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0); 3982 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0); 3983 3984 static int add_tuning_control(struct hda_codec *codec, 3985 hda_nid_t pnid, hda_nid_t nid, 3986 const char *name, int dir) 3987 { 3988 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 3989 int type = dir ? HDA_INPUT : HDA_OUTPUT; 3990 struct snd_kcontrol_new knew = 3991 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 3992 3993 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE | 3994 SNDRV_CTL_ELEM_ACCESS_TLV_READ; 3995 knew.tlv.c = 0; 3996 knew.tlv.p = 0; 3997 switch (pnid) { 3998 case VOICE_FOCUS: 3999 knew.info = voice_focus_ctl_info; 4000 knew.get = tuning_ctl_get; 4001 knew.put = voice_focus_ctl_put; 4002 knew.tlv.p = voice_focus_db_scale; 4003 break; 4004 case MIC_SVM: 4005 knew.info = mic_svm_ctl_info; 4006 knew.get = tuning_ctl_get; 4007 knew.put = mic_svm_ctl_put; 4008 break; 4009 case EQUALIZER: 4010 knew.info = equalizer_ctl_info; 4011 knew.get = tuning_ctl_get; 4012 knew.put = equalizer_ctl_put; 4013 knew.tlv.p = eq_db_scale; 4014 break; 4015 default: 4016 return 0; 4017 } 4018 knew.private_value = 4019 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 4020 sprintf(namestr, "%s %s Volume", name, dirstr[dir]); 4021 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 4022 } 4023 4024 static int add_tuning_ctls(struct hda_codec *codec) 4025 { 4026 int i; 4027 int err; 4028 4029 for (i = 0; i < TUNING_CTLS_COUNT; i++) { 4030 err = add_tuning_control(codec, 4031 ca0132_tuning_ctls[i].parent_nid, 4032 ca0132_tuning_ctls[i].nid, 4033 ca0132_tuning_ctls[i].name, 4034 ca0132_tuning_ctls[i].direct); 4035 if (err < 0) 4036 return err; 4037 } 4038 4039 return 0; 4040 } 4041 4042 static void ca0132_init_tuning_defaults(struct hda_codec *codec) 4043 { 4044 struct ca0132_spec *spec = codec->spec; 4045 int i; 4046 4047 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */ 4048 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10; 4049 /* SVM level defaults to 0.74. */ 4050 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74; 4051 4052 /* EQ defaults to 0dB. */ 4053 for (i = 2; i < TUNING_CTLS_COUNT; i++) 4054 spec->cur_ctl_vals[i] = 24; 4055 } 4056 #endif /*ENABLE_TUNING_CONTROLS*/ 4057 4058 /* 4059 * Select the active output. 4060 * If autodetect is enabled, output will be selected based on jack detection. 4061 * If jack inserted, headphone will be selected, else built-in speakers 4062 * If autodetect is disabled, output will be selected based on selection. 4063 */ 4064 static int ca0132_select_out(struct hda_codec *codec) 4065 { 4066 struct ca0132_spec *spec = codec->spec; 4067 unsigned int pin_ctl; 4068 int jack_present; 4069 int auto_jack; 4070 unsigned int tmp; 4071 int err; 4072 4073 codec_dbg(codec, "ca0132_select_out\n"); 4074 4075 snd_hda_power_up_pm(codec); 4076 4077 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4078 4079 if (auto_jack) 4080 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp); 4081 else 4082 jack_present = 4083 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID]; 4084 4085 if (jack_present) 4086 spec->cur_out_type = HEADPHONE_OUT; 4087 else 4088 spec->cur_out_type = SPEAKER_OUT; 4089 4090 if (spec->cur_out_type == SPEAKER_OUT) { 4091 codec_dbg(codec, "ca0132_select_out speaker\n"); 4092 /*speaker out config*/ 4093 tmp = FLOAT_ONE; 4094 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4095 if (err < 0) 4096 goto exit; 4097 /*enable speaker EQ*/ 4098 tmp = FLOAT_ONE; 4099 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4100 if (err < 0) 4101 goto exit; 4102 4103 /* Setup EAPD */ 4104 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4105 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4106 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4107 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4108 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4109 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4110 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4111 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4112 4113 /* disable headphone node */ 4114 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4115 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4116 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4117 pin_ctl & ~PIN_HP); 4118 /* enable speaker node */ 4119 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4120 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4121 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4122 pin_ctl | PIN_OUT); 4123 } else { 4124 codec_dbg(codec, "ca0132_select_out hp\n"); 4125 /*headphone out config*/ 4126 tmp = FLOAT_ZERO; 4127 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp); 4128 if (err < 0) 4129 goto exit; 4130 /*disable speaker EQ*/ 4131 tmp = FLOAT_ZERO; 4132 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp); 4133 if (err < 0) 4134 goto exit; 4135 4136 /* Setup EAPD */ 4137 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4138 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00); 4139 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4140 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4141 snd_hda_codec_write(codec, spec->out_pins[1], 0, 4142 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02); 4143 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4144 AC_VERB_SET_EAPD_BTLENABLE, 0x02); 4145 4146 /* disable speaker*/ 4147 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4148 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4149 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4150 pin_ctl & ~PIN_HP); 4151 /* enable headphone*/ 4152 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4153 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4154 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4155 pin_ctl | PIN_HP); 4156 } 4157 4158 exit: 4159 snd_hda_power_down_pm(codec); 4160 4161 return err < 0 ? err : 0; 4162 } 4163 4164 static int ae5_headphone_gain_set(struct hda_codec *codec, long val); 4165 static int zxr_headphone_gain_set(struct hda_codec *codec, long val); 4166 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val); 4167 4168 static void ae5_mmio_select_out(struct hda_codec *codec) 4169 { 4170 struct ca0132_spec *spec = codec->spec; 4171 unsigned int i; 4172 4173 for (i = 0; i < AE5_CA0113_OUT_SET_COMMANDS; i++) 4174 ca0113_mmio_command_set(codec, 4175 ae5_ca0113_output_presets[spec->cur_out_type].group[i], 4176 ae5_ca0113_output_presets[spec->cur_out_type].target[i], 4177 ae5_ca0113_output_presets[spec->cur_out_type].vals[i]); 4178 } 4179 4180 /* 4181 * These are the commands needed to setup output on each of the different card 4182 * types. 4183 */ 4184 static void ca0132_alt_select_out_quirk_handler(struct hda_codec *codec) 4185 { 4186 struct ca0132_spec *spec = codec->spec; 4187 unsigned int tmp; 4188 4189 switch (spec->cur_out_type) { 4190 case SPEAKER_OUT: 4191 switch (ca0132_quirk(spec)) { 4192 case QUIRK_SBZ: 4193 ca0113_mmio_gpio_set(codec, 7, false); 4194 ca0113_mmio_gpio_set(codec, 4, true); 4195 ca0113_mmio_gpio_set(codec, 1, true); 4196 chipio_set_control_param(codec, 0x0d, 0x18); 4197 break; 4198 case QUIRK_ZXR: 4199 ca0113_mmio_gpio_set(codec, 2, true); 4200 ca0113_mmio_gpio_set(codec, 3, true); 4201 ca0113_mmio_gpio_set(codec, 5, false); 4202 zxr_headphone_gain_set(codec, 0); 4203 chipio_set_control_param(codec, 0x0d, 0x24); 4204 break; 4205 case QUIRK_R3DI: 4206 chipio_set_control_param(codec, 0x0d, 0x24); 4207 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4208 break; 4209 case QUIRK_R3D: 4210 chipio_set_control_param(codec, 0x0d, 0x24); 4211 ca0113_mmio_gpio_set(codec, 1, true); 4212 break; 4213 case QUIRK_AE5: 4214 ae5_mmio_select_out(codec); 4215 ae5_headphone_gain_set(codec, 2); 4216 tmp = FLOAT_ZERO; 4217 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4218 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4219 chipio_set_control_param(codec, 0x0d, 0xa4); 4220 chipio_write(codec, 0x18b03c, 0x00000012); 4221 break; 4222 default: 4223 break; 4224 } 4225 break; 4226 case HEADPHONE_OUT: 4227 switch (ca0132_quirk(spec)) { 4228 case QUIRK_SBZ: 4229 ca0113_mmio_gpio_set(codec, 7, true); 4230 ca0113_mmio_gpio_set(codec, 4, true); 4231 ca0113_mmio_gpio_set(codec, 1, false); 4232 chipio_set_control_param(codec, 0x0d, 0x12); 4233 break; 4234 case QUIRK_ZXR: 4235 ca0113_mmio_gpio_set(codec, 2, false); 4236 ca0113_mmio_gpio_set(codec, 3, false); 4237 ca0113_mmio_gpio_set(codec, 5, true); 4238 zxr_headphone_gain_set(codec, spec->zxr_gain_set); 4239 chipio_set_control_param(codec, 0x0d, 0x21); 4240 break; 4241 case QUIRK_R3DI: 4242 chipio_set_control_param(codec, 0x0d, 0x21); 4243 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT); 4244 break; 4245 case QUIRK_R3D: 4246 chipio_set_control_param(codec, 0x0d, 0x21); 4247 ca0113_mmio_gpio_set(codec, 0x1, false); 4248 break; 4249 case QUIRK_AE5: 4250 ae5_mmio_select_out(codec); 4251 ae5_headphone_gain_set(codec, 4252 spec->ae5_headphone_gain_val); 4253 tmp = FLOAT_ONE; 4254 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4255 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4256 chipio_set_control_param(codec, 0x0d, 0xa1); 4257 chipio_write(codec, 0x18b03c, 0x00000012); 4258 break; 4259 default: 4260 break; 4261 } 4262 break; 4263 case SURROUND_OUT: 4264 switch (ca0132_quirk(spec)) { 4265 case QUIRK_SBZ: 4266 ca0113_mmio_gpio_set(codec, 7, false); 4267 ca0113_mmio_gpio_set(codec, 4, true); 4268 ca0113_mmio_gpio_set(codec, 1, true); 4269 chipio_set_control_param(codec, 0x0d, 0x18); 4270 break; 4271 case QUIRK_ZXR: 4272 ca0113_mmio_gpio_set(codec, 2, true); 4273 ca0113_mmio_gpio_set(codec, 3, true); 4274 ca0113_mmio_gpio_set(codec, 5, false); 4275 zxr_headphone_gain_set(codec, 0); 4276 chipio_set_control_param(codec, 0x0d, 0x24); 4277 break; 4278 case QUIRK_R3DI: 4279 chipio_set_control_param(codec, 0x0d, 0x24); 4280 r3di_gpio_out_set(codec, R3DI_LINE_OUT); 4281 break; 4282 case QUIRK_R3D: 4283 ca0113_mmio_gpio_set(codec, 1, true); 4284 chipio_set_control_param(codec, 0x0d, 0x24); 4285 break; 4286 case QUIRK_AE5: 4287 ae5_mmio_select_out(codec); 4288 ae5_headphone_gain_set(codec, 2); 4289 tmp = FLOAT_ZERO; 4290 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 4291 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 4292 chipio_set_control_param(codec, 0x0d, 0xa4); 4293 chipio_write(codec, 0x18b03c, 0x00000012); 4294 break; 4295 default: 4296 break; 4297 } 4298 break; 4299 } 4300 } 4301 4302 /* 4303 * This function behaves similarly to the ca0132_select_out funciton above, 4304 * except with a few differences. It adds the ability to select the current 4305 * output with an enumerated control "output source" if the auto detect 4306 * mute switch is set to off. If the auto detect mute switch is enabled, it 4307 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection. 4308 * It also adds the ability to auto-detect the front headphone port. The only 4309 * way to select surround is to disable auto detect, and set Surround with the 4310 * enumerated control. 4311 */ 4312 static int ca0132_alt_select_out(struct hda_codec *codec) 4313 { 4314 struct ca0132_spec *spec = codec->spec; 4315 unsigned int pin_ctl; 4316 int jack_present; 4317 int auto_jack; 4318 unsigned int i; 4319 unsigned int tmp; 4320 int err; 4321 /* Default Headphone is rear headphone */ 4322 hda_nid_t headphone_nid = spec->out_pins[1]; 4323 4324 codec_dbg(codec, "%s\n", __func__); 4325 4326 snd_hda_power_up_pm(codec); 4327 4328 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 4329 4330 /* 4331 * If headphone rear or front is plugged in, set to headphone. 4332 * If neither is plugged in, set to rear line out. Only if 4333 * hp/speaker auto detect is enabled. 4334 */ 4335 if (auto_jack) { 4336 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) || 4337 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp); 4338 4339 if (jack_present) 4340 spec->cur_out_type = HEADPHONE_OUT; 4341 else 4342 spec->cur_out_type = SPEAKER_OUT; 4343 } else 4344 spec->cur_out_type = spec->out_enum_val; 4345 4346 /* Begin DSP output switch */ 4347 tmp = FLOAT_ONE; 4348 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp); 4349 if (err < 0) 4350 goto exit; 4351 4352 ca0132_alt_select_out_quirk_handler(codec); 4353 4354 switch (spec->cur_out_type) { 4355 case SPEAKER_OUT: 4356 codec_dbg(codec, "%s speaker\n", __func__); 4357 4358 /* disable headphone node */ 4359 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4360 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4361 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4362 pin_ctl & ~PIN_HP); 4363 /* enable line-out node */ 4364 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4365 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4366 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4367 pin_ctl | PIN_OUT); 4368 /* Enable EAPD */ 4369 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4370 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4371 4372 /* If PlayEnhancement is enabled, set different source */ 4373 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4374 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4375 else 4376 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4377 break; 4378 case HEADPHONE_OUT: 4379 codec_dbg(codec, "%s hp\n", __func__); 4380 4381 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4382 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 4383 4384 /* disable speaker*/ 4385 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4386 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4387 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4388 pin_ctl & ~PIN_HP); 4389 4390 /* enable headphone, either front or rear */ 4391 4392 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp)) 4393 headphone_nid = spec->out_pins[2]; 4394 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp)) 4395 headphone_nid = spec->out_pins[1]; 4396 4397 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0, 4398 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4399 snd_hda_set_pin_ctl(codec, headphone_nid, 4400 pin_ctl | PIN_HP); 4401 4402 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4403 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE); 4404 else 4405 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO); 4406 break; 4407 case SURROUND_OUT: 4408 codec_dbg(codec, "%s surround\n", __func__); 4409 4410 /* enable line out node */ 4411 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0, 4412 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4413 snd_hda_set_pin_ctl(codec, spec->out_pins[0], 4414 pin_ctl | PIN_OUT); 4415 /* Disable headphone out */ 4416 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0, 4417 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4418 snd_hda_set_pin_ctl(codec, spec->out_pins[1], 4419 pin_ctl & ~PIN_HP); 4420 /* Enable EAPD on line out */ 4421 snd_hda_codec_write(codec, spec->out_pins[0], 0, 4422 AC_VERB_SET_EAPD_BTLENABLE, 0x01); 4423 /* enable center/lfe out node */ 4424 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0, 4425 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4426 snd_hda_set_pin_ctl(codec, spec->out_pins[2], 4427 pin_ctl | PIN_OUT); 4428 /* Now set rear surround node as out. */ 4429 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0, 4430 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 4431 snd_hda_set_pin_ctl(codec, spec->out_pins[3], 4432 pin_ctl | PIN_OUT); 4433 4434 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT); 4435 break; 4436 } 4437 /* 4438 * Surround always sets it's scp command to req 0x04 to FLOAT_EIGHT. 4439 * With this set though, X_BASS cannot be enabled. So, if we have OutFX 4440 * enabled, we need to make sure X_BASS is off, otherwise everything 4441 * sounds all muffled. Running ca0132_effects_set with X_BASS as the 4442 * effect should sort this out. 4443 */ 4444 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4445 ca0132_effects_set(codec, X_BASS, 4446 spec->effects_switch[X_BASS - EFFECT_START_NID]); 4447 4448 /* run through the output dsp commands for the selected output. */ 4449 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) { 4450 err = dspio_set_uint_param(codec, 4451 alt_out_presets[spec->cur_out_type].mids[i], 4452 alt_out_presets[spec->cur_out_type].reqs[i], 4453 alt_out_presets[spec->cur_out_type].vals[i]); 4454 4455 if (err < 0) 4456 goto exit; 4457 } 4458 4459 exit: 4460 snd_hda_power_down_pm(codec); 4461 4462 return err < 0 ? err : 0; 4463 } 4464 4465 static void ca0132_unsol_hp_delayed(struct work_struct *work) 4466 { 4467 struct ca0132_spec *spec = container_of( 4468 to_delayed_work(work), struct ca0132_spec, unsol_hp_work); 4469 struct hda_jack_tbl *jack; 4470 4471 if (ca0132_use_alt_functions(spec)) 4472 ca0132_alt_select_out(spec->codec); 4473 else 4474 ca0132_select_out(spec->codec); 4475 4476 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp); 4477 if (jack) { 4478 jack->block_report = 0; 4479 snd_hda_jack_report_sync(spec->codec); 4480 } 4481 } 4482 4483 static void ca0132_set_dmic(struct hda_codec *codec, int enable); 4484 static int ca0132_mic_boost_set(struct hda_codec *codec, long val); 4485 static void resume_mic1(struct hda_codec *codec, unsigned int oldval); 4486 static int stop_mic1(struct hda_codec *codec); 4487 static int ca0132_cvoice_switch_set(struct hda_codec *codec); 4488 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val); 4489 4490 /* 4491 * Select the active VIP source 4492 */ 4493 static int ca0132_set_vipsource(struct hda_codec *codec, int val) 4494 { 4495 struct ca0132_spec *spec = codec->spec; 4496 unsigned int tmp; 4497 4498 if (spec->dsp_state != DSP_DOWNLOADED) 4499 return 0; 4500 4501 /* if CrystalVoice if off, vipsource should be 0 */ 4502 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4503 (val == 0)) { 4504 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4505 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4506 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4507 if (spec->cur_mic_type == DIGITAL_MIC) 4508 tmp = FLOAT_TWO; 4509 else 4510 tmp = FLOAT_ONE; 4511 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4512 tmp = FLOAT_ZERO; 4513 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4514 } else { 4515 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4516 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4517 if (spec->cur_mic_type == DIGITAL_MIC) 4518 tmp = FLOAT_TWO; 4519 else 4520 tmp = FLOAT_ONE; 4521 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4522 tmp = FLOAT_ONE; 4523 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4524 msleep(20); 4525 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4526 } 4527 4528 return 1; 4529 } 4530 4531 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val) 4532 { 4533 struct ca0132_spec *spec = codec->spec; 4534 unsigned int tmp; 4535 4536 if (spec->dsp_state != DSP_DOWNLOADED) 4537 return 0; 4538 4539 codec_dbg(codec, "%s\n", __func__); 4540 4541 chipio_set_stream_control(codec, 0x03, 0); 4542 chipio_set_stream_control(codec, 0x04, 0); 4543 4544 /* if CrystalVoice is off, vipsource should be 0 */ 4545 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] || 4546 (val == 0) || spec->in_enum_val == REAR_LINE_IN) { 4547 codec_dbg(codec, "%s: off.", __func__); 4548 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 4549 4550 tmp = FLOAT_ZERO; 4551 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4552 4553 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4554 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4555 if (ca0132_quirk(spec) == QUIRK_R3DI) 4556 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4557 4558 4559 if (spec->in_enum_val == REAR_LINE_IN) 4560 tmp = FLOAT_ZERO; 4561 else { 4562 if (ca0132_quirk(spec) == QUIRK_SBZ) 4563 tmp = FLOAT_THREE; 4564 else 4565 tmp = FLOAT_ONE; 4566 } 4567 4568 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4569 4570 } else { 4571 codec_dbg(codec, "%s: on.", __func__); 4572 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000); 4573 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000); 4574 if (ca0132_quirk(spec) == QUIRK_R3DI) 4575 chipio_set_conn_rate(codec, 0x0F, SR_16_000); 4576 4577 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID]) 4578 tmp = FLOAT_TWO; 4579 else 4580 tmp = FLOAT_ONE; 4581 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4582 4583 tmp = FLOAT_ONE; 4584 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 4585 4586 msleep(20); 4587 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val); 4588 } 4589 4590 chipio_set_stream_control(codec, 0x03, 1); 4591 chipio_set_stream_control(codec, 0x04, 1); 4592 4593 return 1; 4594 } 4595 4596 /* 4597 * Select the active microphone. 4598 * If autodetect is enabled, mic will be selected based on jack detection. 4599 * If jack inserted, ext.mic will be selected, else built-in mic 4600 * If autodetect is disabled, mic will be selected based on selection. 4601 */ 4602 static int ca0132_select_mic(struct hda_codec *codec) 4603 { 4604 struct ca0132_spec *spec = codec->spec; 4605 int jack_present; 4606 int auto_jack; 4607 4608 codec_dbg(codec, "ca0132_select_mic\n"); 4609 4610 snd_hda_power_up_pm(codec); 4611 4612 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 4613 4614 if (auto_jack) 4615 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1); 4616 else 4617 jack_present = 4618 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID]; 4619 4620 if (jack_present) 4621 spec->cur_mic_type = LINE_MIC_IN; 4622 else 4623 spec->cur_mic_type = DIGITAL_MIC; 4624 4625 if (spec->cur_mic_type == DIGITAL_MIC) { 4626 /* enable digital Mic */ 4627 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000); 4628 ca0132_set_dmic(codec, 1); 4629 ca0132_mic_boost_set(codec, 0); 4630 /* set voice focus */ 4631 ca0132_effects_set(codec, VOICE_FOCUS, 4632 spec->effects_switch 4633 [VOICE_FOCUS - EFFECT_START_NID]); 4634 } else { 4635 /* disable digital Mic */ 4636 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000); 4637 ca0132_set_dmic(codec, 0); 4638 ca0132_mic_boost_set(codec, spec->cur_mic_boost); 4639 /* disable voice focus */ 4640 ca0132_effects_set(codec, VOICE_FOCUS, 0); 4641 } 4642 4643 snd_hda_power_down_pm(codec); 4644 4645 return 0; 4646 } 4647 4648 /* 4649 * Select the active input. 4650 * Mic detection isn't used, because it's kind of pointless on the SBZ. 4651 * The front mic has no jack-detection, so the only way to switch to it 4652 * is to do it manually in alsamixer. 4653 */ 4654 static int ca0132_alt_select_in(struct hda_codec *codec) 4655 { 4656 struct ca0132_spec *spec = codec->spec; 4657 unsigned int tmp; 4658 4659 codec_dbg(codec, "%s\n", __func__); 4660 4661 snd_hda_power_up_pm(codec); 4662 4663 chipio_set_stream_control(codec, 0x03, 0); 4664 chipio_set_stream_control(codec, 0x04, 0); 4665 4666 spec->cur_mic_type = spec->in_enum_val; 4667 4668 switch (spec->cur_mic_type) { 4669 case REAR_MIC: 4670 switch (ca0132_quirk(spec)) { 4671 case QUIRK_SBZ: 4672 case QUIRK_R3D: 4673 ca0113_mmio_gpio_set(codec, 0, false); 4674 tmp = FLOAT_THREE; 4675 break; 4676 case QUIRK_ZXR: 4677 tmp = FLOAT_THREE; 4678 break; 4679 case QUIRK_R3DI: 4680 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4681 tmp = FLOAT_ONE; 4682 break; 4683 case QUIRK_AE5: 4684 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4685 tmp = FLOAT_THREE; 4686 break; 4687 default: 4688 tmp = FLOAT_ONE; 4689 break; 4690 } 4691 4692 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4693 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4694 if (ca0132_quirk(spec) == QUIRK_R3DI) 4695 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4696 4697 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4698 4699 chipio_set_stream_control(codec, 0x03, 1); 4700 chipio_set_stream_control(codec, 0x04, 1); 4701 switch (ca0132_quirk(spec)) { 4702 case QUIRK_SBZ: 4703 chipio_write(codec, 0x18B098, 0x0000000C); 4704 chipio_write(codec, 0x18B09C, 0x0000000C); 4705 break; 4706 case QUIRK_ZXR: 4707 chipio_write(codec, 0x18B098, 0x0000000C); 4708 chipio_write(codec, 0x18B09C, 0x000000CC); 4709 break; 4710 case QUIRK_AE5: 4711 chipio_write(codec, 0x18B098, 0x0000000C); 4712 chipio_write(codec, 0x18B09C, 0x0000004C); 4713 break; 4714 default: 4715 break; 4716 } 4717 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4718 break; 4719 case REAR_LINE_IN: 4720 ca0132_mic_boost_set(codec, 0); 4721 switch (ca0132_quirk(spec)) { 4722 case QUIRK_SBZ: 4723 case QUIRK_R3D: 4724 ca0113_mmio_gpio_set(codec, 0, false); 4725 break; 4726 case QUIRK_R3DI: 4727 r3di_gpio_mic_set(codec, R3DI_REAR_MIC); 4728 break; 4729 case QUIRK_AE5: 4730 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x00); 4731 break; 4732 default: 4733 break; 4734 } 4735 4736 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4737 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4738 if (ca0132_quirk(spec) == QUIRK_R3DI) 4739 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4740 4741 tmp = FLOAT_ZERO; 4742 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4743 4744 switch (ca0132_quirk(spec)) { 4745 case QUIRK_SBZ: 4746 case QUIRK_AE5: 4747 chipio_write(codec, 0x18B098, 0x00000000); 4748 chipio_write(codec, 0x18B09C, 0x00000000); 4749 break; 4750 default: 4751 break; 4752 } 4753 chipio_set_stream_control(codec, 0x03, 1); 4754 chipio_set_stream_control(codec, 0x04, 1); 4755 break; 4756 case FRONT_MIC: 4757 switch (ca0132_quirk(spec)) { 4758 case QUIRK_SBZ: 4759 case QUIRK_R3D: 4760 ca0113_mmio_gpio_set(codec, 0, true); 4761 ca0113_mmio_gpio_set(codec, 5, false); 4762 tmp = FLOAT_THREE; 4763 break; 4764 case QUIRK_R3DI: 4765 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC); 4766 tmp = FLOAT_ONE; 4767 break; 4768 case QUIRK_AE5: 4769 ca0113_mmio_command_set(codec, 0x48, 0x28, 0x3f); 4770 tmp = FLOAT_THREE; 4771 break; 4772 default: 4773 tmp = FLOAT_ONE; 4774 break; 4775 } 4776 4777 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 4778 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 4779 if (ca0132_quirk(spec) == QUIRK_R3DI) 4780 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 4781 4782 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4783 4784 chipio_set_stream_control(codec, 0x03, 1); 4785 chipio_set_stream_control(codec, 0x04, 1); 4786 4787 switch (ca0132_quirk(spec)) { 4788 case QUIRK_SBZ: 4789 chipio_write(codec, 0x18B098, 0x0000000C); 4790 chipio_write(codec, 0x18B09C, 0x000000CC); 4791 break; 4792 case QUIRK_AE5: 4793 chipio_write(codec, 0x18B098, 0x0000000C); 4794 chipio_write(codec, 0x18B09C, 0x0000004C); 4795 break; 4796 default: 4797 break; 4798 } 4799 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 4800 break; 4801 } 4802 ca0132_cvoice_switch_set(codec); 4803 4804 snd_hda_power_down_pm(codec); 4805 return 0; 4806 } 4807 4808 /* 4809 * Check if VNODE settings take effect immediately. 4810 */ 4811 static bool ca0132_is_vnode_effective(struct hda_codec *codec, 4812 hda_nid_t vnid, 4813 hda_nid_t *shared_nid) 4814 { 4815 struct ca0132_spec *spec = codec->spec; 4816 hda_nid_t nid; 4817 4818 switch (vnid) { 4819 case VNID_SPK: 4820 nid = spec->shared_out_nid; 4821 break; 4822 case VNID_MIC: 4823 nid = spec->shared_mic_nid; 4824 break; 4825 default: 4826 return false; 4827 } 4828 4829 if (shared_nid) 4830 *shared_nid = nid; 4831 4832 return true; 4833 } 4834 4835 /* 4836 * The following functions are control change helpers. 4837 * They return 0 if no changed. Return 1 if changed. 4838 */ 4839 static int ca0132_voicefx_set(struct hda_codec *codec, int enable) 4840 { 4841 struct ca0132_spec *spec = codec->spec; 4842 unsigned int tmp; 4843 4844 /* based on CrystalVoice state to enable VoiceFX. */ 4845 if (enable) { 4846 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ? 4847 FLOAT_ONE : FLOAT_ZERO; 4848 } else { 4849 tmp = FLOAT_ZERO; 4850 } 4851 4852 dspio_set_uint_param(codec, ca0132_voicefx.mid, 4853 ca0132_voicefx.reqs[0], tmp); 4854 4855 return 1; 4856 } 4857 4858 /* 4859 * Set the effects parameters 4860 */ 4861 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val) 4862 { 4863 struct ca0132_spec *spec = codec->spec; 4864 unsigned int on, tmp; 4865 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 4866 int err = 0; 4867 int idx = nid - EFFECT_START_NID; 4868 4869 if ((idx < 0) || (idx >= num_fx)) 4870 return 0; /* no changed */ 4871 4872 /* for out effect, qualify with PE */ 4873 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) { 4874 /* if PE if off, turn off out effects. */ 4875 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) 4876 val = 0; 4877 if (spec->cur_out_type == SURROUND_OUT && nid == X_BASS) 4878 val = 0; 4879 } 4880 4881 /* for in effect, qualify with CrystalVoice */ 4882 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) { 4883 /* if CrystalVoice if off, turn off in effects. */ 4884 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]) 4885 val = 0; 4886 4887 /* Voice Focus applies to 2-ch Mic, Digital Mic */ 4888 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC)) 4889 val = 0; 4890 4891 /* If Voice Focus on SBZ, set to two channel. */ 4892 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec) 4893 && (spec->cur_mic_type != REAR_LINE_IN)) { 4894 if (spec->effects_switch[CRYSTAL_VOICE - 4895 EFFECT_START_NID]) { 4896 4897 if (spec->effects_switch[VOICE_FOCUS - 4898 EFFECT_START_NID]) { 4899 tmp = FLOAT_TWO; 4900 val = 1; 4901 } else 4902 tmp = FLOAT_ONE; 4903 4904 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 4905 } 4906 } 4907 /* 4908 * For SBZ noise reduction, there's an extra command 4909 * to module ID 0x47. No clue why. 4910 */ 4911 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec) 4912 && (spec->cur_mic_type != REAR_LINE_IN)) { 4913 if (spec->effects_switch[CRYSTAL_VOICE - 4914 EFFECT_START_NID]) { 4915 if (spec->effects_switch[NOISE_REDUCTION - 4916 EFFECT_START_NID]) 4917 tmp = FLOAT_ONE; 4918 else 4919 tmp = FLOAT_ZERO; 4920 } else 4921 tmp = FLOAT_ZERO; 4922 4923 dspio_set_uint_param(codec, 0x47, 0x00, tmp); 4924 } 4925 4926 /* If rear line in disable effects. */ 4927 if (ca0132_use_alt_functions(spec) && 4928 spec->in_enum_val == REAR_LINE_IN) 4929 val = 0; 4930 } 4931 4932 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n", 4933 nid, val); 4934 4935 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE; 4936 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid, 4937 ca0132_effects[idx].reqs[0], on); 4938 4939 if (err < 0) 4940 return 0; /* no changed */ 4941 4942 return 1; 4943 } 4944 4945 /* 4946 * Turn on/off Playback Enhancements 4947 */ 4948 static int ca0132_pe_switch_set(struct hda_codec *codec) 4949 { 4950 struct ca0132_spec *spec = codec->spec; 4951 hda_nid_t nid; 4952 int i, ret = 0; 4953 4954 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n", 4955 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]); 4956 4957 if (ca0132_use_alt_functions(spec)) 4958 ca0132_alt_select_out(codec); 4959 4960 i = OUT_EFFECT_START_NID - EFFECT_START_NID; 4961 nid = OUT_EFFECT_START_NID; 4962 /* PE affects all out effects */ 4963 for (; nid < OUT_EFFECT_END_NID; nid++, i++) 4964 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 4965 4966 return ret; 4967 } 4968 4969 /* Check if Mic1 is streaming, if so, stop streaming */ 4970 static int stop_mic1(struct hda_codec *codec) 4971 { 4972 struct ca0132_spec *spec = codec->spec; 4973 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0, 4974 AC_VERB_GET_CONV, 0); 4975 if (oldval != 0) 4976 snd_hda_codec_write(codec, spec->adcs[0], 0, 4977 AC_VERB_SET_CHANNEL_STREAMID, 4978 0); 4979 return oldval; 4980 } 4981 4982 /* Resume Mic1 streaming if it was stopped. */ 4983 static void resume_mic1(struct hda_codec *codec, unsigned int oldval) 4984 { 4985 struct ca0132_spec *spec = codec->spec; 4986 /* Restore the previous stream and channel */ 4987 if (oldval != 0) 4988 snd_hda_codec_write(codec, spec->adcs[0], 0, 4989 AC_VERB_SET_CHANNEL_STREAMID, 4990 oldval); 4991 } 4992 4993 /* 4994 * Turn on/off CrystalVoice 4995 */ 4996 static int ca0132_cvoice_switch_set(struct hda_codec *codec) 4997 { 4998 struct ca0132_spec *spec = codec->spec; 4999 hda_nid_t nid; 5000 int i, ret = 0; 5001 unsigned int oldval; 5002 5003 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n", 5004 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]); 5005 5006 i = IN_EFFECT_START_NID - EFFECT_START_NID; 5007 nid = IN_EFFECT_START_NID; 5008 /* CrystalVoice affects all in effects */ 5009 for (; nid < IN_EFFECT_END_NID; nid++, i++) 5010 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]); 5011 5012 /* including VoiceFX */ 5013 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0)); 5014 5015 /* set correct vipsource */ 5016 oldval = stop_mic1(codec); 5017 if (ca0132_use_alt_functions(spec)) 5018 ret |= ca0132_alt_set_vipsource(codec, 1); 5019 else 5020 ret |= ca0132_set_vipsource(codec, 1); 5021 resume_mic1(codec, oldval); 5022 return ret; 5023 } 5024 5025 static int ca0132_mic_boost_set(struct hda_codec *codec, long val) 5026 { 5027 struct ca0132_spec *spec = codec->spec; 5028 int ret = 0; 5029 5030 if (val) /* on */ 5031 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5032 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3); 5033 else /* off */ 5034 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5035 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0); 5036 5037 return ret; 5038 } 5039 5040 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val) 5041 { 5042 struct ca0132_spec *spec = codec->spec; 5043 int ret = 0; 5044 5045 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0, 5046 HDA_INPUT, 0, HDA_AMP_VOLMASK, val); 5047 return ret; 5048 } 5049 5050 static int ae5_headphone_gain_set(struct hda_codec *codec, long val) 5051 { 5052 unsigned int i; 5053 5054 for (i = 0; i < 4; i++) 5055 ca0113_mmio_command_set(codec, 0x48, 0x11 + i, 5056 ae5_headphone_gain_presets[val].vals[i]); 5057 return 0; 5058 } 5059 5060 /* 5061 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone 5062 * amplifier to handle a 600 ohm load. 5063 */ 5064 static int zxr_headphone_gain_set(struct hda_codec *codec, long val) 5065 { 5066 ca0113_mmio_gpio_set(codec, 1, val); 5067 5068 return 0; 5069 } 5070 5071 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol, 5072 struct snd_ctl_elem_value *ucontrol) 5073 { 5074 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5075 hda_nid_t nid = get_amp_nid(kcontrol); 5076 hda_nid_t shared_nid = 0; 5077 bool effective; 5078 int ret = 0; 5079 struct ca0132_spec *spec = codec->spec; 5080 int auto_jack; 5081 5082 if (nid == VNID_HP_SEL) { 5083 auto_jack = 5084 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5085 if (!auto_jack) { 5086 if (ca0132_use_alt_functions(spec)) 5087 ca0132_alt_select_out(codec); 5088 else 5089 ca0132_select_out(codec); 5090 } 5091 return 1; 5092 } 5093 5094 if (nid == VNID_AMIC1_SEL) { 5095 auto_jack = 5096 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID]; 5097 if (!auto_jack) 5098 ca0132_select_mic(codec); 5099 return 1; 5100 } 5101 5102 if (nid == VNID_HP_ASEL) { 5103 if (ca0132_use_alt_functions(spec)) 5104 ca0132_alt_select_out(codec); 5105 else 5106 ca0132_select_out(codec); 5107 return 1; 5108 } 5109 5110 if (nid == VNID_AMIC1_ASEL) { 5111 ca0132_select_mic(codec); 5112 return 1; 5113 } 5114 5115 /* if effective conditions, then update hw immediately. */ 5116 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5117 if (effective) { 5118 int dir = get_amp_direction(kcontrol); 5119 int ch = get_amp_channels(kcontrol); 5120 unsigned long pval; 5121 5122 mutex_lock(&codec->control_mutex); 5123 pval = kcontrol->private_value; 5124 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5125 0, dir); 5126 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol); 5127 kcontrol->private_value = pval; 5128 mutex_unlock(&codec->control_mutex); 5129 } 5130 5131 return ret; 5132 } 5133 /* End of control change helpers. */ 5134 /* 5135 * Below I've added controls to mess with the effect levels, I've only enabled 5136 * them on the Sound Blaster Z, but they would probably also work on the 5137 * Chromebook. I figured they were probably tuned specifically for it, and left 5138 * out for a reason. 5139 */ 5140 5141 /* Sets DSP effect level from the sliders above the controls */ 5142 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid, 5143 const unsigned int *lookup, int idx) 5144 { 5145 int i = 0; 5146 unsigned int y; 5147 /* 5148 * For X_BASS, req 2 is actually crossover freq instead of 5149 * effect level 5150 */ 5151 if (nid == X_BASS) 5152 y = 2; 5153 else 5154 y = 1; 5155 5156 snd_hda_power_up(codec); 5157 if (nid == XBASS_XOVER) { 5158 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5159 if (ca0132_effects[i].nid == X_BASS) 5160 break; 5161 5162 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5163 ca0132_effects[i].reqs[1], 5164 &(lookup[idx - 1]), sizeof(unsigned int)); 5165 } else { 5166 /* Find the actual effect structure */ 5167 for (i = 0; i < OUT_EFFECTS_COUNT; i++) 5168 if (nid == ca0132_effects[i].nid) 5169 break; 5170 5171 dspio_set_param(codec, ca0132_effects[i].mid, 0x20, 5172 ca0132_effects[i].reqs[y], 5173 &(lookup[idx]), sizeof(unsigned int)); 5174 } 5175 5176 snd_hda_power_down(codec); 5177 5178 return 0; 5179 } 5180 5181 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol, 5182 struct snd_ctl_elem_value *ucontrol) 5183 { 5184 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5185 struct ca0132_spec *spec = codec->spec; 5186 long *valp = ucontrol->value.integer.value; 5187 5188 *valp = spec->xbass_xover_freq; 5189 return 0; 5190 } 5191 5192 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol, 5193 struct snd_ctl_elem_value *ucontrol) 5194 { 5195 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5196 struct ca0132_spec *spec = codec->spec; 5197 hda_nid_t nid = get_amp_nid(kcontrol); 5198 long *valp = ucontrol->value.integer.value; 5199 int idx = nid - OUT_EFFECT_START_NID; 5200 5201 *valp = spec->fx_ctl_val[idx]; 5202 return 0; 5203 } 5204 5205 /* 5206 * The X-bass crossover starts at 10hz, so the min is 1. The 5207 * frequency is set in multiples of 10. 5208 */ 5209 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol, 5210 struct snd_ctl_elem_info *uinfo) 5211 { 5212 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5213 uinfo->count = 1; 5214 uinfo->value.integer.min = 1; 5215 uinfo->value.integer.max = 100; 5216 uinfo->value.integer.step = 1; 5217 5218 return 0; 5219 } 5220 5221 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol, 5222 struct snd_ctl_elem_info *uinfo) 5223 { 5224 int chs = get_amp_channels(kcontrol); 5225 5226 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 5227 uinfo->count = chs == 3 ? 2 : 1; 5228 uinfo->value.integer.min = 0; 5229 uinfo->value.integer.max = 100; 5230 uinfo->value.integer.step = 1; 5231 5232 return 0; 5233 } 5234 5235 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol, 5236 struct snd_ctl_elem_value *ucontrol) 5237 { 5238 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5239 struct ca0132_spec *spec = codec->spec; 5240 hda_nid_t nid = get_amp_nid(kcontrol); 5241 long *valp = ucontrol->value.integer.value; 5242 int idx; 5243 5244 /* any change? */ 5245 if (spec->xbass_xover_freq == *valp) 5246 return 0; 5247 5248 spec->xbass_xover_freq = *valp; 5249 5250 idx = *valp; 5251 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx); 5252 5253 return 0; 5254 } 5255 5256 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol, 5257 struct snd_ctl_elem_value *ucontrol) 5258 { 5259 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5260 struct ca0132_spec *spec = codec->spec; 5261 hda_nid_t nid = get_amp_nid(kcontrol); 5262 long *valp = ucontrol->value.integer.value; 5263 int idx; 5264 5265 idx = nid - EFFECT_START_NID; 5266 /* any change? */ 5267 if (spec->fx_ctl_val[idx] == *valp) 5268 return 0; 5269 5270 spec->fx_ctl_val[idx] = *valp; 5271 5272 idx = *valp; 5273 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx); 5274 5275 return 0; 5276 } 5277 5278 5279 /* 5280 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original 5281 * only has off or full 30 dB, and didn't like making a volume slider that has 5282 * traditional 0-100 in alsamixer that goes in big steps. I like enum better. 5283 */ 5284 #define MIC_BOOST_NUM_OF_STEPS 4 5285 #define MIC_BOOST_ENUM_MAX_STRLEN 10 5286 5287 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol, 5288 struct snd_ctl_elem_info *uinfo) 5289 { 5290 char *sfx = "dB"; 5291 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5292 5293 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5294 uinfo->count = 1; 5295 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS; 5296 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS) 5297 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1; 5298 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx); 5299 strcpy(uinfo->value.enumerated.name, namestr); 5300 return 0; 5301 } 5302 5303 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol, 5304 struct snd_ctl_elem_value *ucontrol) 5305 { 5306 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5307 struct ca0132_spec *spec = codec->spec; 5308 5309 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val; 5310 return 0; 5311 } 5312 5313 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol, 5314 struct snd_ctl_elem_value *ucontrol) 5315 { 5316 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5317 struct ca0132_spec *spec = codec->spec; 5318 int sel = ucontrol->value.enumerated.item[0]; 5319 unsigned int items = MIC_BOOST_NUM_OF_STEPS; 5320 5321 if (sel >= items) 5322 return 0; 5323 5324 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n", 5325 sel); 5326 5327 spec->mic_boost_enum_val = sel; 5328 5329 if (spec->in_enum_val != REAR_LINE_IN) 5330 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val); 5331 5332 return 1; 5333 } 5334 5335 /* 5336 * Sound BlasterX AE-5 Headphone Gain Controls. 5337 */ 5338 #define AE5_HEADPHONE_GAIN_MAX 3 5339 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol, 5340 struct snd_ctl_elem_info *uinfo) 5341 { 5342 char *sfx = " Ohms)"; 5343 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5344 5345 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5346 uinfo->count = 1; 5347 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX; 5348 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX) 5349 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1; 5350 sprintf(namestr, "%s %s", 5351 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name, 5352 sfx); 5353 strcpy(uinfo->value.enumerated.name, namestr); 5354 return 0; 5355 } 5356 5357 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol, 5358 struct snd_ctl_elem_value *ucontrol) 5359 { 5360 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5361 struct ca0132_spec *spec = codec->spec; 5362 5363 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val; 5364 return 0; 5365 } 5366 5367 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol, 5368 struct snd_ctl_elem_value *ucontrol) 5369 { 5370 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5371 struct ca0132_spec *spec = codec->spec; 5372 int sel = ucontrol->value.enumerated.item[0]; 5373 unsigned int items = AE5_HEADPHONE_GAIN_MAX; 5374 5375 if (sel >= items) 5376 return 0; 5377 5378 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n", 5379 sel); 5380 5381 spec->ae5_headphone_gain_val = sel; 5382 5383 if (spec->out_enum_val == HEADPHONE_OUT) 5384 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val); 5385 5386 return 1; 5387 } 5388 5389 /* 5390 * Sound BlasterX AE-5 sound filter enumerated control. 5391 */ 5392 #define AE5_SOUND_FILTER_MAX 3 5393 5394 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol, 5395 struct snd_ctl_elem_info *uinfo) 5396 { 5397 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 5398 5399 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5400 uinfo->count = 1; 5401 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX; 5402 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX) 5403 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1; 5404 sprintf(namestr, "%s", 5405 ae5_filter_presets[uinfo->value.enumerated.item].name); 5406 strcpy(uinfo->value.enumerated.name, namestr); 5407 return 0; 5408 } 5409 5410 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol, 5411 struct snd_ctl_elem_value *ucontrol) 5412 { 5413 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5414 struct ca0132_spec *spec = codec->spec; 5415 5416 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val; 5417 return 0; 5418 } 5419 5420 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol, 5421 struct snd_ctl_elem_value *ucontrol) 5422 { 5423 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5424 struct ca0132_spec *spec = codec->spec; 5425 int sel = ucontrol->value.enumerated.item[0]; 5426 unsigned int items = AE5_SOUND_FILTER_MAX; 5427 5428 if (sel >= items) 5429 return 0; 5430 5431 codec_dbg(codec, "ae5_sound_filter: %s\n", 5432 ae5_filter_presets[sel].name); 5433 5434 spec->ae5_filter_val = sel; 5435 5436 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 5437 ae5_filter_presets[sel].val); 5438 5439 return 1; 5440 } 5441 5442 /* 5443 * Input Select Control for alternative ca0132 codecs. This exists because 5444 * front microphone has no auto-detect, and we need a way to set the rear 5445 * as line-in 5446 */ 5447 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol, 5448 struct snd_ctl_elem_info *uinfo) 5449 { 5450 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5451 uinfo->count = 1; 5452 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS; 5453 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS) 5454 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1; 5455 strcpy(uinfo->value.enumerated.name, 5456 in_src_str[uinfo->value.enumerated.item]); 5457 return 0; 5458 } 5459 5460 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol, 5461 struct snd_ctl_elem_value *ucontrol) 5462 { 5463 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5464 struct ca0132_spec *spec = codec->spec; 5465 5466 ucontrol->value.enumerated.item[0] = spec->in_enum_val; 5467 return 0; 5468 } 5469 5470 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol, 5471 struct snd_ctl_elem_value *ucontrol) 5472 { 5473 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5474 struct ca0132_spec *spec = codec->spec; 5475 int sel = ucontrol->value.enumerated.item[0]; 5476 unsigned int items = IN_SRC_NUM_OF_INPUTS; 5477 5478 if (sel >= items) 5479 return 0; 5480 5481 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n", 5482 sel, in_src_str[sel]); 5483 5484 spec->in_enum_val = sel; 5485 5486 ca0132_alt_select_in(codec); 5487 5488 return 1; 5489 } 5490 5491 /* Sound Blaster Z Output Select Control */ 5492 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol, 5493 struct snd_ctl_elem_info *uinfo) 5494 { 5495 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5496 uinfo->count = 1; 5497 uinfo->value.enumerated.items = NUM_OF_OUTPUTS; 5498 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS) 5499 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1; 5500 strcpy(uinfo->value.enumerated.name, 5501 alt_out_presets[uinfo->value.enumerated.item].name); 5502 return 0; 5503 } 5504 5505 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol, 5506 struct snd_ctl_elem_value *ucontrol) 5507 { 5508 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5509 struct ca0132_spec *spec = codec->spec; 5510 5511 ucontrol->value.enumerated.item[0] = spec->out_enum_val; 5512 return 0; 5513 } 5514 5515 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol, 5516 struct snd_ctl_elem_value *ucontrol) 5517 { 5518 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5519 struct ca0132_spec *spec = codec->spec; 5520 int sel = ucontrol->value.enumerated.item[0]; 5521 unsigned int items = NUM_OF_OUTPUTS; 5522 unsigned int auto_jack; 5523 5524 if (sel >= items) 5525 return 0; 5526 5527 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n", 5528 sel, alt_out_presets[sel].name); 5529 5530 spec->out_enum_val = sel; 5531 5532 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID]; 5533 5534 if (!auto_jack) 5535 ca0132_alt_select_out(codec); 5536 5537 return 1; 5538 } 5539 5540 /* 5541 * Smart Volume output setting control. Three different settings, Normal, 5542 * which takes the value from the smart volume slider. The two others, loud 5543 * and night, disregard the slider value and have uneditable values. 5544 */ 5545 #define NUM_OF_SVM_SETTINGS 3 5546 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" }; 5547 5548 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol, 5549 struct snd_ctl_elem_info *uinfo) 5550 { 5551 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5552 uinfo->count = 1; 5553 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS; 5554 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS) 5555 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1; 5556 strcpy(uinfo->value.enumerated.name, 5557 out_svm_set_enum_str[uinfo->value.enumerated.item]); 5558 return 0; 5559 } 5560 5561 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol, 5562 struct snd_ctl_elem_value *ucontrol) 5563 { 5564 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5565 struct ca0132_spec *spec = codec->spec; 5566 5567 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting; 5568 return 0; 5569 } 5570 5571 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol, 5572 struct snd_ctl_elem_value *ucontrol) 5573 { 5574 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5575 struct ca0132_spec *spec = codec->spec; 5576 int sel = ucontrol->value.enumerated.item[0]; 5577 unsigned int items = NUM_OF_SVM_SETTINGS; 5578 unsigned int idx = SMART_VOLUME - EFFECT_START_NID; 5579 unsigned int tmp; 5580 5581 if (sel >= items) 5582 return 0; 5583 5584 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n", 5585 sel, out_svm_set_enum_str[sel]); 5586 5587 spec->smart_volume_setting = sel; 5588 5589 switch (sel) { 5590 case 0: 5591 tmp = FLOAT_ZERO; 5592 break; 5593 case 1: 5594 tmp = FLOAT_ONE; 5595 break; 5596 case 2: 5597 tmp = FLOAT_TWO; 5598 break; 5599 default: 5600 tmp = FLOAT_ZERO; 5601 break; 5602 } 5603 /* Req 2 is the Smart Volume Setting req. */ 5604 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 5605 ca0132_effects[idx].reqs[2], tmp); 5606 return 1; 5607 } 5608 5609 /* Sound Blaster Z EQ preset controls */ 5610 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol, 5611 struct snd_ctl_elem_info *uinfo) 5612 { 5613 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5614 5615 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5616 uinfo->count = 1; 5617 uinfo->value.enumerated.items = items; 5618 if (uinfo->value.enumerated.item >= items) 5619 uinfo->value.enumerated.item = items - 1; 5620 strcpy(uinfo->value.enumerated.name, 5621 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name); 5622 return 0; 5623 } 5624 5625 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol, 5626 struct snd_ctl_elem_value *ucontrol) 5627 { 5628 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5629 struct ca0132_spec *spec = codec->spec; 5630 5631 ucontrol->value.enumerated.item[0] = spec->eq_preset_val; 5632 return 0; 5633 } 5634 5635 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol, 5636 struct snd_ctl_elem_value *ucontrol) 5637 { 5638 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5639 struct ca0132_spec *spec = codec->spec; 5640 int i, err = 0; 5641 int sel = ucontrol->value.enumerated.item[0]; 5642 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets); 5643 5644 if (sel >= items) 5645 return 0; 5646 5647 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel, 5648 ca0132_alt_eq_presets[sel].name); 5649 /* 5650 * Idx 0 is default. 5651 * Default needs to qualify with CrystalVoice state. 5652 */ 5653 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) { 5654 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid, 5655 ca0132_alt_eq_enum.reqs[i], 5656 ca0132_alt_eq_presets[sel].vals[i]); 5657 if (err < 0) 5658 break; 5659 } 5660 5661 if (err >= 0) 5662 spec->eq_preset_val = sel; 5663 5664 return 1; 5665 } 5666 5667 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol, 5668 struct snd_ctl_elem_info *uinfo) 5669 { 5670 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets); 5671 5672 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 5673 uinfo->count = 1; 5674 uinfo->value.enumerated.items = items; 5675 if (uinfo->value.enumerated.item >= items) 5676 uinfo->value.enumerated.item = items - 1; 5677 strcpy(uinfo->value.enumerated.name, 5678 ca0132_voicefx_presets[uinfo->value.enumerated.item].name); 5679 return 0; 5680 } 5681 5682 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol, 5683 struct snd_ctl_elem_value *ucontrol) 5684 { 5685 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5686 struct ca0132_spec *spec = codec->spec; 5687 5688 ucontrol->value.enumerated.item[0] = spec->voicefx_val; 5689 return 0; 5690 } 5691 5692 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol, 5693 struct snd_ctl_elem_value *ucontrol) 5694 { 5695 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5696 struct ca0132_spec *spec = codec->spec; 5697 int i, err = 0; 5698 int sel = ucontrol->value.enumerated.item[0]; 5699 5700 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets)) 5701 return 0; 5702 5703 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n", 5704 sel, ca0132_voicefx_presets[sel].name); 5705 5706 /* 5707 * Idx 0 is default. 5708 * Default needs to qualify with CrystalVoice state. 5709 */ 5710 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) { 5711 err = dspio_set_uint_param(codec, ca0132_voicefx.mid, 5712 ca0132_voicefx.reqs[i], 5713 ca0132_voicefx_presets[sel].vals[i]); 5714 if (err < 0) 5715 break; 5716 } 5717 5718 if (err >= 0) { 5719 spec->voicefx_val = sel; 5720 /* enable voice fx */ 5721 ca0132_voicefx_set(codec, (sel ? 1 : 0)); 5722 } 5723 5724 return 1; 5725 } 5726 5727 static int ca0132_switch_get(struct snd_kcontrol *kcontrol, 5728 struct snd_ctl_elem_value *ucontrol) 5729 { 5730 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5731 struct ca0132_spec *spec = codec->spec; 5732 hda_nid_t nid = get_amp_nid(kcontrol); 5733 int ch = get_amp_channels(kcontrol); 5734 long *valp = ucontrol->value.integer.value; 5735 5736 /* vnode */ 5737 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5738 if (ch & 1) { 5739 *valp = spec->vnode_lswitch[nid - VNODE_START_NID]; 5740 valp++; 5741 } 5742 if (ch & 2) { 5743 *valp = spec->vnode_rswitch[nid - VNODE_START_NID]; 5744 valp++; 5745 } 5746 return 0; 5747 } 5748 5749 /* effects, include PE and CrystalVoice */ 5750 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) { 5751 *valp = spec->effects_switch[nid - EFFECT_START_NID]; 5752 return 0; 5753 } 5754 5755 /* mic boost */ 5756 if (nid == spec->input_pins[0]) { 5757 *valp = spec->cur_mic_boost; 5758 return 0; 5759 } 5760 5761 return 0; 5762 } 5763 5764 static int ca0132_switch_put(struct snd_kcontrol *kcontrol, 5765 struct snd_ctl_elem_value *ucontrol) 5766 { 5767 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5768 struct ca0132_spec *spec = codec->spec; 5769 hda_nid_t nid = get_amp_nid(kcontrol); 5770 int ch = get_amp_channels(kcontrol); 5771 long *valp = ucontrol->value.integer.value; 5772 int changed = 1; 5773 5774 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n", 5775 nid, *valp); 5776 5777 snd_hda_power_up(codec); 5778 /* vnode */ 5779 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) { 5780 if (ch & 1) { 5781 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp; 5782 valp++; 5783 } 5784 if (ch & 2) { 5785 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp; 5786 valp++; 5787 } 5788 changed = ca0132_vnode_switch_set(kcontrol, ucontrol); 5789 goto exit; 5790 } 5791 5792 /* PE */ 5793 if (nid == PLAY_ENHANCEMENT) { 5794 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5795 changed = ca0132_pe_switch_set(codec); 5796 goto exit; 5797 } 5798 5799 /* CrystalVoice */ 5800 if (nid == CRYSTAL_VOICE) { 5801 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5802 changed = ca0132_cvoice_switch_set(codec); 5803 goto exit; 5804 } 5805 5806 /* out and in effects */ 5807 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) || 5808 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) { 5809 spec->effects_switch[nid - EFFECT_START_NID] = *valp; 5810 changed = ca0132_effects_set(codec, nid, *valp); 5811 goto exit; 5812 } 5813 5814 /* mic boost */ 5815 if (nid == spec->input_pins[0]) { 5816 spec->cur_mic_boost = *valp; 5817 if (ca0132_use_alt_functions(spec)) { 5818 if (spec->in_enum_val != REAR_LINE_IN) 5819 changed = ca0132_mic_boost_set(codec, *valp); 5820 } else { 5821 /* Mic boost does not apply to Digital Mic */ 5822 if (spec->cur_mic_type != DIGITAL_MIC) 5823 changed = ca0132_mic_boost_set(codec, *valp); 5824 } 5825 5826 goto exit; 5827 } 5828 5829 if (nid == ZXR_HEADPHONE_GAIN) { 5830 spec->zxr_gain_set = *valp; 5831 if (spec->cur_out_type == HEADPHONE_OUT) 5832 changed = zxr_headphone_gain_set(codec, *valp); 5833 else 5834 changed = 0; 5835 5836 goto exit; 5837 } 5838 5839 exit: 5840 snd_hda_power_down(codec); 5841 return changed; 5842 } 5843 5844 /* 5845 * Volume related 5846 */ 5847 /* 5848 * Sets the internal DSP decibel level to match the DAC for output, and the 5849 * ADC for input. Currently only the SBZ sets dsp capture volume level, and 5850 * all alternative codecs set DSP playback volume. 5851 */ 5852 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid) 5853 { 5854 struct ca0132_spec *spec = codec->spec; 5855 unsigned int dsp_dir; 5856 unsigned int lookup_val; 5857 5858 if (nid == VNID_SPK) 5859 dsp_dir = DSP_VOL_OUT; 5860 else 5861 dsp_dir = DSP_VOL_IN; 5862 5863 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID]; 5864 5865 dspio_set_uint_param(codec, 5866 ca0132_alt_vol_ctls[dsp_dir].mid, 5867 ca0132_alt_vol_ctls[dsp_dir].reqs[0], 5868 float_vol_db_lookup[lookup_val]); 5869 5870 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID]; 5871 5872 dspio_set_uint_param(codec, 5873 ca0132_alt_vol_ctls[dsp_dir].mid, 5874 ca0132_alt_vol_ctls[dsp_dir].reqs[1], 5875 float_vol_db_lookup[lookup_val]); 5876 5877 dspio_set_uint_param(codec, 5878 ca0132_alt_vol_ctls[dsp_dir].mid, 5879 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO); 5880 } 5881 5882 static int ca0132_volume_info(struct snd_kcontrol *kcontrol, 5883 struct snd_ctl_elem_info *uinfo) 5884 { 5885 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5886 struct ca0132_spec *spec = codec->spec; 5887 hda_nid_t nid = get_amp_nid(kcontrol); 5888 int ch = get_amp_channels(kcontrol); 5889 int dir = get_amp_direction(kcontrol); 5890 unsigned long pval; 5891 int err; 5892 5893 switch (nid) { 5894 case VNID_SPK: 5895 /* follow shared_out info */ 5896 nid = spec->shared_out_nid; 5897 mutex_lock(&codec->control_mutex); 5898 pval = kcontrol->private_value; 5899 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5900 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5901 kcontrol->private_value = pval; 5902 mutex_unlock(&codec->control_mutex); 5903 break; 5904 case VNID_MIC: 5905 /* follow shared_mic info */ 5906 nid = spec->shared_mic_nid; 5907 mutex_lock(&codec->control_mutex); 5908 pval = kcontrol->private_value; 5909 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 5910 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5911 kcontrol->private_value = pval; 5912 mutex_unlock(&codec->control_mutex); 5913 break; 5914 default: 5915 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo); 5916 } 5917 return err; 5918 } 5919 5920 static int ca0132_volume_get(struct snd_kcontrol *kcontrol, 5921 struct snd_ctl_elem_value *ucontrol) 5922 { 5923 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5924 struct ca0132_spec *spec = codec->spec; 5925 hda_nid_t nid = get_amp_nid(kcontrol); 5926 int ch = get_amp_channels(kcontrol); 5927 long *valp = ucontrol->value.integer.value; 5928 5929 /* store the left and right volume */ 5930 if (ch & 1) { 5931 *valp = spec->vnode_lvol[nid - VNODE_START_NID]; 5932 valp++; 5933 } 5934 if (ch & 2) { 5935 *valp = spec->vnode_rvol[nid - VNODE_START_NID]; 5936 valp++; 5937 } 5938 return 0; 5939 } 5940 5941 static int ca0132_volume_put(struct snd_kcontrol *kcontrol, 5942 struct snd_ctl_elem_value *ucontrol) 5943 { 5944 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5945 struct ca0132_spec *spec = codec->spec; 5946 hda_nid_t nid = get_amp_nid(kcontrol); 5947 int ch = get_amp_channels(kcontrol); 5948 long *valp = ucontrol->value.integer.value; 5949 hda_nid_t shared_nid = 0; 5950 bool effective; 5951 int changed = 1; 5952 5953 /* store the left and right volume */ 5954 if (ch & 1) { 5955 spec->vnode_lvol[nid - VNODE_START_NID] = *valp; 5956 valp++; 5957 } 5958 if (ch & 2) { 5959 spec->vnode_rvol[nid - VNODE_START_NID] = *valp; 5960 valp++; 5961 } 5962 5963 /* if effective conditions, then update hw immediately. */ 5964 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid); 5965 if (effective) { 5966 int dir = get_amp_direction(kcontrol); 5967 unsigned long pval; 5968 5969 snd_hda_power_up(codec); 5970 mutex_lock(&codec->control_mutex); 5971 pval = kcontrol->private_value; 5972 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch, 5973 0, dir); 5974 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 5975 kcontrol->private_value = pval; 5976 mutex_unlock(&codec->control_mutex); 5977 snd_hda_power_down(codec); 5978 } 5979 5980 return changed; 5981 } 5982 5983 /* 5984 * This function is the same as the one above, because using an if statement 5985 * inside of the above volume control for the DSP volume would cause too much 5986 * lag. This is a lot more smooth. 5987 */ 5988 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol, 5989 struct snd_ctl_elem_value *ucontrol) 5990 { 5991 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 5992 struct ca0132_spec *spec = codec->spec; 5993 hda_nid_t nid = get_amp_nid(kcontrol); 5994 int ch = get_amp_channels(kcontrol); 5995 long *valp = ucontrol->value.integer.value; 5996 hda_nid_t vnid = 0; 5997 int changed = 1; 5998 5999 switch (nid) { 6000 case 0x02: 6001 vnid = VNID_SPK; 6002 break; 6003 case 0x07: 6004 vnid = VNID_MIC; 6005 break; 6006 } 6007 6008 /* store the left and right volume */ 6009 if (ch & 1) { 6010 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp; 6011 valp++; 6012 } 6013 if (ch & 2) { 6014 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp; 6015 valp++; 6016 } 6017 6018 snd_hda_power_up(codec); 6019 ca0132_alt_dsp_volume_put(codec, vnid); 6020 mutex_lock(&codec->control_mutex); 6021 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol); 6022 mutex_unlock(&codec->control_mutex); 6023 snd_hda_power_down(codec); 6024 6025 return changed; 6026 } 6027 6028 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag, 6029 unsigned int size, unsigned int __user *tlv) 6030 { 6031 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 6032 struct ca0132_spec *spec = codec->spec; 6033 hda_nid_t nid = get_amp_nid(kcontrol); 6034 int ch = get_amp_channels(kcontrol); 6035 int dir = get_amp_direction(kcontrol); 6036 unsigned long pval; 6037 int err; 6038 6039 switch (nid) { 6040 case VNID_SPK: 6041 /* follow shared_out tlv */ 6042 nid = spec->shared_out_nid; 6043 mutex_lock(&codec->control_mutex); 6044 pval = kcontrol->private_value; 6045 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6046 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6047 kcontrol->private_value = pval; 6048 mutex_unlock(&codec->control_mutex); 6049 break; 6050 case VNID_MIC: 6051 /* follow shared_mic tlv */ 6052 nid = spec->shared_mic_nid; 6053 mutex_lock(&codec->control_mutex); 6054 pval = kcontrol->private_value; 6055 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir); 6056 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6057 kcontrol->private_value = pval; 6058 mutex_unlock(&codec->control_mutex); 6059 break; 6060 default: 6061 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv); 6062 } 6063 return err; 6064 } 6065 6066 /* Add volume slider control for effect level */ 6067 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid, 6068 const char *pfx, int dir) 6069 { 6070 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6071 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6072 struct snd_kcontrol_new knew = 6073 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type); 6074 6075 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]); 6076 6077 knew.tlv.c = NULL; 6078 6079 switch (nid) { 6080 case XBASS_XOVER: 6081 knew.info = ca0132_alt_xbass_xover_slider_info; 6082 knew.get = ca0132_alt_xbass_xover_slider_ctl_get; 6083 knew.put = ca0132_alt_xbass_xover_slider_put; 6084 break; 6085 default: 6086 knew.info = ca0132_alt_effect_slider_info; 6087 knew.get = ca0132_alt_slider_ctl_get; 6088 knew.put = ca0132_alt_effect_slider_put; 6089 knew.private_value = 6090 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type); 6091 break; 6092 } 6093 6094 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6095 } 6096 6097 /* 6098 * Added FX: prefix for the alternative codecs, because otherwise the surround 6099 * effect would conflict with the Surround sound volume control. Also seems more 6100 * clear as to what the switches do. Left alone for others. 6101 */ 6102 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid, 6103 const char *pfx, int dir) 6104 { 6105 struct ca0132_spec *spec = codec->spec; 6106 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN]; 6107 int type = dir ? HDA_INPUT : HDA_OUTPUT; 6108 struct snd_kcontrol_new knew = 6109 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type); 6110 /* If using alt_controls, add FX: prefix. But, don't add FX: 6111 * prefix to OutFX or InFX enable controls. 6112 */ 6113 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID)) 6114 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]); 6115 else 6116 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]); 6117 6118 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec)); 6119 } 6120 6121 static int add_voicefx(struct hda_codec *codec) 6122 { 6123 struct snd_kcontrol_new knew = 6124 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name, 6125 VOICEFX, 1, 0, HDA_INPUT); 6126 knew.info = ca0132_voicefx_info; 6127 knew.get = ca0132_voicefx_get; 6128 knew.put = ca0132_voicefx_put; 6129 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec)); 6130 } 6131 6132 /* Create the EQ Preset control */ 6133 static int add_ca0132_alt_eq_presets(struct hda_codec *codec) 6134 { 6135 struct snd_kcontrol_new knew = 6136 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name, 6137 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT); 6138 knew.info = ca0132_alt_eq_preset_info; 6139 knew.get = ca0132_alt_eq_preset_get; 6140 knew.put = ca0132_alt_eq_preset_put; 6141 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM, 6142 snd_ctl_new1(&knew, codec)); 6143 } 6144 6145 /* 6146 * Add enumerated control for the three different settings of the smart volume 6147 * output effect. Normal just uses the slider value, and loud and night are 6148 * their own things that ignore that value. 6149 */ 6150 static int ca0132_alt_add_svm_enum(struct hda_codec *codec) 6151 { 6152 struct snd_kcontrol_new knew = 6153 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting", 6154 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT); 6155 knew.info = ca0132_alt_svm_setting_info; 6156 knew.get = ca0132_alt_svm_setting_get; 6157 knew.put = ca0132_alt_svm_setting_put; 6158 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM, 6159 snd_ctl_new1(&knew, codec)); 6160 6161 } 6162 6163 /* 6164 * Create an Output Select enumerated control for codecs with surround 6165 * out capabilities. 6166 */ 6167 static int ca0132_alt_add_output_enum(struct hda_codec *codec) 6168 { 6169 struct snd_kcontrol_new knew = 6170 HDA_CODEC_MUTE_MONO("Output Select", 6171 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT); 6172 knew.info = ca0132_alt_output_select_get_info; 6173 knew.get = ca0132_alt_output_select_get; 6174 knew.put = ca0132_alt_output_select_put; 6175 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM, 6176 snd_ctl_new1(&knew, codec)); 6177 } 6178 6179 /* 6180 * Create an Input Source enumerated control for the alternate ca0132 codecs 6181 * because the front microphone has no auto-detect, and Line-in has to be set 6182 * somehow. 6183 */ 6184 static int ca0132_alt_add_input_enum(struct hda_codec *codec) 6185 { 6186 struct snd_kcontrol_new knew = 6187 HDA_CODEC_MUTE_MONO("Input Source", 6188 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT); 6189 knew.info = ca0132_alt_input_source_info; 6190 knew.get = ca0132_alt_input_source_get; 6191 knew.put = ca0132_alt_input_source_put; 6192 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM, 6193 snd_ctl_new1(&knew, codec)); 6194 } 6195 6196 /* 6197 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds 6198 * more control than the original mic boost, which is either full 30dB or off. 6199 */ 6200 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec) 6201 { 6202 struct snd_kcontrol_new knew = 6203 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch", 6204 MIC_BOOST_ENUM, 1, 0, HDA_INPUT); 6205 knew.info = ca0132_alt_mic_boost_info; 6206 knew.get = ca0132_alt_mic_boost_get; 6207 knew.put = ca0132_alt_mic_boost_put; 6208 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM, 6209 snd_ctl_new1(&knew, codec)); 6210 6211 } 6212 6213 /* 6214 * Add headphone gain enumerated control for the AE-5. This switches between 6215 * three modes, low, medium, and high. When non-headphone outputs are selected, 6216 * it is automatically set to high. This is the same behavior as Windows. 6217 */ 6218 static int ae5_add_headphone_gain_enum(struct hda_codec *codec) 6219 { 6220 struct snd_kcontrol_new knew = 6221 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain", 6222 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT); 6223 knew.info = ae5_headphone_gain_info; 6224 knew.get = ae5_headphone_gain_get; 6225 knew.put = ae5_headphone_gain_put; 6226 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM, 6227 snd_ctl_new1(&knew, codec)); 6228 } 6229 6230 /* 6231 * Add sound filter enumerated control for the AE-5. This adds three different 6232 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've 6233 * read into it, it changes the DAC's interpolation filter. 6234 */ 6235 static int ae5_add_sound_filter_enum(struct hda_codec *codec) 6236 { 6237 struct snd_kcontrol_new knew = 6238 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter", 6239 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT); 6240 knew.info = ae5_sound_filter_info; 6241 knew.get = ae5_sound_filter_get; 6242 knew.put = ae5_sound_filter_put; 6243 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM, 6244 snd_ctl_new1(&knew, codec)); 6245 } 6246 6247 static int zxr_add_headphone_gain_switch(struct hda_codec *codec) 6248 { 6249 struct snd_kcontrol_new knew = 6250 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain", 6251 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT); 6252 6253 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN, 6254 snd_ctl_new1(&knew, codec)); 6255 } 6256 6257 /* 6258 * Need to create slave controls for the alternate codecs that have surround 6259 * capabilities. 6260 */ 6261 static const char * const ca0132_alt_slave_pfxs[] = { 6262 "Front", "Surround", "Center", "LFE", NULL, 6263 }; 6264 6265 /* 6266 * Also need special channel map, because the default one is incorrect. 6267 * I think this has to do with the pin for rear surround being 0x11, 6268 * and the center/lfe being 0x10. Usually the pin order is the opposite. 6269 */ 6270 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = { 6271 { .channels = 2, 6272 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } }, 6273 { .channels = 4, 6274 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6275 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6276 { .channels = 6, 6277 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR, 6278 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE, 6279 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } }, 6280 { } 6281 }; 6282 6283 /* Add the correct chmap for streams with 6 channels. */ 6284 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec) 6285 { 6286 int err = 0; 6287 struct hda_pcm *pcm; 6288 6289 list_for_each_entry(pcm, &codec->pcm_list_head, list) { 6290 struct hda_pcm_stream *hinfo = 6291 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 6292 struct snd_pcm_chmap *chmap; 6293 const struct snd_pcm_chmap_elem *elem; 6294 6295 elem = ca0132_alt_chmaps; 6296 if (hinfo->channels_max == 6) { 6297 err = snd_pcm_add_chmap_ctls(pcm->pcm, 6298 SNDRV_PCM_STREAM_PLAYBACK, 6299 elem, hinfo->channels_max, 0, &chmap); 6300 if (err < 0) 6301 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!"); 6302 } 6303 } 6304 } 6305 6306 /* 6307 * When changing Node IDs for Mixer Controls below, make sure to update 6308 * Node IDs in ca0132_config() as well. 6309 */ 6310 static const struct snd_kcontrol_new ca0132_mixer[] = { 6311 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT), 6312 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT), 6313 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6314 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6315 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT), 6316 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT), 6317 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6318 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6319 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch", 6320 0x12, 1, HDA_INPUT), 6321 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch", 6322 VNID_HP_SEL, 1, HDA_OUTPUT), 6323 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch", 6324 VNID_AMIC1_SEL, 1, HDA_INPUT), 6325 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6326 VNID_HP_ASEL, 1, HDA_OUTPUT), 6327 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch", 6328 VNID_AMIC1_ASEL, 1, HDA_INPUT), 6329 { } /* end */ 6330 }; 6331 6332 /* 6333 * Desktop specific control mixer. Removes auto-detect for mic, and adds 6334 * surround controls. Also sets both the Front Playback and Capture Volume 6335 * controls to alt so they set the DSP's decibel level. 6336 */ 6337 static const struct snd_kcontrol_new desktop_mixer[] = { 6338 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6339 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6340 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6341 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6342 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6343 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6344 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6345 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6346 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT), 6347 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6348 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6349 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6350 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6351 VNID_HP_ASEL, 1, HDA_OUTPUT), 6352 { } /* end */ 6353 }; 6354 6355 /* 6356 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture 6357 * because it doesn't set decibel levels for the DSP for capture. 6358 */ 6359 static const struct snd_kcontrol_new r3di_mixer[] = { 6360 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT), 6361 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT), 6362 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT), 6363 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT), 6364 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT), 6365 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT), 6366 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT), 6367 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT), 6368 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT), 6369 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT), 6370 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT), 6371 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT), 6372 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch", 6373 VNID_HP_ASEL, 1, HDA_OUTPUT), 6374 { } /* end */ 6375 }; 6376 6377 static int ca0132_build_controls(struct hda_codec *codec) 6378 { 6379 struct ca0132_spec *spec = codec->spec; 6380 int i, num_fx, num_sliders; 6381 int err = 0; 6382 6383 /* Add Mixer controls */ 6384 for (i = 0; i < spec->num_mixers; i++) { 6385 err = snd_hda_add_new_ctls(codec, spec->mixers[i]); 6386 if (err < 0) 6387 return err; 6388 } 6389 /* Setup vmaster with surround slaves for desktop ca0132 devices */ 6390 if (ca0132_use_alt_functions(spec)) { 6391 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT, 6392 spec->tlv); 6393 snd_hda_add_vmaster(codec, "Master Playback Volume", 6394 spec->tlv, ca0132_alt_slave_pfxs, 6395 "Playback Volume"); 6396 err = __snd_hda_add_vmaster(codec, "Master Playback Switch", 6397 NULL, ca0132_alt_slave_pfxs, 6398 "Playback Switch", 6399 true, &spec->vmaster_mute.sw_kctl); 6400 if (err < 0) 6401 return err; 6402 } 6403 6404 /* Add in and out effects controls. 6405 * VoiceFX, PE and CrystalVoice are added separately. 6406 */ 6407 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 6408 for (i = 0; i < num_fx; i++) { 6409 /* Desktop cards break if Echo Cancellation is used. */ 6410 if (ca0132_use_pci_mmio(spec)) { 6411 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID + 6412 OUT_EFFECTS_COUNT)) 6413 continue; 6414 } 6415 6416 err = add_fx_switch(codec, ca0132_effects[i].nid, 6417 ca0132_effects[i].name, 6418 ca0132_effects[i].direct); 6419 if (err < 0) 6420 return err; 6421 } 6422 /* 6423 * If codec has use_alt_controls set to true, add effect level sliders, 6424 * EQ presets, and Smart Volume presets. Also, change names to add FX 6425 * prefix, and change PlayEnhancement and CrystalVoice to match. 6426 */ 6427 if (ca0132_use_alt_controls(spec)) { 6428 err = ca0132_alt_add_svm_enum(codec); 6429 if (err < 0) 6430 return err; 6431 6432 err = add_ca0132_alt_eq_presets(codec); 6433 if (err < 0) 6434 return err; 6435 6436 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6437 "Enable OutFX", 0); 6438 if (err < 0) 6439 return err; 6440 6441 err = add_fx_switch(codec, CRYSTAL_VOICE, 6442 "Enable InFX", 1); 6443 if (err < 0) 6444 return err; 6445 6446 num_sliders = OUT_EFFECTS_COUNT - 1; 6447 for (i = 0; i < num_sliders; i++) { 6448 err = ca0132_alt_add_effect_slider(codec, 6449 ca0132_effects[i].nid, 6450 ca0132_effects[i].name, 6451 ca0132_effects[i].direct); 6452 if (err < 0) 6453 return err; 6454 } 6455 6456 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER, 6457 "X-Bass Crossover", EFX_DIR_OUT); 6458 6459 if (err < 0) 6460 return err; 6461 } else { 6462 err = add_fx_switch(codec, PLAY_ENHANCEMENT, 6463 "PlayEnhancement", 0); 6464 if (err < 0) 6465 return err; 6466 6467 err = add_fx_switch(codec, CRYSTAL_VOICE, 6468 "CrystalVoice", 1); 6469 if (err < 0) 6470 return err; 6471 } 6472 err = add_voicefx(codec); 6473 if (err < 0) 6474 return err; 6475 6476 /* 6477 * If the codec uses alt_functions, you need the enumerated controls 6478 * to select the new outputs and inputs, plus add the new mic boost 6479 * setting control. 6480 */ 6481 if (ca0132_use_alt_functions(spec)) { 6482 err = ca0132_alt_add_output_enum(codec); 6483 if (err < 0) 6484 return err; 6485 err = ca0132_alt_add_mic_boost_enum(codec); 6486 if (err < 0) 6487 return err; 6488 /* 6489 * ZxR only has microphone input, there is no front panel 6490 * header on the card, and aux-in is handled by the DBPro board. 6491 */ 6492 if (ca0132_quirk(spec) != QUIRK_ZXR) { 6493 err = ca0132_alt_add_input_enum(codec); 6494 if (err < 0) 6495 return err; 6496 } 6497 } 6498 6499 if (ca0132_quirk(spec) == QUIRK_AE5) { 6500 err = ae5_add_headphone_gain_enum(codec); 6501 if (err < 0) 6502 return err; 6503 err = ae5_add_sound_filter_enum(codec); 6504 if (err < 0) 6505 return err; 6506 } 6507 6508 if (ca0132_quirk(spec) == QUIRK_ZXR) { 6509 err = zxr_add_headphone_gain_switch(codec); 6510 if (err < 0) 6511 return err; 6512 } 6513 #ifdef ENABLE_TUNING_CONTROLS 6514 add_tuning_ctls(codec); 6515 #endif 6516 6517 err = snd_hda_jack_add_kctls(codec, &spec->autocfg); 6518 if (err < 0) 6519 return err; 6520 6521 if (spec->dig_out) { 6522 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6523 spec->dig_out); 6524 if (err < 0) 6525 return err; 6526 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout); 6527 if (err < 0) 6528 return err; 6529 /* spec->multiout.share_spdif = 1; */ 6530 } 6531 6532 if (spec->dig_in) { 6533 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6534 if (err < 0) 6535 return err; 6536 } 6537 6538 if (ca0132_use_alt_functions(spec)) 6539 ca0132_alt_add_chmap_ctls(codec); 6540 6541 return 0; 6542 } 6543 6544 static int dbpro_build_controls(struct hda_codec *codec) 6545 { 6546 struct ca0132_spec *spec = codec->spec; 6547 int err = 0; 6548 6549 if (spec->dig_out) { 6550 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out, 6551 spec->dig_out); 6552 if (err < 0) 6553 return err; 6554 } 6555 6556 if (spec->dig_in) { 6557 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in); 6558 if (err < 0) 6559 return err; 6560 } 6561 6562 return 0; 6563 } 6564 6565 /* 6566 * PCM 6567 */ 6568 static const struct hda_pcm_stream ca0132_pcm_analog_playback = { 6569 .substreams = 1, 6570 .channels_min = 2, 6571 .channels_max = 6, 6572 .ops = { 6573 .prepare = ca0132_playback_pcm_prepare, 6574 .cleanup = ca0132_playback_pcm_cleanup, 6575 .get_delay = ca0132_playback_pcm_delay, 6576 }, 6577 }; 6578 6579 static const struct hda_pcm_stream ca0132_pcm_analog_capture = { 6580 .substreams = 1, 6581 .channels_min = 2, 6582 .channels_max = 2, 6583 .ops = { 6584 .prepare = ca0132_capture_pcm_prepare, 6585 .cleanup = ca0132_capture_pcm_cleanup, 6586 .get_delay = ca0132_capture_pcm_delay, 6587 }, 6588 }; 6589 6590 static const struct hda_pcm_stream ca0132_pcm_digital_playback = { 6591 .substreams = 1, 6592 .channels_min = 2, 6593 .channels_max = 2, 6594 .ops = { 6595 .open = ca0132_dig_playback_pcm_open, 6596 .close = ca0132_dig_playback_pcm_close, 6597 .prepare = ca0132_dig_playback_pcm_prepare, 6598 .cleanup = ca0132_dig_playback_pcm_cleanup 6599 }, 6600 }; 6601 6602 static const struct hda_pcm_stream ca0132_pcm_digital_capture = { 6603 .substreams = 1, 6604 .channels_min = 2, 6605 .channels_max = 2, 6606 }; 6607 6608 static int ca0132_build_pcms(struct hda_codec *codec) 6609 { 6610 struct ca0132_spec *spec = codec->spec; 6611 struct hda_pcm *info; 6612 6613 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog"); 6614 if (!info) 6615 return -ENOMEM; 6616 if (ca0132_use_alt_functions(spec)) { 6617 info->own_chmap = true; 6618 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap 6619 = ca0132_alt_chmaps; 6620 } 6621 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback; 6622 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0]; 6623 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max = 6624 spec->multiout.max_channels; 6625 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6626 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6627 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6628 6629 /* With the DSP enabled, desktops don't use this ADC. */ 6630 if (!ca0132_use_alt_functions(spec)) { 6631 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2"); 6632 if (!info) 6633 return -ENOMEM; 6634 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6635 ca0132_pcm_analog_capture; 6636 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6637 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1]; 6638 } 6639 6640 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear"); 6641 if (!info) 6642 return -ENOMEM; 6643 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6644 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6645 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2]; 6646 6647 if (!spec->dig_out && !spec->dig_in) 6648 return 0; 6649 6650 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6651 if (!info) 6652 return -ENOMEM; 6653 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6654 if (spec->dig_out) { 6655 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6656 ca0132_pcm_digital_playback; 6657 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6658 } 6659 if (spec->dig_in) { 6660 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6661 ca0132_pcm_digital_capture; 6662 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6663 } 6664 6665 return 0; 6666 } 6667 6668 static int dbpro_build_pcms(struct hda_codec *codec) 6669 { 6670 struct ca0132_spec *spec = codec->spec; 6671 struct hda_pcm *info; 6672 6673 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog"); 6674 if (!info) 6675 return -ENOMEM; 6676 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture; 6677 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1; 6678 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0]; 6679 6680 6681 if (!spec->dig_out && !spec->dig_in) 6682 return 0; 6683 6684 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital"); 6685 if (!info) 6686 return -ENOMEM; 6687 info->pcm_type = HDA_PCM_TYPE_SPDIF; 6688 if (spec->dig_out) { 6689 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = 6690 ca0132_pcm_digital_playback; 6691 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out; 6692 } 6693 if (spec->dig_in) { 6694 info->stream[SNDRV_PCM_STREAM_CAPTURE] = 6695 ca0132_pcm_digital_capture; 6696 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in; 6697 } 6698 6699 return 0; 6700 } 6701 6702 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac) 6703 { 6704 if (pin) { 6705 snd_hda_set_pin_ctl(codec, pin, PIN_HP); 6706 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 6707 snd_hda_codec_write(codec, pin, 0, 6708 AC_VERB_SET_AMP_GAIN_MUTE, 6709 AMP_OUT_UNMUTE); 6710 } 6711 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP)) 6712 snd_hda_codec_write(codec, dac, 0, 6713 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO); 6714 } 6715 6716 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc) 6717 { 6718 if (pin) { 6719 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80); 6720 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP) 6721 snd_hda_codec_write(codec, pin, 0, 6722 AC_VERB_SET_AMP_GAIN_MUTE, 6723 AMP_IN_UNMUTE(0)); 6724 } 6725 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) { 6726 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE, 6727 AMP_IN_UNMUTE(0)); 6728 6729 /* init to 0 dB and unmute. */ 6730 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6731 HDA_AMP_VOLMASK, 0x5a); 6732 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0, 6733 HDA_AMP_MUTE, 0); 6734 } 6735 } 6736 6737 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir) 6738 { 6739 unsigned int caps; 6740 6741 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ? 6742 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP); 6743 snd_hda_override_amp_caps(codec, nid, dir, caps); 6744 } 6745 6746 /* 6747 * Switch between Digital built-in mic and analog mic. 6748 */ 6749 static void ca0132_set_dmic(struct hda_codec *codec, int enable) 6750 { 6751 struct ca0132_spec *spec = codec->spec; 6752 unsigned int tmp; 6753 u8 val; 6754 unsigned int oldval; 6755 6756 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable); 6757 6758 oldval = stop_mic1(codec); 6759 ca0132_set_vipsource(codec, 0); 6760 if (enable) { 6761 /* set DMic input as 2-ch */ 6762 tmp = FLOAT_TWO; 6763 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6764 6765 val = spec->dmic_ctl; 6766 val |= 0x80; 6767 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6768 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6769 6770 if (!(spec->dmic_ctl & 0x20)) 6771 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1); 6772 } else { 6773 /* set AMic input as mono */ 6774 tmp = FLOAT_ONE; 6775 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6776 6777 val = spec->dmic_ctl; 6778 /* clear bit7 and bit5 to disable dmic */ 6779 val &= 0x5f; 6780 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6781 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6782 6783 if (!(spec->dmic_ctl & 0x20)) 6784 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0); 6785 } 6786 ca0132_set_vipsource(codec, 1); 6787 resume_mic1(codec, oldval); 6788 } 6789 6790 /* 6791 * Initialization for Digital Mic. 6792 */ 6793 static void ca0132_init_dmic(struct hda_codec *codec) 6794 { 6795 struct ca0132_spec *spec = codec->spec; 6796 u8 val; 6797 6798 /* Setup Digital Mic here, but don't enable. 6799 * Enable based on jack detect. 6800 */ 6801 6802 /* MCLK uses MPIO1, set to enable. 6803 * Bit 2-0: MPIO select 6804 * Bit 3: set to disable 6805 * Bit 7-4: reserved 6806 */ 6807 val = 0x01; 6808 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6809 VENDOR_CHIPIO_DMIC_MCLK_SET, val); 6810 6811 /* Data1 uses MPIO3. Data2 not use 6812 * Bit 2-0: Data1 MPIO select 6813 * Bit 3: set disable Data1 6814 * Bit 6-4: Data2 MPIO select 6815 * Bit 7: set disable Data2 6816 */ 6817 val = 0x83; 6818 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6819 VENDOR_CHIPIO_DMIC_PIN_SET, val); 6820 6821 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first. 6822 * Bit 3-0: Channel mask 6823 * Bit 4: set for 48KHz, clear for 32KHz 6824 * Bit 5: mode 6825 * Bit 6: set to select Data2, clear for Data1 6826 * Bit 7: set to enable DMic, clear for AMic 6827 */ 6828 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4) 6829 val = 0x33; 6830 else 6831 val = 0x23; 6832 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */ 6833 spec->dmic_ctl = val; 6834 snd_hda_codec_write(codec, spec->input_pins[0], 0, 6835 VENDOR_CHIPIO_DMIC_CTL_SET, val); 6836 } 6837 6838 /* 6839 * Initialization for Analog Mic 2 6840 */ 6841 static void ca0132_init_analog_mic2(struct hda_codec *codec) 6842 { 6843 struct ca0132_spec *spec = codec->spec; 6844 6845 mutex_lock(&spec->chipio_mutex); 6846 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6847 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 6848 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6849 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6850 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6851 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6852 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6853 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D); 6854 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6855 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 6856 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 6857 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 6858 mutex_unlock(&spec->chipio_mutex); 6859 } 6860 6861 static void ca0132_refresh_widget_caps(struct hda_codec *codec) 6862 { 6863 struct ca0132_spec *spec = codec->spec; 6864 int i; 6865 6866 codec_dbg(codec, "ca0132_refresh_widget_caps.\n"); 6867 snd_hda_codec_update_widgets(codec); 6868 6869 for (i = 0; i < spec->multiout.num_dacs; i++) 6870 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT); 6871 6872 for (i = 0; i < spec->num_outputs; i++) 6873 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT); 6874 6875 for (i = 0; i < spec->num_inputs; i++) { 6876 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT); 6877 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT); 6878 } 6879 } 6880 6881 /* 6882 * Creates a dummy stream to bind the output to. This seems to have to be done 6883 * after changing the main outputs source and destination streams. 6884 */ 6885 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec) 6886 { 6887 struct ca0132_spec *spec = codec->spec; 6888 unsigned int stream_format; 6889 6890 stream_format = snd_hdac_calc_stream_format(48000, 2, 6891 SNDRV_PCM_FORMAT_S32_LE, 32, 0); 6892 6893 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id, 6894 0, stream_format); 6895 6896 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]); 6897 } 6898 6899 /* 6900 * Initialize mic for non-chromebook ca0132 implementations. 6901 */ 6902 static void ca0132_alt_init_analog_mics(struct hda_codec *codec) 6903 { 6904 struct ca0132_spec *spec = codec->spec; 6905 unsigned int tmp; 6906 6907 /* Mic 1 Setup */ 6908 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 6909 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 6910 if (ca0132_quirk(spec) == QUIRK_R3DI) { 6911 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6912 tmp = FLOAT_ONE; 6913 } else 6914 tmp = FLOAT_THREE; 6915 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 6916 6917 /* Mic 2 setup (not present on desktop cards) */ 6918 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000); 6919 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000); 6920 if (ca0132_quirk(spec) == QUIRK_R3DI) 6921 chipio_set_conn_rate(codec, 0x0F, SR_96_000); 6922 tmp = FLOAT_ZERO; 6923 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 6924 } 6925 6926 /* 6927 * Sets the source of stream 0x14 to connpointID 0x48, and the destination 6928 * connpointID to 0x91. If this isn't done, the destination is 0x71, and 6929 * you get no sound. I'm guessing this has to do with the Sound Blaster Z 6930 * having an updated DAC, which changes the destination to that DAC. 6931 */ 6932 static void sbz_connect_streams(struct hda_codec *codec) 6933 { 6934 struct ca0132_spec *spec = codec->spec; 6935 6936 mutex_lock(&spec->chipio_mutex); 6937 6938 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n"); 6939 6940 chipio_set_stream_channels(codec, 0x0C, 6); 6941 chipio_set_stream_control(codec, 0x0C, 1); 6942 6943 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */ 6944 chipio_write_no_mutex(codec, 0x18a020, 0x00000043); 6945 6946 /* Setup stream 0x14 with it's source and destination points */ 6947 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91); 6948 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000); 6949 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000); 6950 chipio_set_stream_channels(codec, 0x14, 2); 6951 chipio_set_stream_control(codec, 0x14, 1); 6952 6953 codec_dbg(codec, "Connect Streams exited, mutex released.\n"); 6954 6955 mutex_unlock(&spec->chipio_mutex); 6956 } 6957 6958 /* 6959 * Write data through ChipIO to setup proper stream destinations. 6960 * Not sure how it exactly works, but it seems to direct data 6961 * to different destinations. Example is f8 to c0, e0 to c0. 6962 * All I know is, if you don't set these, you get no sound. 6963 */ 6964 static void sbz_chipio_startup_data(struct hda_codec *codec) 6965 { 6966 struct ca0132_spec *spec = codec->spec; 6967 6968 mutex_lock(&spec->chipio_mutex); 6969 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n"); 6970 6971 /* These control audio output */ 6972 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0); 6973 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1); 6974 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6); 6975 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7); 6976 /* Signal to update I think */ 6977 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 6978 6979 chipio_set_stream_channels(codec, 0x0C, 6); 6980 chipio_set_stream_control(codec, 0x0C, 1); 6981 /* No clue what these control */ 6982 if (ca0132_quirk(spec) == QUIRK_SBZ) { 6983 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0); 6984 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1); 6985 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2); 6986 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3); 6987 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4); 6988 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5); 6989 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6); 6990 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7); 6991 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8); 6992 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9); 6993 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca); 6994 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb); 6995 } else if (ca0132_quirk(spec) == QUIRK_ZXR) { 6996 chipio_write_no_mutex(codec, 0x190038, 0x000140c2); 6997 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3); 6998 chipio_write_no_mutex(codec, 0x190040, 0x000150c4); 6999 chipio_write_no_mutex(codec, 0x190044, 0x000151c5); 7000 chipio_write_no_mutex(codec, 0x190050, 0x000142c8); 7001 chipio_write_no_mutex(codec, 0x190054, 0x000143c9); 7002 chipio_write_no_mutex(codec, 0x190058, 0x000152ca); 7003 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb); 7004 } 7005 chipio_write_no_mutex(codec, 0x19042c, 0x00000001); 7006 7007 codec_dbg(codec, "Startup Data exited, mutex released.\n"); 7008 mutex_unlock(&spec->chipio_mutex); 7009 } 7010 7011 /* 7012 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is 7013 * done after the DSP is loaded. 7014 */ 7015 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec) 7016 { 7017 struct ca0132_spec *spec = codec->spec; 7018 unsigned int tmp, i; 7019 7020 /* 7021 * Gotta run these twice, or else mic works inconsistently. Not clear 7022 * why this is, but multiple tests have confirmed it. 7023 */ 7024 for (i = 0; i < 2; i++) { 7025 switch (ca0132_quirk(spec)) { 7026 case QUIRK_SBZ: 7027 case QUIRK_AE5: 7028 tmp = 0x00000003; 7029 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7030 tmp = 0x00000000; 7031 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7032 tmp = 0x00000001; 7033 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7034 tmp = 0x00000004; 7035 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7036 tmp = 0x00000005; 7037 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7038 tmp = 0x00000000; 7039 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7040 break; 7041 case QUIRK_R3D: 7042 case QUIRK_R3DI: 7043 tmp = 0x00000000; 7044 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp); 7045 tmp = 0x00000001; 7046 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp); 7047 tmp = 0x00000004; 7048 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7049 tmp = 0x00000005; 7050 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7051 tmp = 0x00000000; 7052 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp); 7053 break; 7054 default: 7055 break; 7056 } 7057 msleep(100); 7058 } 7059 } 7060 7061 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec) 7062 { 7063 struct ca0132_spec *spec = codec->spec; 7064 unsigned int tmp; 7065 7066 chipio_set_stream_control(codec, 0x03, 0); 7067 chipio_set_stream_control(codec, 0x04, 0); 7068 7069 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7070 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7071 7072 tmp = FLOAT_THREE; 7073 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7074 7075 chipio_set_stream_control(codec, 0x03, 1); 7076 chipio_set_stream_control(codec, 0x04, 1); 7077 7078 switch (ca0132_quirk(spec)) { 7079 case QUIRK_SBZ: 7080 chipio_write(codec, 0x18b098, 0x0000000c); 7081 chipio_write(codec, 0x18b09C, 0x0000000c); 7082 break; 7083 case QUIRK_AE5: 7084 chipio_write(codec, 0x18b098, 0x0000000c); 7085 chipio_write(codec, 0x18b09c, 0x0000004c); 7086 break; 7087 default: 7088 break; 7089 } 7090 } 7091 7092 static void ae5_post_dsp_register_set(struct hda_codec *codec) 7093 { 7094 struct ca0132_spec *spec = codec->spec; 7095 7096 chipio_8051_write_direct(codec, 0x93, 0x10); 7097 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7098 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 7099 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7100 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 7101 7102 writeb(0xff, spec->mem_base + 0x304); 7103 writeb(0xff, spec->mem_base + 0x304); 7104 writeb(0xff, spec->mem_base + 0x304); 7105 writeb(0xff, spec->mem_base + 0x304); 7106 writeb(0x00, spec->mem_base + 0x100); 7107 writeb(0xff, spec->mem_base + 0x304); 7108 writeb(0x00, spec->mem_base + 0x100); 7109 writeb(0xff, spec->mem_base + 0x304); 7110 writeb(0x00, spec->mem_base + 0x100); 7111 writeb(0xff, spec->mem_base + 0x304); 7112 writeb(0x00, spec->mem_base + 0x100); 7113 writeb(0xff, spec->mem_base + 0x304); 7114 7115 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f); 7116 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 7117 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7118 } 7119 7120 static void ae5_post_dsp_param_setup(struct hda_codec *codec) 7121 { 7122 /* 7123 * Param3 in the 8051's memory is represented by the ascii string 'mch' 7124 * which seems to be 'multichannel'. This is also mentioned in the 7125 * AE-5's registry values in Windows. 7126 */ 7127 chipio_set_control_param(codec, 3, 0); 7128 /* 7129 * I believe ASI is 'audio serial interface' and that it's used to 7130 * change colors on the external LED strip connected to the AE-5. 7131 */ 7132 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1); 7133 7134 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83); 7135 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7136 7137 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7138 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92); 7139 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7140 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa); 7141 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7142 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22); 7143 } 7144 7145 static void ae5_post_dsp_pll_setup(struct hda_codec *codec) 7146 { 7147 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7148 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41); 7149 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7150 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8); 7151 7152 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7153 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45); 7154 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7155 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc); 7156 7157 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7158 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40); 7159 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7160 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb); 7161 7162 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7163 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7164 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7165 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7166 7167 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7168 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51); 7169 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7170 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d); 7171 } 7172 7173 static void ae5_post_dsp_stream_setup(struct hda_codec *codec) 7174 { 7175 struct ca0132_spec *spec = codec->spec; 7176 7177 mutex_lock(&spec->chipio_mutex); 7178 7179 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81); 7180 7181 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000); 7182 7183 chipio_set_stream_channels(codec, 0x0C, 6); 7184 chipio_set_stream_control(codec, 0x0C, 1); 7185 7186 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0); 7187 7188 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0); 7189 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000); 7190 chipio_set_stream_channels(codec, 0x18, 6); 7191 chipio_set_stream_control(codec, 0x18, 1); 7192 7193 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4); 7194 7195 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7196 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43); 7197 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 7198 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7); 7199 7200 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80); 7201 7202 mutex_unlock(&spec->chipio_mutex); 7203 } 7204 7205 static void ae5_post_dsp_startup_data(struct hda_codec *codec) 7206 { 7207 struct ca0132_spec *spec = codec->spec; 7208 7209 mutex_lock(&spec->chipio_mutex); 7210 7211 chipio_write_no_mutex(codec, 0x189000, 0x0001f101); 7212 chipio_write_no_mutex(codec, 0x189004, 0x0001f101); 7213 chipio_write_no_mutex(codec, 0x189024, 0x00014004); 7214 chipio_write_no_mutex(codec, 0x189028, 0x0002000f); 7215 7216 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7217 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7); 7218 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12); 7219 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00); 7220 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48); 7221 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05); 7222 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7223 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7224 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7225 ca0113_mmio_gpio_set(codec, 0, true); 7226 ca0113_mmio_gpio_set(codec, 1, true); 7227 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80); 7228 7229 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012); 7230 7231 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00); 7232 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00); 7233 7234 mutex_unlock(&spec->chipio_mutex); 7235 } 7236 7237 /* 7238 * Setup default parameters for DSP 7239 */ 7240 static void ca0132_setup_defaults(struct hda_codec *codec) 7241 { 7242 struct ca0132_spec *spec = codec->spec; 7243 unsigned int tmp; 7244 int num_fx; 7245 int idx, i; 7246 7247 if (spec->dsp_state != DSP_DOWNLOADED) 7248 return; 7249 7250 /* out, in effects + voicefx */ 7251 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7252 for (idx = 0; idx < num_fx; idx++) { 7253 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7254 dspio_set_uint_param(codec, ca0132_effects[idx].mid, 7255 ca0132_effects[idx].reqs[i], 7256 ca0132_effects[idx].def_vals[i]); 7257 } 7258 } 7259 7260 /*remove DSP headroom*/ 7261 tmp = FLOAT_ZERO; 7262 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7263 7264 /*set speaker EQ bypass attenuation*/ 7265 dspio_set_uint_param(codec, 0x8f, 0x01, tmp); 7266 7267 /* set AMic1 and AMic2 as mono mic */ 7268 tmp = FLOAT_ONE; 7269 dspio_set_uint_param(codec, 0x80, 0x00, tmp); 7270 dspio_set_uint_param(codec, 0x80, 0x01, tmp); 7271 7272 /* set AMic1 as CrystalVoice input */ 7273 tmp = FLOAT_ONE; 7274 dspio_set_uint_param(codec, 0x80, 0x05, tmp); 7275 7276 /* set WUH source */ 7277 tmp = FLOAT_TWO; 7278 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7279 } 7280 7281 /* 7282 * Setup default parameters for Recon3D/Recon3Di DSP. 7283 */ 7284 7285 static void r3d_setup_defaults(struct hda_codec *codec) 7286 { 7287 struct ca0132_spec *spec = codec->spec; 7288 unsigned int tmp; 7289 int num_fx; 7290 int idx, i; 7291 7292 if (spec->dsp_state != DSP_DOWNLOADED) 7293 return; 7294 7295 ca0132_alt_dsp_scp_startup(codec); 7296 ca0132_alt_init_analog_mics(codec); 7297 7298 /*remove DSP headroom*/ 7299 tmp = FLOAT_ZERO; 7300 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7301 7302 /* set WUH source */ 7303 tmp = FLOAT_TWO; 7304 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7305 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7306 7307 /* Set speaker source? */ 7308 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7309 7310 if (ca0132_quirk(spec) == QUIRK_R3DI) 7311 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED); 7312 7313 /* Setup effect defaults */ 7314 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7315 for (idx = 0; idx < num_fx; idx++) { 7316 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7317 dspio_set_uint_param(codec, 7318 ca0132_effects[idx].mid, 7319 ca0132_effects[idx].reqs[i], 7320 ca0132_effects[idx].def_vals[i]); 7321 } 7322 } 7323 } 7324 7325 /* 7326 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on 7327 * than the Chromebook setup. 7328 */ 7329 static void sbz_setup_defaults(struct hda_codec *codec) 7330 { 7331 struct ca0132_spec *spec = codec->spec; 7332 unsigned int tmp; 7333 int num_fx; 7334 int idx, i; 7335 7336 if (spec->dsp_state != DSP_DOWNLOADED) 7337 return; 7338 7339 ca0132_alt_dsp_scp_startup(codec); 7340 ca0132_alt_init_analog_mics(codec); 7341 sbz_connect_streams(codec); 7342 sbz_chipio_startup_data(codec); 7343 7344 chipio_set_stream_control(codec, 0x03, 1); 7345 chipio_set_stream_control(codec, 0x04, 1); 7346 7347 /* 7348 * Sets internal input loopback to off, used to have a switch to 7349 * enable input loopback, but turned out to be way too buggy. 7350 */ 7351 tmp = FLOAT_ONE; 7352 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7353 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7354 7355 /*remove DSP headroom*/ 7356 tmp = FLOAT_ZERO; 7357 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7358 7359 /* set WUH source */ 7360 tmp = FLOAT_TWO; 7361 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7362 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7363 7364 /* Set speaker source? */ 7365 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7366 7367 ca0132_alt_dsp_initial_mic_setup(codec); 7368 7369 /* out, in effects + voicefx */ 7370 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7371 for (idx = 0; idx < num_fx; idx++) { 7372 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7373 dspio_set_uint_param(codec, 7374 ca0132_effects[idx].mid, 7375 ca0132_effects[idx].reqs[i], 7376 ca0132_effects[idx].def_vals[i]); 7377 } 7378 } 7379 7380 ca0132_alt_create_dummy_stream(codec); 7381 } 7382 7383 /* 7384 * Setup default parameters for the Sound BlasterX AE-5 DSP. 7385 */ 7386 static void ae5_setup_defaults(struct hda_codec *codec) 7387 { 7388 struct ca0132_spec *spec = codec->spec; 7389 unsigned int tmp; 7390 int num_fx; 7391 int idx, i; 7392 7393 if (spec->dsp_state != DSP_DOWNLOADED) 7394 return; 7395 7396 ca0132_alt_dsp_scp_startup(codec); 7397 ca0132_alt_init_analog_mics(codec); 7398 chipio_set_stream_control(codec, 0x03, 1); 7399 chipio_set_stream_control(codec, 0x04, 1); 7400 7401 /* New, unknown SCP req's */ 7402 tmp = FLOAT_ZERO; 7403 dspio_set_uint_param(codec, 0x96, 0x29, tmp); 7404 dspio_set_uint_param(codec, 0x96, 0x2a, tmp); 7405 dspio_set_uint_param(codec, 0x80, 0x0d, tmp); 7406 dspio_set_uint_param(codec, 0x80, 0x0e, tmp); 7407 7408 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f); 7409 ca0113_mmio_gpio_set(codec, 0, false); 7410 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00); 7411 7412 /* Internal loopback off */ 7413 tmp = FLOAT_ONE; 7414 dspio_set_uint_param(codec, 0x37, 0x08, tmp); 7415 dspio_set_uint_param(codec, 0x37, 0x10, tmp); 7416 7417 /*remove DSP headroom*/ 7418 tmp = FLOAT_ZERO; 7419 dspio_set_uint_param(codec, 0x96, 0x3C, tmp); 7420 7421 /* set WUH source */ 7422 tmp = FLOAT_TWO; 7423 dspio_set_uint_param(codec, 0x31, 0x00, tmp); 7424 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7425 7426 /* Set speaker source? */ 7427 dspio_set_uint_param(codec, 0x32, 0x00, tmp); 7428 7429 ca0132_alt_dsp_initial_mic_setup(codec); 7430 ae5_post_dsp_register_set(codec); 7431 ae5_post_dsp_param_setup(codec); 7432 ae5_post_dsp_pll_setup(codec); 7433 ae5_post_dsp_stream_setup(codec); 7434 ae5_post_dsp_startup_data(codec); 7435 7436 /* out, in effects + voicefx */ 7437 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1; 7438 for (idx = 0; idx < num_fx; idx++) { 7439 for (i = 0; i <= ca0132_effects[idx].params; i++) { 7440 dspio_set_uint_param(codec, 7441 ca0132_effects[idx].mid, 7442 ca0132_effects[idx].reqs[i], 7443 ca0132_effects[idx].def_vals[i]); 7444 } 7445 } 7446 7447 ca0132_alt_create_dummy_stream(codec); 7448 } 7449 7450 /* 7451 * Initialization of flags in chip 7452 */ 7453 static void ca0132_init_flags(struct hda_codec *codec) 7454 { 7455 struct ca0132_spec *spec = codec->spec; 7456 7457 if (ca0132_use_alt_functions(spec)) { 7458 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1); 7459 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1); 7460 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1); 7461 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1); 7462 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1); 7463 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7464 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0); 7465 chipio_set_control_flag(codec, 7466 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7467 chipio_set_control_flag(codec, 7468 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1); 7469 } else { 7470 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0); 7471 chipio_set_control_flag(codec, 7472 CONTROL_FLAG_PORT_A_COMMON_MODE, 0); 7473 chipio_set_control_flag(codec, 7474 CONTROL_FLAG_PORT_D_COMMON_MODE, 0); 7475 chipio_set_control_flag(codec, 7476 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0); 7477 chipio_set_control_flag(codec, 7478 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0); 7479 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1); 7480 } 7481 } 7482 7483 /* 7484 * Initialization of parameters in chip 7485 */ 7486 static void ca0132_init_params(struct hda_codec *codec) 7487 { 7488 struct ca0132_spec *spec = codec->spec; 7489 7490 if (ca0132_use_alt_functions(spec)) { 7491 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7492 chipio_set_conn_rate(codec, 0x0B, SR_48_000); 7493 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0); 7494 chipio_set_control_param(codec, 0, 0); 7495 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0); 7496 } 7497 7498 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6); 7499 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6); 7500 } 7501 7502 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k) 7503 { 7504 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k); 7505 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k); 7506 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k); 7507 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k); 7508 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k); 7509 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k); 7510 7511 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000); 7512 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000); 7513 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000); 7514 } 7515 7516 static bool ca0132_download_dsp_images(struct hda_codec *codec) 7517 { 7518 bool dsp_loaded = false; 7519 struct ca0132_spec *spec = codec->spec; 7520 const struct dsp_image_seg *dsp_os_image; 7521 const struct firmware *fw_entry; 7522 /* 7523 * Alternate firmwares for different variants. The Recon3Di apparently 7524 * can use the default firmware, but I'll leave the option in case 7525 * it needs it again. 7526 */ 7527 switch (ca0132_quirk(spec)) { 7528 case QUIRK_SBZ: 7529 case QUIRK_R3D: 7530 case QUIRK_AE5: 7531 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE, 7532 codec->card->dev) != 0) { 7533 codec_dbg(codec, "Desktop firmware not found."); 7534 spec->alt_firmware_present = false; 7535 } else { 7536 codec_dbg(codec, "Desktop firmware selected."); 7537 spec->alt_firmware_present = true; 7538 } 7539 break; 7540 case QUIRK_R3DI: 7541 if (request_firmware(&fw_entry, R3DI_EFX_FILE, 7542 codec->card->dev) != 0) { 7543 codec_dbg(codec, "Recon3Di alt firmware not detected."); 7544 spec->alt_firmware_present = false; 7545 } else { 7546 codec_dbg(codec, "Recon3Di firmware selected."); 7547 spec->alt_firmware_present = true; 7548 } 7549 break; 7550 default: 7551 spec->alt_firmware_present = false; 7552 break; 7553 } 7554 /* 7555 * Use default ctefx.bin if no alt firmware is detected, or if none 7556 * exists for your particular codec. 7557 */ 7558 if (!spec->alt_firmware_present) { 7559 codec_dbg(codec, "Default firmware selected."); 7560 if (request_firmware(&fw_entry, EFX_FILE, 7561 codec->card->dev) != 0) 7562 return false; 7563 } 7564 7565 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data); 7566 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) { 7567 codec_err(codec, "ca0132 DSP load image failed\n"); 7568 goto exit_download; 7569 } 7570 7571 dsp_loaded = dspload_wait_loaded(codec); 7572 7573 exit_download: 7574 release_firmware(fw_entry); 7575 7576 return dsp_loaded; 7577 } 7578 7579 static void ca0132_download_dsp(struct hda_codec *codec) 7580 { 7581 struct ca0132_spec *spec = codec->spec; 7582 7583 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP 7584 return; /* NOP */ 7585 #endif 7586 7587 if (spec->dsp_state == DSP_DOWNLOAD_FAILED) 7588 return; /* don't retry failures */ 7589 7590 chipio_enable_clocks(codec); 7591 if (spec->dsp_state != DSP_DOWNLOADED) { 7592 spec->dsp_state = DSP_DOWNLOADING; 7593 7594 if (!ca0132_download_dsp_images(codec)) 7595 spec->dsp_state = DSP_DOWNLOAD_FAILED; 7596 else 7597 spec->dsp_state = DSP_DOWNLOADED; 7598 } 7599 7600 /* For codecs using alt functions, this is already done earlier */ 7601 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec)) 7602 ca0132_set_dsp_msr(codec, true); 7603 } 7604 7605 static void ca0132_process_dsp_response(struct hda_codec *codec, 7606 struct hda_jack_callback *callback) 7607 { 7608 struct ca0132_spec *spec = codec->spec; 7609 7610 codec_dbg(codec, "ca0132_process_dsp_response\n"); 7611 if (spec->wait_scp) { 7612 if (dspio_get_response_data(codec) >= 0) 7613 spec->wait_scp = 0; 7614 } 7615 7616 dspio_clear_response_queue(codec); 7617 } 7618 7619 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7620 { 7621 struct ca0132_spec *spec = codec->spec; 7622 struct hda_jack_tbl *tbl; 7623 7624 /* Delay enabling the HP amp, to let the mic-detection 7625 * state machine run. 7626 */ 7627 cancel_delayed_work_sync(&spec->unsol_hp_work); 7628 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500)); 7629 tbl = snd_hda_jack_tbl_get(codec, cb->nid); 7630 if (tbl) 7631 tbl->block_report = 1; 7632 } 7633 7634 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb) 7635 { 7636 struct ca0132_spec *spec = codec->spec; 7637 7638 if (ca0132_use_alt_functions(spec)) 7639 ca0132_alt_select_in(codec); 7640 else 7641 ca0132_select_mic(codec); 7642 } 7643 7644 static void ca0132_init_unsol(struct hda_codec *codec) 7645 { 7646 struct ca0132_spec *spec = codec->spec; 7647 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback); 7648 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1, 7649 amic_callback); 7650 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP, 7651 ca0132_process_dsp_response); 7652 /* Front headphone jack detection */ 7653 if (ca0132_use_alt_functions(spec)) 7654 snd_hda_jack_detect_enable_callback(codec, 7655 spec->unsol_tag_front_hp, hp_callback); 7656 } 7657 7658 /* 7659 * Verbs tables. 7660 */ 7661 7662 /* Sends before DSP download. */ 7663 static struct hda_verb ca0132_base_init_verbs[] = { 7664 /*enable ct extension*/ 7665 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1}, 7666 {} 7667 }; 7668 7669 /* Send at exit. */ 7670 static struct hda_verb ca0132_base_exit_verbs[] = { 7671 /*set afg to D3*/ 7672 {0x01, AC_VERB_SET_POWER_STATE, 0x03}, 7673 /*disable ct extension*/ 7674 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0}, 7675 {} 7676 }; 7677 7678 /* Other verbs tables. Sends after DSP download. */ 7679 7680 static struct hda_verb ca0132_init_verbs0[] = { 7681 /* chip init verbs */ 7682 {0x15, 0x70D, 0xF0}, 7683 {0x15, 0x70E, 0xFE}, 7684 {0x15, 0x707, 0x75}, 7685 {0x15, 0x707, 0xD3}, 7686 {0x15, 0x707, 0x09}, 7687 {0x15, 0x707, 0x53}, 7688 {0x15, 0x707, 0xD4}, 7689 {0x15, 0x707, 0xEF}, 7690 {0x15, 0x707, 0x75}, 7691 {0x15, 0x707, 0xD3}, 7692 {0x15, 0x707, 0x09}, 7693 {0x15, 0x707, 0x02}, 7694 {0x15, 0x707, 0x37}, 7695 {0x15, 0x707, 0x78}, 7696 {0x15, 0x53C, 0xCE}, 7697 {0x15, 0x575, 0xC9}, 7698 {0x15, 0x53D, 0xCE}, 7699 {0x15, 0x5B7, 0xC9}, 7700 {0x15, 0x70D, 0xE8}, 7701 {0x15, 0x70E, 0xFE}, 7702 {0x15, 0x707, 0x02}, 7703 {0x15, 0x707, 0x68}, 7704 {0x15, 0x707, 0x62}, 7705 {0x15, 0x53A, 0xCE}, 7706 {0x15, 0x546, 0xC9}, 7707 {0x15, 0x53B, 0xCE}, 7708 {0x15, 0x5E8, 0xC9}, 7709 {} 7710 }; 7711 7712 /* Extra init verbs for desktop cards. */ 7713 static struct hda_verb ca0132_init_verbs1[] = { 7714 {0x15, 0x70D, 0x20}, 7715 {0x15, 0x70E, 0x19}, 7716 {0x15, 0x707, 0x00}, 7717 {0x15, 0x539, 0xCE}, 7718 {0x15, 0x546, 0xC9}, 7719 {0x15, 0x70D, 0xB7}, 7720 {0x15, 0x70E, 0x09}, 7721 {0x15, 0x707, 0x10}, 7722 {0x15, 0x70D, 0xAF}, 7723 {0x15, 0x70E, 0x09}, 7724 {0x15, 0x707, 0x01}, 7725 {0x15, 0x707, 0x05}, 7726 {0x15, 0x70D, 0x73}, 7727 {0x15, 0x70E, 0x09}, 7728 {0x15, 0x707, 0x14}, 7729 {0x15, 0x6FF, 0xC4}, 7730 {} 7731 }; 7732 7733 static void ca0132_init_chip(struct hda_codec *codec) 7734 { 7735 struct ca0132_spec *spec = codec->spec; 7736 int num_fx; 7737 int i; 7738 unsigned int on; 7739 7740 mutex_init(&spec->chipio_mutex); 7741 7742 spec->cur_out_type = SPEAKER_OUT; 7743 if (!ca0132_use_alt_functions(spec)) 7744 spec->cur_mic_type = DIGITAL_MIC; 7745 else 7746 spec->cur_mic_type = REAR_MIC; 7747 7748 spec->cur_mic_boost = 0; 7749 7750 for (i = 0; i < VNODES_COUNT; i++) { 7751 spec->vnode_lvol[i] = 0x5a; 7752 spec->vnode_rvol[i] = 0x5a; 7753 spec->vnode_lswitch[i] = 0; 7754 spec->vnode_rswitch[i] = 0; 7755 } 7756 7757 /* 7758 * Default states for effects are in ca0132_effects[]. 7759 */ 7760 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT; 7761 for (i = 0; i < num_fx; i++) { 7762 on = (unsigned int)ca0132_effects[i].reqs[0]; 7763 spec->effects_switch[i] = on ? 1 : 0; 7764 } 7765 /* 7766 * Sets defaults for the effect slider controls, only for alternative 7767 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz. 7768 */ 7769 if (ca0132_use_alt_controls(spec)) { 7770 spec->xbass_xover_freq = 8; 7771 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++) 7772 spec->fx_ctl_val[i] = effect_slider_defaults[i]; 7773 } 7774 7775 spec->voicefx_val = 0; 7776 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1; 7777 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0; 7778 7779 /* 7780 * The ZxR doesn't have a front panel header, and it's line-in is on 7781 * the daughter board. So, there is no input enum control, and we need 7782 * to make sure that spec->in_enum_val is set properly. 7783 */ 7784 if (ca0132_quirk(spec) == QUIRK_ZXR) 7785 spec->in_enum_val = REAR_MIC; 7786 7787 #ifdef ENABLE_TUNING_CONTROLS 7788 ca0132_init_tuning_defaults(codec); 7789 #endif 7790 } 7791 7792 /* 7793 * Recon3Di exit specific commands. 7794 */ 7795 /* prevents popping noise on shutdown */ 7796 static void r3di_gpio_shutdown(struct hda_codec *codec) 7797 { 7798 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00); 7799 } 7800 7801 /* 7802 * Sound Blaster Z exit specific commands. 7803 */ 7804 static void sbz_region2_exit(struct hda_codec *codec) 7805 { 7806 struct ca0132_spec *spec = codec->spec; 7807 unsigned int i; 7808 7809 for (i = 0; i < 4; i++) 7810 writeb(0x0, spec->mem_base + 0x100); 7811 for (i = 0; i < 8; i++) 7812 writeb(0xb3, spec->mem_base + 0x304); 7813 7814 ca0113_mmio_gpio_set(codec, 0, false); 7815 ca0113_mmio_gpio_set(codec, 1, false); 7816 ca0113_mmio_gpio_set(codec, 4, true); 7817 ca0113_mmio_gpio_set(codec, 5, false); 7818 ca0113_mmio_gpio_set(codec, 7, false); 7819 } 7820 7821 static void sbz_set_pin_ctl_default(struct hda_codec *codec) 7822 { 7823 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13}; 7824 unsigned int i; 7825 7826 snd_hda_codec_write(codec, 0x11, 0, 7827 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40); 7828 7829 for (i = 0; i < 5; i++) 7830 snd_hda_codec_write(codec, pins[i], 0, 7831 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00); 7832 } 7833 7834 static void ca0132_clear_unsolicited(struct hda_codec *codec) 7835 { 7836 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13}; 7837 unsigned int i; 7838 7839 for (i = 0; i < 7; i++) { 7840 snd_hda_codec_write(codec, pins[i], 0, 7841 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00); 7842 } 7843 } 7844 7845 /* On shutdown, sends commands in sets of three */ 7846 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir, 7847 int mask, int data) 7848 { 7849 if (dir >= 0) 7850 snd_hda_codec_write(codec, 0x01, 0, 7851 AC_VERB_SET_GPIO_DIRECTION, dir); 7852 if (mask >= 0) 7853 snd_hda_codec_write(codec, 0x01, 0, 7854 AC_VERB_SET_GPIO_MASK, mask); 7855 7856 if (data >= 0) 7857 snd_hda_codec_write(codec, 0x01, 0, 7858 AC_VERB_SET_GPIO_DATA, data); 7859 } 7860 7861 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec) 7862 { 7863 hda_nid_t pins[7] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01}; 7864 unsigned int i; 7865 7866 for (i = 0; i < 7; i++) 7867 snd_hda_codec_write(codec, pins[i], 0, 7868 AC_VERB_SET_POWER_STATE, 0x03); 7869 } 7870 7871 static void sbz_exit_chip(struct hda_codec *codec) 7872 { 7873 chipio_set_stream_control(codec, 0x03, 0); 7874 chipio_set_stream_control(codec, 0x04, 0); 7875 7876 /* Mess with GPIO */ 7877 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1); 7878 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05); 7879 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01); 7880 7881 chipio_set_stream_control(codec, 0x14, 0); 7882 chipio_set_stream_control(codec, 0x0C, 0); 7883 7884 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7885 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7886 7887 chipio_write(codec, 0x18a020, 0x00000083); 7888 7889 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03); 7890 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07); 7891 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06); 7892 7893 chipio_set_stream_control(codec, 0x0C, 0); 7894 7895 chipio_set_control_param(codec, 0x0D, 0x24); 7896 7897 ca0132_clear_unsolicited(codec); 7898 sbz_set_pin_ctl_default(codec); 7899 7900 snd_hda_codec_write(codec, 0x0B, 0, 7901 AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7902 7903 sbz_region2_exit(codec); 7904 } 7905 7906 static void r3d_exit_chip(struct hda_codec *codec) 7907 { 7908 ca0132_clear_unsolicited(codec); 7909 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7910 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b); 7911 } 7912 7913 static void ae5_exit_chip(struct hda_codec *codec) 7914 { 7915 chipio_set_stream_control(codec, 0x03, 0); 7916 chipio_set_stream_control(codec, 0x04, 0); 7917 7918 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 7919 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7920 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 7921 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00); 7922 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00); 7923 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00); 7924 ca0113_mmio_gpio_set(codec, 0, false); 7925 ca0113_mmio_gpio_set(codec, 1, false); 7926 7927 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7928 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7929 7930 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0); 7931 7932 chipio_set_stream_control(codec, 0x18, 0); 7933 chipio_set_stream_control(codec, 0x0c, 0); 7934 7935 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83); 7936 } 7937 7938 static void zxr_exit_chip(struct hda_codec *codec) 7939 { 7940 chipio_set_stream_control(codec, 0x03, 0); 7941 chipio_set_stream_control(codec, 0x04, 0); 7942 chipio_set_stream_control(codec, 0x14, 0); 7943 chipio_set_stream_control(codec, 0x0C, 0); 7944 7945 chipio_set_conn_rate(codec, 0x41, SR_192_000); 7946 chipio_set_conn_rate(codec, 0x91, SR_192_000); 7947 7948 chipio_write(codec, 0x18a020, 0x00000083); 7949 7950 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00); 7951 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53); 7952 7953 ca0132_clear_unsolicited(codec); 7954 sbz_set_pin_ctl_default(codec); 7955 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00); 7956 7957 ca0113_mmio_gpio_set(codec, 5, false); 7958 ca0113_mmio_gpio_set(codec, 2, false); 7959 ca0113_mmio_gpio_set(codec, 3, false); 7960 ca0113_mmio_gpio_set(codec, 0, false); 7961 ca0113_mmio_gpio_set(codec, 4, true); 7962 ca0113_mmio_gpio_set(codec, 0, true); 7963 ca0113_mmio_gpio_set(codec, 5, true); 7964 ca0113_mmio_gpio_set(codec, 2, false); 7965 ca0113_mmio_gpio_set(codec, 3, false); 7966 } 7967 7968 static void ca0132_exit_chip(struct hda_codec *codec) 7969 { 7970 /* put any chip cleanup stuffs here. */ 7971 7972 if (dspload_is_loaded(codec)) 7973 dsp_reset(codec); 7974 } 7975 7976 /* 7977 * This fixes a problem that was hard to reproduce. Very rarely, I would 7978 * boot up, and there would be no sound, but the DSP indicated it had loaded 7979 * properly. I did a few memory dumps to see if anything was different, and 7980 * there were a few areas of memory uninitialized with a1a2a3a4. This function 7981 * checks if those areas are uninitialized, and if they are, it'll attempt to 7982 * reload the card 3 times. Usually it fixes by the second. 7983 */ 7984 static void sbz_dsp_startup_check(struct hda_codec *codec) 7985 { 7986 struct ca0132_spec *spec = codec->spec; 7987 unsigned int dsp_data_check[4]; 7988 unsigned int cur_address = 0x390; 7989 unsigned int i; 7990 unsigned int failure = 0; 7991 unsigned int reload = 3; 7992 7993 if (spec->startup_check_entered) 7994 return; 7995 7996 spec->startup_check_entered = true; 7997 7998 for (i = 0; i < 4; i++) { 7999 chipio_read(codec, cur_address, &dsp_data_check[i]); 8000 cur_address += 0x4; 8001 } 8002 for (i = 0; i < 4; i++) { 8003 if (dsp_data_check[i] == 0xa1a2a3a4) 8004 failure = 1; 8005 } 8006 8007 codec_dbg(codec, "Startup Check: %d ", failure); 8008 if (failure) 8009 codec_info(codec, "DSP not initialized properly. Attempting to fix."); 8010 /* 8011 * While the failure condition is true, and we haven't reached our 8012 * three reload limit, continue trying to reload the driver and 8013 * fix the issue. 8014 */ 8015 while (failure && (reload != 0)) { 8016 codec_info(codec, "Reloading... Tries left: %d", reload); 8017 sbz_exit_chip(codec); 8018 spec->dsp_state = DSP_DOWNLOAD_INIT; 8019 codec->patch_ops.init(codec); 8020 failure = 0; 8021 for (i = 0; i < 4; i++) { 8022 chipio_read(codec, cur_address, &dsp_data_check[i]); 8023 cur_address += 0x4; 8024 } 8025 for (i = 0; i < 4; i++) { 8026 if (dsp_data_check[i] == 0xa1a2a3a4) 8027 failure = 1; 8028 } 8029 reload--; 8030 } 8031 8032 if (!failure && reload < 3) 8033 codec_info(codec, "DSP fixed."); 8034 8035 if (!failure) 8036 return; 8037 8038 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory."); 8039 } 8040 8041 /* 8042 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add 8043 * extra precision for decibel values. If you had the dB value in floating point 8044 * you would take the value after the decimal point, multiply by 64, and divide 8045 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to 8046 * implement fixed point or floating point dB volumes. For now, I'll set them 8047 * to 0 just incase a value has lingered from a boot into Windows. 8048 */ 8049 static void ca0132_alt_vol_setup(struct hda_codec *codec) 8050 { 8051 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00); 8052 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00); 8053 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00); 8054 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00); 8055 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00); 8056 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00); 8057 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00); 8058 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00); 8059 } 8060 8061 /* 8062 * Extra commands that don't really fit anywhere else. 8063 */ 8064 static void sbz_pre_dsp_setup(struct hda_codec *codec) 8065 { 8066 struct ca0132_spec *spec = codec->spec; 8067 8068 writel(0x00820680, spec->mem_base + 0x01C); 8069 writel(0x00820680, spec->mem_base + 0x01C); 8070 8071 chipio_write(codec, 0x18b0a4, 0x000000c2); 8072 8073 snd_hda_codec_write(codec, 0x11, 0, 8074 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8075 } 8076 8077 static void r3d_pre_dsp_setup(struct hda_codec *codec) 8078 { 8079 chipio_write(codec, 0x18b0a4, 0x000000c2); 8080 8081 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8082 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8083 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8084 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8085 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8086 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8087 8088 snd_hda_codec_write(codec, 0x11, 0, 8089 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44); 8090 } 8091 8092 static void r3di_pre_dsp_setup(struct hda_codec *codec) 8093 { 8094 chipio_write(codec, 0x18b0a4, 0x000000c2); 8095 8096 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8097 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E); 8098 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8099 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C); 8100 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8101 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B); 8102 8103 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8104 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20); 8105 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8106 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19); 8107 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8108 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00); 8109 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8110 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40); 8111 8112 snd_hda_codec_write(codec, 0x11, 0, 8113 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04); 8114 } 8115 8116 /* 8117 * These are sent before the DSP is downloaded. Not sure 8118 * what they do, or if they're necessary. Could possibly 8119 * be removed. Figure they're better to leave in. 8120 */ 8121 static void ca0132_mmio_init(struct hda_codec *codec) 8122 { 8123 struct ca0132_spec *spec = codec->spec; 8124 8125 if (ca0132_quirk(spec) == QUIRK_AE5) 8126 writel(0x00000001, spec->mem_base + 0x400); 8127 else 8128 writel(0x00000000, spec->mem_base + 0x400); 8129 8130 if (ca0132_quirk(spec) == QUIRK_AE5) 8131 writel(0x00000001, spec->mem_base + 0x408); 8132 else 8133 writel(0x00000000, spec->mem_base + 0x408); 8134 8135 if (ca0132_quirk(spec) == QUIRK_AE5) 8136 writel(0x00000001, spec->mem_base + 0x40c); 8137 else 8138 writel(0x00000000, spec->mem_base + 0x40C); 8139 8140 if (ca0132_quirk(spec) == QUIRK_ZXR) 8141 writel(0x00880640, spec->mem_base + 0x01C); 8142 else 8143 writel(0x00880680, spec->mem_base + 0x01C); 8144 8145 if (ca0132_quirk(spec) == QUIRK_AE5) 8146 writel(0x00000080, spec->mem_base + 0xC0C); 8147 else 8148 writel(0x00000083, spec->mem_base + 0xC0C); 8149 8150 writel(0x00000030, spec->mem_base + 0xC00); 8151 writel(0x00000000, spec->mem_base + 0xC04); 8152 8153 if (ca0132_quirk(spec) == QUIRK_AE5) 8154 writel(0x00000000, spec->mem_base + 0xC0C); 8155 else 8156 writel(0x00000003, spec->mem_base + 0xC0C); 8157 8158 writel(0x00000003, spec->mem_base + 0xC0C); 8159 writel(0x00000003, spec->mem_base + 0xC0C); 8160 writel(0x00000003, spec->mem_base + 0xC0C); 8161 8162 if (ca0132_quirk(spec) == QUIRK_AE5) 8163 writel(0x00000001, spec->mem_base + 0xC08); 8164 else 8165 writel(0x000000C1, spec->mem_base + 0xC08); 8166 8167 writel(0x000000F1, spec->mem_base + 0xC08); 8168 writel(0x00000001, spec->mem_base + 0xC08); 8169 writel(0x000000C7, spec->mem_base + 0xC08); 8170 writel(0x000000C1, spec->mem_base + 0xC08); 8171 writel(0x00000080, spec->mem_base + 0xC04); 8172 8173 if (ca0132_quirk(spec) == QUIRK_AE5) { 8174 writel(0x00000000, spec->mem_base + 0x42c); 8175 writel(0x00000000, spec->mem_base + 0x46c); 8176 writel(0x00000000, spec->mem_base + 0x4ac); 8177 writel(0x00000000, spec->mem_base + 0x4ec); 8178 writel(0x00000000, spec->mem_base + 0x43c); 8179 writel(0x00000000, spec->mem_base + 0x47c); 8180 writel(0x00000000, spec->mem_base + 0x4bc); 8181 writel(0x00000000, spec->mem_base + 0x4fc); 8182 writel(0x00000600, spec->mem_base + 0x100); 8183 writel(0x00000014, spec->mem_base + 0x410); 8184 writel(0x0000060f, spec->mem_base + 0x100); 8185 writel(0x0000070f, spec->mem_base + 0x100); 8186 writel(0x00000aff, spec->mem_base + 0x830); 8187 writel(0x00000000, spec->mem_base + 0x86c); 8188 writel(0x0000006b, spec->mem_base + 0x800); 8189 writel(0x00000001, spec->mem_base + 0x86c); 8190 writel(0x0000006b, spec->mem_base + 0x800); 8191 writel(0x00000057, spec->mem_base + 0x804); 8192 writel(0x00800000, spec->mem_base + 0x20c); 8193 } 8194 } 8195 8196 /* 8197 * This function writes to some SFR's, does some region2 writes, and then 8198 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does 8199 * what it does. 8200 */ 8201 static void ae5_register_set(struct hda_codec *codec) 8202 { 8203 struct ca0132_spec *spec = codec->spec; 8204 8205 chipio_8051_write_direct(codec, 0x93, 0x10); 8206 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8207 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44); 8208 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8209 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2); 8210 8211 writeb(0x0f, spec->mem_base + 0x304); 8212 writeb(0x0f, spec->mem_base + 0x304); 8213 writeb(0x0f, spec->mem_base + 0x304); 8214 writeb(0x0f, spec->mem_base + 0x304); 8215 writeb(0x0e, spec->mem_base + 0x100); 8216 writeb(0x1f, spec->mem_base + 0x304); 8217 writeb(0x0c, spec->mem_base + 0x100); 8218 writeb(0x3f, spec->mem_base + 0x304); 8219 writeb(0x08, spec->mem_base + 0x100); 8220 writeb(0x7f, spec->mem_base + 0x304); 8221 writeb(0x00, spec->mem_base + 0x100); 8222 writeb(0xff, spec->mem_base + 0x304); 8223 8224 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f); 8225 8226 chipio_8051_write_direct(codec, 0x90, 0x00); 8227 chipio_8051_write_direct(codec, 0x90, 0x10); 8228 8229 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83); 8230 8231 chipio_write(codec, 0x18b0a4, 0x000000c2); 8232 8233 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8234 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00); 8235 } 8236 8237 /* 8238 * Extra init functions for alternative ca0132 codecs. Done 8239 * here so they don't clutter up the main ca0132_init function 8240 * anymore than they have to. 8241 */ 8242 static void ca0132_alt_init(struct hda_codec *codec) 8243 { 8244 struct ca0132_spec *spec = codec->spec; 8245 8246 ca0132_alt_vol_setup(codec); 8247 8248 switch (ca0132_quirk(spec)) { 8249 case QUIRK_SBZ: 8250 codec_dbg(codec, "SBZ alt_init"); 8251 ca0132_gpio_init(codec); 8252 sbz_pre_dsp_setup(codec); 8253 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8254 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8255 break; 8256 case QUIRK_R3DI: 8257 codec_dbg(codec, "R3DI alt_init"); 8258 ca0132_gpio_init(codec); 8259 ca0132_gpio_setup(codec); 8260 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING); 8261 r3di_pre_dsp_setup(codec); 8262 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8263 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4); 8264 break; 8265 case QUIRK_R3D: 8266 r3d_pre_dsp_setup(codec); 8267 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8268 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8269 break; 8270 case QUIRK_AE5: 8271 ca0132_gpio_init(codec); 8272 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8273 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49); 8274 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8275 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88); 8276 chipio_write(codec, 0x18b030, 0x00000020); 8277 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8278 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8279 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f); 8280 break; 8281 case QUIRK_ZXR: 8282 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8283 snd_hda_sequence_write(codec, spec->desktop_init_verbs); 8284 break; 8285 default: 8286 break; 8287 } 8288 } 8289 8290 static int ca0132_init(struct hda_codec *codec) 8291 { 8292 struct ca0132_spec *spec = codec->spec; 8293 struct auto_pin_cfg *cfg = &spec->autocfg; 8294 int i; 8295 bool dsp_loaded; 8296 8297 /* 8298 * If the DSP is already downloaded, and init has been entered again, 8299 * there's only two reasons for it. One, the codec has awaken from a 8300 * suspended state, and in that case dspload_is_loaded will return 8301 * false, and the init will be ran again. The other reason it gets 8302 * re entered is on startup for some reason it triggers a suspend and 8303 * resume state. In this case, it will check if the DSP is downloaded, 8304 * and not run the init function again. For codecs using alt_functions, 8305 * it will check if the DSP is loaded properly. 8306 */ 8307 if (spec->dsp_state == DSP_DOWNLOADED) { 8308 dsp_loaded = dspload_is_loaded(codec); 8309 if (!dsp_loaded) { 8310 spec->dsp_reload = true; 8311 spec->dsp_state = DSP_DOWNLOAD_INIT; 8312 } else { 8313 if (ca0132_quirk(spec) == QUIRK_SBZ) 8314 sbz_dsp_startup_check(codec); 8315 return 0; 8316 } 8317 } 8318 8319 if (spec->dsp_state != DSP_DOWNLOAD_FAILED) 8320 spec->dsp_state = DSP_DOWNLOAD_INIT; 8321 spec->curr_chip_addx = INVALID_CHIP_ADDRESS; 8322 8323 if (ca0132_use_pci_mmio(spec)) 8324 ca0132_mmio_init(codec); 8325 8326 snd_hda_power_up_pm(codec); 8327 8328 if (ca0132_quirk(spec) == QUIRK_AE5) 8329 ae5_register_set(codec); 8330 8331 ca0132_init_unsol(codec); 8332 ca0132_init_params(codec); 8333 ca0132_init_flags(codec); 8334 8335 snd_hda_sequence_write(codec, spec->base_init_verbs); 8336 8337 if (ca0132_use_alt_functions(spec)) 8338 ca0132_alt_init(codec); 8339 8340 ca0132_download_dsp(codec); 8341 8342 ca0132_refresh_widget_caps(codec); 8343 8344 switch (ca0132_quirk(spec)) { 8345 case QUIRK_R3DI: 8346 case QUIRK_R3D: 8347 r3d_setup_defaults(codec); 8348 break; 8349 case QUIRK_SBZ: 8350 case QUIRK_ZXR: 8351 sbz_setup_defaults(codec); 8352 break; 8353 case QUIRK_AE5: 8354 ae5_setup_defaults(codec); 8355 break; 8356 default: 8357 ca0132_setup_defaults(codec); 8358 ca0132_init_analog_mic2(codec); 8359 ca0132_init_dmic(codec); 8360 break; 8361 } 8362 8363 for (i = 0; i < spec->num_outputs; i++) 8364 init_output(codec, spec->out_pins[i], spec->dacs[0]); 8365 8366 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8367 8368 for (i = 0; i < spec->num_inputs; i++) 8369 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8370 8371 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8372 8373 if (!ca0132_use_alt_functions(spec)) { 8374 snd_hda_sequence_write(codec, spec->chip_init_verbs); 8375 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8376 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D); 8377 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 8378 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20); 8379 } 8380 8381 if (ca0132_quirk(spec) == QUIRK_SBZ) 8382 ca0132_gpio_setup(codec); 8383 8384 snd_hda_sequence_write(codec, spec->spec_init_verbs); 8385 if (ca0132_use_alt_functions(spec)) { 8386 ca0132_alt_select_out(codec); 8387 ca0132_alt_select_in(codec); 8388 } else { 8389 ca0132_select_out(codec); 8390 ca0132_select_mic(codec); 8391 } 8392 8393 snd_hda_jack_report_sync(codec); 8394 8395 /* 8396 * Re set the PlayEnhancement switch on a resume event, because the 8397 * controls will not be reloaded. 8398 */ 8399 if (spec->dsp_reload) { 8400 spec->dsp_reload = false; 8401 ca0132_pe_switch_set(codec); 8402 } 8403 8404 snd_hda_power_down_pm(codec); 8405 8406 return 0; 8407 } 8408 8409 static int dbpro_init(struct hda_codec *codec) 8410 { 8411 struct ca0132_spec *spec = codec->spec; 8412 struct auto_pin_cfg *cfg = &spec->autocfg; 8413 unsigned int i; 8414 8415 init_output(codec, cfg->dig_out_pins[0], spec->dig_out); 8416 init_input(codec, cfg->dig_in_pin, spec->dig_in); 8417 8418 for (i = 0; i < spec->num_inputs; i++) 8419 init_input(codec, spec->input_pins[i], spec->adcs[i]); 8420 8421 return 0; 8422 } 8423 8424 static void ca0132_free(struct hda_codec *codec) 8425 { 8426 struct ca0132_spec *spec = codec->spec; 8427 8428 cancel_delayed_work_sync(&spec->unsol_hp_work); 8429 snd_hda_power_up(codec); 8430 switch (ca0132_quirk(spec)) { 8431 case QUIRK_SBZ: 8432 sbz_exit_chip(codec); 8433 break; 8434 case QUIRK_ZXR: 8435 zxr_exit_chip(codec); 8436 break; 8437 case QUIRK_R3D: 8438 r3d_exit_chip(codec); 8439 break; 8440 case QUIRK_AE5: 8441 ae5_exit_chip(codec); 8442 break; 8443 case QUIRK_R3DI: 8444 r3di_gpio_shutdown(codec); 8445 break; 8446 default: 8447 break; 8448 } 8449 8450 snd_hda_sequence_write(codec, spec->base_exit_verbs); 8451 ca0132_exit_chip(codec); 8452 8453 snd_hda_power_down(codec); 8454 #ifdef CONFIG_PCI 8455 if (spec->mem_base) 8456 pci_iounmap(codec->bus->pci, spec->mem_base); 8457 #endif 8458 kfree(spec->spec_init_verbs); 8459 kfree(codec->spec); 8460 } 8461 8462 static void dbpro_free(struct hda_codec *codec) 8463 { 8464 struct ca0132_spec *spec = codec->spec; 8465 8466 zxr_dbpro_power_state_shutdown(codec); 8467 8468 kfree(spec->spec_init_verbs); 8469 kfree(codec->spec); 8470 } 8471 8472 static void ca0132_reboot_notify(struct hda_codec *codec) 8473 { 8474 codec->patch_ops.free(codec); 8475 } 8476 8477 static const struct hda_codec_ops ca0132_patch_ops = { 8478 .build_controls = ca0132_build_controls, 8479 .build_pcms = ca0132_build_pcms, 8480 .init = ca0132_init, 8481 .free = ca0132_free, 8482 .unsol_event = snd_hda_jack_unsol_event, 8483 .reboot_notify = ca0132_reboot_notify, 8484 }; 8485 8486 static const struct hda_codec_ops dbpro_patch_ops = { 8487 .build_controls = dbpro_build_controls, 8488 .build_pcms = dbpro_build_pcms, 8489 .init = dbpro_init, 8490 .free = dbpro_free, 8491 }; 8492 8493 static void ca0132_config(struct hda_codec *codec) 8494 { 8495 struct ca0132_spec *spec = codec->spec; 8496 8497 spec->dacs[0] = 0x2; 8498 spec->dacs[1] = 0x3; 8499 spec->dacs[2] = 0x4; 8500 8501 spec->multiout.dac_nids = spec->dacs; 8502 spec->multiout.num_dacs = 3; 8503 8504 if (!ca0132_use_alt_functions(spec)) 8505 spec->multiout.max_channels = 2; 8506 else 8507 spec->multiout.max_channels = 6; 8508 8509 switch (ca0132_quirk(spec)) { 8510 case QUIRK_ALIENWARE: 8511 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__); 8512 snd_hda_apply_pincfgs(codec, alienware_pincfgs); 8513 break; 8514 case QUIRK_SBZ: 8515 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__); 8516 snd_hda_apply_pincfgs(codec, sbz_pincfgs); 8517 break; 8518 case QUIRK_ZXR: 8519 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__); 8520 snd_hda_apply_pincfgs(codec, zxr_pincfgs); 8521 break; 8522 case QUIRK_R3D: 8523 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__); 8524 snd_hda_apply_pincfgs(codec, r3d_pincfgs); 8525 break; 8526 case QUIRK_R3DI: 8527 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__); 8528 snd_hda_apply_pincfgs(codec, r3di_pincfgs); 8529 break; 8530 case QUIRK_AE5: 8531 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__); 8532 snd_hda_apply_pincfgs(codec, ae5_pincfgs); 8533 break; 8534 default: 8535 break; 8536 } 8537 8538 switch (ca0132_quirk(spec)) { 8539 case QUIRK_ALIENWARE: 8540 spec->num_outputs = 2; 8541 spec->out_pins[0] = 0x0b; /* speaker out */ 8542 spec->out_pins[1] = 0x0f; 8543 spec->shared_out_nid = 0x2; 8544 spec->unsol_tag_hp = 0x0f; 8545 8546 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8547 spec->adcs[1] = 0x8; /* analog mic2 */ 8548 spec->adcs[2] = 0xa; /* what u hear */ 8549 8550 spec->num_inputs = 3; 8551 spec->input_pins[0] = 0x12; 8552 spec->input_pins[1] = 0x11; 8553 spec->input_pins[2] = 0x13; 8554 spec->shared_mic_nid = 0x7; 8555 spec->unsol_tag_amic1 = 0x11; 8556 break; 8557 case QUIRK_SBZ: 8558 case QUIRK_R3D: 8559 spec->num_outputs = 2; 8560 spec->out_pins[0] = 0x0B; /* Line out */ 8561 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8562 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8563 spec->out_pins[3] = 0x11; /* Rear surround */ 8564 spec->shared_out_nid = 0x2; 8565 spec->unsol_tag_hp = spec->out_pins[1]; 8566 spec->unsol_tag_front_hp = spec->out_pins[2]; 8567 8568 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8569 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8570 spec->adcs[2] = 0xa; /* what u hear */ 8571 8572 spec->num_inputs = 2; 8573 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8574 spec->input_pins[1] = 0x13; /* What U Hear */ 8575 spec->shared_mic_nid = 0x7; 8576 spec->unsol_tag_amic1 = spec->input_pins[0]; 8577 8578 /* SPDIF I/O */ 8579 spec->dig_out = 0x05; 8580 spec->multiout.dig_out_nid = spec->dig_out; 8581 spec->dig_in = 0x09; 8582 break; 8583 case QUIRK_ZXR: 8584 spec->num_outputs = 2; 8585 spec->out_pins[0] = 0x0B; /* Line out */ 8586 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8587 spec->out_pins[2] = 0x10; /* Center/LFE */ 8588 spec->out_pins[3] = 0x11; /* Rear surround */ 8589 spec->shared_out_nid = 0x2; 8590 spec->unsol_tag_hp = spec->out_pins[1]; 8591 spec->unsol_tag_front_hp = spec->out_pins[2]; 8592 8593 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8594 spec->adcs[1] = 0x8; /* Not connected, no front mic */ 8595 spec->adcs[2] = 0xa; /* what u hear */ 8596 8597 spec->num_inputs = 2; 8598 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8599 spec->input_pins[1] = 0x13; /* What U Hear */ 8600 spec->shared_mic_nid = 0x7; 8601 spec->unsol_tag_amic1 = spec->input_pins[0]; 8602 break; 8603 case QUIRK_ZXR_DBPRO: 8604 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */ 8605 8606 spec->num_inputs = 1; 8607 spec->input_pins[0] = 0x11; /* RCA Line-in */ 8608 8609 spec->dig_out = 0x05; 8610 spec->multiout.dig_out_nid = spec->dig_out; 8611 8612 spec->dig_in = 0x09; 8613 break; 8614 case QUIRK_AE5: 8615 spec->num_outputs = 2; 8616 spec->out_pins[0] = 0x0B; /* Line out */ 8617 spec->out_pins[1] = 0x11; /* Rear headphone out */ 8618 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8619 spec->out_pins[3] = 0x0F; /* Rear surround */ 8620 spec->shared_out_nid = 0x2; 8621 spec->unsol_tag_hp = spec->out_pins[1]; 8622 spec->unsol_tag_front_hp = spec->out_pins[2]; 8623 8624 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */ 8625 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */ 8626 spec->adcs[2] = 0xa; /* what u hear */ 8627 8628 spec->num_inputs = 2; 8629 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8630 spec->input_pins[1] = 0x13; /* What U Hear */ 8631 spec->shared_mic_nid = 0x7; 8632 spec->unsol_tag_amic1 = spec->input_pins[0]; 8633 8634 /* SPDIF I/O */ 8635 spec->dig_out = 0x05; 8636 spec->multiout.dig_out_nid = spec->dig_out; 8637 break; 8638 case QUIRK_R3DI: 8639 spec->num_outputs = 2; 8640 spec->out_pins[0] = 0x0B; /* Line out */ 8641 spec->out_pins[1] = 0x0F; /* Rear headphone out */ 8642 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/ 8643 spec->out_pins[3] = 0x11; /* Rear surround */ 8644 spec->shared_out_nid = 0x2; 8645 spec->unsol_tag_hp = spec->out_pins[1]; 8646 spec->unsol_tag_front_hp = spec->out_pins[2]; 8647 8648 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */ 8649 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */ 8650 spec->adcs[2] = 0x0a; /* what u hear */ 8651 8652 spec->num_inputs = 2; 8653 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */ 8654 spec->input_pins[1] = 0x13; /* What U Hear */ 8655 spec->shared_mic_nid = 0x7; 8656 spec->unsol_tag_amic1 = spec->input_pins[0]; 8657 8658 /* SPDIF I/O */ 8659 spec->dig_out = 0x05; 8660 spec->multiout.dig_out_nid = spec->dig_out; 8661 break; 8662 default: 8663 spec->num_outputs = 2; 8664 spec->out_pins[0] = 0x0b; /* speaker out */ 8665 spec->out_pins[1] = 0x10; /* headphone out */ 8666 spec->shared_out_nid = 0x2; 8667 spec->unsol_tag_hp = spec->out_pins[1]; 8668 8669 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */ 8670 spec->adcs[1] = 0x8; /* analog mic2 */ 8671 spec->adcs[2] = 0xa; /* what u hear */ 8672 8673 spec->num_inputs = 3; 8674 spec->input_pins[0] = 0x12; 8675 spec->input_pins[1] = 0x11; 8676 spec->input_pins[2] = 0x13; 8677 spec->shared_mic_nid = 0x7; 8678 spec->unsol_tag_amic1 = spec->input_pins[0]; 8679 8680 /* SPDIF I/O */ 8681 spec->dig_out = 0x05; 8682 spec->multiout.dig_out_nid = spec->dig_out; 8683 spec->dig_in = 0x09; 8684 break; 8685 } 8686 } 8687 8688 static int ca0132_prepare_verbs(struct hda_codec *codec) 8689 { 8690 /* Verbs + terminator (an empty element) */ 8691 #define NUM_SPEC_VERBS 2 8692 struct ca0132_spec *spec = codec->spec; 8693 8694 spec->chip_init_verbs = ca0132_init_verbs0; 8695 /* 8696 * Since desktop cards use pci_mmio, this can be used to determine 8697 * whether or not to use these verbs instead of a separate bool. 8698 */ 8699 if (ca0132_use_pci_mmio(spec)) 8700 spec->desktop_init_verbs = ca0132_init_verbs1; 8701 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS, 8702 sizeof(struct hda_verb), 8703 GFP_KERNEL); 8704 if (!spec->spec_init_verbs) 8705 return -ENOMEM; 8706 8707 /* config EAPD */ 8708 spec->spec_init_verbs[0].nid = 0x0b; 8709 spec->spec_init_verbs[0].param = 0x78D; 8710 spec->spec_init_verbs[0].verb = 0x00; 8711 8712 /* Previously commented configuration */ 8713 /* 8714 spec->spec_init_verbs[2].nid = 0x0b; 8715 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE; 8716 spec->spec_init_verbs[2].verb = 0x02; 8717 8718 spec->spec_init_verbs[3].nid = 0x10; 8719 spec->spec_init_verbs[3].param = 0x78D; 8720 spec->spec_init_verbs[3].verb = 0x02; 8721 8722 spec->spec_init_verbs[4].nid = 0x10; 8723 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE; 8724 spec->spec_init_verbs[4].verb = 0x02; 8725 */ 8726 8727 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */ 8728 return 0; 8729 } 8730 8731 /* 8732 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular 8733 * Sound Blaster Z cards. However, they have different HDA codec subsystem 8734 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro 8735 * daughter boards ID. 8736 */ 8737 static void sbz_detect_quirk(struct hda_codec *codec) 8738 { 8739 struct ca0132_spec *spec = codec->spec; 8740 8741 switch (codec->core.subsystem_id) { 8742 case 0x11020033: 8743 spec->quirk = QUIRK_ZXR; 8744 break; 8745 case 0x1102003f: 8746 spec->quirk = QUIRK_ZXR_DBPRO; 8747 break; 8748 default: 8749 spec->quirk = QUIRK_SBZ; 8750 break; 8751 } 8752 } 8753 8754 static int patch_ca0132(struct hda_codec *codec) 8755 { 8756 struct ca0132_spec *spec; 8757 int err; 8758 const struct snd_pci_quirk *quirk; 8759 8760 codec_dbg(codec, "patch_ca0132\n"); 8761 8762 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 8763 if (!spec) 8764 return -ENOMEM; 8765 codec->spec = spec; 8766 spec->codec = codec; 8767 8768 /* Detect codec quirk */ 8769 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks); 8770 if (quirk) 8771 spec->quirk = quirk->value; 8772 else 8773 spec->quirk = QUIRK_NONE; 8774 if (ca0132_quirk(spec) == QUIRK_SBZ) 8775 sbz_detect_quirk(codec); 8776 8777 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO) 8778 codec->patch_ops = dbpro_patch_ops; 8779 else 8780 codec->patch_ops = ca0132_patch_ops; 8781 8782 codec->pcm_format_first = 1; 8783 codec->no_sticky_stream = 1; 8784 8785 8786 spec->dsp_state = DSP_DOWNLOAD_INIT; 8787 spec->num_mixers = 1; 8788 8789 /* Set which mixers each quirk uses. */ 8790 switch (ca0132_quirk(spec)) { 8791 case QUIRK_SBZ: 8792 spec->mixers[0] = desktop_mixer; 8793 snd_hda_codec_set_name(codec, "Sound Blaster Z"); 8794 break; 8795 case QUIRK_ZXR: 8796 spec->mixers[0] = desktop_mixer; 8797 snd_hda_codec_set_name(codec, "Sound Blaster ZxR"); 8798 break; 8799 case QUIRK_ZXR_DBPRO: 8800 break; 8801 case QUIRK_R3D: 8802 spec->mixers[0] = desktop_mixer; 8803 snd_hda_codec_set_name(codec, "Recon3D"); 8804 break; 8805 case QUIRK_R3DI: 8806 spec->mixers[0] = r3di_mixer; 8807 snd_hda_codec_set_name(codec, "Recon3Di"); 8808 break; 8809 case QUIRK_AE5: 8810 spec->mixers[0] = desktop_mixer; 8811 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5"); 8812 break; 8813 default: 8814 spec->mixers[0] = ca0132_mixer; 8815 break; 8816 } 8817 8818 /* Setup whether or not to use alt functions/controls/pci_mmio */ 8819 switch (ca0132_quirk(spec)) { 8820 case QUIRK_SBZ: 8821 case QUIRK_R3D: 8822 case QUIRK_AE5: 8823 case QUIRK_ZXR: 8824 spec->use_alt_controls = true; 8825 spec->use_alt_functions = true; 8826 spec->use_pci_mmio = true; 8827 break; 8828 case QUIRK_R3DI: 8829 spec->use_alt_controls = true; 8830 spec->use_alt_functions = true; 8831 spec->use_pci_mmio = false; 8832 break; 8833 default: 8834 spec->use_alt_controls = false; 8835 spec->use_alt_functions = false; 8836 spec->use_pci_mmio = false; 8837 break; 8838 } 8839 8840 #ifdef CONFIG_PCI 8841 if (spec->use_pci_mmio) { 8842 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20); 8843 if (spec->mem_base == NULL) { 8844 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE."); 8845 spec->quirk = QUIRK_NONE; 8846 } 8847 } 8848 #endif 8849 8850 spec->base_init_verbs = ca0132_base_init_verbs; 8851 spec->base_exit_verbs = ca0132_base_exit_verbs; 8852 8853 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed); 8854 8855 ca0132_init_chip(codec); 8856 8857 ca0132_config(codec); 8858 8859 err = ca0132_prepare_verbs(codec); 8860 if (err < 0) 8861 goto error; 8862 8863 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL); 8864 if (err < 0) 8865 goto error; 8866 8867 return 0; 8868 8869 error: 8870 ca0132_free(codec); 8871 return err; 8872 } 8873 8874 /* 8875 * patch entries 8876 */ 8877 static struct hda_device_id snd_hda_id_ca0132[] = { 8878 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132), 8879 {} /* terminator */ 8880 }; 8881 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132); 8882 8883 MODULE_LICENSE("GPL"); 8884 MODULE_DESCRIPTION("Creative Sound Core3D codec"); 8885 8886 static struct hda_codec_driver ca0132_driver = { 8887 .id = snd_hda_id_ca0132, 8888 }; 8889 8890 module_hda_codec_driver(ca0132_driver); 8891