1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1126-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rv1126-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 compatible = "rockchip,rv1126"; 19 20 interrupt-parent = <&gic>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c2 = &i2c2; 25 i2c3 = &i2c3; 26 serial0 = &uart0; 27 serial1 = &uart1; 28 serial2 = &uart2; 29 serial3 = &uart3; 30 serial4 = &uart4; 31 serial5 = &uart5; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu0: cpu@f00 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0xf00>; 42 enable-method = "psci"; 43 clocks = <&cru ARMCLK>; 44 }; 45 46 cpu1: cpu@f01 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a7"; 49 reg = <0xf01>; 50 enable-method = "psci"; 51 clocks = <&cru ARMCLK>; 52 }; 53 54 cpu2: cpu@f02 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a7"; 57 reg = <0xf02>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 }; 61 62 cpu3: cpu@f03 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a7"; 65 reg = <0xf03>; 66 enable-method = "psci"; 67 clocks = <&cru ARMCLK>; 68 }; 69 }; 70 71 arm-pmu { 72 compatible = "arm,cortex-a7-pmu"; 73 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 74 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 75 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 77 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 78 }; 79 80 psci { 81 compatible = "arm,psci-1.0"; 82 method = "smc"; 83 }; 84 85 timer { 86 compatible = "arm,armv7-timer"; 87 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 88 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 89 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 91 clock-frequency = <24000000>; 92 }; 93 94 display_subsystem { 95 compatible = "rockchip,display-subsystem"; 96 ports = <&vop_out>; 97 }; 98 99 xin24m: oscillator { 100 compatible = "fixed-clock"; 101 clock-frequency = <24000000>; 102 clock-output-names = "xin24m"; 103 #clock-cells = <0>; 104 }; 105 106 grf: syscon@fe000000 { 107 compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; 108 reg = <0xfe000000 0x20000>; 109 }; 110 111 pmugrf: syscon@fe020000 { 112 compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; 113 reg = <0xfe020000 0x1000>; 114 115 pmu_io_domains: io-domains { 116 compatible = "rockchip,rv1126-pmu-io-voltage-domain"; 117 status = "disabled"; 118 }; 119 }; 120 121 qos_emmc: qos@fe860000 { 122 compatible = "rockchip,rv1126-qos", "syscon"; 123 reg = <0xfe860000 0x20>; 124 }; 125 126 qos_nandc: qos@fe860080 { 127 compatible = "rockchip,rv1126-qos", "syscon"; 128 reg = <0xfe860080 0x20>; 129 }; 130 131 qos_sfc: qos@fe860200 { 132 compatible = "rockchip,rv1126-qos", "syscon"; 133 reg = <0xfe860200 0x20>; 134 }; 135 136 qos_sdio: qos@fe86c000 { 137 compatible = "rockchip,rv1126-qos", "syscon"; 138 reg = <0xfe86c000 0x20>; 139 }; 140 141 qos_iep: qos@fe8a0000 { 142 compatible = "rockchip,rv1126-qos", "syscon"; 143 reg = <0xfe8a0000 0x20>; 144 }; 145 146 qos_rga_rd: qos@fe8a0080 { 147 compatible = "rockchip,rv1126-qos", "syscon"; 148 reg = <0xfe8a0080 0x20>; 149 }; 150 151 qos_rga_wr: qos@fe8a0100 { 152 compatible = "rockchip,rv1126-qos", "syscon"; 153 reg = <0xfe8a0100 0x20>; 154 }; 155 156 qos_vop: qos@fe8a0180 { 157 compatible = "rockchip,rv1126-qos", "syscon"; 158 reg = <0xfe8a0180 0x20>; 159 }; 160 161 gic: interrupt-controller@feff0000 { 162 compatible = "arm,gic-400"; 163 interrupt-controller; 164 #interrupt-cells = <3>; 165 #address-cells = <0>; 166 167 reg = <0xfeff1000 0x1000>, 168 <0xfeff2000 0x2000>, 169 <0xfeff4000 0x2000>, 170 <0xfeff6000 0x2000>; 171 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 172 }; 173 174 pmu: power-management@ff3e0000 { 175 compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; 176 reg = <0xff3e0000 0x1000>; 177 178 power: power-controller { 179 compatible = "rockchip,rv1126-power-controller"; 180 #power-domain-cells = <1>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 power-domain@RV1126_PD_NVM { 185 reg = <RV1126_PD_NVM>; 186 clocks = <&cru HCLK_EMMC>, 187 <&cru CLK_EMMC>, 188 <&cru HCLK_NANDC>, 189 <&cru CLK_NANDC>, 190 <&cru HCLK_SFC>, 191 <&cru HCLK_SFCXIP>, 192 <&cru SCLK_SFC>; 193 pm_qos = <&qos_emmc>, 194 <&qos_nandc>, 195 <&qos_sfc>; 196 #power-domain-cells = <0>; 197 }; 198 199 power-domain@RV1126_PD_SDIO { 200 reg = <RV1126_PD_SDIO>; 201 clocks = <&cru HCLK_SDIO>, 202 <&cru CLK_SDIO>; 203 pm_qos = <&qos_sdio>; 204 #power-domain-cells = <0>; 205 }; 206 207 power-domain@RV1126_PD_VO { 208 reg = <RV1126_PD_VO>; 209 clocks = <&cru ACLK_RGA>, 210 <&cru HCLK_RGA>, 211 <&cru CLK_RGA_CORE>, 212 <&cru ACLK_VOP>, 213 <&cru HCLK_VOP>, 214 <&cru DCLK_VOP>, 215 <&cru PCLK_DSIHOST>, 216 <&cru ACLK_IEP>, 217 <&cru HCLK_IEP>, 218 <&cru CLK_IEP_CORE>; 219 pm_qos = <&qos_rga_rd>, 220 <&qos_rga_wr>, 221 <&qos_vop>, 222 <&qos_iep>; 223 #power-domain-cells = <0>; 224 }; 225 }; 226 }; 227 228 i2c0: i2c@ff3f0000 { 229 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 230 reg = <0xff3f0000 0x1000>; 231 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 232 rockchip,grf = <&pmugrf>; 233 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; 234 clock-names = "i2c", "pclk"; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&i2c0_xfer>; 237 #address-cells = <1>; 238 #size-cells = <0>; 239 status = "disabled"; 240 }; 241 242 i2c2: i2c@ff400000 { 243 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 244 reg = <0xff400000 0x1000>; 245 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 246 rockchip,grf = <&pmugrf>; 247 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>; 248 clock-names = "i2c", "pclk"; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&i2c2_xfer>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 256 uart1: serial@ff410000 { 257 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 258 reg = <0xff410000 0x100>; 259 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <24000000>; 261 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; 262 clock-names = "baudclk", "apb_pclk"; 263 dmas = <&dmac 7>, <&dmac 6>; 264 dma-names = "tx", "rx"; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&uart1m0_xfer>; 267 reg-shift = <2>; 268 reg-io-width = <4>; 269 status = "disabled"; 270 }; 271 272 pwm2: pwm@ff430020 { 273 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 274 reg = <0xff430020 0x10>; 275 clock-names = "pwm", "pclk"; 276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&pwm2m0_pins>; 279 #pwm-cells = <3>; 280 status = "disabled"; 281 }; 282 283 pmucru: clock-controller@ff480000 { 284 compatible = "rockchip,rv1126-pmucru"; 285 reg = <0xff480000 0x1000>; 286 rockchip,grf = <&grf>; 287 #clock-cells = <1>; 288 #reset-cells = <1>; 289 }; 290 291 cru: clock-controller@ff490000 { 292 compatible = "rockchip,rv1126-cru"; 293 reg = <0xff490000 0x1000>; 294 clocks = <&xin24m>; 295 clock-names = "xin24m"; 296 rockchip,grf = <&grf>; 297 #clock-cells = <1>; 298 #reset-cells = <1>; 299 }; 300 301 dmac: dma-controller@ff4e0000 { 302 compatible = "arm,pl330", "arm,primecell"; 303 reg = <0xff4e0000 0x4000>; 304 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 306 #dma-cells = <1>; 307 arm,pl330-periph-burst; 308 clocks = <&cru ACLK_DMAC>; 309 clock-names = "apb_pclk"; 310 }; 311 312 i2c3: i2c@ff520000 { 313 compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; 314 reg = <0xff520000 0x1000>; 315 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 316 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 317 clock-names = "i2c", "pclk"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&i2c3m0_xfer>; 320 rockchip,grf = <&pmugrf>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 status = "disabled"; 324 }; 325 326 pwm11: pwm@ff550030 { 327 compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm"; 328 reg = <0xff550030 0x10>; 329 clock-names = "pwm", "pclk"; 330 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 331 pinctrl-0 = <&pwm11m0_pins>; 332 pinctrl-names = "default"; 333 #pwm-cells = <3>; 334 status = "disabled"; 335 }; 336 337 uart0: serial@ff560000 { 338 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 339 reg = <0xff560000 0x100>; 340 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 341 clock-frequency = <24000000>; 342 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 343 clock-names = "baudclk", "apb_pclk"; 344 dmas = <&dmac 5>, <&dmac 4>; 345 dma-names = "tx", "rx"; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&uart0_xfer>; 348 reg-shift = <2>; 349 reg-io-width = <4>; 350 status = "disabled"; 351 }; 352 353 uart2: serial@ff570000 { 354 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 355 reg = <0xff570000 0x100>; 356 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 357 clock-frequency = <24000000>; 358 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 359 clock-names = "baudclk", "apb_pclk"; 360 dmas = <&dmac 9>, <&dmac 8>; 361 dma-names = "tx", "rx"; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&uart2m1_xfer>; 364 reg-shift = <2>; 365 reg-io-width = <4>; 366 status = "disabled"; 367 }; 368 369 uart3: serial@ff580000 { 370 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 371 reg = <0xff580000 0x100>; 372 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 373 clock-frequency = <24000000>; 374 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 375 clock-names = "baudclk", "apb_pclk"; 376 dmas = <&dmac 11>, <&dmac 10>; 377 dma-names = "tx", "rx"; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&uart3m0_xfer>; 380 reg-shift = <2>; 381 reg-io-width = <4>; 382 status = "disabled"; 383 }; 384 385 uart4: serial@ff590000 { 386 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 387 reg = <0xff590000 0x100>; 388 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 389 clock-frequency = <24000000>; 390 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 391 clock-names = "baudclk", "apb_pclk"; 392 dmas = <&dmac 13>, <&dmac 12>; 393 dma-names = "tx", "rx"; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&uart4m0_xfer>; 396 reg-shift = <2>; 397 reg-io-width = <4>; 398 status = "disabled"; 399 }; 400 401 uart5: serial@ff5a0000 { 402 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 403 reg = <0xff5a0000 0x100>; 404 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 405 clock-frequency = <24000000>; 406 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 407 clock-names = "baudclk", "apb_pclk"; 408 dmas = <&dmac 15>, <&dmac 14>; 409 dma-names = "tx", "rx"; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&uart5m0_xfer>; 412 reg-shift = <2>; 413 reg-io-width = <4>; 414 status = "disabled"; 415 }; 416 417 saradc: adc@ff5e0000 { 418 compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; 419 reg = <0xff5e0000 0x100>; 420 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 421 #io-channel-cells = <1>; 422 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 423 clock-names = "saradc", "apb_pclk"; 424 resets = <&cru SRST_SARADC_P>; 425 reset-names = "saradc-apb"; 426 status = "disabled"; 427 }; 428 429 timer0: timer@ff660000 { 430 compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; 431 reg = <0xff660000 0x20>; 432 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 434 clock-names = "pclk", "timer"; 435 }; 436 437 vop: vop@ffb00000 { 438 compatible = "rockchip,rv1126-vop"; 439 reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; 440 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 441 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 442 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; 443 reset-names = "axi", "ahb", "dclk"; 444 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; 445 iommus = <&vop_mmu>; 446 power-domains = <&power RV1126_PD_VO>; 447 status = "disabled"; 448 449 vop_out: port { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 vop_out_rgb: endpoint@0 { 454 reg = <0>; 455 }; 456 457 vop_out_dsi: endpoint@1 { 458 reg = <1>; 459 }; 460 }; 461 }; 462 463 vop_mmu: iommu@ffb00f00 { 464 compatible = "rockchip,iommu"; 465 reg = <0xffb00f00 0x100>; 466 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 467 clock-names = "aclk", "iface"; 468 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 469 #iommu-cells = <0>; 470 power-domains = <&power RV1126_PD_VO>; 471 status = "disabled"; 472 }; 473 474 gmac: ethernet@ffc40000 { 475 compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 476 reg = <0xffc40000 0x4000>; 477 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 479 interrupt-names = "macirq", "eth_wake_irq"; 480 rockchip,grf = <&grf>; 481 clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 482 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 483 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 484 <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 485 clock-names = "stmmaceth", "mac_clk_rx", 486 "mac_clk_tx", "clk_mac_ref", 487 "aclk_mac", "pclk_mac", 488 "clk_mac_speed", "ptp_ref"; 489 resets = <&cru SRST_GMAC_A>; 490 reset-names = "stmmaceth"; 491 492 snps,mixed-burst; 493 snps,tso; 494 495 snps,axi-config = <&stmmac_axi_setup>; 496 snps,mtl-rx-config = <&mtl_rx_setup>; 497 snps,mtl-tx-config = <&mtl_tx_setup>; 498 status = "disabled"; 499 500 mdio: mdio { 501 compatible = "snps,dwmac-mdio"; 502 #address-cells = <0x1>; 503 #size-cells = <0x0>; 504 }; 505 506 stmmac_axi_setup: stmmac-axi-config { 507 snps,wr_osr_lmt = <4>; 508 snps,rd_osr_lmt = <8>; 509 snps,blen = <0 0 0 0 16 8 4>; 510 }; 511 512 mtl_rx_setup: rx-queues-config { 513 snps,rx-queues-to-use = <1>; 514 queue0 {}; 515 }; 516 517 mtl_tx_setup: tx-queues-config { 518 snps,tx-queues-to-use = <1>; 519 queue0 {}; 520 }; 521 }; 522 523 emmc: mmc@ffc50000 { 524 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 525 reg = <0xffc50000 0x4000>; 526 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, 528 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 529 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 530 fifo-depth = <0x100>; 531 max-frequency = <200000000>; 532 power-domains = <&power RV1126_PD_NVM>; 533 status = "disabled"; 534 }; 535 536 sdmmc: mmc@ffc60000 { 537 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 538 reg = <0xffc60000 0x4000>; 539 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, 541 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 542 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 543 fifo-depth = <0x100>; 544 max-frequency = <200000000>; 545 status = "disabled"; 546 }; 547 548 sdio: mmc@ffc70000 { 549 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 550 reg = <0xffc70000 0x4000>; 551 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, 553 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 554 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 555 fifo-depth = <0x100>; 556 max-frequency = <200000000>; 557 power-domains = <&power RV1126_PD_SDIO>; 558 status = "disabled"; 559 }; 560 561 sfc: spi@ffc90000 { 562 compatible = "rockchip,sfc"; 563 reg = <0xffc90000 0x4000>; 564 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 565 assigned-clocks = <&cru SCLK_SFC>; 566 assigned-clock-rates = <80000000>; 567 clock-names = "clk_sfc", "hclk_sfc"; 568 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 569 power-domains = <&power RV1126_PD_NVM>; 570 status = "disabled"; 571 }; 572 573 pinctrl: pinctrl { 574 compatible = "rockchip,rv1126-pinctrl"; 575 rockchip,grf = <&grf>; 576 rockchip,pmu = <&pmugrf>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 ranges; 580 581 gpio0: gpio@ff460000 { 582 compatible = "rockchip,gpio-bank"; 583 reg = <0xff460000 0x100>; 584 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; 586 gpio-controller; 587 #gpio-cells = <2>; 588 interrupt-controller; 589 #interrupt-cells = <2>; 590 }; 591 592 gpio1: gpio@ff620000 { 593 compatible = "rockchip,gpio-bank"; 594 reg = <0xff620000 0x100>; 595 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 597 gpio-controller; 598 #gpio-cells = <2>; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 }; 602 603 gpio2: gpio@ff630000 { 604 compatible = "rockchip,gpio-bank"; 605 reg = <0xff630000 0x100>; 606 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 608 gpio-controller; 609 #gpio-cells = <2>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 }; 613 614 gpio3: gpio@ff640000 { 615 compatible = "rockchip,gpio-bank"; 616 reg = <0xff640000 0x100>; 617 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 619 gpio-controller; 620 #gpio-cells = <2>; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 625 gpio4: gpio@ff650000 { 626 compatible = "rockchip,gpio-bank"; 627 reg = <0xff650000 0x100>; 628 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 630 gpio-controller; 631 #gpio-cells = <2>; 632 interrupt-controller; 633 #interrupt-cells = <2>; 634 }; 635 }; 636}; 637 638#include "rv1126-pinctrl.dtsi" 639