xref: /linux/scripts/dtc/include-prefixes/arm/rockchip/rv1126-pinctrl.dtsi (revision 212cda94739b1644e38ef4f588bb580c12feb9a7) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
4 */
5
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <arm64/rockchip/rockchip-pinconf.dtsi>
8
9/*
10 * This file is auto generated by pin2dts tool, please keep these code
11 * by adding changes at end of this file.
12 */
13&pinctrl {
14	clk_out_ethernet {
15		/omit-if-no-ref/
16		clk_out_ethernetm1_pins: clk-out-ethernetm1-pins {
17			rockchip,pins =
18				/* clk_out_ethernet_m1 */
19				<2 RK_PC5 2 &pcfg_pull_none>;
20		};
21	};
22	emmc {
23		/omit-if-no-ref/
24		emmc_rstnout: emmc-rstnout {
25			rockchip,pins =
26				/* emmc_rstn */
27				<1 RK_PA3 2 &pcfg_pull_none>;
28		};
29		/omit-if-no-ref/
30		emmc_bus8: emmc-bus8 {
31			rockchip,pins =
32				/* emmc_d0 */
33				<0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
34				/* emmc_d1 */
35				<0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
36				/* emmc_d2 */
37				<0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
38				/* emmc_d3 */
39				<0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
40				/* emmc_d4 */
41				<0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
42				/* emmc_d5 */
43				<0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
44				/* emmc_d6 */
45				<0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
46				/* emmc_d7 */
47				<0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
48		};
49		/omit-if-no-ref/
50		emmc_clk: emmc-clk {
51			rockchip,pins =
52				/* emmc_clko */
53				<0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
54		};
55		/omit-if-no-ref/
56		emmc_cmd: emmc-cmd {
57			rockchip,pins =
58				/* emmc_cmd */
59				<0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
60		};
61	};
62	fspi {
63		/omit-if-no-ref/
64		fspi_pins: fspi-pins {
65			rockchip,pins =
66				/* fspi_clk */
67				<1 RK_PA3 3 &pcfg_pull_down>,
68				/* fspi_cs0n */
69				<0 RK_PD4 3 &pcfg_pull_up>,
70				/* fspi_d0 */
71				<1 RK_PA0 3 &pcfg_pull_up>,
72				/* fspi_d1 */
73				<1 RK_PA1 3 &pcfg_pull_up>,
74				/* fspi_d2 */
75				<0 RK_PD6 3 &pcfg_pull_up>,
76				/* fspi_d3 */
77				<1 RK_PA2 3 &pcfg_pull_up>;
78		};
79	};
80	i2c0 {
81		/omit-if-no-ref/
82		i2c0_xfer: i2c0-xfer {
83			rockchip,pins =
84				/* i2c0_scl */
85				<0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
86				/* i2c0_sda */
87				<0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
88		};
89	};
90	i2c2 {
91		/omit-if-no-ref/
92		i2c2_xfer: i2c2-xfer {
93			rockchip,pins =
94				/* i2c2_scl */
95				<0 RK_PC2 1 &pcfg_pull_none_drv_level_0_smt>,
96				/* i2c2_sda */
97				<0 RK_PC3 1 &pcfg_pull_none_drv_level_0_smt>;
98		};
99	};
100	i2c3 {
101		/omit-if-no-ref/
102		i2c3m0_xfer: i2c3m0-xfer {
103			rockchip,pins =
104				/* i2c3_scl_m0 */
105				<3 RK_PA4 5 &pcfg_pull_none>,
106				/* i2c3_sda_m0 */
107				<3 RK_PA5 5 &pcfg_pull_none>;
108		};
109		/omit-if-no-ref/
110		i2c3m1_xfer: i2c3m1-xfer {
111			rockchip,pins =
112				/* i2c3_scl_m1 */
113				<2 RK_PD4 7 &pcfg_pull_none>,
114				/* i2c3_sda_m1 */
115				<2 RK_PD5 7 &pcfg_pull_none>;
116		};
117		/omit-if-no-ref/
118		i2c3m2_xfer: i2c3m2-xfer {
119			rockchip,pins =
120				/* i2c3_scl_m2 */
121				<1 RK_PD6 3 &pcfg_pull_none>,
122				/* i2c3_sda_m2 */
123				<1 RK_PD7 3 &pcfg_pull_none>;
124		};
125	};
126	i2s0 {
127		i2s0m0_lrck_tx: i2s0m0-lrck-tx {
128			rockchip,pins =
129			/* i2s0_lrck_tx_m0 */
130			<3 RK_PD3 1 &pcfg_pull_none>;
131		};
132		i2s0m0_lrck_rx: i2s0m0-lrck-rx {
133			rockchip,pins =
134			/* i2s0_lrck_rx_m0 */
135			<3 RK_PD4 1 &pcfg_pull_none>;
136		};
137		i2s0m0_mclk: i2s0m0-mclk {
138			rockchip,pins =
139			/* i2s0_mclk_m0 */
140			<3 RK_PD2 1 &pcfg_pull_none>;
141		};
142		i2s0m0_sclk_rx: i2s0m0-sclk-rx {
143			rockchip,pins =
144			/* i2s0_sclk_rx_m0 */
145			<3 RK_PD1 1 &pcfg_pull_none>;
146		};
147		i2s0m0_sclk_tx: i2s0m0-sclk-tx {
148			rockchip,pins =
149			/* i2s0_sclk_tx_m0 */
150			<3 RK_PD0 1 &pcfg_pull_none>;
151		};
152		i2s0m0_sdi0: i2s0m0-sdi0 {
153			rockchip,pins =
154			/* i2s0_sdi0_m0 */
155			<3 RK_PD6 1 &pcfg_pull_none>;
156		};
157		i2s0m0_sdo0: i2s0m0-sdo0 {
158			rockchip,pins =
159			/* i2s0_sdo0_m0 */
160			<3 RK_PD5 1 &pcfg_pull_none>;
161		};
162		i2s0m0_sdo1_sdi3: i2s0m0-sdo1-sdi3 {
163			rockchip,pins =
164			/* i2s0_sdo1_sdi3_m0 */
165			<3 RK_PD7 1 &pcfg_pull_none>;
166		};
167		i2s0m0_sdo2_sdi2: i2s0m0-sdo2-sdi2 {
168			rockchip,pins =
169			/* i2s0_sdo2_sdi2_m0 */
170			<4 RK_PA0 1 &pcfg_pull_none>;
171		};
172		i2s0m0_sdo3_sdi1: i2s0m0-sdo3-sdi1 {
173			rockchip,pins =
174			/* i2s0_sdo3_sdi1_m0 */
175			<4 RK_PA1 1 &pcfg_pull_none>;
176		};
177		i2s0m1_lrck_tx: i2s0m1-lrck-tx {
178			rockchip,pins =
179			/* i2s0_lrck_tx_m1 */
180			<3 RK_PA5 3 &pcfg_pull_none>;
181		};
182		i2s0m1_lrck_rx: i2s0m1-lrck-rx {
183			rockchip,pins =
184			/* i2s0_lrck_rx_m1 */
185			<3 RK_PB2 3 &pcfg_pull_none>;
186		};
187		i2s0m1_mclk: i2s0m1-mclk {
188			rockchip,pins =
189			/* i2s0_mclk_m1 */
190			<3 RK_PB0 3 &pcfg_pull_none>;
191		};
192		i2s0m1_sclk_rx: i2s0m1-sclk-rx {
193			rockchip,pins =
194			/* i2s0_sclk_rx_m1 */
195			<3 RK_PB1 3 &pcfg_pull_none>;
196		};
197		i2s0m1_sclk_tx: i2s0m1-sclk-tx {
198			rockchip,pins =
199			/* i2s0_sclk_tx_m1 */
200			<3 RK_PA4 3 &pcfg_pull_none>;
201		};
202		i2s0m1_sdi0: i2s0m1-sdi0 {
203			rockchip,pins =
204			/* i2s0_sdi0_m1 */
205			<3 RK_PA7 3 &pcfg_pull_none>;
206		};
207		i2s0m1_sdo0: i2s0m1-sdo0 {
208			rockchip,pins =
209			/* i2s0_sdo0_m1 */
210			<3 RK_PA6 3 &pcfg_pull_none>;
211		};
212		i2s0m1_sdo1_sdi3: i2s0m1-sdo1-sdi3 {
213			rockchip,pins =
214			/* i2s0_sdo1_sdi3_m1 */
215			<3 RK_PB3 3 &pcfg_pull_none>;
216		};
217		i2s0m1_sdo2_sdi2: i2s0m1-sdo2-sdi2 {
218			rockchip,pins =
219			/* i2s0_sdo2_sdi2_m1 */
220			<3 RK_PB4 3 &pcfg_pull_none>;
221		};
222		i2s0m1_sdo3_sdi1: i2s0m1-sdo3-sdi1 {
223			rockchip,pins =
224			/* i2s0_sdo3_sdi1_m1 */
225			<3 RK_PB5 3 &pcfg_pull_none>;
226		};
227	};
228	pwm2 {
229		/omit-if-no-ref/
230		pwm2m0_pins: pwm2m0-pins {
231			rockchip,pins =
232				/* pwm2_pin_m0 */
233				<0 RK_PC0 3 &pcfg_pull_none>;
234		};
235	};
236	pwm11 {
237		/omit-if-no-ref/
238		pwm11m0_pins: pwm11m0-pins {
239			rockchip,pins =
240				/* pwm11_pin_m0 */
241				<3 RK_PA7 6 &pcfg_pull_none>;
242		};
243	};
244	rgmii {
245		/omit-if-no-ref/
246		rgmiim1_miim: rgmiim1-miim {
247			rockchip,pins =
248				/* rgmii_mdc_m1 */
249				<2 RK_PC2 2 &pcfg_pull_none>,
250				/* rgmii_mdio_m1 */
251				<2 RK_PC1 2 &pcfg_pull_none>;
252		};
253		/omit-if-no-ref/
254		rgmiim1_rxer: rgmiim1-rxer {
255			rockchip,pins =
256				/* rgmii_rxer_m1 */
257				<2 RK_PC0 2 &pcfg_pull_none>;
258		};
259		/omit-if-no-ref/
260		rgmiim1_bus2: rgmiim1-bus2 {
261			rockchip,pins =
262				/* rgmii_rxd0_m1 */
263				<2 RK_PB5 2 &pcfg_pull_none>,
264				/* rgmii_rxd1_m1 */
265				<2 RK_PB6 2 &pcfg_pull_none>,
266				/* rgmii_rxdv_m1 */
267				<2 RK_PB4 2 &pcfg_pull_none>,
268				/* rgmii_txd0_m1 */
269				<2 RK_PC3 2 &pcfg_pull_none_drv_level_3>,
270				/* rgmii_txd1_m1 */
271				<2 RK_PC4 2 &pcfg_pull_none_drv_level_3>,
272				/* rgmii_txen_m1 */
273				<2 RK_PC6 2 &pcfg_pull_none_drv_level_3>;
274		};
275		/omit-if-no-ref/
276		rgmiim1_bus4: rgmiim1-bus4 {
277			rockchip,pins =
278				/* rgmii_rxclk_m1 */
279				<2 RK_PD3 2 &pcfg_pull_none>,
280				/* rgmii_rxd2_m1 */
281				<2 RK_PC7 2 &pcfg_pull_none>,
282				/* rgmii_rxd3_m1 */
283				<2 RK_PD0 2 &pcfg_pull_none>,
284				/* rgmii_txclk_m1 */
285				<2 RK_PD2 2 &pcfg_pull_none_drv_level_3>,
286				/* rgmii_txd2_m1 */
287				<2 RK_PD1 2 &pcfg_pull_none_drv_level_3>,
288				/* rgmii_txd3_m1 */
289				<2 RK_PA4 2 &pcfg_pull_none_drv_level_3>;
290		};
291		/omit-if-no-ref/
292		rgmiim1_mclkinout: rgmiim1-mclkinout {
293			rockchip,pins =
294				/* rgmii_clk_m1 */
295				<2 RK_PB7 2 &pcfg_pull_none>;
296		};
297	};
298	sdmmc0 {
299		/omit-if-no-ref/
300		sdmmc0_bus4: sdmmc0-bus4 {
301			rockchip,pins =
302				/* sdmmc0_d0 */
303				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
304				/* sdmmc0_d1 */
305				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
306				/* sdmmc0_d2 */
307				<1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
308				/* sdmmc0_d3 */
309				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
310		};
311		/omit-if-no-ref/
312		sdmmc0_clk: sdmmc0-clk {
313			rockchip,pins =
314				/* sdmmc0_clk */
315				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
316		};
317		/omit-if-no-ref/
318		sdmmc0_cmd: sdmmc0-cmd {
319			rockchip,pins =
320				/* sdmmc0_cmd */
321				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
322		};
323		/omit-if-no-ref/
324		sdmmc0_det: sdmmc0-det {
325			rockchip,pins =
326				<0 RK_PA3 1 &pcfg_pull_none>;
327		};
328		/omit-if-no-ref/
329		sdmmc0_pwr: sdmmc0-pwr {
330			rockchip,pins =
331				<0 RK_PC0 1 &pcfg_pull_none>;
332		};
333	};
334	sdmmc1 {
335		/omit-if-no-ref/
336		sdmmc1_bus4: sdmmc1-bus4 {
337			rockchip,pins =
338				/* sdmmc1_d0 */
339				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
340				/* sdmmc1_d1 */
341				<1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
342				/* sdmmc1_d2 */
343				<1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
344				/* sdmmc1_d3 */
345				<1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
346		};
347		/omit-if-no-ref/
348		sdmmc1_clk: sdmmc1-clk {
349			rockchip,pins =
350				/* sdmmc1_clk */
351				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
352		};
353		/omit-if-no-ref/
354		sdmmc1_cmd: sdmmc1-cmd {
355			rockchip,pins =
356				/* sdmmc1_cmd */
357				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
358		};
359		/omit-if-no-ref/
360		sdmmc1_det: sdmmc1-det {
361			rockchip,pins =
362				<1 RK_PD0 2 &pcfg_pull_none>;
363		};
364		/omit-if-no-ref/
365		sdmmc1_pwr: sdmmc1-pwr {
366			rockchip,pins =
367				<1 RK_PD1 2 &pcfg_pull_none>;
368		};
369	};
370	uart0 {
371		/omit-if-no-ref/
372		uart0_xfer: uart0-xfer {
373			rockchip,pins =
374				/* uart0_rx */
375				<1 RK_PC2 1 &pcfg_pull_up>,
376				/* uart0_tx */
377				<1 RK_PC3 1 &pcfg_pull_up>;
378		};
379		/omit-if-no-ref/
380		uart0_ctsn: uart0-ctsn {
381			rockchip,pins =
382				<1 RK_PC1 1 &pcfg_pull_none>;
383		};
384		/omit-if-no-ref/
385		uart0_rtsn: uart0-rtsn {
386			rockchip,pins =
387				<1 RK_PC0 1 &pcfg_pull_none>;
388		};
389		/omit-if-no-ref/
390		uart0_rtsn_gpio: uart0-rts-pin {
391			rockchip,pins =
392				<1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
393		};
394	};
395	uart1 {
396		/omit-if-no-ref/
397		uart1m0_xfer: uart1m0-xfer {
398			rockchip,pins =
399				/* uart1_rx_m0 */
400				<0 RK_PB7 2 &pcfg_pull_up>,
401				/* uart1_tx_m0 */
402				<0 RK_PB6 2 &pcfg_pull_up>;
403		};
404	};
405	uart2 {
406		/omit-if-no-ref/
407		uart2m1_xfer: uart2m1-xfer {
408			rockchip,pins =
409				/* uart2_rx_m1 */
410				<3 RK_PA3 1 &pcfg_pull_up>,
411				/* uart2_tx_m1 */
412				<3 RK_PA2 1 &pcfg_pull_up>;
413		};
414	};
415	uart3 {
416		/omit-if-no-ref/
417		uart3m0_xfer: uart3m0-xfer {
418			rockchip,pins =
419				/* uart3_rx_m0 */
420				<3 RK_PC7 4 &pcfg_pull_up>,
421				/* uart3_tx_m0 */
422				<3 RK_PC6 4 &pcfg_pull_up>;
423		};
424		/omit-if-no-ref/
425		uart3m2_xfer: uart3m2-xfer {
426			rockchip,pins =
427				/* uart3_rx_m2 */
428				<3 RK_PA1 4 &pcfg_pull_up>,
429				/* uart3_tx_m2 */
430				<3 RK_PA0 4 &pcfg_pull_up>;
431		};
432	};
433	uart4 {
434		/omit-if-no-ref/
435		uart4m0_xfer: uart4m0-xfer {
436			rockchip,pins =
437				/* uart4_rx_m0 */
438				<3 RK_PA5 4 &pcfg_pull_up>,
439				/* uart4_tx_m0 */
440				<3 RK_PA4 4 &pcfg_pull_up>;
441		};
442		/omit-if-no-ref/
443		uart4m2_xfer: uart4m2-xfer {
444			rockchip,pins =
445				/* uart4_rx_m2 */
446				<1 RK_PD4 3 &pcfg_pull_up>,
447				/* uart4_tx_m2 */
448				<1 RK_PD5 3 &pcfg_pull_up>;
449		};
450	};
451	uart5 {
452		/omit-if-no-ref/
453		uart5m0_xfer: uart5m0-xfer {
454			rockchip,pins =
455				/* uart5_rx_m0 */
456				<3 RK_PA7 4 &pcfg_pull_up>,
457				/* uart5_tx_m0 */
458				<3 RK_PA6 4 &pcfg_pull_up>;
459		};
460		/omit-if-no-ref/
461		uart5m2_xfer: uart5m2-xfer {
462			rockchip,pins =
463				/* uart5_rx_m2 */
464				<2 RK_PA1 3 &pcfg_pull_up>,
465				/* uart5_tx_m2 */
466				<2 RK_PA0 3 &pcfg_pull_up>;
467		};
468	};
469};
470