1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include <arm64/rockchip/rockchip-pinconf.dtsi> 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 clk_out_ethernet { 15 /omit-if-no-ref/ 16 clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { 17 rockchip,pins = 18 /* clk_out_ethernet_m1 */ 19 <2 RK_PC5 2 &pcfg_pull_none>; 20 }; 21 }; 22 emmc { 23 /omit-if-no-ref/ 24 emmc_rstnout: emmc-rstnout { 25 rockchip,pins = 26 /* emmc_rstn */ 27 <1 RK_PA3 2 &pcfg_pull_none>; 28 }; 29 /omit-if-no-ref/ 30 emmc_bus8: emmc-bus8 { 31 rockchip,pins = 32 /* emmc_d0 */ 33 <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, 34 /* emmc_d1 */ 35 <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, 36 /* emmc_d2 */ 37 <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, 38 /* emmc_d3 */ 39 <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, 40 /* emmc_d4 */ 41 <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, 42 /* emmc_d5 */ 43 <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, 44 /* emmc_d6 */ 45 <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, 46 /* emmc_d7 */ 47 <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; 48 }; 49 /omit-if-no-ref/ 50 emmc_clk: emmc-clk { 51 rockchip,pins = 52 /* emmc_clko */ 53 <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; 54 }; 55 /omit-if-no-ref/ 56 emmc_cmd: emmc-cmd { 57 rockchip,pins = 58 /* emmc_cmd */ 59 <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; 60 }; 61 }; 62 fspi { 63 /omit-if-no-ref/ 64 fspi_pins: fspi-pins { 65 rockchip,pins = 66 /* fspi_clk */ 67 <1 RK_PA3 3 &pcfg_pull_down>, 68 /* fspi_cs0n */ 69 <0 RK_PD4 3 &pcfg_pull_up>, 70 /* fspi_d0 */ 71 <1 RK_PA0 3 &pcfg_pull_up>, 72 /* fspi_d1 */ 73 <1 RK_PA1 3 &pcfg_pull_up>, 74 /* fspi_d2 */ 75 <0 RK_PD6 3 &pcfg_pull_up>, 76 /* fspi_d3 */ 77 <1 RK_PA2 3 &pcfg_pull_up>; 78 }; 79 }; 80 i2c0 { 81 /omit-if-no-ref/ 82 i2c0_xfer: i2c0-xfer { 83 rockchip,pins = 84 /* i2c0_scl */ 85 <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, 86 /* i2c0_sda */ 87 <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; 88 }; 89 }; 90 pwm2 { 91 /omit-if-no-ref/ 92 pwm2m0_pins: pwm2m0-pins { 93 rockchip,pins = 94 /* pwm2_pin_m0 */ 95 <0 RK_PC0 3 &pcfg_pull_none>; 96 }; 97 }; 98 pwm11 { 99 /omit-if-no-ref/ 100 pwm11m0_pins: pwm11m0-pins { 101 rockchip,pins = 102 /* pwm11_pin_m0 */ 103 <3 RK_PA7 6 &pcfg_pull_none>; 104 }; 105 }; 106 rgmii { 107 /omit-if-no-ref/ 108 rgmiim1_pins: rgmiim1-pins { 109 rockchip,pins = 110 /* rgmii_mdc_m1 */ 111 <2 RK_PC2 2 &pcfg_pull_none>, 112 /* rgmii_mdio_m1 */ 113 <2 RK_PC1 2 &pcfg_pull_none>, 114 /* rgmii_rxclk_m1 */ 115 <2 RK_PD3 2 &pcfg_pull_none>, 116 /* rgmii_rxd0_m1 */ 117 <2 RK_PB5 2 &pcfg_pull_none>, 118 /* rgmii_rxd1_m1 */ 119 <2 RK_PB6 2 &pcfg_pull_none>, 120 /* rgmii_rxd2_m1 */ 121 <2 RK_PC7 2 &pcfg_pull_none>, 122 /* rgmii_rxd3_m1 */ 123 <2 RK_PD0 2 &pcfg_pull_none>, 124 /* rgmii_rxdv_m1 */ 125 <2 RK_PB4 2 &pcfg_pull_none>, 126 /* rgmii_txclk_m1 */ 127 <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, 128 /* rgmii_txd0_m1 */ 129 <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, 130 /* rgmii_txd1_m1 */ 131 <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, 132 /* rgmii_txd2_m1 */ 133 <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, 134 /* rgmii_txd3_m1 */ 135 <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, 136 /* rgmii_txen_m1 */ 137 <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; 138 }; 139 }; 140 sdmmc0 { 141 /omit-if-no-ref/ 142 sdmmc0_bus4: sdmmc0-bus4 { 143 rockchip,pins = 144 /* sdmmc0_d0 */ 145 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, 146 /* sdmmc0_d1 */ 147 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, 148 /* sdmmc0_d2 */ 149 <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, 150 /* sdmmc0_d3 */ 151 <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; 152 }; 153 /omit-if-no-ref/ 154 sdmmc0_clk: sdmmc0-clk { 155 rockchip,pins = 156 /* sdmmc0_clk */ 157 <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; 158 }; 159 /omit-if-no-ref/ 160 sdmmc0_cmd: sdmmc0-cmd { 161 rockchip,pins = 162 /* sdmmc0_cmd */ 163 <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 164 }; 165 /omit-if-no-ref/ 166 sdmmc0_det: sdmmc0-det { 167 rockchip,pins = 168 <0 RK_PA3 1 &pcfg_pull_none>; 169 }; 170 /omit-if-no-ref/ 171 sdmmc0_pwr: sdmmc0-pwr { 172 rockchip,pins = 173 <0 RK_PC0 1 &pcfg_pull_none>; 174 }; 175 }; 176 sdmmc1 { 177 /omit-if-no-ref/ 178 sdmmc1_bus4: sdmmc1-bus4 { 179 rockchip,pins = 180 /* sdmmc1_d0 */ 181 <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, 182 /* sdmmc1_d1 */ 183 <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, 184 /* sdmmc1_d2 */ 185 <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, 186 /* sdmmc1_d3 */ 187 <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; 188 }; 189 /omit-if-no-ref/ 190 sdmmc1_clk: sdmmc1-clk { 191 rockchip,pins = 192 /* sdmmc1_clk */ 193 <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; 194 }; 195 /omit-if-no-ref/ 196 sdmmc1_cmd: sdmmc1-cmd { 197 rockchip,pins = 198 /* sdmmc1_cmd */ 199 <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; 200 }; 201 /omit-if-no-ref/ 202 sdmmc1_det: sdmmc1-det { 203 rockchip,pins = 204 <1 RK_PD0 2 &pcfg_pull_none>; 205 }; 206 /omit-if-no-ref/ 207 sdmmc1_pwr: sdmmc1-pwr { 208 rockchip,pins = 209 <1 RK_PD1 2 &pcfg_pull_none>; 210 }; 211 }; 212 uart0 { 213 /omit-if-no-ref/ 214 uart0_xfer: uart0-xfer { 215 rockchip,pins = 216 /* uart0_rx */ 217 <1 RK_PC2 1 &pcfg_pull_up>, 218 /* uart0_tx */ 219 <1 RK_PC3 1 &pcfg_pull_up>; 220 }; 221 /omit-if-no-ref/ 222 uart0_ctsn: uart0-ctsn { 223 rockchip,pins = 224 <1 RK_PC1 1 &pcfg_pull_none>; 225 }; 226 /omit-if-no-ref/ 227 uart0_rtsn: uart0-rtsn { 228 rockchip,pins = 229 <1 RK_PC0 1 &pcfg_pull_none>; 230 }; 231 /omit-if-no-ref/ 232 uart0_rtsn_gpio: uart0-rts-pin { 233 rockchip,pins = 234 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 235 }; 236 }; 237 uart1 { 238 /omit-if-no-ref/ 239 uart1m0_xfer: uart1m0-xfer { 240 rockchip,pins = 241 /* uart1_rx_m0 */ 242 <0 RK_PB7 2 &pcfg_pull_up>, 243 /* uart1_tx_m0 */ 244 <0 RK_PB6 2 &pcfg_pull_up>; 245 }; 246 }; 247 uart2 { 248 /omit-if-no-ref/ 249 uart2m1_xfer: uart2m1-xfer { 250 rockchip,pins = 251 /* uart2_rx_m1 */ 252 <3 RK_PA3 1 &pcfg_pull_up>, 253 /* uart2_tx_m1 */ 254 <3 RK_PA2 1 &pcfg_pull_up>; 255 }; 256 }; 257 uart3 { 258 /omit-if-no-ref/ 259 uart3m0_xfer: uart3m0-xfer { 260 rockchip,pins = 261 /* uart3_rx_m0 */ 262 <3 RK_PC7 4 &pcfg_pull_up>, 263 /* uart3_tx_m0 */ 264 <3 RK_PC6 4 &pcfg_pull_up>; 265 }; 266 }; 267 uart4 { 268 /omit-if-no-ref/ 269 uart4m0_xfer: uart4m0-xfer { 270 rockchip,pins = 271 /* uart4_rx_m0 */ 272 <3 RK_PA5 4 &pcfg_pull_up>, 273 /* uart4_tx_m0 */ 274 <3 RK_PA4 4 &pcfg_pull_up>; 275 }; 276 }; 277 uart5 { 278 /omit-if-no-ref/ 279 uart5m0_xfer: uart5m0-xfer { 280 rockchip,pins = 281 /* uart5_rx_m0 */ 282 <3 RK_PA7 4 &pcfg_pull_up>, 283 /* uart5_tx_m0 */ 284 <3 RK_PA6 4 &pcfg_pull_up>; 285 }; 286 /omit-if-no-ref/ 287 uart5m2_xfer: uart5m2-xfer { 288 rockchip,pins = 289 /* uart5_rx_m2 */ 290 <2 RK_PA1 3 &pcfg_pull_up>, 291 /* uart5_tx_m2 */ 292 <2 RK_PA0 3 &pcfg_pull_up>; 293 }; 294 }; 295}; 296