1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Universal Flash Storage Host controller driver 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #ifndef _UFSHCD_H 13 #define _UFSHCD_H 14 15 #include <linux/bitfield.h> 16 #include <linux/blk-crypto-profile.h> 17 #include <linux/blk-mq.h> 18 #include <linux/devfreq.h> 19 #include <linux/fault-inject.h> 20 #include <linux/debugfs.h> 21 #include <linux/msi.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/dma-direction.h> 24 #include <scsi/scsi_device.h> 25 #include <scsi/scsi_host.h> 26 #include <ufs/unipro.h> 27 #include <ufs/ufs.h> 28 #include <ufs/ufs_quirks.h> 29 #include <ufs/ufshci.h> 30 31 #define UFSHCD "ufshcd" 32 33 struct scsi_device; 34 struct ufs_hba; 35 36 enum dev_cmd_type { 37 DEV_CMD_TYPE_NOP = 0x0, 38 DEV_CMD_TYPE_QUERY = 0x1, 39 DEV_CMD_TYPE_RPMB = 0x2, 40 }; 41 42 enum ufs_event_type { 43 /* uic specific errors */ 44 UFS_EVT_PA_ERR = 0, 45 UFS_EVT_DL_ERR, 46 UFS_EVT_NL_ERR, 47 UFS_EVT_TL_ERR, 48 UFS_EVT_DME_ERR, 49 50 /* fatal errors */ 51 UFS_EVT_AUTO_HIBERN8_ERR, 52 UFS_EVT_FATAL_ERR, 53 UFS_EVT_LINK_STARTUP_FAIL, 54 UFS_EVT_RESUME_ERR, 55 UFS_EVT_SUSPEND_ERR, 56 UFS_EVT_WL_SUSP_ERR, 57 UFS_EVT_WL_RES_ERR, 58 59 /* abnormal events */ 60 UFS_EVT_DEV_RESET, 61 UFS_EVT_HOST_RESET, 62 UFS_EVT_ABORT, 63 64 UFS_EVT_CNT, 65 }; 66 67 /** 68 * struct uic_command - UIC command structure 69 * @command: UIC command 70 * @argument1: UIC command argument 1 71 * @argument2: UIC command argument 2 72 * @argument3: UIC command argument 3 73 * @cmd_active: Indicate if UIC command is outstanding 74 * @done: UIC command completion 75 */ 76 struct uic_command { 77 const u32 command; 78 const u32 argument1; 79 u32 argument2; 80 u32 argument3; 81 int cmd_active; 82 struct completion done; 83 }; 84 85 /* Used to differentiate the power management options */ 86 enum ufs_pm_op { 87 UFS_RUNTIME_PM, 88 UFS_SYSTEM_PM, 89 UFS_SHUTDOWN_PM, 90 }; 91 92 /* Host <-> Device UniPro Link state */ 93 enum uic_link_state { 94 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */ 95 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */ 96 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */ 97 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */ 98 }; 99 100 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE) 101 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \ 102 UIC_LINK_ACTIVE_STATE) 103 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \ 104 UIC_LINK_HIBERN8_STATE) 105 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \ 106 UIC_LINK_BROKEN_STATE) 107 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE) 108 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \ 109 UIC_LINK_ACTIVE_STATE) 110 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \ 111 UIC_LINK_HIBERN8_STATE) 112 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \ 113 UIC_LINK_BROKEN_STATE) 114 115 #define ufshcd_set_ufs_dev_active(h) \ 116 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE) 117 #define ufshcd_set_ufs_dev_sleep(h) \ 118 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE) 119 #define ufshcd_set_ufs_dev_poweroff(h) \ 120 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE) 121 #define ufshcd_set_ufs_dev_deepsleep(h) \ 122 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE) 123 #define ufshcd_is_ufs_dev_active(h) \ 124 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE) 125 #define ufshcd_is_ufs_dev_sleep(h) \ 126 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE) 127 #define ufshcd_is_ufs_dev_poweroff(h) \ 128 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE) 129 #define ufshcd_is_ufs_dev_deepsleep(h) \ 130 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE) 131 132 /* 133 * UFS Power management levels. 134 * Each level is in increasing order of power savings, except DeepSleep 135 * which is lower than PowerDown with power on but not PowerDown with 136 * power off. 137 */ 138 enum ufs_pm_level { 139 UFS_PM_LVL_0, 140 UFS_PM_LVL_1, 141 UFS_PM_LVL_2, 142 UFS_PM_LVL_3, 143 UFS_PM_LVL_4, 144 UFS_PM_LVL_5, 145 UFS_PM_LVL_6, 146 UFS_PM_LVL_MAX 147 }; 148 149 struct ufs_pm_lvl_states { 150 enum ufs_dev_pwr_mode dev_state; 151 enum uic_link_state link_state; 152 }; 153 154 /** 155 * struct ufshcd_lrb - local reference block 156 * @utr_descriptor_ptr: UTRD address of the command 157 * @ucd_req_ptr: UCD address of the command 158 * @ucd_rsp_ptr: Response UPIU address for this command 159 * @ucd_prdt_ptr: PRDT address of the command 160 * @utrd_dma_addr: UTRD dma address for debug 161 * @ucd_prdt_dma_addr: PRDT dma address for debug 162 * @ucd_rsp_dma_addr: UPIU response dma address for debug 163 * @ucd_req_dma_addr: UPIU request dma address for debug 164 * @cmd: pointer to SCSI command 165 * @scsi_status: SCSI status of the command 166 * @command_type: SCSI, UFS, Query. 167 * @task_tag: Task tag of the command 168 * @lun: LUN of the command 169 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation) 170 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC) 171 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock) 172 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC) 173 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock) 174 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none) 175 * @data_unit_num: the data unit number for the first block for inline crypto 176 * @req_abort_skip: skip request abort task flag 177 */ 178 struct ufshcd_lrb { 179 struct utp_transfer_req_desc *utr_descriptor_ptr; 180 struct utp_upiu_req *ucd_req_ptr; 181 struct utp_upiu_rsp *ucd_rsp_ptr; 182 struct ufshcd_sg_entry *ucd_prdt_ptr; 183 184 dma_addr_t utrd_dma_addr; 185 dma_addr_t ucd_req_dma_addr; 186 dma_addr_t ucd_rsp_dma_addr; 187 dma_addr_t ucd_prdt_dma_addr; 188 189 struct scsi_cmnd *cmd; 190 int scsi_status; 191 192 int command_type; 193 int task_tag; 194 u8 lun; /* UPIU LUN id field is only 8-bit wide */ 195 bool intr_cmd; 196 ktime_t issue_time_stamp; 197 u64 issue_time_stamp_local_clock; 198 ktime_t compl_time_stamp; 199 u64 compl_time_stamp_local_clock; 200 #ifdef CONFIG_SCSI_UFS_CRYPTO 201 int crypto_key_slot; 202 u64 data_unit_num; 203 #endif 204 205 bool req_abort_skip; 206 }; 207 208 /** 209 * struct ufs_query_req - parameters for building a query request 210 * @query_func: UPIU header query function 211 * @upiu_req: the query request data 212 */ 213 struct ufs_query_req { 214 u8 query_func; 215 struct utp_upiu_query upiu_req; 216 }; 217 218 /** 219 * struct ufs_query_resp - UPIU QUERY 220 * @response: device response code 221 * @upiu_res: query response data 222 */ 223 struct ufs_query_res { 224 struct utp_upiu_query upiu_res; 225 }; 226 227 /** 228 * struct ufs_query - holds relevant data structures for query request 229 * @request: request upiu and function 230 * @descriptor: buffer for sending/receiving descriptor 231 * @response: response upiu and response 232 */ 233 struct ufs_query { 234 struct ufs_query_req request; 235 u8 *descriptor; 236 struct ufs_query_res response; 237 }; 238 239 /** 240 * struct ufs_dev_cmd - all assosiated fields with device management commands 241 * @type: device management command type - Query, NOP OUT 242 * @lock: lock to allow one command at a time 243 * @complete: internal commands completion 244 * @query: Device management query information 245 */ 246 struct ufs_dev_cmd { 247 enum dev_cmd_type type; 248 struct mutex lock; 249 struct completion *complete; 250 struct ufs_query query; 251 }; 252 253 /** 254 * struct ufs_clk_info - UFS clock related info 255 * @list: list headed by hba->clk_list_head 256 * @clk: clock node 257 * @name: clock name 258 * @max_freq: maximum frequency supported by the clock 259 * @min_freq: min frequency that can be used for clock scaling 260 * @curr_freq: indicates the current frequency that it is set to 261 * @keep_link_active: indicates that the clk should not be disabled if 262 * link is active 263 * @enabled: variable to check against multiple enable/disable 264 */ 265 struct ufs_clk_info { 266 struct list_head list; 267 struct clk *clk; 268 const char *name; 269 u32 max_freq; 270 u32 min_freq; 271 u32 curr_freq; 272 bool keep_link_active; 273 bool enabled; 274 }; 275 276 enum ufs_notify_change_status { 277 PRE_CHANGE, 278 POST_CHANGE, 279 }; 280 281 struct ufs_pa_layer_attr { 282 u32 gear_rx; 283 u32 gear_tx; 284 u32 lane_rx; 285 u32 lane_tx; 286 u32 pwr_rx; 287 u32 pwr_tx; 288 u32 hs_rate; 289 }; 290 291 struct ufs_pwr_mode_info { 292 bool is_valid; 293 struct ufs_pa_layer_attr info; 294 }; 295 296 /** 297 * struct ufs_hba_variant_ops - variant specific callbacks 298 * @name: variant name 299 * @max_num_rtt: maximum RTT supported by the host 300 * @init: called when the driver is initialized 301 * @exit: called to cleanup everything done in init 302 * @set_dma_mask: For setting another DMA mask than indicated by the 64AS 303 * capability bit. 304 * @get_ufs_hci_version: called to get UFS HCI version 305 * @clk_scale_notify: notifies that clks are scaled up/down 306 * @setup_clocks: called before touching any of the controller registers 307 * @hce_enable_notify: called before and after HCE enable bit is set to allow 308 * variant specific Uni-Pro initialization. 309 * @link_startup_notify: called before and after Link startup is carried out 310 * to allow variant specific Uni-Pro initialization. 311 * @pwr_change_notify: called before and after a power mode change 312 * is carried out to allow vendor spesific capabilities 313 * to be set. PRE_CHANGE can modify final_params based 314 * on desired_pwr_mode, but POST_CHANGE must not alter 315 * the final_params parameter 316 * @setup_xfer_req: called before any transfer request is issued 317 * to set some things 318 * @setup_task_mgmt: called before any task management request is issued 319 * to set some things 320 * @hibern8_notify: called around hibern8 enter/exit 321 * @apply_dev_quirks: called to apply device specific quirks 322 * @fixup_dev_quirks: called to modify device specific quirks 323 * @suspend: called during host controller PM callback 324 * @resume: called during host controller PM callback 325 * @dbg_register_dump: used to dump controller debug information 326 * @phy_initialization: used to initialize phys 327 * @device_reset: called to issue a reset pulse on the UFS device 328 * @config_scaling_param: called to configure clock scaling parameters 329 * @fill_crypto_prdt: initialize crypto-related fields in the PRDT 330 * @event_notify: called to notify important events 331 * @mcq_config_resource: called to configure MCQ platform resources 332 * @get_hba_mac: reports maximum number of outstanding commands supported by 333 * the controller. Should be implemented for UFSHCI 4.0 or later 334 * controllers that are not compliant with the UFSHCI 4.0 specification. 335 * @op_runtime_config: called to config Operation and runtime regs Pointers 336 * @get_outstanding_cqs: called to get outstanding completion queues 337 * @config_esi: called to config Event Specific Interrupt 338 * @config_scsi_dev: called to configure SCSI device parameters 339 * @freq_to_gear_speed: called to map clock frequency to the max supported gear speed 340 */ 341 struct ufs_hba_variant_ops { 342 const char *name; 343 int max_num_rtt; 344 int (*init)(struct ufs_hba *); 345 void (*exit)(struct ufs_hba *); 346 u32 (*get_ufs_hci_version)(struct ufs_hba *); 347 int (*set_dma_mask)(struct ufs_hba *); 348 int (*clk_scale_notify)(struct ufs_hba *, bool, unsigned long, 349 enum ufs_notify_change_status); 350 int (*setup_clocks)(struct ufs_hba *, bool, 351 enum ufs_notify_change_status); 352 int (*hce_enable_notify)(struct ufs_hba *, 353 enum ufs_notify_change_status); 354 int (*link_startup_notify)(struct ufs_hba *, 355 enum ufs_notify_change_status); 356 int (*pwr_change_notify)(struct ufs_hba *, 357 enum ufs_notify_change_status status, 358 const struct ufs_pa_layer_attr *desired_pwr_mode, 359 struct ufs_pa_layer_attr *final_params); 360 void (*setup_xfer_req)(struct ufs_hba *hba, int tag, 361 bool is_scsi_cmd); 362 void (*setup_task_mgmt)(struct ufs_hba *, int, u8); 363 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme, 364 enum ufs_notify_change_status); 365 int (*apply_dev_quirks)(struct ufs_hba *hba); 366 void (*fixup_dev_quirks)(struct ufs_hba *hba); 367 int (*suspend)(struct ufs_hba *, enum ufs_pm_op, 368 enum ufs_notify_change_status); 369 int (*resume)(struct ufs_hba *, enum ufs_pm_op); 370 void (*dbg_register_dump)(struct ufs_hba *hba); 371 int (*phy_initialization)(struct ufs_hba *); 372 int (*device_reset)(struct ufs_hba *hba); 373 void (*config_scaling_param)(struct ufs_hba *hba, 374 struct devfreq_dev_profile *profile, 375 struct devfreq_simple_ondemand_data *data); 376 int (*fill_crypto_prdt)(struct ufs_hba *hba, 377 const struct bio_crypt_ctx *crypt_ctx, 378 void *prdt, unsigned int num_segments); 379 void (*event_notify)(struct ufs_hba *hba, 380 enum ufs_event_type evt, void *data); 381 int (*mcq_config_resource)(struct ufs_hba *hba); 382 int (*get_hba_mac)(struct ufs_hba *hba); 383 int (*op_runtime_config)(struct ufs_hba *hba); 384 int (*get_outstanding_cqs)(struct ufs_hba *hba, 385 unsigned long *ocqs); 386 int (*config_esi)(struct ufs_hba *hba); 387 void (*config_scsi_dev)(struct scsi_device *sdev); 388 u32 (*freq_to_gear_speed)(struct ufs_hba *hba, unsigned long freq); 389 }; 390 391 /* clock gating state */ 392 enum clk_gating_state { 393 CLKS_OFF, 394 CLKS_ON, 395 REQ_CLKS_OFF, 396 REQ_CLKS_ON, 397 }; 398 399 /** 400 * struct ufs_clk_gating - UFS clock gating related info 401 * @gate_work: worker to turn off clocks after some delay as specified in 402 * delay_ms 403 * @ungate_work: worker to turn on clocks that will be used in case of 404 * interrupt context 405 * @clk_gating_workq: workqueue for clock gating work. 406 * @lock: serialize access to some struct ufs_clk_gating members. An outer lock 407 * relative to the host lock 408 * @state: the current clocks state 409 * @delay_ms: gating delay in ms 410 * @is_suspended: clk gating is suspended when set to 1 which can be used 411 * during suspend/resume 412 * @delay_attr: sysfs attribute to control delay_attr 413 * @enable_attr: sysfs attribute to enable/disable clock gating 414 * @is_enabled: Indicates the current status of clock gating 415 * @is_initialized: Indicates whether clock gating is initialized or not 416 * @active_reqs: number of requests that are pending and should be waited for 417 * completion before gating clocks. 418 */ 419 struct ufs_clk_gating { 420 struct delayed_work gate_work; 421 struct work_struct ungate_work; 422 struct workqueue_struct *clk_gating_workq; 423 424 spinlock_t lock; 425 426 enum clk_gating_state state; 427 unsigned long delay_ms; 428 bool is_suspended; 429 struct device_attribute delay_attr; 430 struct device_attribute enable_attr; 431 bool is_enabled; 432 bool is_initialized; 433 int active_reqs; 434 }; 435 436 /** 437 * struct ufs_clk_scaling - UFS clock scaling related data 438 * @workq: workqueue to schedule devfreq suspend/resume work 439 * @suspend_work: worker to suspend devfreq 440 * @resume_work: worker to resume devfreq 441 * @lock: serialize access to some struct ufs_clk_scaling members 442 * @active_reqs: number of requests that are pending. If this is zero when 443 * devfreq ->target() function is called then schedule "suspend_work" to 444 * suspend devfreq. 445 * @tot_busy_t: Total busy time in current polling window 446 * @window_start_t: Start time (in jiffies) of the current polling window 447 * @busy_start_t: Start time of current busy period 448 * @enable_attr: sysfs attribute to enable/disable clock scaling 449 * @saved_pwr_info: UFS power mode may also be changed during scaling and this 450 * one keeps track of previous power mode. 451 * @target_freq: frequency requested by devfreq framework 452 * @min_gear: lowest HS gear to scale down to 453 * @wb_gear: enable Write Booster when HS gear scales above or equal to it, else 454 * disable Write Booster 455 * @is_enabled: tracks if scaling is currently enabled or not, controlled by 456 * clkscale_enable sysfs node 457 * @is_allowed: tracks if scaling is currently allowed or not, used to block 458 * clock scaling which is not invoked from devfreq governor 459 * @is_initialized: Indicates whether clock scaling is initialized or not 460 * @is_busy_started: tracks if busy period has started or not 461 * @is_suspended: tracks if devfreq is suspended or not 462 */ 463 struct ufs_clk_scaling { 464 struct workqueue_struct *workq; 465 struct work_struct suspend_work; 466 struct work_struct resume_work; 467 468 spinlock_t lock; 469 470 int active_reqs; 471 unsigned long tot_busy_t; 472 ktime_t window_start_t; 473 ktime_t busy_start_t; 474 struct device_attribute enable_attr; 475 struct ufs_pa_layer_attr saved_pwr_info; 476 unsigned long target_freq; 477 u32 min_gear; 478 u32 wb_gear; 479 bool is_enabled; 480 bool is_allowed; 481 bool is_initialized; 482 bool is_busy_started; 483 bool is_suspended; 484 bool suspend_on_no_request; 485 }; 486 487 #define UFS_EVENT_HIST_LENGTH 8 488 /** 489 * struct ufs_event_hist - keeps history of errors 490 * @pos: index to indicate cyclic buffer position 491 * @val: cyclic buffer for registers value 492 * @tstamp: cyclic buffer for time stamp 493 * @cnt: error counter 494 */ 495 struct ufs_event_hist { 496 int pos; 497 u32 val[UFS_EVENT_HIST_LENGTH]; 498 u64 tstamp[UFS_EVENT_HIST_LENGTH]; 499 unsigned long long cnt; 500 }; 501 502 /** 503 * struct ufs_stats - keeps usage/err statistics 504 * @last_intr_status: record the last interrupt status. 505 * @last_intr_ts: record the last interrupt timestamp. 506 * @hibern8_exit_cnt: Counter to keep track of number of exits, 507 * reset this after link-startup. 508 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit. 509 * Clear after the first successful command completion. 510 * @event: array with event history. 511 */ 512 struct ufs_stats { 513 u32 last_intr_status; 514 u64 last_intr_ts; 515 516 u32 hibern8_exit_cnt; 517 u64 last_hibern8_exit_tstamp; 518 struct ufs_event_hist event[UFS_EVT_CNT]; 519 }; 520 521 /** 522 * enum ufshcd_state - UFS host controller state 523 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command 524 * processing. 525 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process 526 * SCSI commands. 527 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled. 528 * SCSI commands may be submitted to the controller. 529 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail 530 * newly submitted SCSI commands with error code DID_BAD_TARGET. 531 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery 532 * failed. Fail all SCSI commands with error code DID_ERROR. 533 */ 534 enum ufshcd_state { 535 UFSHCD_STATE_RESET, 536 UFSHCD_STATE_OPERATIONAL, 537 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL, 538 UFSHCD_STATE_EH_SCHEDULED_FATAL, 539 UFSHCD_STATE_ERROR, 540 }; 541 542 enum ufshcd_quirks { 543 /* Interrupt aggregation support is broken */ 544 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0, 545 546 /* 547 * delay before each dme command is required as the unipro 548 * layer has shown instabilities 549 */ 550 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1, 551 552 /* 553 * If UFS host controller is having issue in processing LCC (Line 554 * Control Command) coming from device then enable this quirk. 555 * When this quirk is enabled, host controller driver should disable 556 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE 557 * attribute of device to 0). 558 */ 559 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2, 560 561 /* 562 * The attribute PA_RXHSUNTERMCAP specifies whether or not the 563 * inbound Link supports unterminated line in HS mode. Setting this 564 * attribute to 1 fixes moving to HS gear. 565 */ 566 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3, 567 568 /* 569 * This quirk needs to be enabled if the host controller only allows 570 * accessing the peer dme attributes in AUTO mode (FAST AUTO or 571 * SLOW AUTO). 572 */ 573 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4, 574 575 /* 576 * This quirk needs to be enabled if the host controller doesn't 577 * advertise the correct version in UFS_VER register. If this quirk 578 * is enabled, standard UFS host driver will call the vendor specific 579 * ops (get_ufs_hci_version) to get the correct version. 580 */ 581 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5, 582 583 /* 584 * Clear handling for transfer/task request list is just opposite. 585 */ 586 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6, 587 588 /* 589 * This quirk needs to be enabled if host controller doesn't allow 590 * that the interrupt aggregation timer and counter are reset by s/w. 591 */ 592 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7, 593 594 /* 595 * This quirks needs to be enabled if host controller cannot be 596 * enabled via HCE register. 597 */ 598 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8, 599 600 /* 601 * This quirk needs to be enabled if the host controller regards 602 * resolution of the values of PRDTO and PRDTL in UTRD as byte. 603 */ 604 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9, 605 606 /* 607 * This quirk needs to be enabled if the host controller reports 608 * OCS FATAL ERROR with device error through sense data 609 */ 610 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10, 611 612 /* 613 * This quirk needs to be enabled if the host controller has 614 * auto-hibernate capability but it doesn't work. 615 */ 616 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11, 617 618 /* 619 * This quirk needs to disable manual flush for write booster 620 */ 621 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12, 622 623 /* 624 * This quirk needs to disable unipro timeout values 625 * before power mode change 626 */ 627 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13, 628 629 /* 630 * This quirk needs to be enabled if the host controller does not 631 * support UIC command 632 */ 633 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15, 634 635 /* 636 * This quirk needs to be enabled if the host controller cannot 637 * support physical host configuration. 638 */ 639 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16, 640 641 /* 642 * This quirk needs to be enabled if the host controller has 643 * auto-hibernate capability but it's FASTAUTO only. 644 */ 645 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18, 646 647 /* 648 * This quirk needs to be enabled if the host controller needs 649 * to reinit the device after switching to maximum gear. 650 */ 651 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19, 652 653 /* 654 * Some host raises interrupt (per queue) in addition to 655 * CQES (traditional) when ESI is disabled. 656 * Enable this quirk will disable CQES and use per queue interrupt. 657 */ 658 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20, 659 660 /* 661 * Some host does not implement SQ Run Time Command (SQRTC) register 662 * thus need this quirk to skip related flow. 663 */ 664 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21, 665 666 /* 667 * This quirk needs to be enabled if the host controller supports inline 668 * encryption but it needs to initialize the crypto capabilities in a 669 * nonstandard way and/or needs to override blk_crypto_ll_ops. If 670 * enabled, the standard code won't initialize the blk_crypto_profile; 671 * ufs_hba_variant_ops::init() must do it instead. 672 */ 673 UFSHCD_QUIRK_CUSTOM_CRYPTO_PROFILE = 1 << 22, 674 675 /* 676 * This quirk needs to be enabled if the host controller supports inline 677 * encryption but does not support the CRYPTO_GENERAL_ENABLE bit, i.e. 678 * host controller initialization fails if that bit is set. 679 */ 680 UFSHCD_QUIRK_BROKEN_CRYPTO_ENABLE = 1 << 23, 681 682 /* 683 * This quirk needs to be enabled if the host controller driver copies 684 * cryptographic keys into the PRDT in order to send them to hardware, 685 * and therefore the PRDT should be zeroized after each request (as per 686 * the standard best practice for managing keys). 687 */ 688 UFSHCD_QUIRK_KEYS_IN_PRDT = 1 << 24, 689 690 /* 691 * This quirk indicates that the controller reports the value 1 (not 692 * supported) in the Legacy Single DoorBell Support (LSDBS) bit of the 693 * Controller Capabilities register although it supports the legacy 694 * single doorbell mode. 695 */ 696 UFSHCD_QUIRK_BROKEN_LSDBS_CAP = 1 << 25, 697 }; 698 699 enum ufshcd_caps { 700 /* Allow dynamic clk gating */ 701 UFSHCD_CAP_CLK_GATING = 1 << 0, 702 703 /* Allow hiberb8 with clk gating */ 704 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1, 705 706 /* Allow dynamic clk scaling */ 707 UFSHCD_CAP_CLK_SCALING = 1 << 2, 708 709 /* Allow auto bkops to enabled during runtime suspend */ 710 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3, 711 712 /* 713 * This capability allows host controller driver to use the UFS HCI's 714 * interrupt aggregation capability. 715 * CAUTION: Enabling this might reduce overall UFS throughput. 716 */ 717 UFSHCD_CAP_INTR_AGGR = 1 << 4, 718 719 /* 720 * This capability allows the device auto-bkops to be always enabled 721 * except during suspend (both runtime and suspend). 722 * Enabling this capability means that device will always be allowed 723 * to do background operation when it's active but it might degrade 724 * the performance of ongoing read/write operations. 725 */ 726 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5, 727 728 /* 729 * This capability allows host controller driver to automatically 730 * enable runtime power management by itself instead of waiting 731 * for userspace to control the power management. 732 */ 733 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6, 734 735 /* 736 * This capability allows the host controller driver to turn-on 737 * WriteBooster, if the underlying device supports it and is 738 * provisioned to be used. This would increase the write performance. 739 */ 740 UFSHCD_CAP_WB_EN = 1 << 7, 741 742 /* 743 * This capability allows the host controller driver to use the 744 * inline crypto engine, if it is present 745 */ 746 UFSHCD_CAP_CRYPTO = 1 << 8, 747 748 /* 749 * This capability allows the controller regulators to be put into 750 * lpm mode aggressively during clock gating. 751 * This would increase power savings. 752 */ 753 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9, 754 755 /* 756 * This capability allows the host controller driver to use DeepSleep, 757 * if it is supported by the UFS device. The host controller driver must 758 * support device hardware reset via the hba->device_reset() callback, 759 * in order to exit DeepSleep state. 760 */ 761 UFSHCD_CAP_DEEPSLEEP = 1 << 10, 762 763 /* 764 * This capability allows the host controller driver to use temperature 765 * notification if it is supported by the UFS device. 766 */ 767 UFSHCD_CAP_TEMP_NOTIF = 1 << 11, 768 769 /* 770 * Enable WriteBooster when scaling up the clock and disable 771 * WriteBooster when scaling the clock down. 772 */ 773 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12, 774 }; 775 776 struct ufs_hba_variant_params { 777 struct devfreq_dev_profile devfreq_profile; 778 struct devfreq_simple_ondemand_data ondemand_data; 779 u16 hba_enable_delay_us; 780 u32 wb_flush_threshold; 781 }; 782 783 struct ufs_hba_monitor { 784 unsigned long chunk_size; 785 786 unsigned long nr_sec_rw[2]; 787 ktime_t total_busy[2]; 788 789 unsigned long nr_req[2]; 790 /* latencies*/ 791 ktime_t lat_sum[2]; 792 ktime_t lat_max[2]; 793 ktime_t lat_min[2]; 794 795 u32 nr_queued[2]; 796 ktime_t busy_start_ts[2]; 797 798 ktime_t enabled_ts; 799 bool enabled; 800 }; 801 802 /** 803 * struct ufshcd_res_info_t - MCQ related resource regions 804 * 805 * @name: resource name 806 * @resource: pointer to resource region 807 * @base: register base address 808 */ 809 struct ufshcd_res_info { 810 const char *name; 811 struct resource *resource; 812 void __iomem *base; 813 }; 814 815 enum ufshcd_res { 816 RES_UFS, 817 RES_MCQ, 818 RES_MCQ_SQD, 819 RES_MCQ_SQIS, 820 RES_MCQ_CQD, 821 RES_MCQ_CQIS, 822 RES_MCQ_VS, 823 RES_MAX, 824 }; 825 826 /** 827 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers 828 * 829 * @offset: Doorbell Address Offset 830 * @stride: Steps proportional to queue [0...31] 831 * @base: base address 832 */ 833 struct ufshcd_mcq_opr_info_t { 834 unsigned long offset; 835 unsigned long stride; 836 void __iomem *base; 837 }; 838 839 enum ufshcd_mcq_opr { 840 OPR_SQD, 841 OPR_SQIS, 842 OPR_CQD, 843 OPR_CQIS, 844 OPR_MAX, 845 }; 846 847 /** 848 * struct ufs_hba - per adapter private structure 849 * @mmio_base: UFSHCI base register address 850 * @ucdl_base_addr: UFS Command Descriptor base address 851 * @utrdl_base_addr: UTP Transfer Request Descriptor base address 852 * @utmrdl_base_addr: UTP Task Management Descriptor base address 853 * @ucdl_dma_addr: UFS Command Descriptor DMA address 854 * @utrdl_dma_addr: UTRDL DMA address 855 * @utmrdl_dma_addr: UTMRDL DMA address 856 * @host: Scsi_Host instance of the driver 857 * @dev: device handle 858 * @ufs_device_wlun: WLUN that controls the entire UFS device. 859 * @hwmon_device: device instance registered with the hwmon core. 860 * @curr_dev_pwr_mode: active UFS device power mode. 861 * @uic_link_state: active state of the link to the UFS device. 862 * @rpm_lvl: desired UFS power management level during runtime PM. 863 * @spm_lvl: desired UFS power management level during system PM. 864 * @pm_op_in_progress: whether or not a PM operation is in progress. 865 * @ahit: value of Auto-Hibernate Idle Timer register. 866 * @lrb: local reference block 867 * @outstanding_tasks: Bits representing outstanding task requests 868 * @outstanding_lock: Protects @outstanding_reqs. 869 * @outstanding_reqs: Bits representing outstanding transfer requests 870 * @capabilities: UFS Controller Capabilities 871 * @mcq_capabilities: UFS Multi Circular Queue capabilities 872 * @nutrs: Transfer Request Queue depth supported by controller 873 * @nortt - Max outstanding RTTs supported by controller 874 * @nutmrs: Task Management Queue depth supported by controller 875 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock. 876 * @ufs_version: UFS Version to which controller complies 877 * @vops: pointer to variant specific operations 878 * @vps: pointer to variant specific parameters 879 * @priv: pointer to variant specific private data 880 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields) 881 * @irq: Irq number of the controller 882 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled. 883 * @dev_ref_clk_freq: reference clock frequency 884 * @quirks: bitmask with information about deviations from the UFSHCI standard. 885 * @dev_quirks: bitmask with information about deviations from the UFS standard. 886 * @tmf_tag_set: TMF tag set. 887 * @tmf_queue: Used to allocate TMF tags. 888 * @tmf_rqs: array with pointers to TMF requests while these are in progress. 889 * @active_uic_cmd: pointer to active UIC command. 890 * @uic_cmd_mutex: mutex used for serializing UIC command processing. 891 * @uic_async_done: completion used to wait for power mode or hibernation state 892 * changes. 893 * @ufshcd_state: UFSHCD state 894 * @eh_flags: Error handling flags 895 * @intr_mask: Interrupt Mask Bits 896 * @ee_ctrl_mask: Exception event control mask 897 * @ee_drv_mask: Exception event mask for driver 898 * @ee_usr_mask: Exception event mask for user (set via debugfs) 899 * @ee_ctrl_mutex: Used to serialize exception event information. 900 * @is_powered: flag to check if HBA is powered 901 * @shutting_down: flag to check if shutdown has been invoked 902 * @host_sem: semaphore used to serialize concurrent contexts 903 * @eh_wq: Workqueue that eh_work works on 904 * @eh_work: Worker to handle UFS errors that require s/w attention 905 * @eeh_work: Worker to handle exception events 906 * @errors: HBA errors 907 * @uic_error: UFS interconnect layer error status 908 * @saved_err: sticky error mask 909 * @saved_uic_err: sticky UIC error mask 910 * @ufs_stats: various error counters 911 * @force_reset: flag to force eh_work perform a full reset 912 * @force_pmc: flag to force a power mode change 913 * @silence_err_logs: flag to silence error logs 914 * @dev_cmd: ufs device management command information 915 * @last_dme_cmd_tstamp: time stamp of the last completed DME command 916 * @nop_out_timeout: NOP OUT timeout value 917 * @dev_info: information about the UFS device 918 * @auto_bkops_enabled: to track whether bkops is enabled in device 919 * @vreg_info: UFS device voltage regulator information 920 * @clk_list_head: UFS host controller clocks list node head 921 * @use_pm_opp: Indicates whether OPP based scaling is used or not 922 * @req_abort_count: number of times ufshcd_abort() has been called 923 * @lanes_per_direction: number of lanes per data direction between the UFS 924 * controller and the UFS device. 925 * @pwr_info: holds current power mode 926 * @max_pwr_info: keeps the device max valid pwm 927 * @clk_gating: information related to clock gating 928 * @caps: bitmask with information about UFS controller capabilities 929 * @devfreq: frequency scaling information owned by the devfreq core 930 * @clk_scaling: frequency scaling information owned by the UFS driver 931 * @system_suspending: system suspend has been started and system resume has 932 * not yet finished. 933 * @is_sys_suspended: UFS device has been suspended because of system suspend 934 * @urgent_bkops_lvl: keeps track of urgent bkops level for device 935 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for 936 * device is known or not. 937 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling 938 * @clk_scaling_lock: used to serialize device commands and clock scaling 939 * @desc_size: descriptor sizes reported by device 940 * @bsg_dev: struct device associated with the BSG queue 941 * @bsg_queue: BSG queue associated with the UFS controller 942 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power 943 * management) after the UFS device has finished a WriteBooster buffer 944 * flush or auto BKOP. 945 * @monitor: statistics about UFS commands 946 * @crypto_capabilities: Content of crypto capabilities register (0x100) 947 * @crypto_cap_array: Array of crypto capabilities 948 * @crypto_cfg_register: Start of the crypto cfg array 949 * @crypto_profile: the crypto profile of this hba (if applicable) 950 * @debugfs_root: UFS controller debugfs root directory 951 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay 952 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore 953 * ee_ctrl_mask 954 * @luns_avail: number of regular and well known LUNs supported by the UFS 955 * device 956 * @nr_hw_queues: number of hardware queues configured 957 * @nr_queues: number of Queues of different queue types 958 * @complete_put: whether or not to call ufshcd_rpm_put() from inside 959 * ufshcd_resume_complete() 960 * @mcq_sup: is mcq supported by UFSHC 961 * @mcq_enabled: is mcq ready to accept requests 962 * @res: array of resource info of MCQ registers 963 * @mcq_base: Multi circular queue registers base address 964 * @uhq: array of supported hardware queues 965 * @dev_cmd_queue: Queue for issuing device management commands 966 * @mcq_opr: MCQ operation and runtime registers 967 * @ufs_rtc_update_work: A work for UFS RTC periodic update 968 * @pm_qos_req: PM QoS request handle 969 * @pm_qos_enabled: flag to check if pm qos is enabled 970 * @critical_health_count: count of critical health exceptions 971 */ 972 struct ufs_hba { 973 void __iomem *mmio_base; 974 975 /* Virtual memory reference */ 976 struct utp_transfer_cmd_desc *ucdl_base_addr; 977 struct utp_transfer_req_desc *utrdl_base_addr; 978 struct utp_task_req_desc *utmrdl_base_addr; 979 980 /* DMA memory reference */ 981 dma_addr_t ucdl_dma_addr; 982 dma_addr_t utrdl_dma_addr; 983 dma_addr_t utmrdl_dma_addr; 984 985 struct Scsi_Host *host; 986 struct device *dev; 987 struct scsi_device *ufs_device_wlun; 988 989 #ifdef CONFIG_SCSI_UFS_HWMON 990 struct device *hwmon_device; 991 #endif 992 993 enum ufs_dev_pwr_mode curr_dev_pwr_mode; 994 enum uic_link_state uic_link_state; 995 /* Desired UFS power management level during runtime PM */ 996 enum ufs_pm_level rpm_lvl; 997 /* Desired UFS power management level during system PM */ 998 enum ufs_pm_level spm_lvl; 999 int pm_op_in_progress; 1000 1001 /* Auto-Hibernate Idle Timer register value */ 1002 u32 ahit; 1003 1004 struct ufshcd_lrb *lrb; 1005 1006 unsigned long outstanding_tasks; 1007 spinlock_t outstanding_lock; 1008 unsigned long outstanding_reqs; 1009 1010 u32 capabilities; 1011 int nutrs; 1012 int nortt; 1013 u32 mcq_capabilities; 1014 int nutmrs; 1015 u32 reserved_slot; 1016 u32 ufs_version; 1017 const struct ufs_hba_variant_ops *vops; 1018 struct ufs_hba_variant_params *vps; 1019 void *priv; 1020 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1021 size_t sg_entry_size; 1022 #endif 1023 unsigned int irq; 1024 bool is_irq_enabled; 1025 enum ufs_ref_clk_freq dev_ref_clk_freq; 1026 1027 unsigned int quirks; /* Deviations from standard UFSHCI spec. */ 1028 1029 /* Device deviations from standard UFS device spec. */ 1030 unsigned int dev_quirks; 1031 1032 struct blk_mq_tag_set tmf_tag_set; 1033 struct request_queue *tmf_queue; 1034 struct request **tmf_rqs; 1035 1036 struct uic_command *active_uic_cmd; 1037 struct mutex uic_cmd_mutex; 1038 struct completion *uic_async_done; 1039 1040 enum ufshcd_state ufshcd_state; 1041 u32 eh_flags; 1042 u32 intr_mask; 1043 u16 ee_ctrl_mask; 1044 u16 ee_drv_mask; 1045 u16 ee_usr_mask; 1046 struct mutex ee_ctrl_mutex; 1047 bool is_powered; 1048 bool shutting_down; 1049 struct semaphore host_sem; 1050 1051 /* Work Queues */ 1052 struct workqueue_struct *eh_wq; 1053 struct work_struct eh_work; 1054 struct work_struct eeh_work; 1055 1056 /* HBA Errors */ 1057 u32 errors; 1058 u32 uic_error; 1059 u32 saved_err; 1060 u32 saved_uic_err; 1061 struct ufs_stats ufs_stats; 1062 bool force_reset; 1063 bool force_pmc; 1064 bool silence_err_logs; 1065 1066 /* Device management request data */ 1067 struct ufs_dev_cmd dev_cmd; 1068 ktime_t last_dme_cmd_tstamp; 1069 int nop_out_timeout; 1070 1071 /* Keeps information of the UFS device connected to this host */ 1072 struct ufs_dev_info dev_info; 1073 bool auto_bkops_enabled; 1074 struct ufs_vreg_info vreg_info; 1075 struct list_head clk_list_head; 1076 bool use_pm_opp; 1077 1078 /* Number of requests aborts */ 1079 int req_abort_count; 1080 1081 /* Number of lanes available (1 or 2) for Rx/Tx */ 1082 u32 lanes_per_direction; 1083 struct ufs_pa_layer_attr pwr_info; 1084 struct ufs_pwr_mode_info max_pwr_info; 1085 1086 struct ufs_clk_gating clk_gating; 1087 /* Control to enable/disable host capabilities */ 1088 u32 caps; 1089 1090 struct devfreq *devfreq; 1091 struct ufs_clk_scaling clk_scaling; 1092 bool system_suspending; 1093 bool is_sys_suspended; 1094 1095 enum bkops_status urgent_bkops_lvl; 1096 bool is_urgent_bkops_lvl_checked; 1097 1098 struct mutex wb_mutex; 1099 struct rw_semaphore clk_scaling_lock; 1100 1101 struct device bsg_dev; 1102 struct request_queue *bsg_queue; 1103 struct delayed_work rpm_dev_flush_recheck_work; 1104 1105 struct ufs_hba_monitor monitor; 1106 1107 #ifdef CONFIG_SCSI_UFS_CRYPTO 1108 union ufs_crypto_capabilities crypto_capabilities; 1109 union ufs_crypto_cap_entry *crypto_cap_array; 1110 u32 crypto_cfg_register; 1111 struct blk_crypto_profile crypto_profile; 1112 #endif 1113 #ifdef CONFIG_DEBUG_FS 1114 struct dentry *debugfs_root; 1115 struct delayed_work debugfs_ee_work; 1116 u32 debugfs_ee_rate_limit_ms; 1117 #endif 1118 #ifdef CONFIG_SCSI_UFS_FAULT_INJECTION 1119 struct fault_attr trigger_eh_attr; 1120 struct fault_attr timeout_attr; 1121 #endif 1122 u32 luns_avail; 1123 unsigned int nr_hw_queues; 1124 unsigned int nr_queues[HCTX_MAX_TYPES]; 1125 bool complete_put; 1126 bool scsi_host_added; 1127 bool mcq_sup; 1128 bool lsdb_sup; 1129 bool mcq_enabled; 1130 struct ufshcd_res_info res[RES_MAX]; 1131 void __iomem *mcq_base; 1132 struct ufs_hw_queue *uhq; 1133 struct ufs_hw_queue *dev_cmd_queue; 1134 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX]; 1135 1136 struct delayed_work ufs_rtc_update_work; 1137 struct pm_qos_request pm_qos_req; 1138 bool pm_qos_enabled; 1139 1140 int critical_health_count; 1141 }; 1142 1143 /** 1144 * struct ufs_hw_queue - per hardware queue structure 1145 * @mcq_sq_head: base address of submission queue head pointer 1146 * @mcq_sq_tail: base address of submission queue tail pointer 1147 * @mcq_cq_head: base address of completion queue head pointer 1148 * @mcq_cq_tail: base address of completion queue tail pointer 1149 * @sqe_base_addr: submission queue entry base address 1150 * @sqe_dma_addr: submission queue dma address 1151 * @cqe_base_addr: completion queue base address 1152 * @cqe_dma_addr: completion queue dma address 1153 * @max_entries: max number of slots in this hardware queue 1154 * @id: hardware queue ID 1155 * @sq_tp_slot: current slot to which SQ tail pointer is pointing 1156 * @sq_lock: serialize submission queue access 1157 * @cq_tail_slot: current slot to which CQ tail pointer is pointing 1158 * @cq_head_slot: current slot to which CQ head pointer is pointing 1159 * @cq_lock: Synchronize between multiple polling instances 1160 * @sq_mutex: prevent submission queue concurrent access 1161 */ 1162 struct ufs_hw_queue { 1163 void __iomem *mcq_sq_head; 1164 void __iomem *mcq_sq_tail; 1165 void __iomem *mcq_cq_head; 1166 void __iomem *mcq_cq_tail; 1167 1168 struct utp_transfer_req_desc *sqe_base_addr; 1169 dma_addr_t sqe_dma_addr; 1170 struct cq_entry *cqe_base_addr; 1171 dma_addr_t cqe_dma_addr; 1172 u32 max_entries; 1173 u32 id; 1174 u32 sq_tail_slot; 1175 spinlock_t sq_lock; 1176 u32 cq_tail_slot; 1177 u32 cq_head_slot; 1178 spinlock_t cq_lock; 1179 /* prevent concurrent access to submission queue */ 1180 struct mutex sq_mutex; 1181 }; 1182 1183 #define MCQ_QCFG_SIZE 0x40 1184 1185 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba, 1186 enum ufshcd_mcq_opr opr, int idx) 1187 { 1188 return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx; 1189 } 1190 1191 static inline unsigned int ufshcd_mcq_cfg_offset(unsigned int reg, int idx) 1192 { 1193 return reg + MCQ_QCFG_SIZE * idx; 1194 } 1195 1196 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE 1197 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1198 { 1199 return hba->sg_entry_size; 1200 } 1201 1202 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size) 1203 { 1204 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry)); 1205 hba->sg_entry_size = sg_entry_size; 1206 } 1207 #else 1208 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba) 1209 { 1210 return sizeof(struct ufshcd_sg_entry); 1211 } 1212 1213 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \ 1214 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); }) 1215 #endif 1216 1217 #ifdef CONFIG_SCSI_UFS_CRYPTO 1218 static inline struct ufs_hba * 1219 ufs_hba_from_crypto_profile(struct blk_crypto_profile *profile) 1220 { 1221 return container_of(profile, struct ufs_hba, crypto_profile); 1222 } 1223 #endif 1224 1225 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba) 1226 { 1227 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba); 1228 } 1229 1230 /* Returns true if clocks can be gated. Otherwise false */ 1231 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba) 1232 { 1233 return hba->caps & UFSHCD_CAP_CLK_GATING; 1234 } 1235 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba) 1236 { 1237 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; 1238 } 1239 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba) 1240 { 1241 return hba->caps & UFSHCD_CAP_CLK_SCALING; 1242 } 1243 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba) 1244 { 1245 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND; 1246 } 1247 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba) 1248 { 1249 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND; 1250 } 1251 1252 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba) 1253 { 1254 return (hba->caps & UFSHCD_CAP_INTR_AGGR) && 1255 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR); 1256 } 1257 1258 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba) 1259 { 1260 return !!(ufshcd_is_link_hibern8(hba) && 1261 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE)); 1262 } 1263 1264 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba) 1265 { 1266 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) && 1267 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8); 1268 } 1269 1270 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba) 1271 { 1272 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit); 1273 } 1274 1275 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba) 1276 { 1277 return hba->caps & UFSHCD_CAP_WB_EN; 1278 } 1279 1280 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba) 1281 { 1282 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING; 1283 } 1284 1285 #define ufsmcq_writel(hba, val, reg) \ 1286 writel((val), (hba)->mcq_base + (reg)) 1287 #define ufsmcq_readl(hba, reg) \ 1288 readl((hba)->mcq_base + (reg)) 1289 1290 #define ufsmcq_writelx(hba, val, reg) \ 1291 writel_relaxed((val), (hba)->mcq_base + (reg)) 1292 #define ufsmcq_readlx(hba, reg) \ 1293 readl_relaxed((hba)->mcq_base + (reg)) 1294 1295 #define ufshcd_writel(hba, val, reg) \ 1296 writel((val), (hba)->mmio_base + (reg)) 1297 #define ufshcd_readl(hba, reg) \ 1298 readl((hba)->mmio_base + (reg)) 1299 1300 /** 1301 * ufshcd_rmwl - perform read/modify/write for a controller register 1302 * @hba: per adapter instance 1303 * @mask: mask to apply on read value 1304 * @val: actual value to write 1305 * @reg: register address 1306 */ 1307 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg) 1308 { 1309 u32 tmp; 1310 1311 tmp = ufshcd_readl(hba, reg); 1312 tmp &= ~mask; 1313 tmp |= (val & mask); 1314 ufshcd_writel(hba, tmp, reg); 1315 } 1316 1317 void ufshcd_enable_irq(struct ufs_hba *hba); 1318 void ufshcd_disable_irq(struct ufs_hba *hba); 1319 int ufshcd_alloc_host(struct device *, struct ufs_hba **); 1320 int ufshcd_hba_enable(struct ufs_hba *hba); 1321 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int); 1322 int ufshcd_link_recovery(struct ufs_hba *hba); 1323 int ufshcd_make_hba_operational(struct ufs_hba *hba); 1324 void ufshcd_remove(struct ufs_hba *); 1325 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba); 1326 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba); 1327 void ufshcd_delay_us(unsigned long us, unsigned long tolerance); 1328 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk); 1329 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val); 1330 void ufshcd_hba_stop(struct ufs_hba *hba); 1331 void ufshcd_schedule_eh_work(struct ufs_hba *hba); 1332 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds); 1333 unsigned int ufshcd_mcq_queue_cfg_addr(struct ufs_hba *hba); 1334 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i); 1335 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i); 1336 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba, 1337 struct ufs_hw_queue *hwq); 1338 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba); 1339 void ufshcd_mcq_enable(struct ufs_hba *hba); 1340 void ufshcd_mcq_enable_esi(struct ufs_hba *hba); 1341 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg); 1342 1343 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1344 struct dev_pm_opp *opp, void *data, 1345 bool scaling_down); 1346 /** 1347 * ufshcd_set_variant - set variant specific data to the hba 1348 * @hba: per adapter instance 1349 * @variant: pointer to variant specific data 1350 */ 1351 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant) 1352 { 1353 BUG_ON(!hba); 1354 hba->priv = variant; 1355 } 1356 1357 /** 1358 * ufshcd_get_variant - get variant specific data from the hba 1359 * @hba: per adapter instance 1360 */ 1361 static inline void *ufshcd_get_variant(struct ufs_hba *hba) 1362 { 1363 BUG_ON(!hba); 1364 return hba->priv; 1365 } 1366 1367 #ifdef CONFIG_PM 1368 extern int ufshcd_runtime_suspend(struct device *dev); 1369 extern int ufshcd_runtime_resume(struct device *dev); 1370 #endif 1371 #ifdef CONFIG_PM_SLEEP 1372 extern int ufshcd_system_suspend(struct device *dev); 1373 extern int ufshcd_system_resume(struct device *dev); 1374 extern int ufshcd_system_freeze(struct device *dev); 1375 extern int ufshcd_system_thaw(struct device *dev); 1376 extern int ufshcd_system_restore(struct device *dev); 1377 #endif 1378 1379 extern int ufshcd_dme_reset(struct ufs_hba *hba); 1380 extern int ufshcd_dme_enable(struct ufs_hba *hba); 1381 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 1382 int agreed_gear, 1383 int adapt_val); 1384 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 1385 u8 attr_set, u32 mib_val, u8 peer); 1386 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 1387 u32 *mib_val, u8 peer); 1388 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba, 1389 struct ufs_pa_layer_attr *desired_pwr_mode); 1390 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode); 1391 1392 /* UIC command interfaces for DME primitives */ 1393 #define DME_LOCAL 0 1394 #define DME_PEER 1 1395 #define ATTR_SET_NOR 0 /* NORMAL */ 1396 #define ATTR_SET_ST 1 /* STATIC */ 1397 1398 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel, 1399 u32 mib_val) 1400 { 1401 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1402 mib_val, DME_LOCAL); 1403 } 1404 1405 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel, 1406 u32 mib_val) 1407 { 1408 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1409 mib_val, DME_LOCAL); 1410 } 1411 1412 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel, 1413 u32 mib_val) 1414 { 1415 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR, 1416 mib_val, DME_PEER); 1417 } 1418 1419 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel, 1420 u32 mib_val) 1421 { 1422 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST, 1423 mib_val, DME_PEER); 1424 } 1425 1426 static inline int ufshcd_dme_get(struct ufs_hba *hba, 1427 u32 attr_sel, u32 *mib_val) 1428 { 1429 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL); 1430 } 1431 1432 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba, 1433 u32 attr_sel, u32 *mib_val) 1434 { 1435 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER); 1436 } 1437 1438 static inline bool ufshcd_is_hs_mode(const struct ufs_pa_layer_attr *pwr_info) 1439 { 1440 return (pwr_info->pwr_rx == FAST_MODE || 1441 pwr_info->pwr_rx == FASTAUTO_MODE) && 1442 (pwr_info->pwr_tx == FAST_MODE || 1443 pwr_info->pwr_tx == FASTAUTO_MODE); 1444 } 1445 1446 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba) 1447 { 1448 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0); 1449 } 1450 1451 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit); 1452 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 1453 const struct ufs_dev_quirk *fixups); 1454 #define SD_ASCII_STD true 1455 #define SD_RAW false 1456 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 1457 u8 **buf, bool ascii); 1458 1459 void ufshcd_hold(struct ufs_hba *hba); 1460 void ufshcd_release(struct ufs_hba *hba); 1461 1462 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value); 1463 1464 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg); 1465 1466 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd); 1467 1468 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 1469 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req, 1470 struct ufs_ehs *ehs_rsp, int sg_cnt, 1471 struct scatterlist *sg_list, enum dma_data_direction dir); 1472 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable); 1473 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable); 1474 int ufshcd_suspend_prepare(struct device *dev); 1475 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm); 1476 void ufshcd_resume_complete(struct device *dev); 1477 bool ufshcd_is_hba_active(struct ufs_hba *hba); 1478 void ufshcd_pm_qos_init(struct ufs_hba *hba); 1479 void ufshcd_pm_qos_exit(struct ufs_hba *hba); 1480 1481 /* Wrapper functions for safely calling variant operations */ 1482 static inline int ufshcd_vops_init(struct ufs_hba *hba) 1483 { 1484 if (hba->vops && hba->vops->init) 1485 return hba->vops->init(hba); 1486 1487 return 0; 1488 } 1489 1490 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba) 1491 { 1492 if (hba->vops && hba->vops->phy_initialization) 1493 return hba->vops->phy_initialization(hba); 1494 1495 return 0; 1496 } 1497 1498 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[]; 1499 1500 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 1501 const char *prefix); 1502 1503 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask); 1504 int ufshcd_write_ee_control(struct ufs_hba *hba); 1505 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 1506 const u16 *other_mask, u16 set, u16 clr); 1507 1508 #endif /* End of Header */ 1509