1dc3bf49eSMasahiro Yamada /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 253e0c72dSLiam Girdwood /* 353e0c72dSLiam Girdwood * This file is provided under a dual BSD/GPLv2 license. When using or 453e0c72dSLiam Girdwood * redistributing this file, you may do so under either license. 553e0c72dSLiam Girdwood * 653e0c72dSLiam Girdwood * Copyright(c) 2018 Intel Corporation. All rights reserved. 753e0c72dSLiam Girdwood */ 853e0c72dSLiam Girdwood 953e0c72dSLiam Girdwood #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 1053e0c72dSLiam Girdwood #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ 1153e0c72dSLiam Girdwood 1253e0c72dSLiam Girdwood #include <sound/sof/header.h> 1353e0c72dSLiam Girdwood 1453e0c72dSLiam Girdwood /* ssc1: TINTE */ 1553e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) 1653e0c72dSLiam Girdwood /* ssc1: PINTE */ 1753e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) 1853e0c72dSLiam Girdwood /* ssc2: SMTATF */ 1953e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) 2053e0c72dSLiam Girdwood /* ssc2: MMRATF */ 2153e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) 2253e0c72dSLiam Girdwood /* ssc2: PSPSTWFDFD */ 2353e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) 2453e0c72dSLiam Girdwood /* ssc2: PSPSRWFDFD */ 2553e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) 2653e0c72dSLiam Girdwood /* ssc1: LBM */ 2753e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) 2853e0c72dSLiam Girdwood 2953e0c72dSLiam Girdwood /* here is the possibility to define others aux macros */ 3053e0c72dSLiam Girdwood 3153e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 3253e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 3353e0c72dSLiam Girdwood 3453e0c72dSLiam Girdwood /* SSP clocks control settings 3553e0c72dSLiam Girdwood * 3653e0c72dSLiam Girdwood * Macros for clks_control field in sof_ipc_dai_ssp_params struct. 3753e0c72dSLiam Girdwood */ 3853e0c72dSLiam Girdwood 3953e0c72dSLiam Girdwood /* mclk 0 disable */ 4053e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) 4153e0c72dSLiam Girdwood /* mclk 1 disable */ 4253e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) 4353e0c72dSLiam Girdwood /* mclk keep active */ 4453e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) 4553e0c72dSLiam Girdwood /* bclk keep active */ 4653e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) 4753e0c72dSLiam Girdwood /* fs keep active */ 4853e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) 4953e0c72dSLiam Girdwood /* bclk idle */ 5053e0c72dSLiam Girdwood #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 5153e0c72dSLiam Girdwood 5253e0c72dSLiam Girdwood /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ 5353e0c72dSLiam Girdwood struct sof_ipc_dai_ssp_params { 5453e0c72dSLiam Girdwood struct sof_ipc_hdr hdr; 5553e0c72dSLiam Girdwood uint16_t reserved1; 5653e0c72dSLiam Girdwood uint16_t mclk_id; 5753e0c72dSLiam Girdwood 5853e0c72dSLiam Girdwood uint32_t mclk_rate; /* mclk frequency in Hz */ 5953e0c72dSLiam Girdwood uint32_t fsync_rate; /* fsync frequency in Hz */ 6053e0c72dSLiam Girdwood uint32_t bclk_rate; /* bclk frequency in Hz */ 6153e0c72dSLiam Girdwood 6253e0c72dSLiam Girdwood /* TDM */ 6353e0c72dSLiam Girdwood uint32_t tdm_slots; 6453e0c72dSLiam Girdwood uint32_t rx_slots; 6553e0c72dSLiam Girdwood uint32_t tx_slots; 6653e0c72dSLiam Girdwood 6753e0c72dSLiam Girdwood /* data */ 6853e0c72dSLiam Girdwood uint32_t sample_valid_bits; 6953e0c72dSLiam Girdwood uint16_t tdm_slot_width; 7053e0c72dSLiam Girdwood uint16_t reserved2; /* alignment */ 7153e0c72dSLiam Girdwood 7253e0c72dSLiam Girdwood /* MCLK */ 7353e0c72dSLiam Girdwood uint32_t mclk_direction; 7453e0c72dSLiam Girdwood 7553e0c72dSLiam Girdwood uint16_t frame_pulse_width; 7653e0c72dSLiam Girdwood uint16_t tdm_per_slot_padding_flag; 7753e0c72dSLiam Girdwood uint32_t clks_control; 7853e0c72dSLiam Girdwood uint32_t quirks; 796298b787SJanusz Jankowski uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 806298b787SJanusz Jankowski * will be driven, before sending data 816298b787SJanusz Jankowski */ 8253e0c72dSLiam Girdwood } __packed; 8353e0c72dSLiam Girdwood 8453e0c72dSLiam Girdwood /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ 8553e0c72dSLiam Girdwood struct sof_ipc_dai_hda_params { 8653e0c72dSLiam Girdwood struct sof_ipc_hdr hdr; 8753e0c72dSLiam Girdwood uint32_t link_dma_ch; 8853e0c72dSLiam Girdwood } __packed; 8953e0c72dSLiam Girdwood 90f8e25018SPierre-Louis Bossart /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 91f8e25018SPierre-Louis Bossart struct sof_ipc_dai_alh_params { 92f8e25018SPierre-Louis Bossart struct sof_ipc_hdr hdr; 93f8e25018SPierre-Louis Bossart uint32_t stream_id; 94f8e25018SPierre-Louis Bossart 95f8e25018SPierre-Louis Bossart /* reserved for future use */ 96f8e25018SPierre-Louis Bossart uint32_t reserved[15]; 97f8e25018SPierre-Louis Bossart } __packed; 98f8e25018SPierre-Louis Bossart 9953e0c72dSLiam Girdwood /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ 10053e0c72dSLiam Girdwood 10153e0c72dSLiam Girdwood /* This struct is defined per 2ch PDM controller available in the platform. 10253e0c72dSLiam Girdwood * Normally it is sufficient to set the used microphone specific enables to 1 10353e0c72dSLiam Girdwood * and keep other parameters as zero. The customizations are: 10453e0c72dSLiam Girdwood * 10553e0c72dSLiam Girdwood * 1. If a device mixes different microphones types with different polarity 10653e0c72dSLiam Girdwood * and/or the absolute polarity matters the PCM signal from a microphone 10753e0c72dSLiam Girdwood * can be inverted with the controls. 10853e0c72dSLiam Girdwood * 10953e0c72dSLiam Girdwood * 2. If the microphones in a stereo pair do not appear in captured stream 11053e0c72dSLiam Girdwood * in desired order due to board schematics choises they can be swapped with 11153e0c72dSLiam Girdwood * the clk_edge parameter. 11253e0c72dSLiam Girdwood * 11353e0c72dSLiam Girdwood * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter 11453e0c72dSLiam Girdwood * that delays the sampling time of data by half cycles of DMIC source clock 11553e0c72dSLiam Girdwood * can be tried for improvement. However there is no guarantee for this to fix 11653e0c72dSLiam Girdwood * data integrity problems. 11753e0c72dSLiam Girdwood */ 11853e0c72dSLiam Girdwood struct sof_ipc_dai_dmic_pdm_ctrl { 11953e0c72dSLiam Girdwood struct sof_ipc_hdr hdr; 12053e0c72dSLiam Girdwood uint16_t id; /**< PDM controller ID */ 12153e0c72dSLiam Girdwood 12253e0c72dSLiam Girdwood uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ 12353e0c72dSLiam Girdwood uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ 12453e0c72dSLiam Girdwood 12553e0c72dSLiam Girdwood uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ 12653e0c72dSLiam Girdwood uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ 12753e0c72dSLiam Girdwood 12853e0c72dSLiam Girdwood uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ 12953e0c72dSLiam Girdwood uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ 13053e0c72dSLiam Girdwood 13153e0c72dSLiam Girdwood uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ 13253e0c72dSLiam Girdwood } __packed; 13353e0c72dSLiam Girdwood 13453e0c72dSLiam Girdwood /* This struct contains the global settings for all 2ch PDM controllers. The 13553e0c72dSLiam Girdwood * version number used in configuration data is checked vs. version used by 13653e0c72dSLiam Girdwood * device driver src/drivers/dmic.c need to match. It is incremented from 13753e0c72dSLiam Girdwood * initial value 1 if updates done for the to driver would alter the operation 138*79a4ff94SSeppo Ingalsuo * of the microphone. 13953e0c72dSLiam Girdwood * 14053e0c72dSLiam Girdwood * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) 14153e0c72dSLiam Girdwood * parameters need to be set as defined in microphone data sheet. E.g. clock 14253e0c72dSLiam Girdwood * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are 14353e0c72dSLiam Girdwood * multi-mode capable and there may be denied mic clock frequencies between 14453e0c72dSLiam Girdwood * the modes. In such case set the clock range limits of the desired mode to 14553e0c72dSLiam Girdwood * avoid the driver to set clock to an illegal rate. 14653e0c72dSLiam Girdwood * 14753e0c72dSLiam Girdwood * The duty cycle could be set to 48-52% if not known. Generally these 14853e0c72dSLiam Girdwood * parameters can be altered within data sheet specified limits to match 14953e0c72dSLiam Girdwood * required audio application performance power. 15053e0c72dSLiam Girdwood * 15153e0c72dSLiam Girdwood * The microphone clock needs to be usually about 50-80 times the used audio 15253e0c72dSLiam Girdwood * sample rate. With highest sample rates above 48 kHz this can relaxed 15353e0c72dSLiam Girdwood * somewhat. 15453e0c72dSLiam Girdwood * 15553e0c72dSLiam Girdwood * The parameter wake_up_time describes how long time the microphone needs 15653e0c72dSLiam Girdwood * for the data line to produce valid output from mic clock start. The driver 15753e0c72dSLiam Girdwood * will mute the captured audio for the given time. The min_clock_on_time 15853e0c72dSLiam Girdwood * parameter is used to prevent too short clock bursts to happen. The driver 15953e0c72dSLiam Girdwood * will keep the clock active after capture stop if this time is not yet 16053e0c72dSLiam Girdwood * met. The unit for both is microseconds (us). Exceed of 100 ms will be 16153e0c72dSLiam Girdwood * treated as an error. 16253e0c72dSLiam Girdwood */ 16353e0c72dSLiam Girdwood struct sof_ipc_dai_dmic_params { 16453e0c72dSLiam Girdwood struct sof_ipc_hdr hdr; 16553e0c72dSLiam Girdwood uint32_t driver_ipc_version; /**< Version (1..N) */ 16653e0c72dSLiam Girdwood 16753e0c72dSLiam Girdwood uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ 16853e0c72dSLiam Girdwood uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ 16953e0c72dSLiam Girdwood 17053e0c72dSLiam Girdwood uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ 17153e0c72dSLiam Girdwood uint32_t reserved_1; /**< Reserved */ 17253e0c72dSLiam Girdwood uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ 17353e0c72dSLiam Girdwood uint16_t reserved_2; /**< Reserved */ 17453e0c72dSLiam Girdwood 17553e0c72dSLiam Girdwood uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ 17653e0c72dSLiam Girdwood uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ 17753e0c72dSLiam Girdwood 17853e0c72dSLiam Girdwood uint32_t num_pdm_active; /**< Number of active pdm controllers */ 17953e0c72dSLiam Girdwood 18053e0c72dSLiam Girdwood uint32_t wake_up_time; /**< Time from clock start to data (us) */ 18153e0c72dSLiam Girdwood uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ 1827df43911SSeppo Ingalsuo uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ 18353e0c72dSLiam Girdwood 18453e0c72dSLiam Girdwood /* reserved for future use */ 1857df43911SSeppo Ingalsuo uint32_t reserved[5]; 18653e0c72dSLiam Girdwood 18753e0c72dSLiam Girdwood /**< variable number of pdm controller config */ 18853e0c72dSLiam Girdwood struct sof_ipc_dai_dmic_pdm_ctrl pdm[0]; 18953e0c72dSLiam Girdwood } __packed; 19053e0c72dSLiam Girdwood 19153e0c72dSLiam Girdwood #endif 192