1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 71 }; 72 73 enum { 74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 75 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 76 }; 77 78 enum { 79 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 80 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 81 MLX5_CMD_OP_INIT_HCA = 0x102, 82 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 83 MLX5_CMD_OP_ENABLE_HCA = 0x104, 84 MLX5_CMD_OP_DISABLE_HCA = 0x105, 85 MLX5_CMD_OP_QUERY_PAGES = 0x107, 86 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 87 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 88 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 89 MLX5_CMD_OP_SET_ISSI = 0x10b, 90 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 91 MLX5_CMD_OP_CREATE_MKEY = 0x200, 92 MLX5_CMD_OP_QUERY_MKEY = 0x201, 93 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 94 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 95 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 96 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 97 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 98 MLX5_CMD_OP_CREATE_EQ = 0x301, 99 MLX5_CMD_OP_DESTROY_EQ = 0x302, 100 MLX5_CMD_OP_QUERY_EQ = 0x303, 101 MLX5_CMD_OP_GEN_EQE = 0x304, 102 MLX5_CMD_OP_CREATE_CQ = 0x400, 103 MLX5_CMD_OP_DESTROY_CQ = 0x401, 104 MLX5_CMD_OP_QUERY_CQ = 0x402, 105 MLX5_CMD_OP_MODIFY_CQ = 0x403, 106 MLX5_CMD_OP_CREATE_QP = 0x500, 107 MLX5_CMD_OP_DESTROY_QP = 0x501, 108 MLX5_CMD_OP_RST2INIT_QP = 0x502, 109 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 110 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 111 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 112 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 113 MLX5_CMD_OP_2ERR_QP = 0x507, 114 MLX5_CMD_OP_2RST_QP = 0x50a, 115 MLX5_CMD_OP_QUERY_QP = 0x50b, 116 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 117 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 118 MLX5_CMD_OP_CREATE_PSV = 0x600, 119 MLX5_CMD_OP_DESTROY_PSV = 0x601, 120 MLX5_CMD_OP_CREATE_SRQ = 0x700, 121 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 122 MLX5_CMD_OP_QUERY_SRQ = 0x702, 123 MLX5_CMD_OP_ARM_RQ = 0x703, 124 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 125 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 126 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 127 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 128 MLX5_CMD_OP_CREATE_DCT = 0x710, 129 MLX5_CMD_OP_DESTROY_DCT = 0x711, 130 MLX5_CMD_OP_DRAIN_DCT = 0x712, 131 MLX5_CMD_OP_QUERY_DCT = 0x713, 132 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 133 MLX5_CMD_OP_CREATE_XRQ = 0x717, 134 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 135 MLX5_CMD_OP_QUERY_XRQ = 0x719, 136 MLX5_CMD_OP_ARM_XRQ = 0x71a, 137 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 138 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 139 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 140 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 141 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 142 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 143 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 144 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 145 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 146 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 147 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 148 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 149 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 150 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 151 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 152 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 153 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 154 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 155 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 156 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 157 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 158 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 159 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 160 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 161 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 162 MLX5_CMD_OP_ALLOC_PD = 0x800, 163 MLX5_CMD_OP_DEALLOC_PD = 0x801, 164 MLX5_CMD_OP_ALLOC_UAR = 0x802, 165 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 166 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 167 MLX5_CMD_OP_ACCESS_REG = 0x805, 168 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 169 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 170 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 171 MLX5_CMD_OP_MAD_IFC = 0x50d, 172 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 173 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 174 MLX5_CMD_OP_NOP = 0x80d, 175 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 176 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 177 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 178 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 179 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 180 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 181 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 182 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 183 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 184 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 185 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 186 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 187 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 188 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 189 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 190 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 191 MLX5_CMD_OP_CREATE_LAG = 0x840, 192 MLX5_CMD_OP_MODIFY_LAG = 0x841, 193 MLX5_CMD_OP_QUERY_LAG = 0x842, 194 MLX5_CMD_OP_DESTROY_LAG = 0x843, 195 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 196 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 197 MLX5_CMD_OP_CREATE_TIR = 0x900, 198 MLX5_CMD_OP_MODIFY_TIR = 0x901, 199 MLX5_CMD_OP_DESTROY_TIR = 0x902, 200 MLX5_CMD_OP_QUERY_TIR = 0x903, 201 MLX5_CMD_OP_CREATE_SQ = 0x904, 202 MLX5_CMD_OP_MODIFY_SQ = 0x905, 203 MLX5_CMD_OP_DESTROY_SQ = 0x906, 204 MLX5_CMD_OP_QUERY_SQ = 0x907, 205 MLX5_CMD_OP_CREATE_RQ = 0x908, 206 MLX5_CMD_OP_MODIFY_RQ = 0x909, 207 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 208 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 209 MLX5_CMD_OP_QUERY_RQ = 0x90b, 210 MLX5_CMD_OP_CREATE_RMP = 0x90c, 211 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 212 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 213 MLX5_CMD_OP_QUERY_RMP = 0x90f, 214 MLX5_CMD_OP_CREATE_TIS = 0x912, 215 MLX5_CMD_OP_MODIFY_TIS = 0x913, 216 MLX5_CMD_OP_DESTROY_TIS = 0x914, 217 MLX5_CMD_OP_QUERY_TIS = 0x915, 218 MLX5_CMD_OP_CREATE_RQT = 0x916, 219 MLX5_CMD_OP_MODIFY_RQT = 0x917, 220 MLX5_CMD_OP_DESTROY_RQT = 0x918, 221 MLX5_CMD_OP_QUERY_RQT = 0x919, 222 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 223 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 224 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 225 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 226 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 227 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 228 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 229 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 230 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 231 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 232 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 233 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 234 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 235 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 236 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, 237 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, 238 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 239 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 240 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 241 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 242 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 243 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 244 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 245 MLX5_CMD_OP_MAX 246 }; 247 248 struct mlx5_ifc_flow_table_fields_supported_bits { 249 u8 outer_dmac[0x1]; 250 u8 outer_smac[0x1]; 251 u8 outer_ether_type[0x1]; 252 u8 outer_ip_version[0x1]; 253 u8 outer_first_prio[0x1]; 254 u8 outer_first_cfi[0x1]; 255 u8 outer_first_vid[0x1]; 256 u8 outer_ipv4_ttl[0x1]; 257 u8 outer_second_prio[0x1]; 258 u8 outer_second_cfi[0x1]; 259 u8 outer_second_vid[0x1]; 260 u8 reserved_at_b[0x1]; 261 u8 outer_sip[0x1]; 262 u8 outer_dip[0x1]; 263 u8 outer_frag[0x1]; 264 u8 outer_ip_protocol[0x1]; 265 u8 outer_ip_ecn[0x1]; 266 u8 outer_ip_dscp[0x1]; 267 u8 outer_udp_sport[0x1]; 268 u8 outer_udp_dport[0x1]; 269 u8 outer_tcp_sport[0x1]; 270 u8 outer_tcp_dport[0x1]; 271 u8 outer_tcp_flags[0x1]; 272 u8 outer_gre_protocol[0x1]; 273 u8 outer_gre_key[0x1]; 274 u8 outer_vxlan_vni[0x1]; 275 u8 reserved_at_1a[0x5]; 276 u8 source_eswitch_port[0x1]; 277 278 u8 inner_dmac[0x1]; 279 u8 inner_smac[0x1]; 280 u8 inner_ether_type[0x1]; 281 u8 inner_ip_version[0x1]; 282 u8 inner_first_prio[0x1]; 283 u8 inner_first_cfi[0x1]; 284 u8 inner_first_vid[0x1]; 285 u8 reserved_at_27[0x1]; 286 u8 inner_second_prio[0x1]; 287 u8 inner_second_cfi[0x1]; 288 u8 inner_second_vid[0x1]; 289 u8 reserved_at_2b[0x1]; 290 u8 inner_sip[0x1]; 291 u8 inner_dip[0x1]; 292 u8 inner_frag[0x1]; 293 u8 inner_ip_protocol[0x1]; 294 u8 inner_ip_ecn[0x1]; 295 u8 inner_ip_dscp[0x1]; 296 u8 inner_udp_sport[0x1]; 297 u8 inner_udp_dport[0x1]; 298 u8 inner_tcp_sport[0x1]; 299 u8 inner_tcp_dport[0x1]; 300 u8 inner_tcp_flags[0x1]; 301 u8 reserved_at_37[0x9]; 302 u8 reserved_at_40[0x17]; 303 u8 outer_esp_spi[0x1]; 304 u8 reserved_at_58[0x2]; 305 u8 bth_dst_qp[0x1]; 306 307 u8 reserved_at_5b[0x25]; 308 }; 309 310 struct mlx5_ifc_flow_table_prop_layout_bits { 311 u8 ft_support[0x1]; 312 u8 reserved_at_1[0x1]; 313 u8 flow_counter[0x1]; 314 u8 flow_modify_en[0x1]; 315 u8 modify_root[0x1]; 316 u8 identified_miss_table_mode[0x1]; 317 u8 flow_table_modify[0x1]; 318 u8 encap[0x1]; 319 u8 decap[0x1]; 320 u8 reserved_at_9[0x1]; 321 u8 pop_vlan[0x1]; 322 u8 push_vlan[0x1]; 323 u8 reserved_at_c[0x14]; 324 325 u8 reserved_at_20[0x2]; 326 u8 log_max_ft_size[0x6]; 327 u8 log_max_modify_header_context[0x8]; 328 u8 max_modify_header_actions[0x8]; 329 u8 max_ft_level[0x8]; 330 331 u8 reserved_at_40[0x20]; 332 333 u8 reserved_at_60[0x18]; 334 u8 log_max_ft_num[0x8]; 335 336 u8 reserved_at_80[0x18]; 337 u8 log_max_destination[0x8]; 338 339 u8 log_max_flow_counter[0x8]; 340 u8 reserved_at_a8[0x10]; 341 u8 log_max_flow[0x8]; 342 343 u8 reserved_at_c0[0x40]; 344 345 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 346 347 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 348 }; 349 350 struct mlx5_ifc_odp_per_transport_service_cap_bits { 351 u8 send[0x1]; 352 u8 receive[0x1]; 353 u8 write[0x1]; 354 u8 read[0x1]; 355 u8 atomic[0x1]; 356 u8 srq_receive[0x1]; 357 u8 reserved_at_6[0x1a]; 358 }; 359 360 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 361 u8 smac_47_16[0x20]; 362 363 u8 smac_15_0[0x10]; 364 u8 ethertype[0x10]; 365 366 u8 dmac_47_16[0x20]; 367 368 u8 dmac_15_0[0x10]; 369 u8 first_prio[0x3]; 370 u8 first_cfi[0x1]; 371 u8 first_vid[0xc]; 372 373 u8 ip_protocol[0x8]; 374 u8 ip_dscp[0x6]; 375 u8 ip_ecn[0x2]; 376 u8 cvlan_tag[0x1]; 377 u8 svlan_tag[0x1]; 378 u8 frag[0x1]; 379 u8 ip_version[0x4]; 380 u8 tcp_flags[0x9]; 381 382 u8 tcp_sport[0x10]; 383 u8 tcp_dport[0x10]; 384 385 u8 reserved_at_c0[0x18]; 386 u8 ttl_hoplimit[0x8]; 387 388 u8 udp_sport[0x10]; 389 u8 udp_dport[0x10]; 390 391 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 392 393 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 394 }; 395 396 struct mlx5_ifc_fte_match_set_misc_bits { 397 u8 reserved_at_0[0x8]; 398 u8 source_sqn[0x18]; 399 400 u8 source_eswitch_owner_vhca_id[0x10]; 401 u8 source_port[0x10]; 402 403 u8 outer_second_prio[0x3]; 404 u8 outer_second_cfi[0x1]; 405 u8 outer_second_vid[0xc]; 406 u8 inner_second_prio[0x3]; 407 u8 inner_second_cfi[0x1]; 408 u8 inner_second_vid[0xc]; 409 410 u8 outer_second_cvlan_tag[0x1]; 411 u8 inner_second_cvlan_tag[0x1]; 412 u8 outer_second_svlan_tag[0x1]; 413 u8 inner_second_svlan_tag[0x1]; 414 u8 reserved_at_64[0xc]; 415 u8 gre_protocol[0x10]; 416 417 u8 gre_key_h[0x18]; 418 u8 gre_key_l[0x8]; 419 420 u8 vxlan_vni[0x18]; 421 u8 reserved_at_b8[0x8]; 422 423 u8 reserved_at_c0[0x20]; 424 425 u8 reserved_at_e0[0xc]; 426 u8 outer_ipv6_flow_label[0x14]; 427 428 u8 reserved_at_100[0xc]; 429 u8 inner_ipv6_flow_label[0x14]; 430 431 u8 reserved_at_120[0x28]; 432 u8 bth_dst_qp[0x18]; 433 u8 reserved_at_160[0x20]; 434 u8 outer_esp_spi[0x20]; 435 u8 reserved_at_1a0[0x60]; 436 }; 437 438 struct mlx5_ifc_cmd_pas_bits { 439 u8 pa_h[0x20]; 440 441 u8 pa_l[0x14]; 442 u8 reserved_at_34[0xc]; 443 }; 444 445 struct mlx5_ifc_uint64_bits { 446 u8 hi[0x20]; 447 448 u8 lo[0x20]; 449 }; 450 451 enum { 452 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 453 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 454 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 455 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 456 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 457 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 458 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 459 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 460 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 461 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 462 }; 463 464 struct mlx5_ifc_ads_bits { 465 u8 fl[0x1]; 466 u8 free_ar[0x1]; 467 u8 reserved_at_2[0xe]; 468 u8 pkey_index[0x10]; 469 470 u8 reserved_at_20[0x8]; 471 u8 grh[0x1]; 472 u8 mlid[0x7]; 473 u8 rlid[0x10]; 474 475 u8 ack_timeout[0x5]; 476 u8 reserved_at_45[0x3]; 477 u8 src_addr_index[0x8]; 478 u8 reserved_at_50[0x4]; 479 u8 stat_rate[0x4]; 480 u8 hop_limit[0x8]; 481 482 u8 reserved_at_60[0x4]; 483 u8 tclass[0x8]; 484 u8 flow_label[0x14]; 485 486 u8 rgid_rip[16][0x8]; 487 488 u8 reserved_at_100[0x4]; 489 u8 f_dscp[0x1]; 490 u8 f_ecn[0x1]; 491 u8 reserved_at_106[0x1]; 492 u8 f_eth_prio[0x1]; 493 u8 ecn[0x2]; 494 u8 dscp[0x6]; 495 u8 udp_sport[0x10]; 496 497 u8 dei_cfi[0x1]; 498 u8 eth_prio[0x3]; 499 u8 sl[0x4]; 500 u8 vhca_port_num[0x8]; 501 u8 rmac_47_32[0x10]; 502 503 u8 rmac_31_0[0x20]; 504 }; 505 506 struct mlx5_ifc_flow_table_nic_cap_bits { 507 u8 nic_rx_multi_path_tirs[0x1]; 508 u8 nic_rx_multi_path_tirs_fts[0x1]; 509 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 510 u8 reserved_at_3[0x1fd]; 511 512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 513 514 u8 reserved_at_400[0x200]; 515 516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 517 518 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 519 520 u8 reserved_at_a00[0x200]; 521 522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 523 524 u8 reserved_at_e00[0x7200]; 525 }; 526 527 struct mlx5_ifc_flow_table_eswitch_cap_bits { 528 u8 reserved_at_0[0x1c]; 529 u8 fdb_multi_path_to_table[0x1]; 530 u8 reserved_at_1d[0x1e3]; 531 532 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 533 534 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 535 536 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 537 538 u8 reserved_at_800[0x7800]; 539 }; 540 541 struct mlx5_ifc_e_switch_cap_bits { 542 u8 vport_svlan_strip[0x1]; 543 u8 vport_cvlan_strip[0x1]; 544 u8 vport_svlan_insert[0x1]; 545 u8 vport_cvlan_insert_if_not_exist[0x1]; 546 u8 vport_cvlan_insert_overwrite[0x1]; 547 u8 reserved_at_5[0x18]; 548 u8 merged_eswitch[0x1]; 549 u8 nic_vport_node_guid_modify[0x1]; 550 u8 nic_vport_port_guid_modify[0x1]; 551 552 u8 vxlan_encap_decap[0x1]; 553 u8 nvgre_encap_decap[0x1]; 554 u8 reserved_at_22[0x9]; 555 u8 log_max_encap_headers[0x5]; 556 u8 reserved_2b[0x6]; 557 u8 max_encap_header_size[0xa]; 558 559 u8 reserved_40[0x7c0]; 560 561 }; 562 563 struct mlx5_ifc_qos_cap_bits { 564 u8 packet_pacing[0x1]; 565 u8 esw_scheduling[0x1]; 566 u8 esw_bw_share[0x1]; 567 u8 esw_rate_limit[0x1]; 568 u8 reserved_at_4[0x1]; 569 u8 packet_pacing_burst_bound[0x1]; 570 u8 packet_pacing_typical_size[0x1]; 571 u8 reserved_at_7[0x19]; 572 573 u8 reserved_at_20[0x20]; 574 575 u8 packet_pacing_max_rate[0x20]; 576 577 u8 packet_pacing_min_rate[0x20]; 578 579 u8 reserved_at_80[0x10]; 580 u8 packet_pacing_rate_table_size[0x10]; 581 582 u8 esw_element_type[0x10]; 583 u8 esw_tsar_type[0x10]; 584 585 u8 reserved_at_c0[0x10]; 586 u8 max_qos_para_vport[0x10]; 587 588 u8 max_tsar_bw_share[0x20]; 589 590 u8 reserved_at_100[0x700]; 591 }; 592 593 struct mlx5_ifc_debug_cap_bits { 594 u8 reserved_at_0[0x20]; 595 596 u8 reserved_at_20[0x2]; 597 u8 stall_detect[0x1]; 598 u8 reserved_at_23[0x1d]; 599 600 u8 reserved_at_40[0x7c0]; 601 }; 602 603 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 604 u8 csum_cap[0x1]; 605 u8 vlan_cap[0x1]; 606 u8 lro_cap[0x1]; 607 u8 lro_psh_flag[0x1]; 608 u8 lro_time_stamp[0x1]; 609 u8 reserved_at_5[0x2]; 610 u8 wqe_vlan_insert[0x1]; 611 u8 self_lb_en_modifiable[0x1]; 612 u8 reserved_at_9[0x2]; 613 u8 max_lso_cap[0x5]; 614 u8 multi_pkt_send_wqe[0x2]; 615 u8 wqe_inline_mode[0x2]; 616 u8 rss_ind_tbl_cap[0x4]; 617 u8 reg_umr_sq[0x1]; 618 u8 scatter_fcs[0x1]; 619 u8 enhanced_multi_pkt_send_wqe[0x1]; 620 u8 tunnel_lso_const_out_ip_id[0x1]; 621 u8 reserved_at_1c[0x2]; 622 u8 tunnel_stateless_gre[0x1]; 623 u8 tunnel_stateless_vxlan[0x1]; 624 625 u8 swp[0x1]; 626 u8 swp_csum[0x1]; 627 u8 swp_lso[0x1]; 628 u8 reserved_at_23[0x1b]; 629 u8 max_geneve_opt_len[0x1]; 630 u8 tunnel_stateless_geneve_rx[0x1]; 631 632 u8 reserved_at_40[0x10]; 633 u8 lro_min_mss_size[0x10]; 634 635 u8 reserved_at_60[0x120]; 636 637 u8 lro_timer_supported_periods[4][0x20]; 638 639 u8 reserved_at_200[0x600]; 640 }; 641 642 struct mlx5_ifc_roce_cap_bits { 643 u8 roce_apm[0x1]; 644 u8 reserved_at_1[0x1f]; 645 646 u8 reserved_at_20[0x60]; 647 648 u8 reserved_at_80[0xc]; 649 u8 l3_type[0x4]; 650 u8 reserved_at_90[0x8]; 651 u8 roce_version[0x8]; 652 653 u8 reserved_at_a0[0x10]; 654 u8 r_roce_dest_udp_port[0x10]; 655 656 u8 r_roce_max_src_udp_port[0x10]; 657 u8 r_roce_min_src_udp_port[0x10]; 658 659 u8 reserved_at_e0[0x10]; 660 u8 roce_address_table_size[0x10]; 661 662 u8 reserved_at_100[0x700]; 663 }; 664 665 struct mlx5_ifc_device_mem_cap_bits { 666 u8 memic[0x1]; 667 u8 reserved_at_1[0x1f]; 668 669 u8 reserved_at_20[0xb]; 670 u8 log_min_memic_alloc_size[0x5]; 671 u8 reserved_at_30[0x8]; 672 u8 log_max_memic_addr_alignment[0x8]; 673 674 u8 memic_bar_start_addr[0x40]; 675 676 u8 memic_bar_size[0x20]; 677 678 u8 max_memic_size[0x20]; 679 680 u8 reserved_at_c0[0x740]; 681 }; 682 683 enum { 684 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 685 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 686 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 687 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 688 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 689 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 690 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 691 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 692 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 693 }; 694 695 enum { 696 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 697 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 698 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 699 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 700 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 701 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 702 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 703 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 704 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 705 }; 706 707 struct mlx5_ifc_atomic_caps_bits { 708 u8 reserved_at_0[0x40]; 709 710 u8 atomic_req_8B_endianness_mode[0x2]; 711 u8 reserved_at_42[0x4]; 712 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 713 714 u8 reserved_at_47[0x19]; 715 716 u8 reserved_at_60[0x20]; 717 718 u8 reserved_at_80[0x10]; 719 u8 atomic_operations[0x10]; 720 721 u8 reserved_at_a0[0x10]; 722 u8 atomic_size_qp[0x10]; 723 724 u8 reserved_at_c0[0x10]; 725 u8 atomic_size_dc[0x10]; 726 727 u8 reserved_at_e0[0x720]; 728 }; 729 730 struct mlx5_ifc_odp_cap_bits { 731 u8 reserved_at_0[0x40]; 732 733 u8 sig[0x1]; 734 u8 reserved_at_41[0x1f]; 735 736 u8 reserved_at_60[0x20]; 737 738 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 739 740 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 741 742 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 743 744 u8 reserved_at_e0[0x720]; 745 }; 746 747 struct mlx5_ifc_calc_op { 748 u8 reserved_at_0[0x10]; 749 u8 reserved_at_10[0x9]; 750 u8 op_swap_endianness[0x1]; 751 u8 op_min[0x1]; 752 u8 op_xor[0x1]; 753 u8 op_or[0x1]; 754 u8 op_and[0x1]; 755 u8 op_max[0x1]; 756 u8 op_add[0x1]; 757 }; 758 759 struct mlx5_ifc_vector_calc_cap_bits { 760 u8 calc_matrix[0x1]; 761 u8 reserved_at_1[0x1f]; 762 u8 reserved_at_20[0x8]; 763 u8 max_vec_count[0x8]; 764 u8 reserved_at_30[0xd]; 765 u8 max_chunk_size[0x3]; 766 struct mlx5_ifc_calc_op calc0; 767 struct mlx5_ifc_calc_op calc1; 768 struct mlx5_ifc_calc_op calc2; 769 struct mlx5_ifc_calc_op calc3; 770 771 u8 reserved_at_e0[0x720]; 772 }; 773 774 enum { 775 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 776 MLX5_WQ_TYPE_CYCLIC = 0x1, 777 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 778 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 779 }; 780 781 enum { 782 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 783 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 784 }; 785 786 enum { 787 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 788 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 789 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 790 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 791 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 792 }; 793 794 enum { 795 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 796 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 797 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 798 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 799 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 800 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 801 }; 802 803 enum { 804 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 805 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 806 }; 807 808 enum { 809 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 810 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 811 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 812 }; 813 814 enum { 815 MLX5_CAP_PORT_TYPE_IB = 0x0, 816 MLX5_CAP_PORT_TYPE_ETH = 0x1, 817 }; 818 819 enum { 820 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 821 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 822 MLX5_CAP_UMR_FENCE_NONE = 0x2, 823 }; 824 825 struct mlx5_ifc_cmd_hca_cap_bits { 826 u8 reserved_at_0[0x30]; 827 u8 vhca_id[0x10]; 828 829 u8 reserved_at_40[0x40]; 830 831 u8 log_max_srq_sz[0x8]; 832 u8 log_max_qp_sz[0x8]; 833 u8 reserved_at_90[0xb]; 834 u8 log_max_qp[0x5]; 835 836 u8 reserved_at_a0[0xb]; 837 u8 log_max_srq[0x5]; 838 u8 reserved_at_b0[0x10]; 839 840 u8 reserved_at_c0[0x8]; 841 u8 log_max_cq_sz[0x8]; 842 u8 reserved_at_d0[0xb]; 843 u8 log_max_cq[0x5]; 844 845 u8 log_max_eq_sz[0x8]; 846 u8 reserved_at_e8[0x2]; 847 u8 log_max_mkey[0x6]; 848 u8 reserved_at_f0[0xc]; 849 u8 log_max_eq[0x4]; 850 851 u8 max_indirection[0x8]; 852 u8 fixed_buffer_size[0x1]; 853 u8 log_max_mrw_sz[0x7]; 854 u8 force_teardown[0x1]; 855 u8 reserved_at_111[0x1]; 856 u8 log_max_bsf_list_size[0x6]; 857 u8 umr_extended_translation_offset[0x1]; 858 u8 null_mkey[0x1]; 859 u8 log_max_klm_list_size[0x6]; 860 861 u8 reserved_at_120[0xa]; 862 u8 log_max_ra_req_dc[0x6]; 863 u8 reserved_at_130[0xa]; 864 u8 log_max_ra_res_dc[0x6]; 865 866 u8 reserved_at_140[0xa]; 867 u8 log_max_ra_req_qp[0x6]; 868 u8 reserved_at_150[0xa]; 869 u8 log_max_ra_res_qp[0x6]; 870 871 u8 end_pad[0x1]; 872 u8 cc_query_allowed[0x1]; 873 u8 cc_modify_allowed[0x1]; 874 u8 start_pad[0x1]; 875 u8 cache_line_128byte[0x1]; 876 u8 reserved_at_165[0xa]; 877 u8 qcam_reg[0x1]; 878 u8 gid_table_size[0x10]; 879 880 u8 out_of_seq_cnt[0x1]; 881 u8 vport_counters[0x1]; 882 u8 retransmission_q_counters[0x1]; 883 u8 debug[0x1]; 884 u8 modify_rq_counter_set_id[0x1]; 885 u8 rq_delay_drop[0x1]; 886 u8 max_qp_cnt[0xa]; 887 u8 pkey_table_size[0x10]; 888 889 u8 vport_group_manager[0x1]; 890 u8 vhca_group_manager[0x1]; 891 u8 ib_virt[0x1]; 892 u8 eth_virt[0x1]; 893 u8 vnic_env_queue_counters[0x1]; 894 u8 ets[0x1]; 895 u8 nic_flow_table[0x1]; 896 u8 eswitch_flow_table[0x1]; 897 u8 device_memory[0x1]; 898 u8 mcam_reg[0x1]; 899 u8 pcam_reg[0x1]; 900 u8 local_ca_ack_delay[0x5]; 901 u8 port_module_event[0x1]; 902 u8 enhanced_error_q_counters[0x1]; 903 u8 ports_check[0x1]; 904 u8 reserved_at_1b3[0x1]; 905 u8 disable_link_up[0x1]; 906 u8 beacon_led[0x1]; 907 u8 port_type[0x2]; 908 u8 num_ports[0x8]; 909 910 u8 reserved_at_1c0[0x1]; 911 u8 pps[0x1]; 912 u8 pps_modify[0x1]; 913 u8 log_max_msg[0x5]; 914 u8 reserved_at_1c8[0x4]; 915 u8 max_tc[0x4]; 916 u8 temp_warn_event[0x1]; 917 u8 dcbx[0x1]; 918 u8 general_notification_event[0x1]; 919 u8 reserved_at_1d3[0x2]; 920 u8 fpga[0x1]; 921 u8 rol_s[0x1]; 922 u8 rol_g[0x1]; 923 u8 reserved_at_1d8[0x1]; 924 u8 wol_s[0x1]; 925 u8 wol_g[0x1]; 926 u8 wol_a[0x1]; 927 u8 wol_b[0x1]; 928 u8 wol_m[0x1]; 929 u8 wol_u[0x1]; 930 u8 wol_p[0x1]; 931 932 u8 stat_rate_support[0x10]; 933 u8 reserved_at_1f0[0xc]; 934 u8 cqe_version[0x4]; 935 936 u8 compact_address_vector[0x1]; 937 u8 striding_rq[0x1]; 938 u8 reserved_at_202[0x1]; 939 u8 ipoib_enhanced_offloads[0x1]; 940 u8 ipoib_basic_offloads[0x1]; 941 u8 reserved_at_205[0x1]; 942 u8 repeated_block_disabled[0x1]; 943 u8 umr_modify_entity_size_disabled[0x1]; 944 u8 umr_modify_atomic_disabled[0x1]; 945 u8 umr_indirect_mkey_disabled[0x1]; 946 u8 umr_fence[0x2]; 947 u8 reserved_at_20c[0x3]; 948 u8 drain_sigerr[0x1]; 949 u8 cmdif_checksum[0x2]; 950 u8 sigerr_cqe[0x1]; 951 u8 reserved_at_213[0x1]; 952 u8 wq_signature[0x1]; 953 u8 sctr_data_cqe[0x1]; 954 u8 reserved_at_216[0x1]; 955 u8 sho[0x1]; 956 u8 tph[0x1]; 957 u8 rf[0x1]; 958 u8 dct[0x1]; 959 u8 qos[0x1]; 960 u8 eth_net_offloads[0x1]; 961 u8 roce[0x1]; 962 u8 atomic[0x1]; 963 u8 reserved_at_21f[0x1]; 964 965 u8 cq_oi[0x1]; 966 u8 cq_resize[0x1]; 967 u8 cq_moderation[0x1]; 968 u8 reserved_at_223[0x3]; 969 u8 cq_eq_remap[0x1]; 970 u8 pg[0x1]; 971 u8 block_lb_mc[0x1]; 972 u8 reserved_at_229[0x1]; 973 u8 scqe_break_moderation[0x1]; 974 u8 cq_period_start_from_cqe[0x1]; 975 u8 cd[0x1]; 976 u8 reserved_at_22d[0x1]; 977 u8 apm[0x1]; 978 u8 vector_calc[0x1]; 979 u8 umr_ptr_rlky[0x1]; 980 u8 imaicl[0x1]; 981 u8 reserved_at_232[0x4]; 982 u8 qkv[0x1]; 983 u8 pkv[0x1]; 984 u8 set_deth_sqpn[0x1]; 985 u8 reserved_at_239[0x3]; 986 u8 xrc[0x1]; 987 u8 ud[0x1]; 988 u8 uc[0x1]; 989 u8 rc[0x1]; 990 991 u8 uar_4k[0x1]; 992 u8 reserved_at_241[0x9]; 993 u8 uar_sz[0x6]; 994 u8 reserved_at_250[0x8]; 995 u8 log_pg_sz[0x8]; 996 997 u8 bf[0x1]; 998 u8 driver_version[0x1]; 999 u8 pad_tx_eth_packet[0x1]; 1000 u8 reserved_at_263[0x8]; 1001 u8 log_bf_reg_size[0x5]; 1002 1003 u8 reserved_at_270[0xb]; 1004 u8 lag_master[0x1]; 1005 u8 num_lag_ports[0x4]; 1006 1007 u8 reserved_at_280[0x10]; 1008 u8 max_wqe_sz_sq[0x10]; 1009 1010 u8 reserved_at_2a0[0x10]; 1011 u8 max_wqe_sz_rq[0x10]; 1012 1013 u8 max_flow_counter_31_16[0x10]; 1014 u8 max_wqe_sz_sq_dc[0x10]; 1015 1016 u8 reserved_at_2e0[0x7]; 1017 u8 max_qp_mcg[0x19]; 1018 1019 u8 reserved_at_300[0x18]; 1020 u8 log_max_mcg[0x8]; 1021 1022 u8 reserved_at_320[0x3]; 1023 u8 log_max_transport_domain[0x5]; 1024 u8 reserved_at_328[0x3]; 1025 u8 log_max_pd[0x5]; 1026 u8 reserved_at_330[0xb]; 1027 u8 log_max_xrcd[0x5]; 1028 1029 u8 nic_receive_steering_discard[0x1]; 1030 u8 receive_discard_vport_down[0x1]; 1031 u8 transmit_discard_vport_down[0x1]; 1032 u8 reserved_at_343[0x5]; 1033 u8 log_max_flow_counter_bulk[0x8]; 1034 u8 max_flow_counter_15_0[0x10]; 1035 1036 1037 u8 reserved_at_360[0x3]; 1038 u8 log_max_rq[0x5]; 1039 u8 reserved_at_368[0x3]; 1040 u8 log_max_sq[0x5]; 1041 u8 reserved_at_370[0x3]; 1042 u8 log_max_tir[0x5]; 1043 u8 reserved_at_378[0x3]; 1044 u8 log_max_tis[0x5]; 1045 1046 u8 basic_cyclic_rcv_wqe[0x1]; 1047 u8 reserved_at_381[0x2]; 1048 u8 log_max_rmp[0x5]; 1049 u8 reserved_at_388[0x3]; 1050 u8 log_max_rqt[0x5]; 1051 u8 reserved_at_390[0x3]; 1052 u8 log_max_rqt_size[0x5]; 1053 u8 reserved_at_398[0x3]; 1054 u8 log_max_tis_per_sq[0x5]; 1055 1056 u8 ext_stride_num_range[0x1]; 1057 u8 reserved_at_3a1[0x2]; 1058 u8 log_max_stride_sz_rq[0x5]; 1059 u8 reserved_at_3a8[0x3]; 1060 u8 log_min_stride_sz_rq[0x5]; 1061 u8 reserved_at_3b0[0x3]; 1062 u8 log_max_stride_sz_sq[0x5]; 1063 u8 reserved_at_3b8[0x3]; 1064 u8 log_min_stride_sz_sq[0x5]; 1065 1066 u8 hairpin[0x1]; 1067 u8 reserved_at_3c1[0x2]; 1068 u8 log_max_hairpin_queues[0x5]; 1069 u8 reserved_at_3c8[0x3]; 1070 u8 log_max_hairpin_wq_data_sz[0x5]; 1071 u8 reserved_at_3d0[0x3]; 1072 u8 log_max_hairpin_num_packets[0x5]; 1073 u8 reserved_at_3d8[0x3]; 1074 u8 log_max_wq_sz[0x5]; 1075 1076 u8 nic_vport_change_event[0x1]; 1077 u8 disable_local_lb_uc[0x1]; 1078 u8 disable_local_lb_mc[0x1]; 1079 u8 log_min_hairpin_wq_data_sz[0x5]; 1080 u8 reserved_at_3e8[0x3]; 1081 u8 log_max_vlan_list[0x5]; 1082 u8 reserved_at_3f0[0x3]; 1083 u8 log_max_current_mc_list[0x5]; 1084 u8 reserved_at_3f8[0x3]; 1085 u8 log_max_current_uc_list[0x5]; 1086 1087 u8 reserved_at_400[0x80]; 1088 1089 u8 reserved_at_480[0x3]; 1090 u8 log_max_l2_table[0x5]; 1091 u8 reserved_at_488[0x8]; 1092 u8 log_uar_page_sz[0x10]; 1093 1094 u8 reserved_at_4a0[0x20]; 1095 u8 device_frequency_mhz[0x20]; 1096 u8 device_frequency_khz[0x20]; 1097 1098 u8 reserved_at_500[0x20]; 1099 u8 num_of_uars_per_page[0x20]; 1100 u8 reserved_at_540[0x40]; 1101 1102 u8 reserved_at_580[0x3d]; 1103 u8 cqe_128_always[0x1]; 1104 u8 cqe_compression_128[0x1]; 1105 u8 cqe_compression[0x1]; 1106 1107 u8 cqe_compression_timeout[0x10]; 1108 u8 cqe_compression_max_num[0x10]; 1109 1110 u8 reserved_at_5e0[0x10]; 1111 u8 tag_matching[0x1]; 1112 u8 rndv_offload_rc[0x1]; 1113 u8 rndv_offload_dc[0x1]; 1114 u8 log_tag_matching_list_sz[0x5]; 1115 u8 reserved_at_5f8[0x3]; 1116 u8 log_max_xrq[0x5]; 1117 1118 u8 affiliate_nic_vport_criteria[0x8]; 1119 u8 native_port_num[0x8]; 1120 u8 num_vhca_ports[0x8]; 1121 u8 reserved_at_618[0x6]; 1122 u8 sw_owner_id[0x1]; 1123 u8 reserved_at_61f[0x1e1]; 1124 }; 1125 1126 enum mlx5_flow_destination_type { 1127 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1128 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1129 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, 1130 1131 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99, 1132 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, 1133 }; 1134 1135 struct mlx5_ifc_dest_format_struct_bits { 1136 u8 destination_type[0x8]; 1137 u8 destination_id[0x18]; 1138 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1139 u8 reserved_at_21[0xf]; 1140 u8 destination_eswitch_owner_vhca_id[0x10]; 1141 }; 1142 1143 struct mlx5_ifc_flow_counter_list_bits { 1144 u8 flow_counter_id[0x20]; 1145 1146 u8 reserved_at_20[0x20]; 1147 }; 1148 1149 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1150 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1151 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1152 u8 reserved_at_0[0x40]; 1153 }; 1154 1155 struct mlx5_ifc_fte_match_param_bits { 1156 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1157 1158 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1159 1160 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1161 1162 u8 reserved_at_600[0xa00]; 1163 }; 1164 1165 enum { 1166 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1167 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1168 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1169 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1170 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1171 }; 1172 1173 struct mlx5_ifc_rx_hash_field_select_bits { 1174 u8 l3_prot_type[0x1]; 1175 u8 l4_prot_type[0x1]; 1176 u8 selected_fields[0x1e]; 1177 }; 1178 1179 enum { 1180 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1181 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1182 }; 1183 1184 enum { 1185 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1186 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1187 }; 1188 1189 struct mlx5_ifc_wq_bits { 1190 u8 wq_type[0x4]; 1191 u8 wq_signature[0x1]; 1192 u8 end_padding_mode[0x2]; 1193 u8 cd_slave[0x1]; 1194 u8 reserved_at_8[0x18]; 1195 1196 u8 hds_skip_first_sge[0x1]; 1197 u8 log2_hds_buf_size[0x3]; 1198 u8 reserved_at_24[0x7]; 1199 u8 page_offset[0x5]; 1200 u8 lwm[0x10]; 1201 1202 u8 reserved_at_40[0x8]; 1203 u8 pd[0x18]; 1204 1205 u8 reserved_at_60[0x8]; 1206 u8 uar_page[0x18]; 1207 1208 u8 dbr_addr[0x40]; 1209 1210 u8 hw_counter[0x20]; 1211 1212 u8 sw_counter[0x20]; 1213 1214 u8 reserved_at_100[0xc]; 1215 u8 log_wq_stride[0x4]; 1216 u8 reserved_at_110[0x3]; 1217 u8 log_wq_pg_sz[0x5]; 1218 u8 reserved_at_118[0x3]; 1219 u8 log_wq_sz[0x5]; 1220 1221 u8 reserved_at_120[0x3]; 1222 u8 log_hairpin_num_packets[0x5]; 1223 u8 reserved_at_128[0x3]; 1224 u8 log_hairpin_data_sz[0x5]; 1225 1226 u8 reserved_at_130[0x4]; 1227 u8 log_wqe_num_of_strides[0x4]; 1228 u8 two_byte_shift_en[0x1]; 1229 u8 reserved_at_139[0x4]; 1230 u8 log_wqe_stride_size[0x3]; 1231 1232 u8 reserved_at_140[0x4c0]; 1233 1234 struct mlx5_ifc_cmd_pas_bits pas[0]; 1235 }; 1236 1237 struct mlx5_ifc_rq_num_bits { 1238 u8 reserved_at_0[0x8]; 1239 u8 rq_num[0x18]; 1240 }; 1241 1242 struct mlx5_ifc_mac_address_layout_bits { 1243 u8 reserved_at_0[0x10]; 1244 u8 mac_addr_47_32[0x10]; 1245 1246 u8 mac_addr_31_0[0x20]; 1247 }; 1248 1249 struct mlx5_ifc_vlan_layout_bits { 1250 u8 reserved_at_0[0x14]; 1251 u8 vlan[0x0c]; 1252 1253 u8 reserved_at_20[0x20]; 1254 }; 1255 1256 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1257 u8 reserved_at_0[0xa0]; 1258 1259 u8 min_time_between_cnps[0x20]; 1260 1261 u8 reserved_at_c0[0x12]; 1262 u8 cnp_dscp[0x6]; 1263 u8 reserved_at_d8[0x4]; 1264 u8 cnp_prio_mode[0x1]; 1265 u8 cnp_802p_prio[0x3]; 1266 1267 u8 reserved_at_e0[0x720]; 1268 }; 1269 1270 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1271 u8 reserved_at_0[0x60]; 1272 1273 u8 reserved_at_60[0x4]; 1274 u8 clamp_tgt_rate[0x1]; 1275 u8 reserved_at_65[0x3]; 1276 u8 clamp_tgt_rate_after_time_inc[0x1]; 1277 u8 reserved_at_69[0x17]; 1278 1279 u8 reserved_at_80[0x20]; 1280 1281 u8 rpg_time_reset[0x20]; 1282 1283 u8 rpg_byte_reset[0x20]; 1284 1285 u8 rpg_threshold[0x20]; 1286 1287 u8 rpg_max_rate[0x20]; 1288 1289 u8 rpg_ai_rate[0x20]; 1290 1291 u8 rpg_hai_rate[0x20]; 1292 1293 u8 rpg_gd[0x20]; 1294 1295 u8 rpg_min_dec_fac[0x20]; 1296 1297 u8 rpg_min_rate[0x20]; 1298 1299 u8 reserved_at_1c0[0xe0]; 1300 1301 u8 rate_to_set_on_first_cnp[0x20]; 1302 1303 u8 dce_tcp_g[0x20]; 1304 1305 u8 dce_tcp_rtt[0x20]; 1306 1307 u8 rate_reduce_monitor_period[0x20]; 1308 1309 u8 reserved_at_320[0x20]; 1310 1311 u8 initial_alpha_value[0x20]; 1312 1313 u8 reserved_at_360[0x4a0]; 1314 }; 1315 1316 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1317 u8 reserved_at_0[0x80]; 1318 1319 u8 rppp_max_rps[0x20]; 1320 1321 u8 rpg_time_reset[0x20]; 1322 1323 u8 rpg_byte_reset[0x20]; 1324 1325 u8 rpg_threshold[0x20]; 1326 1327 u8 rpg_max_rate[0x20]; 1328 1329 u8 rpg_ai_rate[0x20]; 1330 1331 u8 rpg_hai_rate[0x20]; 1332 1333 u8 rpg_gd[0x20]; 1334 1335 u8 rpg_min_dec_fac[0x20]; 1336 1337 u8 rpg_min_rate[0x20]; 1338 1339 u8 reserved_at_1c0[0x640]; 1340 }; 1341 1342 enum { 1343 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1344 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1345 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1346 }; 1347 1348 struct mlx5_ifc_resize_field_select_bits { 1349 u8 resize_field_select[0x20]; 1350 }; 1351 1352 enum { 1353 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1354 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1355 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1356 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1357 }; 1358 1359 struct mlx5_ifc_modify_field_select_bits { 1360 u8 modify_field_select[0x20]; 1361 }; 1362 1363 struct mlx5_ifc_field_select_r_roce_np_bits { 1364 u8 field_select_r_roce_np[0x20]; 1365 }; 1366 1367 struct mlx5_ifc_field_select_r_roce_rp_bits { 1368 u8 field_select_r_roce_rp[0x20]; 1369 }; 1370 1371 enum { 1372 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1373 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1374 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1375 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1376 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1377 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1378 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1379 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1380 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1381 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1382 }; 1383 1384 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1385 u8 field_select_8021qaurp[0x20]; 1386 }; 1387 1388 struct mlx5_ifc_phys_layer_cntrs_bits { 1389 u8 time_since_last_clear_high[0x20]; 1390 1391 u8 time_since_last_clear_low[0x20]; 1392 1393 u8 symbol_errors_high[0x20]; 1394 1395 u8 symbol_errors_low[0x20]; 1396 1397 u8 sync_headers_errors_high[0x20]; 1398 1399 u8 sync_headers_errors_low[0x20]; 1400 1401 u8 edpl_bip_errors_lane0_high[0x20]; 1402 1403 u8 edpl_bip_errors_lane0_low[0x20]; 1404 1405 u8 edpl_bip_errors_lane1_high[0x20]; 1406 1407 u8 edpl_bip_errors_lane1_low[0x20]; 1408 1409 u8 edpl_bip_errors_lane2_high[0x20]; 1410 1411 u8 edpl_bip_errors_lane2_low[0x20]; 1412 1413 u8 edpl_bip_errors_lane3_high[0x20]; 1414 1415 u8 edpl_bip_errors_lane3_low[0x20]; 1416 1417 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 1418 1419 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 1420 1421 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 1422 1423 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 1424 1425 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 1426 1427 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 1428 1429 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 1430 1431 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 1432 1433 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 1434 1435 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 1436 1437 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 1438 1439 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 1440 1441 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 1442 1443 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 1444 1445 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 1446 1447 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 1448 1449 u8 rs_fec_corrected_blocks_high[0x20]; 1450 1451 u8 rs_fec_corrected_blocks_low[0x20]; 1452 1453 u8 rs_fec_uncorrectable_blocks_high[0x20]; 1454 1455 u8 rs_fec_uncorrectable_blocks_low[0x20]; 1456 1457 u8 rs_fec_no_errors_blocks_high[0x20]; 1458 1459 u8 rs_fec_no_errors_blocks_low[0x20]; 1460 1461 u8 rs_fec_single_error_blocks_high[0x20]; 1462 1463 u8 rs_fec_single_error_blocks_low[0x20]; 1464 1465 u8 rs_fec_corrected_symbols_total_high[0x20]; 1466 1467 u8 rs_fec_corrected_symbols_total_low[0x20]; 1468 1469 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 1470 1471 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 1472 1473 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 1474 1475 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 1476 1477 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 1478 1479 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 1480 1481 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 1482 1483 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 1484 1485 u8 link_down_events[0x20]; 1486 1487 u8 successful_recovery_events[0x20]; 1488 1489 u8 reserved_at_640[0x180]; 1490 }; 1491 1492 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 1493 u8 time_since_last_clear_high[0x20]; 1494 1495 u8 time_since_last_clear_low[0x20]; 1496 1497 u8 phy_received_bits_high[0x20]; 1498 1499 u8 phy_received_bits_low[0x20]; 1500 1501 u8 phy_symbol_errors_high[0x20]; 1502 1503 u8 phy_symbol_errors_low[0x20]; 1504 1505 u8 phy_corrected_bits_high[0x20]; 1506 1507 u8 phy_corrected_bits_low[0x20]; 1508 1509 u8 phy_corrected_bits_lane0_high[0x20]; 1510 1511 u8 phy_corrected_bits_lane0_low[0x20]; 1512 1513 u8 phy_corrected_bits_lane1_high[0x20]; 1514 1515 u8 phy_corrected_bits_lane1_low[0x20]; 1516 1517 u8 phy_corrected_bits_lane2_high[0x20]; 1518 1519 u8 phy_corrected_bits_lane2_low[0x20]; 1520 1521 u8 phy_corrected_bits_lane3_high[0x20]; 1522 1523 u8 phy_corrected_bits_lane3_low[0x20]; 1524 1525 u8 reserved_at_200[0x5c0]; 1526 }; 1527 1528 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 1529 u8 symbol_error_counter[0x10]; 1530 1531 u8 link_error_recovery_counter[0x8]; 1532 1533 u8 link_downed_counter[0x8]; 1534 1535 u8 port_rcv_errors[0x10]; 1536 1537 u8 port_rcv_remote_physical_errors[0x10]; 1538 1539 u8 port_rcv_switch_relay_errors[0x10]; 1540 1541 u8 port_xmit_discards[0x10]; 1542 1543 u8 port_xmit_constraint_errors[0x8]; 1544 1545 u8 port_rcv_constraint_errors[0x8]; 1546 1547 u8 reserved_at_70[0x8]; 1548 1549 u8 link_overrun_errors[0x8]; 1550 1551 u8 reserved_at_80[0x10]; 1552 1553 u8 vl_15_dropped[0x10]; 1554 1555 u8 reserved_at_a0[0x80]; 1556 1557 u8 port_xmit_wait[0x20]; 1558 }; 1559 1560 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { 1561 u8 transmit_queue_high[0x20]; 1562 1563 u8 transmit_queue_low[0x20]; 1564 1565 u8 reserved_at_40[0x780]; 1566 }; 1567 1568 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 1569 u8 rx_octets_high[0x20]; 1570 1571 u8 rx_octets_low[0x20]; 1572 1573 u8 reserved_at_40[0xc0]; 1574 1575 u8 rx_frames_high[0x20]; 1576 1577 u8 rx_frames_low[0x20]; 1578 1579 u8 tx_octets_high[0x20]; 1580 1581 u8 tx_octets_low[0x20]; 1582 1583 u8 reserved_at_180[0xc0]; 1584 1585 u8 tx_frames_high[0x20]; 1586 1587 u8 tx_frames_low[0x20]; 1588 1589 u8 rx_pause_high[0x20]; 1590 1591 u8 rx_pause_low[0x20]; 1592 1593 u8 rx_pause_duration_high[0x20]; 1594 1595 u8 rx_pause_duration_low[0x20]; 1596 1597 u8 tx_pause_high[0x20]; 1598 1599 u8 tx_pause_low[0x20]; 1600 1601 u8 tx_pause_duration_high[0x20]; 1602 1603 u8 tx_pause_duration_low[0x20]; 1604 1605 u8 rx_pause_transition_high[0x20]; 1606 1607 u8 rx_pause_transition_low[0x20]; 1608 1609 u8 reserved_at_3c0[0x40]; 1610 1611 u8 device_stall_minor_watermark_cnt_high[0x20]; 1612 1613 u8 device_stall_minor_watermark_cnt_low[0x20]; 1614 1615 u8 device_stall_critical_watermark_cnt_high[0x20]; 1616 1617 u8 device_stall_critical_watermark_cnt_low[0x20]; 1618 1619 u8 reserved_at_480[0x340]; 1620 }; 1621 1622 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 1623 u8 port_transmit_wait_high[0x20]; 1624 1625 u8 port_transmit_wait_low[0x20]; 1626 1627 u8 reserved_at_40[0x100]; 1628 1629 u8 rx_buffer_almost_full_high[0x20]; 1630 1631 u8 rx_buffer_almost_full_low[0x20]; 1632 1633 u8 rx_buffer_full_high[0x20]; 1634 1635 u8 rx_buffer_full_low[0x20]; 1636 1637 u8 reserved_at_1c0[0x600]; 1638 }; 1639 1640 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 1641 u8 dot3stats_alignment_errors_high[0x20]; 1642 1643 u8 dot3stats_alignment_errors_low[0x20]; 1644 1645 u8 dot3stats_fcs_errors_high[0x20]; 1646 1647 u8 dot3stats_fcs_errors_low[0x20]; 1648 1649 u8 dot3stats_single_collision_frames_high[0x20]; 1650 1651 u8 dot3stats_single_collision_frames_low[0x20]; 1652 1653 u8 dot3stats_multiple_collision_frames_high[0x20]; 1654 1655 u8 dot3stats_multiple_collision_frames_low[0x20]; 1656 1657 u8 dot3stats_sqe_test_errors_high[0x20]; 1658 1659 u8 dot3stats_sqe_test_errors_low[0x20]; 1660 1661 u8 dot3stats_deferred_transmissions_high[0x20]; 1662 1663 u8 dot3stats_deferred_transmissions_low[0x20]; 1664 1665 u8 dot3stats_late_collisions_high[0x20]; 1666 1667 u8 dot3stats_late_collisions_low[0x20]; 1668 1669 u8 dot3stats_excessive_collisions_high[0x20]; 1670 1671 u8 dot3stats_excessive_collisions_low[0x20]; 1672 1673 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 1674 1675 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 1676 1677 u8 dot3stats_carrier_sense_errors_high[0x20]; 1678 1679 u8 dot3stats_carrier_sense_errors_low[0x20]; 1680 1681 u8 dot3stats_frame_too_longs_high[0x20]; 1682 1683 u8 dot3stats_frame_too_longs_low[0x20]; 1684 1685 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 1686 1687 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 1688 1689 u8 dot3stats_symbol_errors_high[0x20]; 1690 1691 u8 dot3stats_symbol_errors_low[0x20]; 1692 1693 u8 dot3control_in_unknown_opcodes_high[0x20]; 1694 1695 u8 dot3control_in_unknown_opcodes_low[0x20]; 1696 1697 u8 dot3in_pause_frames_high[0x20]; 1698 1699 u8 dot3in_pause_frames_low[0x20]; 1700 1701 u8 dot3out_pause_frames_high[0x20]; 1702 1703 u8 dot3out_pause_frames_low[0x20]; 1704 1705 u8 reserved_at_400[0x3c0]; 1706 }; 1707 1708 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 1709 u8 ether_stats_drop_events_high[0x20]; 1710 1711 u8 ether_stats_drop_events_low[0x20]; 1712 1713 u8 ether_stats_octets_high[0x20]; 1714 1715 u8 ether_stats_octets_low[0x20]; 1716 1717 u8 ether_stats_pkts_high[0x20]; 1718 1719 u8 ether_stats_pkts_low[0x20]; 1720 1721 u8 ether_stats_broadcast_pkts_high[0x20]; 1722 1723 u8 ether_stats_broadcast_pkts_low[0x20]; 1724 1725 u8 ether_stats_multicast_pkts_high[0x20]; 1726 1727 u8 ether_stats_multicast_pkts_low[0x20]; 1728 1729 u8 ether_stats_crc_align_errors_high[0x20]; 1730 1731 u8 ether_stats_crc_align_errors_low[0x20]; 1732 1733 u8 ether_stats_undersize_pkts_high[0x20]; 1734 1735 u8 ether_stats_undersize_pkts_low[0x20]; 1736 1737 u8 ether_stats_oversize_pkts_high[0x20]; 1738 1739 u8 ether_stats_oversize_pkts_low[0x20]; 1740 1741 u8 ether_stats_fragments_high[0x20]; 1742 1743 u8 ether_stats_fragments_low[0x20]; 1744 1745 u8 ether_stats_jabbers_high[0x20]; 1746 1747 u8 ether_stats_jabbers_low[0x20]; 1748 1749 u8 ether_stats_collisions_high[0x20]; 1750 1751 u8 ether_stats_collisions_low[0x20]; 1752 1753 u8 ether_stats_pkts64octets_high[0x20]; 1754 1755 u8 ether_stats_pkts64octets_low[0x20]; 1756 1757 u8 ether_stats_pkts65to127octets_high[0x20]; 1758 1759 u8 ether_stats_pkts65to127octets_low[0x20]; 1760 1761 u8 ether_stats_pkts128to255octets_high[0x20]; 1762 1763 u8 ether_stats_pkts128to255octets_low[0x20]; 1764 1765 u8 ether_stats_pkts256to511octets_high[0x20]; 1766 1767 u8 ether_stats_pkts256to511octets_low[0x20]; 1768 1769 u8 ether_stats_pkts512to1023octets_high[0x20]; 1770 1771 u8 ether_stats_pkts512to1023octets_low[0x20]; 1772 1773 u8 ether_stats_pkts1024to1518octets_high[0x20]; 1774 1775 u8 ether_stats_pkts1024to1518octets_low[0x20]; 1776 1777 u8 ether_stats_pkts1519to2047octets_high[0x20]; 1778 1779 u8 ether_stats_pkts1519to2047octets_low[0x20]; 1780 1781 u8 ether_stats_pkts2048to4095octets_high[0x20]; 1782 1783 u8 ether_stats_pkts2048to4095octets_low[0x20]; 1784 1785 u8 ether_stats_pkts4096to8191octets_high[0x20]; 1786 1787 u8 ether_stats_pkts4096to8191octets_low[0x20]; 1788 1789 u8 ether_stats_pkts8192to10239octets_high[0x20]; 1790 1791 u8 ether_stats_pkts8192to10239octets_low[0x20]; 1792 1793 u8 reserved_at_540[0x280]; 1794 }; 1795 1796 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 1797 u8 if_in_octets_high[0x20]; 1798 1799 u8 if_in_octets_low[0x20]; 1800 1801 u8 if_in_ucast_pkts_high[0x20]; 1802 1803 u8 if_in_ucast_pkts_low[0x20]; 1804 1805 u8 if_in_discards_high[0x20]; 1806 1807 u8 if_in_discards_low[0x20]; 1808 1809 u8 if_in_errors_high[0x20]; 1810 1811 u8 if_in_errors_low[0x20]; 1812 1813 u8 if_in_unknown_protos_high[0x20]; 1814 1815 u8 if_in_unknown_protos_low[0x20]; 1816 1817 u8 if_out_octets_high[0x20]; 1818 1819 u8 if_out_octets_low[0x20]; 1820 1821 u8 if_out_ucast_pkts_high[0x20]; 1822 1823 u8 if_out_ucast_pkts_low[0x20]; 1824 1825 u8 if_out_discards_high[0x20]; 1826 1827 u8 if_out_discards_low[0x20]; 1828 1829 u8 if_out_errors_high[0x20]; 1830 1831 u8 if_out_errors_low[0x20]; 1832 1833 u8 if_in_multicast_pkts_high[0x20]; 1834 1835 u8 if_in_multicast_pkts_low[0x20]; 1836 1837 u8 if_in_broadcast_pkts_high[0x20]; 1838 1839 u8 if_in_broadcast_pkts_low[0x20]; 1840 1841 u8 if_out_multicast_pkts_high[0x20]; 1842 1843 u8 if_out_multicast_pkts_low[0x20]; 1844 1845 u8 if_out_broadcast_pkts_high[0x20]; 1846 1847 u8 if_out_broadcast_pkts_low[0x20]; 1848 1849 u8 reserved_at_340[0x480]; 1850 }; 1851 1852 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 1853 u8 a_frames_transmitted_ok_high[0x20]; 1854 1855 u8 a_frames_transmitted_ok_low[0x20]; 1856 1857 u8 a_frames_received_ok_high[0x20]; 1858 1859 u8 a_frames_received_ok_low[0x20]; 1860 1861 u8 a_frame_check_sequence_errors_high[0x20]; 1862 1863 u8 a_frame_check_sequence_errors_low[0x20]; 1864 1865 u8 a_alignment_errors_high[0x20]; 1866 1867 u8 a_alignment_errors_low[0x20]; 1868 1869 u8 a_octets_transmitted_ok_high[0x20]; 1870 1871 u8 a_octets_transmitted_ok_low[0x20]; 1872 1873 u8 a_octets_received_ok_high[0x20]; 1874 1875 u8 a_octets_received_ok_low[0x20]; 1876 1877 u8 a_multicast_frames_xmitted_ok_high[0x20]; 1878 1879 u8 a_multicast_frames_xmitted_ok_low[0x20]; 1880 1881 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 1882 1883 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 1884 1885 u8 a_multicast_frames_received_ok_high[0x20]; 1886 1887 u8 a_multicast_frames_received_ok_low[0x20]; 1888 1889 u8 a_broadcast_frames_received_ok_high[0x20]; 1890 1891 u8 a_broadcast_frames_received_ok_low[0x20]; 1892 1893 u8 a_in_range_length_errors_high[0x20]; 1894 1895 u8 a_in_range_length_errors_low[0x20]; 1896 1897 u8 a_out_of_range_length_field_high[0x20]; 1898 1899 u8 a_out_of_range_length_field_low[0x20]; 1900 1901 u8 a_frame_too_long_errors_high[0x20]; 1902 1903 u8 a_frame_too_long_errors_low[0x20]; 1904 1905 u8 a_symbol_error_during_carrier_high[0x20]; 1906 1907 u8 a_symbol_error_during_carrier_low[0x20]; 1908 1909 u8 a_mac_control_frames_transmitted_high[0x20]; 1910 1911 u8 a_mac_control_frames_transmitted_low[0x20]; 1912 1913 u8 a_mac_control_frames_received_high[0x20]; 1914 1915 u8 a_mac_control_frames_received_low[0x20]; 1916 1917 u8 a_unsupported_opcodes_received_high[0x20]; 1918 1919 u8 a_unsupported_opcodes_received_low[0x20]; 1920 1921 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 1922 1923 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 1924 1925 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 1926 1927 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 1928 1929 u8 reserved_at_4c0[0x300]; 1930 }; 1931 1932 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 1933 u8 life_time_counter_high[0x20]; 1934 1935 u8 life_time_counter_low[0x20]; 1936 1937 u8 rx_errors[0x20]; 1938 1939 u8 tx_errors[0x20]; 1940 1941 u8 l0_to_recovery_eieos[0x20]; 1942 1943 u8 l0_to_recovery_ts[0x20]; 1944 1945 u8 l0_to_recovery_framing[0x20]; 1946 1947 u8 l0_to_recovery_retrain[0x20]; 1948 1949 u8 crc_error_dllp[0x20]; 1950 1951 u8 crc_error_tlp[0x20]; 1952 1953 u8 tx_overflow_buffer_pkt_high[0x20]; 1954 1955 u8 tx_overflow_buffer_pkt_low[0x20]; 1956 1957 u8 outbound_stalled_reads[0x20]; 1958 1959 u8 outbound_stalled_writes[0x20]; 1960 1961 u8 outbound_stalled_reads_events[0x20]; 1962 1963 u8 outbound_stalled_writes_events[0x20]; 1964 1965 u8 reserved_at_200[0x5c0]; 1966 }; 1967 1968 struct mlx5_ifc_cmd_inter_comp_event_bits { 1969 u8 command_completion_vector[0x20]; 1970 1971 u8 reserved_at_20[0xc0]; 1972 }; 1973 1974 struct mlx5_ifc_stall_vl_event_bits { 1975 u8 reserved_at_0[0x18]; 1976 u8 port_num[0x1]; 1977 u8 reserved_at_19[0x3]; 1978 u8 vl[0x4]; 1979 1980 u8 reserved_at_20[0xa0]; 1981 }; 1982 1983 struct mlx5_ifc_db_bf_congestion_event_bits { 1984 u8 event_subtype[0x8]; 1985 u8 reserved_at_8[0x8]; 1986 u8 congestion_level[0x8]; 1987 u8 reserved_at_18[0x8]; 1988 1989 u8 reserved_at_20[0xa0]; 1990 }; 1991 1992 struct mlx5_ifc_gpio_event_bits { 1993 u8 reserved_at_0[0x60]; 1994 1995 u8 gpio_event_hi[0x20]; 1996 1997 u8 gpio_event_lo[0x20]; 1998 1999 u8 reserved_at_a0[0x40]; 2000 }; 2001 2002 struct mlx5_ifc_port_state_change_event_bits { 2003 u8 reserved_at_0[0x40]; 2004 2005 u8 port_num[0x4]; 2006 u8 reserved_at_44[0x1c]; 2007 2008 u8 reserved_at_60[0x80]; 2009 }; 2010 2011 struct mlx5_ifc_dropped_packet_logged_bits { 2012 u8 reserved_at_0[0xe0]; 2013 }; 2014 2015 enum { 2016 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2017 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2018 }; 2019 2020 struct mlx5_ifc_cq_error_bits { 2021 u8 reserved_at_0[0x8]; 2022 u8 cqn[0x18]; 2023 2024 u8 reserved_at_20[0x20]; 2025 2026 u8 reserved_at_40[0x18]; 2027 u8 syndrome[0x8]; 2028 2029 u8 reserved_at_60[0x80]; 2030 }; 2031 2032 struct mlx5_ifc_rdma_page_fault_event_bits { 2033 u8 bytes_committed[0x20]; 2034 2035 u8 r_key[0x20]; 2036 2037 u8 reserved_at_40[0x10]; 2038 u8 packet_len[0x10]; 2039 2040 u8 rdma_op_len[0x20]; 2041 2042 u8 rdma_va[0x40]; 2043 2044 u8 reserved_at_c0[0x5]; 2045 u8 rdma[0x1]; 2046 u8 write[0x1]; 2047 u8 requestor[0x1]; 2048 u8 qp_number[0x18]; 2049 }; 2050 2051 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2052 u8 bytes_committed[0x20]; 2053 2054 u8 reserved_at_20[0x10]; 2055 u8 wqe_index[0x10]; 2056 2057 u8 reserved_at_40[0x10]; 2058 u8 len[0x10]; 2059 2060 u8 reserved_at_60[0x60]; 2061 2062 u8 reserved_at_c0[0x5]; 2063 u8 rdma[0x1]; 2064 u8 write_read[0x1]; 2065 u8 requestor[0x1]; 2066 u8 qpn[0x18]; 2067 }; 2068 2069 struct mlx5_ifc_qp_events_bits { 2070 u8 reserved_at_0[0xa0]; 2071 2072 u8 type[0x8]; 2073 u8 reserved_at_a8[0x18]; 2074 2075 u8 reserved_at_c0[0x8]; 2076 u8 qpn_rqn_sqn[0x18]; 2077 }; 2078 2079 struct mlx5_ifc_dct_events_bits { 2080 u8 reserved_at_0[0xc0]; 2081 2082 u8 reserved_at_c0[0x8]; 2083 u8 dct_number[0x18]; 2084 }; 2085 2086 struct mlx5_ifc_comp_event_bits { 2087 u8 reserved_at_0[0xc0]; 2088 2089 u8 reserved_at_c0[0x8]; 2090 u8 cq_number[0x18]; 2091 }; 2092 2093 enum { 2094 MLX5_QPC_STATE_RST = 0x0, 2095 MLX5_QPC_STATE_INIT = 0x1, 2096 MLX5_QPC_STATE_RTR = 0x2, 2097 MLX5_QPC_STATE_RTS = 0x3, 2098 MLX5_QPC_STATE_SQER = 0x4, 2099 MLX5_QPC_STATE_ERR = 0x6, 2100 MLX5_QPC_STATE_SQD = 0x7, 2101 MLX5_QPC_STATE_SUSPENDED = 0x9, 2102 }; 2103 2104 enum { 2105 MLX5_QPC_ST_RC = 0x0, 2106 MLX5_QPC_ST_UC = 0x1, 2107 MLX5_QPC_ST_UD = 0x2, 2108 MLX5_QPC_ST_XRC = 0x3, 2109 MLX5_QPC_ST_DCI = 0x5, 2110 MLX5_QPC_ST_QP0 = 0x7, 2111 MLX5_QPC_ST_QP1 = 0x8, 2112 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2113 MLX5_QPC_ST_REG_UMR = 0xc, 2114 }; 2115 2116 enum { 2117 MLX5_QPC_PM_STATE_ARMED = 0x0, 2118 MLX5_QPC_PM_STATE_REARM = 0x1, 2119 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2120 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 2121 }; 2122 2123 enum { 2124 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 2125 }; 2126 2127 enum { 2128 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2129 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2130 }; 2131 2132 enum { 2133 MLX5_QPC_MTU_256_BYTES = 0x1, 2134 MLX5_QPC_MTU_512_BYTES = 0x2, 2135 MLX5_QPC_MTU_1K_BYTES = 0x3, 2136 MLX5_QPC_MTU_2K_BYTES = 0x4, 2137 MLX5_QPC_MTU_4K_BYTES = 0x5, 2138 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2139 }; 2140 2141 enum { 2142 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2143 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2144 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2145 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2146 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2147 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2148 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2149 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2150 }; 2151 2152 enum { 2153 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2154 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2155 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2156 }; 2157 2158 enum { 2159 MLX5_QPC_CS_RES_DISABLE = 0x0, 2160 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2161 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2162 }; 2163 2164 struct mlx5_ifc_qpc_bits { 2165 u8 state[0x4]; 2166 u8 lag_tx_port_affinity[0x4]; 2167 u8 st[0x8]; 2168 u8 reserved_at_10[0x3]; 2169 u8 pm_state[0x2]; 2170 u8 reserved_at_15[0x3]; 2171 u8 offload_type[0x4]; 2172 u8 end_padding_mode[0x2]; 2173 u8 reserved_at_1e[0x2]; 2174 2175 u8 wq_signature[0x1]; 2176 u8 block_lb_mc[0x1]; 2177 u8 atomic_like_write_en[0x1]; 2178 u8 latency_sensitive[0x1]; 2179 u8 reserved_at_24[0x1]; 2180 u8 drain_sigerr[0x1]; 2181 u8 reserved_at_26[0x2]; 2182 u8 pd[0x18]; 2183 2184 u8 mtu[0x3]; 2185 u8 log_msg_max[0x5]; 2186 u8 reserved_at_48[0x1]; 2187 u8 log_rq_size[0x4]; 2188 u8 log_rq_stride[0x3]; 2189 u8 no_sq[0x1]; 2190 u8 log_sq_size[0x4]; 2191 u8 reserved_at_55[0x6]; 2192 u8 rlky[0x1]; 2193 u8 ulp_stateless_offload_mode[0x4]; 2194 2195 u8 counter_set_id[0x8]; 2196 u8 uar_page[0x18]; 2197 2198 u8 reserved_at_80[0x8]; 2199 u8 user_index[0x18]; 2200 2201 u8 reserved_at_a0[0x3]; 2202 u8 log_page_size[0x5]; 2203 u8 remote_qpn[0x18]; 2204 2205 struct mlx5_ifc_ads_bits primary_address_path; 2206 2207 struct mlx5_ifc_ads_bits secondary_address_path; 2208 2209 u8 log_ack_req_freq[0x4]; 2210 u8 reserved_at_384[0x4]; 2211 u8 log_sra_max[0x3]; 2212 u8 reserved_at_38b[0x2]; 2213 u8 retry_count[0x3]; 2214 u8 rnr_retry[0x3]; 2215 u8 reserved_at_393[0x1]; 2216 u8 fre[0x1]; 2217 u8 cur_rnr_retry[0x3]; 2218 u8 cur_retry_count[0x3]; 2219 u8 reserved_at_39b[0x5]; 2220 2221 u8 reserved_at_3a0[0x20]; 2222 2223 u8 reserved_at_3c0[0x8]; 2224 u8 next_send_psn[0x18]; 2225 2226 u8 reserved_at_3e0[0x8]; 2227 u8 cqn_snd[0x18]; 2228 2229 u8 reserved_at_400[0x8]; 2230 u8 deth_sqpn[0x18]; 2231 2232 u8 reserved_at_420[0x20]; 2233 2234 u8 reserved_at_440[0x8]; 2235 u8 last_acked_psn[0x18]; 2236 2237 u8 reserved_at_460[0x8]; 2238 u8 ssn[0x18]; 2239 2240 u8 reserved_at_480[0x8]; 2241 u8 log_rra_max[0x3]; 2242 u8 reserved_at_48b[0x1]; 2243 u8 atomic_mode[0x4]; 2244 u8 rre[0x1]; 2245 u8 rwe[0x1]; 2246 u8 rae[0x1]; 2247 u8 reserved_at_493[0x1]; 2248 u8 page_offset[0x6]; 2249 u8 reserved_at_49a[0x3]; 2250 u8 cd_slave_receive[0x1]; 2251 u8 cd_slave_send[0x1]; 2252 u8 cd_master[0x1]; 2253 2254 u8 reserved_at_4a0[0x3]; 2255 u8 min_rnr_nak[0x5]; 2256 u8 next_rcv_psn[0x18]; 2257 2258 u8 reserved_at_4c0[0x8]; 2259 u8 xrcd[0x18]; 2260 2261 u8 reserved_at_4e0[0x8]; 2262 u8 cqn_rcv[0x18]; 2263 2264 u8 dbr_addr[0x40]; 2265 2266 u8 q_key[0x20]; 2267 2268 u8 reserved_at_560[0x5]; 2269 u8 rq_type[0x3]; 2270 u8 srqn_rmpn_xrqn[0x18]; 2271 2272 u8 reserved_at_580[0x8]; 2273 u8 rmsn[0x18]; 2274 2275 u8 hw_sq_wqebb_counter[0x10]; 2276 u8 sw_sq_wqebb_counter[0x10]; 2277 2278 u8 hw_rq_counter[0x20]; 2279 2280 u8 sw_rq_counter[0x20]; 2281 2282 u8 reserved_at_600[0x20]; 2283 2284 u8 reserved_at_620[0xf]; 2285 u8 cgs[0x1]; 2286 u8 cs_req[0x8]; 2287 u8 cs_res[0x8]; 2288 2289 u8 dc_access_key[0x40]; 2290 2291 u8 reserved_at_680[0xc0]; 2292 }; 2293 2294 struct mlx5_ifc_roce_addr_layout_bits { 2295 u8 source_l3_address[16][0x8]; 2296 2297 u8 reserved_at_80[0x3]; 2298 u8 vlan_valid[0x1]; 2299 u8 vlan_id[0xc]; 2300 u8 source_mac_47_32[0x10]; 2301 2302 u8 source_mac_31_0[0x20]; 2303 2304 u8 reserved_at_c0[0x14]; 2305 u8 roce_l3_type[0x4]; 2306 u8 roce_version[0x8]; 2307 2308 u8 reserved_at_e0[0x20]; 2309 }; 2310 2311 union mlx5_ifc_hca_cap_union_bits { 2312 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 2313 struct mlx5_ifc_odp_cap_bits odp_cap; 2314 struct mlx5_ifc_atomic_caps_bits atomic_caps; 2315 struct mlx5_ifc_roce_cap_bits roce_cap; 2316 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 2317 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 2318 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 2319 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 2320 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 2321 struct mlx5_ifc_qos_cap_bits qos_cap; 2322 struct mlx5_ifc_fpga_cap_bits fpga_cap; 2323 u8 reserved_at_0[0x8000]; 2324 }; 2325 2326 enum { 2327 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 2328 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2329 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2330 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2331 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, 2332 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 2333 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 2334 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 2335 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 2336 }; 2337 2338 struct mlx5_ifc_vlan_bits { 2339 u8 ethtype[0x10]; 2340 u8 prio[0x3]; 2341 u8 cfi[0x1]; 2342 u8 vid[0xc]; 2343 }; 2344 2345 struct mlx5_ifc_flow_context_bits { 2346 struct mlx5_ifc_vlan_bits push_vlan; 2347 2348 u8 group_id[0x20]; 2349 2350 u8 reserved_at_40[0x8]; 2351 u8 flow_tag[0x18]; 2352 2353 u8 reserved_at_60[0x10]; 2354 u8 action[0x10]; 2355 2356 u8 reserved_at_80[0x8]; 2357 u8 destination_list_size[0x18]; 2358 2359 u8 reserved_at_a0[0x8]; 2360 u8 flow_counter_list_size[0x18]; 2361 2362 u8 encap_id[0x20]; 2363 2364 u8 modify_header_id[0x20]; 2365 2366 u8 reserved_at_100[0x100]; 2367 2368 struct mlx5_ifc_fte_match_param_bits match_value; 2369 2370 u8 reserved_at_1200[0x600]; 2371 2372 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; 2373 }; 2374 2375 enum { 2376 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2377 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2378 }; 2379 2380 struct mlx5_ifc_xrc_srqc_bits { 2381 u8 state[0x4]; 2382 u8 log_xrc_srq_size[0x4]; 2383 u8 reserved_at_8[0x18]; 2384 2385 u8 wq_signature[0x1]; 2386 u8 cont_srq[0x1]; 2387 u8 reserved_at_22[0x1]; 2388 u8 rlky[0x1]; 2389 u8 basic_cyclic_rcv_wqe[0x1]; 2390 u8 log_rq_stride[0x3]; 2391 u8 xrcd[0x18]; 2392 2393 u8 page_offset[0x6]; 2394 u8 reserved_at_46[0x2]; 2395 u8 cqn[0x18]; 2396 2397 u8 reserved_at_60[0x20]; 2398 2399 u8 user_index_equal_xrc_srqn[0x1]; 2400 u8 reserved_at_81[0x1]; 2401 u8 log_page_size[0x6]; 2402 u8 user_index[0x18]; 2403 2404 u8 reserved_at_a0[0x20]; 2405 2406 u8 reserved_at_c0[0x8]; 2407 u8 pd[0x18]; 2408 2409 u8 lwm[0x10]; 2410 u8 wqe_cnt[0x10]; 2411 2412 u8 reserved_at_100[0x40]; 2413 2414 u8 db_record_addr_h[0x20]; 2415 2416 u8 db_record_addr_l[0x1e]; 2417 u8 reserved_at_17e[0x2]; 2418 2419 u8 reserved_at_180[0x80]; 2420 }; 2421 2422 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2423 u8 counter_error_queues[0x20]; 2424 2425 u8 total_error_queues[0x20]; 2426 2427 u8 send_queue_priority_update_flow[0x20]; 2428 2429 u8 reserved_at_60[0x20]; 2430 2431 u8 nic_receive_steering_discard[0x40]; 2432 2433 u8 receive_discard_vport_down[0x40]; 2434 2435 u8 transmit_discard_vport_down[0x40]; 2436 2437 u8 reserved_at_140[0xec0]; 2438 }; 2439 2440 struct mlx5_ifc_traffic_counter_bits { 2441 u8 packets[0x40]; 2442 2443 u8 octets[0x40]; 2444 }; 2445 2446 struct mlx5_ifc_tisc_bits { 2447 u8 strict_lag_tx_port_affinity[0x1]; 2448 u8 reserved_at_1[0x3]; 2449 u8 lag_tx_port_affinity[0x04]; 2450 2451 u8 reserved_at_8[0x4]; 2452 u8 prio[0x4]; 2453 u8 reserved_at_10[0x10]; 2454 2455 u8 reserved_at_20[0x100]; 2456 2457 u8 reserved_at_120[0x8]; 2458 u8 transport_domain[0x18]; 2459 2460 u8 reserved_at_140[0x8]; 2461 u8 underlay_qpn[0x18]; 2462 u8 reserved_at_160[0x3a0]; 2463 }; 2464 2465 enum { 2466 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2467 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2468 }; 2469 2470 enum { 2471 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2472 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2473 }; 2474 2475 enum { 2476 MLX5_RX_HASH_FN_NONE = 0x0, 2477 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 2478 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 2479 }; 2480 2481 enum { 2482 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, 2483 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, 2484 }; 2485 2486 struct mlx5_ifc_tirc_bits { 2487 u8 reserved_at_0[0x20]; 2488 2489 u8 disp_type[0x4]; 2490 u8 reserved_at_24[0x1c]; 2491 2492 u8 reserved_at_40[0x40]; 2493 2494 u8 reserved_at_80[0x4]; 2495 u8 lro_timeout_period_usecs[0x10]; 2496 u8 lro_enable_mask[0x4]; 2497 u8 lro_max_ip_payload_size[0x8]; 2498 2499 u8 reserved_at_a0[0x40]; 2500 2501 u8 reserved_at_e0[0x8]; 2502 u8 inline_rqn[0x18]; 2503 2504 u8 rx_hash_symmetric[0x1]; 2505 u8 reserved_at_101[0x1]; 2506 u8 tunneled_offload_en[0x1]; 2507 u8 reserved_at_103[0x5]; 2508 u8 indirect_table[0x18]; 2509 2510 u8 rx_hash_fn[0x4]; 2511 u8 reserved_at_124[0x2]; 2512 u8 self_lb_block[0x2]; 2513 u8 transport_domain[0x18]; 2514 2515 u8 rx_hash_toeplitz_key[10][0x20]; 2516 2517 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2518 2519 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2520 2521 u8 reserved_at_2c0[0x4c0]; 2522 }; 2523 2524 enum { 2525 MLX5_SRQC_STATE_GOOD = 0x0, 2526 MLX5_SRQC_STATE_ERROR = 0x1, 2527 }; 2528 2529 struct mlx5_ifc_srqc_bits { 2530 u8 state[0x4]; 2531 u8 log_srq_size[0x4]; 2532 u8 reserved_at_8[0x18]; 2533 2534 u8 wq_signature[0x1]; 2535 u8 cont_srq[0x1]; 2536 u8 reserved_at_22[0x1]; 2537 u8 rlky[0x1]; 2538 u8 reserved_at_24[0x1]; 2539 u8 log_rq_stride[0x3]; 2540 u8 xrcd[0x18]; 2541 2542 u8 page_offset[0x6]; 2543 u8 reserved_at_46[0x2]; 2544 u8 cqn[0x18]; 2545 2546 u8 reserved_at_60[0x20]; 2547 2548 u8 reserved_at_80[0x2]; 2549 u8 log_page_size[0x6]; 2550 u8 reserved_at_88[0x18]; 2551 2552 u8 reserved_at_a0[0x20]; 2553 2554 u8 reserved_at_c0[0x8]; 2555 u8 pd[0x18]; 2556 2557 u8 lwm[0x10]; 2558 u8 wqe_cnt[0x10]; 2559 2560 u8 reserved_at_100[0x40]; 2561 2562 u8 dbr_addr[0x40]; 2563 2564 u8 reserved_at_180[0x80]; 2565 }; 2566 2567 enum { 2568 MLX5_SQC_STATE_RST = 0x0, 2569 MLX5_SQC_STATE_RDY = 0x1, 2570 MLX5_SQC_STATE_ERR = 0x3, 2571 }; 2572 2573 struct mlx5_ifc_sqc_bits { 2574 u8 rlky[0x1]; 2575 u8 cd_master[0x1]; 2576 u8 fre[0x1]; 2577 u8 flush_in_error_en[0x1]; 2578 u8 allow_multi_pkt_send_wqe[0x1]; 2579 u8 min_wqe_inline_mode[0x3]; 2580 u8 state[0x4]; 2581 u8 reg_umr[0x1]; 2582 u8 allow_swp[0x1]; 2583 u8 hairpin[0x1]; 2584 u8 reserved_at_f[0x11]; 2585 2586 u8 reserved_at_20[0x8]; 2587 u8 user_index[0x18]; 2588 2589 u8 reserved_at_40[0x8]; 2590 u8 cqn[0x18]; 2591 2592 u8 reserved_at_60[0x8]; 2593 u8 hairpin_peer_rq[0x18]; 2594 2595 u8 reserved_at_80[0x10]; 2596 u8 hairpin_peer_vhca[0x10]; 2597 2598 u8 reserved_at_a0[0x50]; 2599 2600 u8 packet_pacing_rate_limit_index[0x10]; 2601 u8 tis_lst_sz[0x10]; 2602 u8 reserved_at_110[0x10]; 2603 2604 u8 reserved_at_120[0x40]; 2605 2606 u8 reserved_at_160[0x8]; 2607 u8 tis_num_0[0x18]; 2608 2609 struct mlx5_ifc_wq_bits wq; 2610 }; 2611 2612 enum { 2613 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2614 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2615 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2616 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2617 }; 2618 2619 struct mlx5_ifc_scheduling_context_bits { 2620 u8 element_type[0x8]; 2621 u8 reserved_at_8[0x18]; 2622 2623 u8 element_attributes[0x20]; 2624 2625 u8 parent_element_id[0x20]; 2626 2627 u8 reserved_at_60[0x40]; 2628 2629 u8 bw_share[0x20]; 2630 2631 u8 max_average_bw[0x20]; 2632 2633 u8 reserved_at_e0[0x120]; 2634 }; 2635 2636 struct mlx5_ifc_rqtc_bits { 2637 u8 reserved_at_0[0xa0]; 2638 2639 u8 reserved_at_a0[0x10]; 2640 u8 rqt_max_size[0x10]; 2641 2642 u8 reserved_at_c0[0x10]; 2643 u8 rqt_actual_size[0x10]; 2644 2645 u8 reserved_at_e0[0x6a0]; 2646 2647 struct mlx5_ifc_rq_num_bits rq_num[0]; 2648 }; 2649 2650 enum { 2651 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2652 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2653 }; 2654 2655 enum { 2656 MLX5_RQC_STATE_RST = 0x0, 2657 MLX5_RQC_STATE_RDY = 0x1, 2658 MLX5_RQC_STATE_ERR = 0x3, 2659 }; 2660 2661 struct mlx5_ifc_rqc_bits { 2662 u8 rlky[0x1]; 2663 u8 delay_drop_en[0x1]; 2664 u8 scatter_fcs[0x1]; 2665 u8 vsd[0x1]; 2666 u8 mem_rq_type[0x4]; 2667 u8 state[0x4]; 2668 u8 reserved_at_c[0x1]; 2669 u8 flush_in_error_en[0x1]; 2670 u8 hairpin[0x1]; 2671 u8 reserved_at_f[0x11]; 2672 2673 u8 reserved_at_20[0x8]; 2674 u8 user_index[0x18]; 2675 2676 u8 reserved_at_40[0x8]; 2677 u8 cqn[0x18]; 2678 2679 u8 counter_set_id[0x8]; 2680 u8 reserved_at_68[0x18]; 2681 2682 u8 reserved_at_80[0x8]; 2683 u8 rmpn[0x18]; 2684 2685 u8 reserved_at_a0[0x8]; 2686 u8 hairpin_peer_sq[0x18]; 2687 2688 u8 reserved_at_c0[0x10]; 2689 u8 hairpin_peer_vhca[0x10]; 2690 2691 u8 reserved_at_e0[0xa0]; 2692 2693 struct mlx5_ifc_wq_bits wq; 2694 }; 2695 2696 enum { 2697 MLX5_RMPC_STATE_RDY = 0x1, 2698 MLX5_RMPC_STATE_ERR = 0x3, 2699 }; 2700 2701 struct mlx5_ifc_rmpc_bits { 2702 u8 reserved_at_0[0x8]; 2703 u8 state[0x4]; 2704 u8 reserved_at_c[0x14]; 2705 2706 u8 basic_cyclic_rcv_wqe[0x1]; 2707 u8 reserved_at_21[0x1f]; 2708 2709 u8 reserved_at_40[0x140]; 2710 2711 struct mlx5_ifc_wq_bits wq; 2712 }; 2713 2714 struct mlx5_ifc_nic_vport_context_bits { 2715 u8 reserved_at_0[0x5]; 2716 u8 min_wqe_inline_mode[0x3]; 2717 u8 reserved_at_8[0x15]; 2718 u8 disable_mc_local_lb[0x1]; 2719 u8 disable_uc_local_lb[0x1]; 2720 u8 roce_en[0x1]; 2721 2722 u8 arm_change_event[0x1]; 2723 u8 reserved_at_21[0x1a]; 2724 u8 event_on_mtu[0x1]; 2725 u8 event_on_promisc_change[0x1]; 2726 u8 event_on_vlan_change[0x1]; 2727 u8 event_on_mc_address_change[0x1]; 2728 u8 event_on_uc_address_change[0x1]; 2729 2730 u8 reserved_at_40[0xc]; 2731 2732 u8 affiliation_criteria[0x4]; 2733 u8 affiliated_vhca_id[0x10]; 2734 2735 u8 reserved_at_60[0xd0]; 2736 2737 u8 mtu[0x10]; 2738 2739 u8 system_image_guid[0x40]; 2740 u8 port_guid[0x40]; 2741 u8 node_guid[0x40]; 2742 2743 u8 reserved_at_200[0x140]; 2744 u8 qkey_violation_counter[0x10]; 2745 u8 reserved_at_350[0x430]; 2746 2747 u8 promisc_uc[0x1]; 2748 u8 promisc_mc[0x1]; 2749 u8 promisc_all[0x1]; 2750 u8 reserved_at_783[0x2]; 2751 u8 allowed_list_type[0x3]; 2752 u8 reserved_at_788[0xc]; 2753 u8 allowed_list_size[0xc]; 2754 2755 struct mlx5_ifc_mac_address_layout_bits permanent_address; 2756 2757 u8 reserved_at_7e0[0x20]; 2758 2759 u8 current_uc_mac_address[0][0x40]; 2760 }; 2761 2762 enum { 2763 MLX5_MKC_ACCESS_MODE_PA = 0x0, 2764 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 2765 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 2766 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 2767 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 2768 }; 2769 2770 struct mlx5_ifc_mkc_bits { 2771 u8 reserved_at_0[0x1]; 2772 u8 free[0x1]; 2773 u8 reserved_at_2[0x1]; 2774 u8 access_mode_4_2[0x3]; 2775 u8 reserved_at_6[0x7]; 2776 u8 relaxed_ordering_write[0x1]; 2777 u8 reserved_at_e[0x1]; 2778 u8 small_fence_on_rdma_read_response[0x1]; 2779 u8 umr_en[0x1]; 2780 u8 a[0x1]; 2781 u8 rw[0x1]; 2782 u8 rr[0x1]; 2783 u8 lw[0x1]; 2784 u8 lr[0x1]; 2785 u8 access_mode_1_0[0x2]; 2786 u8 reserved_at_18[0x8]; 2787 2788 u8 qpn[0x18]; 2789 u8 mkey_7_0[0x8]; 2790 2791 u8 reserved_at_40[0x20]; 2792 2793 u8 length64[0x1]; 2794 u8 bsf_en[0x1]; 2795 u8 sync_umr[0x1]; 2796 u8 reserved_at_63[0x2]; 2797 u8 expected_sigerr_count[0x1]; 2798 u8 reserved_at_66[0x1]; 2799 u8 en_rinval[0x1]; 2800 u8 pd[0x18]; 2801 2802 u8 start_addr[0x40]; 2803 2804 u8 len[0x40]; 2805 2806 u8 bsf_octword_size[0x20]; 2807 2808 u8 reserved_at_120[0x80]; 2809 2810 u8 translations_octword_size[0x20]; 2811 2812 u8 reserved_at_1c0[0x1b]; 2813 u8 log_page_size[0x5]; 2814 2815 u8 reserved_at_1e0[0x20]; 2816 }; 2817 2818 struct mlx5_ifc_pkey_bits { 2819 u8 reserved_at_0[0x10]; 2820 u8 pkey[0x10]; 2821 }; 2822 2823 struct mlx5_ifc_array128_auto_bits { 2824 u8 array128_auto[16][0x8]; 2825 }; 2826 2827 struct mlx5_ifc_hca_vport_context_bits { 2828 u8 field_select[0x20]; 2829 2830 u8 reserved_at_20[0xe0]; 2831 2832 u8 sm_virt_aware[0x1]; 2833 u8 has_smi[0x1]; 2834 u8 has_raw[0x1]; 2835 u8 grh_required[0x1]; 2836 u8 reserved_at_104[0xc]; 2837 u8 port_physical_state[0x4]; 2838 u8 vport_state_policy[0x4]; 2839 u8 port_state[0x4]; 2840 u8 vport_state[0x4]; 2841 2842 u8 reserved_at_120[0x20]; 2843 2844 u8 system_image_guid[0x40]; 2845 2846 u8 port_guid[0x40]; 2847 2848 u8 node_guid[0x40]; 2849 2850 u8 cap_mask1[0x20]; 2851 2852 u8 cap_mask1_field_select[0x20]; 2853 2854 u8 cap_mask2[0x20]; 2855 2856 u8 cap_mask2_field_select[0x20]; 2857 2858 u8 reserved_at_280[0x80]; 2859 2860 u8 lid[0x10]; 2861 u8 reserved_at_310[0x4]; 2862 u8 init_type_reply[0x4]; 2863 u8 lmc[0x3]; 2864 u8 subnet_timeout[0x5]; 2865 2866 u8 sm_lid[0x10]; 2867 u8 sm_sl[0x4]; 2868 u8 reserved_at_334[0xc]; 2869 2870 u8 qkey_violation_counter[0x10]; 2871 u8 pkey_violation_counter[0x10]; 2872 2873 u8 reserved_at_360[0xca0]; 2874 }; 2875 2876 struct mlx5_ifc_esw_vport_context_bits { 2877 u8 reserved_at_0[0x3]; 2878 u8 vport_svlan_strip[0x1]; 2879 u8 vport_cvlan_strip[0x1]; 2880 u8 vport_svlan_insert[0x1]; 2881 u8 vport_cvlan_insert[0x2]; 2882 u8 reserved_at_8[0x18]; 2883 2884 u8 reserved_at_20[0x20]; 2885 2886 u8 svlan_cfi[0x1]; 2887 u8 svlan_pcp[0x3]; 2888 u8 svlan_id[0xc]; 2889 u8 cvlan_cfi[0x1]; 2890 u8 cvlan_pcp[0x3]; 2891 u8 cvlan_id[0xc]; 2892 2893 u8 reserved_at_60[0x7a0]; 2894 }; 2895 2896 enum { 2897 MLX5_EQC_STATUS_OK = 0x0, 2898 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 2899 }; 2900 2901 enum { 2902 MLX5_EQC_ST_ARMED = 0x9, 2903 MLX5_EQC_ST_FIRED = 0xa, 2904 }; 2905 2906 struct mlx5_ifc_eqc_bits { 2907 u8 status[0x4]; 2908 u8 reserved_at_4[0x9]; 2909 u8 ec[0x1]; 2910 u8 oi[0x1]; 2911 u8 reserved_at_f[0x5]; 2912 u8 st[0x4]; 2913 u8 reserved_at_18[0x8]; 2914 2915 u8 reserved_at_20[0x20]; 2916 2917 u8 reserved_at_40[0x14]; 2918 u8 page_offset[0x6]; 2919 u8 reserved_at_5a[0x6]; 2920 2921 u8 reserved_at_60[0x3]; 2922 u8 log_eq_size[0x5]; 2923 u8 uar_page[0x18]; 2924 2925 u8 reserved_at_80[0x20]; 2926 2927 u8 reserved_at_a0[0x18]; 2928 u8 intr[0x8]; 2929 2930 u8 reserved_at_c0[0x3]; 2931 u8 log_page_size[0x5]; 2932 u8 reserved_at_c8[0x18]; 2933 2934 u8 reserved_at_e0[0x60]; 2935 2936 u8 reserved_at_140[0x8]; 2937 u8 consumer_counter[0x18]; 2938 2939 u8 reserved_at_160[0x8]; 2940 u8 producer_counter[0x18]; 2941 2942 u8 reserved_at_180[0x80]; 2943 }; 2944 2945 enum { 2946 MLX5_DCTC_STATE_ACTIVE = 0x0, 2947 MLX5_DCTC_STATE_DRAINING = 0x1, 2948 MLX5_DCTC_STATE_DRAINED = 0x2, 2949 }; 2950 2951 enum { 2952 MLX5_DCTC_CS_RES_DISABLE = 0x0, 2953 MLX5_DCTC_CS_RES_NA = 0x1, 2954 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 2955 }; 2956 2957 enum { 2958 MLX5_DCTC_MTU_256_BYTES = 0x1, 2959 MLX5_DCTC_MTU_512_BYTES = 0x2, 2960 MLX5_DCTC_MTU_1K_BYTES = 0x3, 2961 MLX5_DCTC_MTU_2K_BYTES = 0x4, 2962 MLX5_DCTC_MTU_4K_BYTES = 0x5, 2963 }; 2964 2965 struct mlx5_ifc_dctc_bits { 2966 u8 reserved_at_0[0x4]; 2967 u8 state[0x4]; 2968 u8 reserved_at_8[0x18]; 2969 2970 u8 reserved_at_20[0x8]; 2971 u8 user_index[0x18]; 2972 2973 u8 reserved_at_40[0x8]; 2974 u8 cqn[0x18]; 2975 2976 u8 counter_set_id[0x8]; 2977 u8 atomic_mode[0x4]; 2978 u8 rre[0x1]; 2979 u8 rwe[0x1]; 2980 u8 rae[0x1]; 2981 u8 atomic_like_write_en[0x1]; 2982 u8 latency_sensitive[0x1]; 2983 u8 rlky[0x1]; 2984 u8 free_ar[0x1]; 2985 u8 reserved_at_73[0xd]; 2986 2987 u8 reserved_at_80[0x8]; 2988 u8 cs_res[0x8]; 2989 u8 reserved_at_90[0x3]; 2990 u8 min_rnr_nak[0x5]; 2991 u8 reserved_at_98[0x8]; 2992 2993 u8 reserved_at_a0[0x8]; 2994 u8 srqn_xrqn[0x18]; 2995 2996 u8 reserved_at_c0[0x8]; 2997 u8 pd[0x18]; 2998 2999 u8 tclass[0x8]; 3000 u8 reserved_at_e8[0x4]; 3001 u8 flow_label[0x14]; 3002 3003 u8 dc_access_key[0x40]; 3004 3005 u8 reserved_at_140[0x5]; 3006 u8 mtu[0x3]; 3007 u8 port[0x8]; 3008 u8 pkey_index[0x10]; 3009 3010 u8 reserved_at_160[0x8]; 3011 u8 my_addr_index[0x8]; 3012 u8 reserved_at_170[0x8]; 3013 u8 hop_limit[0x8]; 3014 3015 u8 dc_access_key_violation_count[0x20]; 3016 3017 u8 reserved_at_1a0[0x14]; 3018 u8 dei_cfi[0x1]; 3019 u8 eth_prio[0x3]; 3020 u8 ecn[0x2]; 3021 u8 dscp[0x6]; 3022 3023 u8 reserved_at_1c0[0x40]; 3024 }; 3025 3026 enum { 3027 MLX5_CQC_STATUS_OK = 0x0, 3028 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3029 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3030 }; 3031 3032 enum { 3033 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 3034 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 3035 }; 3036 3037 enum { 3038 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 3039 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 3040 MLX5_CQC_ST_FIRED = 0xa, 3041 }; 3042 3043 enum { 3044 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3045 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3046 MLX5_CQ_PERIOD_NUM_MODES 3047 }; 3048 3049 struct mlx5_ifc_cqc_bits { 3050 u8 status[0x4]; 3051 u8 reserved_at_4[0x4]; 3052 u8 cqe_sz[0x3]; 3053 u8 cc[0x1]; 3054 u8 reserved_at_c[0x1]; 3055 u8 scqe_break_moderation_en[0x1]; 3056 u8 oi[0x1]; 3057 u8 cq_period_mode[0x2]; 3058 u8 cqe_comp_en[0x1]; 3059 u8 mini_cqe_res_format[0x2]; 3060 u8 st[0x4]; 3061 u8 reserved_at_18[0x8]; 3062 3063 u8 reserved_at_20[0x20]; 3064 3065 u8 reserved_at_40[0x14]; 3066 u8 page_offset[0x6]; 3067 u8 reserved_at_5a[0x6]; 3068 3069 u8 reserved_at_60[0x3]; 3070 u8 log_cq_size[0x5]; 3071 u8 uar_page[0x18]; 3072 3073 u8 reserved_at_80[0x4]; 3074 u8 cq_period[0xc]; 3075 u8 cq_max_count[0x10]; 3076 3077 u8 reserved_at_a0[0x18]; 3078 u8 c_eqn[0x8]; 3079 3080 u8 reserved_at_c0[0x3]; 3081 u8 log_page_size[0x5]; 3082 u8 reserved_at_c8[0x18]; 3083 3084 u8 reserved_at_e0[0x20]; 3085 3086 u8 reserved_at_100[0x8]; 3087 u8 last_notified_index[0x18]; 3088 3089 u8 reserved_at_120[0x8]; 3090 u8 last_solicit_index[0x18]; 3091 3092 u8 reserved_at_140[0x8]; 3093 u8 consumer_counter[0x18]; 3094 3095 u8 reserved_at_160[0x8]; 3096 u8 producer_counter[0x18]; 3097 3098 u8 reserved_at_180[0x40]; 3099 3100 u8 dbr_addr[0x40]; 3101 }; 3102 3103 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3104 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3105 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3106 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3107 u8 reserved_at_0[0x800]; 3108 }; 3109 3110 struct mlx5_ifc_query_adapter_param_block_bits { 3111 u8 reserved_at_0[0xc0]; 3112 3113 u8 reserved_at_c0[0x8]; 3114 u8 ieee_vendor_id[0x18]; 3115 3116 u8 reserved_at_e0[0x10]; 3117 u8 vsd_vendor_id[0x10]; 3118 3119 u8 vsd[208][0x8]; 3120 3121 u8 vsd_contd_psid[16][0x8]; 3122 }; 3123 3124 enum { 3125 MLX5_XRQC_STATE_GOOD = 0x0, 3126 MLX5_XRQC_STATE_ERROR = 0x1, 3127 }; 3128 3129 enum { 3130 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3131 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3132 }; 3133 3134 enum { 3135 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3136 }; 3137 3138 struct mlx5_ifc_tag_matching_topology_context_bits { 3139 u8 log_matching_list_sz[0x4]; 3140 u8 reserved_at_4[0xc]; 3141 u8 append_next_index[0x10]; 3142 3143 u8 sw_phase_cnt[0x10]; 3144 u8 hw_phase_cnt[0x10]; 3145 3146 u8 reserved_at_40[0x40]; 3147 }; 3148 3149 struct mlx5_ifc_xrqc_bits { 3150 u8 state[0x4]; 3151 u8 rlkey[0x1]; 3152 u8 reserved_at_5[0xf]; 3153 u8 topology[0x4]; 3154 u8 reserved_at_18[0x4]; 3155 u8 offload[0x4]; 3156 3157 u8 reserved_at_20[0x8]; 3158 u8 user_index[0x18]; 3159 3160 u8 reserved_at_40[0x8]; 3161 u8 cqn[0x18]; 3162 3163 u8 reserved_at_60[0xa0]; 3164 3165 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3166 3167 u8 reserved_at_180[0x280]; 3168 3169 struct mlx5_ifc_wq_bits wq; 3170 }; 3171 3172 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3173 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3174 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3175 u8 reserved_at_0[0x20]; 3176 }; 3177 3178 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3179 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3180 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3181 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3182 u8 reserved_at_0[0x20]; 3183 }; 3184 3185 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 3186 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 3187 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 3188 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 3189 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 3190 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 3191 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 3192 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 3193 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 3194 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 3195 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 3196 u8 reserved_at_0[0x7c0]; 3197 }; 3198 3199 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 3200 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 3201 u8 reserved_at_0[0x7c0]; 3202 }; 3203 3204 union mlx5_ifc_event_auto_bits { 3205 struct mlx5_ifc_comp_event_bits comp_event; 3206 struct mlx5_ifc_dct_events_bits dct_events; 3207 struct mlx5_ifc_qp_events_bits qp_events; 3208 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3209 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3210 struct mlx5_ifc_cq_error_bits cq_error; 3211 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3212 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3213 struct mlx5_ifc_gpio_event_bits gpio_event; 3214 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3215 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3216 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3217 u8 reserved_at_0[0xe0]; 3218 }; 3219 3220 struct mlx5_ifc_health_buffer_bits { 3221 u8 reserved_at_0[0x100]; 3222 3223 u8 assert_existptr[0x20]; 3224 3225 u8 assert_callra[0x20]; 3226 3227 u8 reserved_at_140[0x40]; 3228 3229 u8 fw_version[0x20]; 3230 3231 u8 hw_id[0x20]; 3232 3233 u8 reserved_at_1c0[0x20]; 3234 3235 u8 irisc_index[0x8]; 3236 u8 synd[0x8]; 3237 u8 ext_synd[0x10]; 3238 }; 3239 3240 struct mlx5_ifc_register_loopback_control_bits { 3241 u8 no_lb[0x1]; 3242 u8 reserved_at_1[0x7]; 3243 u8 port[0x8]; 3244 u8 reserved_at_10[0x10]; 3245 3246 u8 reserved_at_20[0x60]; 3247 }; 3248 3249 struct mlx5_ifc_vport_tc_element_bits { 3250 u8 traffic_class[0x4]; 3251 u8 reserved_at_4[0xc]; 3252 u8 vport_number[0x10]; 3253 }; 3254 3255 struct mlx5_ifc_vport_element_bits { 3256 u8 reserved_at_0[0x10]; 3257 u8 vport_number[0x10]; 3258 }; 3259 3260 enum { 3261 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 3262 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 3263 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 3264 }; 3265 3266 struct mlx5_ifc_tsar_element_bits { 3267 u8 reserved_at_0[0x8]; 3268 u8 tsar_type[0x8]; 3269 u8 reserved_at_10[0x10]; 3270 }; 3271 3272 enum { 3273 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3274 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3275 }; 3276 3277 struct mlx5_ifc_teardown_hca_out_bits { 3278 u8 status[0x8]; 3279 u8 reserved_at_8[0x18]; 3280 3281 u8 syndrome[0x20]; 3282 3283 u8 reserved_at_40[0x3f]; 3284 3285 u8 force_state[0x1]; 3286 }; 3287 3288 enum { 3289 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3290 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3291 }; 3292 3293 struct mlx5_ifc_teardown_hca_in_bits { 3294 u8 opcode[0x10]; 3295 u8 reserved_at_10[0x10]; 3296 3297 u8 reserved_at_20[0x10]; 3298 u8 op_mod[0x10]; 3299 3300 u8 reserved_at_40[0x10]; 3301 u8 profile[0x10]; 3302 3303 u8 reserved_at_60[0x20]; 3304 }; 3305 3306 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3307 u8 status[0x8]; 3308 u8 reserved_at_8[0x18]; 3309 3310 u8 syndrome[0x20]; 3311 3312 u8 reserved_at_40[0x40]; 3313 }; 3314 3315 struct mlx5_ifc_sqerr2rts_qp_in_bits { 3316 u8 opcode[0x10]; 3317 u8 reserved_at_10[0x10]; 3318 3319 u8 reserved_at_20[0x10]; 3320 u8 op_mod[0x10]; 3321 3322 u8 reserved_at_40[0x8]; 3323 u8 qpn[0x18]; 3324 3325 u8 reserved_at_60[0x20]; 3326 3327 u8 opt_param_mask[0x20]; 3328 3329 u8 reserved_at_a0[0x20]; 3330 3331 struct mlx5_ifc_qpc_bits qpc; 3332 3333 u8 reserved_at_800[0x80]; 3334 }; 3335 3336 struct mlx5_ifc_sqd2rts_qp_out_bits { 3337 u8 status[0x8]; 3338 u8 reserved_at_8[0x18]; 3339 3340 u8 syndrome[0x20]; 3341 3342 u8 reserved_at_40[0x40]; 3343 }; 3344 3345 struct mlx5_ifc_sqd2rts_qp_in_bits { 3346 u8 opcode[0x10]; 3347 u8 reserved_at_10[0x10]; 3348 3349 u8 reserved_at_20[0x10]; 3350 u8 op_mod[0x10]; 3351 3352 u8 reserved_at_40[0x8]; 3353 u8 qpn[0x18]; 3354 3355 u8 reserved_at_60[0x20]; 3356 3357 u8 opt_param_mask[0x20]; 3358 3359 u8 reserved_at_a0[0x20]; 3360 3361 struct mlx5_ifc_qpc_bits qpc; 3362 3363 u8 reserved_at_800[0x80]; 3364 }; 3365 3366 struct mlx5_ifc_set_roce_address_out_bits { 3367 u8 status[0x8]; 3368 u8 reserved_at_8[0x18]; 3369 3370 u8 syndrome[0x20]; 3371 3372 u8 reserved_at_40[0x40]; 3373 }; 3374 3375 struct mlx5_ifc_set_roce_address_in_bits { 3376 u8 opcode[0x10]; 3377 u8 reserved_at_10[0x10]; 3378 3379 u8 reserved_at_20[0x10]; 3380 u8 op_mod[0x10]; 3381 3382 u8 roce_address_index[0x10]; 3383 u8 reserved_at_50[0xc]; 3384 u8 vhca_port_num[0x4]; 3385 3386 u8 reserved_at_60[0x20]; 3387 3388 struct mlx5_ifc_roce_addr_layout_bits roce_address; 3389 }; 3390 3391 struct mlx5_ifc_set_mad_demux_out_bits { 3392 u8 status[0x8]; 3393 u8 reserved_at_8[0x18]; 3394 3395 u8 syndrome[0x20]; 3396 3397 u8 reserved_at_40[0x40]; 3398 }; 3399 3400 enum { 3401 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 3402 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 3403 }; 3404 3405 struct mlx5_ifc_set_mad_demux_in_bits { 3406 u8 opcode[0x10]; 3407 u8 reserved_at_10[0x10]; 3408 3409 u8 reserved_at_20[0x10]; 3410 u8 op_mod[0x10]; 3411 3412 u8 reserved_at_40[0x20]; 3413 3414 u8 reserved_at_60[0x6]; 3415 u8 demux_mode[0x2]; 3416 u8 reserved_at_68[0x18]; 3417 }; 3418 3419 struct mlx5_ifc_set_l2_table_entry_out_bits { 3420 u8 status[0x8]; 3421 u8 reserved_at_8[0x18]; 3422 3423 u8 syndrome[0x20]; 3424 3425 u8 reserved_at_40[0x40]; 3426 }; 3427 3428 struct mlx5_ifc_set_l2_table_entry_in_bits { 3429 u8 opcode[0x10]; 3430 u8 reserved_at_10[0x10]; 3431 3432 u8 reserved_at_20[0x10]; 3433 u8 op_mod[0x10]; 3434 3435 u8 reserved_at_40[0x60]; 3436 3437 u8 reserved_at_a0[0x8]; 3438 u8 table_index[0x18]; 3439 3440 u8 reserved_at_c0[0x20]; 3441 3442 u8 reserved_at_e0[0x13]; 3443 u8 vlan_valid[0x1]; 3444 u8 vlan[0xc]; 3445 3446 struct mlx5_ifc_mac_address_layout_bits mac_address; 3447 3448 u8 reserved_at_140[0xc0]; 3449 }; 3450 3451 struct mlx5_ifc_set_issi_out_bits { 3452 u8 status[0x8]; 3453 u8 reserved_at_8[0x18]; 3454 3455 u8 syndrome[0x20]; 3456 3457 u8 reserved_at_40[0x40]; 3458 }; 3459 3460 struct mlx5_ifc_set_issi_in_bits { 3461 u8 opcode[0x10]; 3462 u8 reserved_at_10[0x10]; 3463 3464 u8 reserved_at_20[0x10]; 3465 u8 op_mod[0x10]; 3466 3467 u8 reserved_at_40[0x10]; 3468 u8 current_issi[0x10]; 3469 3470 u8 reserved_at_60[0x20]; 3471 }; 3472 3473 struct mlx5_ifc_set_hca_cap_out_bits { 3474 u8 status[0x8]; 3475 u8 reserved_at_8[0x18]; 3476 3477 u8 syndrome[0x20]; 3478 3479 u8 reserved_at_40[0x40]; 3480 }; 3481 3482 struct mlx5_ifc_set_hca_cap_in_bits { 3483 u8 opcode[0x10]; 3484 u8 reserved_at_10[0x10]; 3485 3486 u8 reserved_at_20[0x10]; 3487 u8 op_mod[0x10]; 3488 3489 u8 reserved_at_40[0x40]; 3490 3491 union mlx5_ifc_hca_cap_union_bits capability; 3492 }; 3493 3494 enum { 3495 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 3496 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 3497 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 3498 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 3499 }; 3500 3501 struct mlx5_ifc_set_fte_out_bits { 3502 u8 status[0x8]; 3503 u8 reserved_at_8[0x18]; 3504 3505 u8 syndrome[0x20]; 3506 3507 u8 reserved_at_40[0x40]; 3508 }; 3509 3510 struct mlx5_ifc_set_fte_in_bits { 3511 u8 opcode[0x10]; 3512 u8 reserved_at_10[0x10]; 3513 3514 u8 reserved_at_20[0x10]; 3515 u8 op_mod[0x10]; 3516 3517 u8 other_vport[0x1]; 3518 u8 reserved_at_41[0xf]; 3519 u8 vport_number[0x10]; 3520 3521 u8 reserved_at_60[0x20]; 3522 3523 u8 table_type[0x8]; 3524 u8 reserved_at_88[0x18]; 3525 3526 u8 reserved_at_a0[0x8]; 3527 u8 table_id[0x18]; 3528 3529 u8 reserved_at_c0[0x18]; 3530 u8 modify_enable_mask[0x8]; 3531 3532 u8 reserved_at_e0[0x20]; 3533 3534 u8 flow_index[0x20]; 3535 3536 u8 reserved_at_120[0xe0]; 3537 3538 struct mlx5_ifc_flow_context_bits flow_context; 3539 }; 3540 3541 struct mlx5_ifc_rts2rts_qp_out_bits { 3542 u8 status[0x8]; 3543 u8 reserved_at_8[0x18]; 3544 3545 u8 syndrome[0x20]; 3546 3547 u8 reserved_at_40[0x40]; 3548 }; 3549 3550 struct mlx5_ifc_rts2rts_qp_in_bits { 3551 u8 opcode[0x10]; 3552 u8 reserved_at_10[0x10]; 3553 3554 u8 reserved_at_20[0x10]; 3555 u8 op_mod[0x10]; 3556 3557 u8 reserved_at_40[0x8]; 3558 u8 qpn[0x18]; 3559 3560 u8 reserved_at_60[0x20]; 3561 3562 u8 opt_param_mask[0x20]; 3563 3564 u8 reserved_at_a0[0x20]; 3565 3566 struct mlx5_ifc_qpc_bits qpc; 3567 3568 u8 reserved_at_800[0x80]; 3569 }; 3570 3571 struct mlx5_ifc_rtr2rts_qp_out_bits { 3572 u8 status[0x8]; 3573 u8 reserved_at_8[0x18]; 3574 3575 u8 syndrome[0x20]; 3576 3577 u8 reserved_at_40[0x40]; 3578 }; 3579 3580 struct mlx5_ifc_rtr2rts_qp_in_bits { 3581 u8 opcode[0x10]; 3582 u8 reserved_at_10[0x10]; 3583 3584 u8 reserved_at_20[0x10]; 3585 u8 op_mod[0x10]; 3586 3587 u8 reserved_at_40[0x8]; 3588 u8 qpn[0x18]; 3589 3590 u8 reserved_at_60[0x20]; 3591 3592 u8 opt_param_mask[0x20]; 3593 3594 u8 reserved_at_a0[0x20]; 3595 3596 struct mlx5_ifc_qpc_bits qpc; 3597 3598 u8 reserved_at_800[0x80]; 3599 }; 3600 3601 struct mlx5_ifc_rst2init_qp_out_bits { 3602 u8 status[0x8]; 3603 u8 reserved_at_8[0x18]; 3604 3605 u8 syndrome[0x20]; 3606 3607 u8 reserved_at_40[0x40]; 3608 }; 3609 3610 struct mlx5_ifc_rst2init_qp_in_bits { 3611 u8 opcode[0x10]; 3612 u8 reserved_at_10[0x10]; 3613 3614 u8 reserved_at_20[0x10]; 3615 u8 op_mod[0x10]; 3616 3617 u8 reserved_at_40[0x8]; 3618 u8 qpn[0x18]; 3619 3620 u8 reserved_at_60[0x20]; 3621 3622 u8 opt_param_mask[0x20]; 3623 3624 u8 reserved_at_a0[0x20]; 3625 3626 struct mlx5_ifc_qpc_bits qpc; 3627 3628 u8 reserved_at_800[0x80]; 3629 }; 3630 3631 struct mlx5_ifc_query_xrq_out_bits { 3632 u8 status[0x8]; 3633 u8 reserved_at_8[0x18]; 3634 3635 u8 syndrome[0x20]; 3636 3637 u8 reserved_at_40[0x40]; 3638 3639 struct mlx5_ifc_xrqc_bits xrq_context; 3640 }; 3641 3642 struct mlx5_ifc_query_xrq_in_bits { 3643 u8 opcode[0x10]; 3644 u8 reserved_at_10[0x10]; 3645 3646 u8 reserved_at_20[0x10]; 3647 u8 op_mod[0x10]; 3648 3649 u8 reserved_at_40[0x8]; 3650 u8 xrqn[0x18]; 3651 3652 u8 reserved_at_60[0x20]; 3653 }; 3654 3655 struct mlx5_ifc_query_xrc_srq_out_bits { 3656 u8 status[0x8]; 3657 u8 reserved_at_8[0x18]; 3658 3659 u8 syndrome[0x20]; 3660 3661 u8 reserved_at_40[0x40]; 3662 3663 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 3664 3665 u8 reserved_at_280[0x600]; 3666 3667 u8 pas[0][0x40]; 3668 }; 3669 3670 struct mlx5_ifc_query_xrc_srq_in_bits { 3671 u8 opcode[0x10]; 3672 u8 reserved_at_10[0x10]; 3673 3674 u8 reserved_at_20[0x10]; 3675 u8 op_mod[0x10]; 3676 3677 u8 reserved_at_40[0x8]; 3678 u8 xrc_srqn[0x18]; 3679 3680 u8 reserved_at_60[0x20]; 3681 }; 3682 3683 enum { 3684 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 3685 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 3686 }; 3687 3688 struct mlx5_ifc_query_vport_state_out_bits { 3689 u8 status[0x8]; 3690 u8 reserved_at_8[0x18]; 3691 3692 u8 syndrome[0x20]; 3693 3694 u8 reserved_at_40[0x20]; 3695 3696 u8 reserved_at_60[0x18]; 3697 u8 admin_state[0x4]; 3698 u8 state[0x4]; 3699 }; 3700 3701 enum { 3702 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 3703 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 3704 }; 3705 3706 struct mlx5_ifc_query_vport_state_in_bits { 3707 u8 opcode[0x10]; 3708 u8 reserved_at_10[0x10]; 3709 3710 u8 reserved_at_20[0x10]; 3711 u8 op_mod[0x10]; 3712 3713 u8 other_vport[0x1]; 3714 u8 reserved_at_41[0xf]; 3715 u8 vport_number[0x10]; 3716 3717 u8 reserved_at_60[0x20]; 3718 }; 3719 3720 struct mlx5_ifc_query_vnic_env_out_bits { 3721 u8 status[0x8]; 3722 u8 reserved_at_8[0x18]; 3723 3724 u8 syndrome[0x20]; 3725 3726 u8 reserved_at_40[0x40]; 3727 3728 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 3729 }; 3730 3731 enum { 3732 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 3733 }; 3734 3735 struct mlx5_ifc_query_vnic_env_in_bits { 3736 u8 opcode[0x10]; 3737 u8 reserved_at_10[0x10]; 3738 3739 u8 reserved_at_20[0x10]; 3740 u8 op_mod[0x10]; 3741 3742 u8 other_vport[0x1]; 3743 u8 reserved_at_41[0xf]; 3744 u8 vport_number[0x10]; 3745 3746 u8 reserved_at_60[0x20]; 3747 }; 3748 3749 struct mlx5_ifc_query_vport_counter_out_bits { 3750 u8 status[0x8]; 3751 u8 reserved_at_8[0x18]; 3752 3753 u8 syndrome[0x20]; 3754 3755 u8 reserved_at_40[0x40]; 3756 3757 struct mlx5_ifc_traffic_counter_bits received_errors; 3758 3759 struct mlx5_ifc_traffic_counter_bits transmit_errors; 3760 3761 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 3762 3763 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 3764 3765 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 3766 3767 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 3768 3769 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 3770 3771 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 3772 3773 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 3774 3775 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 3776 3777 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 3778 3779 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 3780 3781 u8 reserved_at_680[0xa00]; 3782 }; 3783 3784 enum { 3785 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 3786 }; 3787 3788 struct mlx5_ifc_query_vport_counter_in_bits { 3789 u8 opcode[0x10]; 3790 u8 reserved_at_10[0x10]; 3791 3792 u8 reserved_at_20[0x10]; 3793 u8 op_mod[0x10]; 3794 3795 u8 other_vport[0x1]; 3796 u8 reserved_at_41[0xb]; 3797 u8 port_num[0x4]; 3798 u8 vport_number[0x10]; 3799 3800 u8 reserved_at_60[0x60]; 3801 3802 u8 clear[0x1]; 3803 u8 reserved_at_c1[0x1f]; 3804 3805 u8 reserved_at_e0[0x20]; 3806 }; 3807 3808 struct mlx5_ifc_query_tis_out_bits { 3809 u8 status[0x8]; 3810 u8 reserved_at_8[0x18]; 3811 3812 u8 syndrome[0x20]; 3813 3814 u8 reserved_at_40[0x40]; 3815 3816 struct mlx5_ifc_tisc_bits tis_context; 3817 }; 3818 3819 struct mlx5_ifc_query_tis_in_bits { 3820 u8 opcode[0x10]; 3821 u8 reserved_at_10[0x10]; 3822 3823 u8 reserved_at_20[0x10]; 3824 u8 op_mod[0x10]; 3825 3826 u8 reserved_at_40[0x8]; 3827 u8 tisn[0x18]; 3828 3829 u8 reserved_at_60[0x20]; 3830 }; 3831 3832 struct mlx5_ifc_query_tir_out_bits { 3833 u8 status[0x8]; 3834 u8 reserved_at_8[0x18]; 3835 3836 u8 syndrome[0x20]; 3837 3838 u8 reserved_at_40[0xc0]; 3839 3840 struct mlx5_ifc_tirc_bits tir_context; 3841 }; 3842 3843 struct mlx5_ifc_query_tir_in_bits { 3844 u8 opcode[0x10]; 3845 u8 reserved_at_10[0x10]; 3846 3847 u8 reserved_at_20[0x10]; 3848 u8 op_mod[0x10]; 3849 3850 u8 reserved_at_40[0x8]; 3851 u8 tirn[0x18]; 3852 3853 u8 reserved_at_60[0x20]; 3854 }; 3855 3856 struct mlx5_ifc_query_srq_out_bits { 3857 u8 status[0x8]; 3858 u8 reserved_at_8[0x18]; 3859 3860 u8 syndrome[0x20]; 3861 3862 u8 reserved_at_40[0x40]; 3863 3864 struct mlx5_ifc_srqc_bits srq_context_entry; 3865 3866 u8 reserved_at_280[0x600]; 3867 3868 u8 pas[0][0x40]; 3869 }; 3870 3871 struct mlx5_ifc_query_srq_in_bits { 3872 u8 opcode[0x10]; 3873 u8 reserved_at_10[0x10]; 3874 3875 u8 reserved_at_20[0x10]; 3876 u8 op_mod[0x10]; 3877 3878 u8 reserved_at_40[0x8]; 3879 u8 srqn[0x18]; 3880 3881 u8 reserved_at_60[0x20]; 3882 }; 3883 3884 struct mlx5_ifc_query_sq_out_bits { 3885 u8 status[0x8]; 3886 u8 reserved_at_8[0x18]; 3887 3888 u8 syndrome[0x20]; 3889 3890 u8 reserved_at_40[0xc0]; 3891 3892 struct mlx5_ifc_sqc_bits sq_context; 3893 }; 3894 3895 struct mlx5_ifc_query_sq_in_bits { 3896 u8 opcode[0x10]; 3897 u8 reserved_at_10[0x10]; 3898 3899 u8 reserved_at_20[0x10]; 3900 u8 op_mod[0x10]; 3901 3902 u8 reserved_at_40[0x8]; 3903 u8 sqn[0x18]; 3904 3905 u8 reserved_at_60[0x20]; 3906 }; 3907 3908 struct mlx5_ifc_query_special_contexts_out_bits { 3909 u8 status[0x8]; 3910 u8 reserved_at_8[0x18]; 3911 3912 u8 syndrome[0x20]; 3913 3914 u8 dump_fill_mkey[0x20]; 3915 3916 u8 resd_lkey[0x20]; 3917 3918 u8 null_mkey[0x20]; 3919 3920 u8 reserved_at_a0[0x60]; 3921 }; 3922 3923 struct mlx5_ifc_query_special_contexts_in_bits { 3924 u8 opcode[0x10]; 3925 u8 reserved_at_10[0x10]; 3926 3927 u8 reserved_at_20[0x10]; 3928 u8 op_mod[0x10]; 3929 3930 u8 reserved_at_40[0x40]; 3931 }; 3932 3933 struct mlx5_ifc_query_scheduling_element_out_bits { 3934 u8 opcode[0x10]; 3935 u8 reserved_at_10[0x10]; 3936 3937 u8 reserved_at_20[0x10]; 3938 u8 op_mod[0x10]; 3939 3940 u8 reserved_at_40[0xc0]; 3941 3942 struct mlx5_ifc_scheduling_context_bits scheduling_context; 3943 3944 u8 reserved_at_300[0x100]; 3945 }; 3946 3947 enum { 3948 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 3949 }; 3950 3951 struct mlx5_ifc_query_scheduling_element_in_bits { 3952 u8 opcode[0x10]; 3953 u8 reserved_at_10[0x10]; 3954 3955 u8 reserved_at_20[0x10]; 3956 u8 op_mod[0x10]; 3957 3958 u8 scheduling_hierarchy[0x8]; 3959 u8 reserved_at_48[0x18]; 3960 3961 u8 scheduling_element_id[0x20]; 3962 3963 u8 reserved_at_80[0x180]; 3964 }; 3965 3966 struct mlx5_ifc_query_rqt_out_bits { 3967 u8 status[0x8]; 3968 u8 reserved_at_8[0x18]; 3969 3970 u8 syndrome[0x20]; 3971 3972 u8 reserved_at_40[0xc0]; 3973 3974 struct mlx5_ifc_rqtc_bits rqt_context; 3975 }; 3976 3977 struct mlx5_ifc_query_rqt_in_bits { 3978 u8 opcode[0x10]; 3979 u8 reserved_at_10[0x10]; 3980 3981 u8 reserved_at_20[0x10]; 3982 u8 op_mod[0x10]; 3983 3984 u8 reserved_at_40[0x8]; 3985 u8 rqtn[0x18]; 3986 3987 u8 reserved_at_60[0x20]; 3988 }; 3989 3990 struct mlx5_ifc_query_rq_out_bits { 3991 u8 status[0x8]; 3992 u8 reserved_at_8[0x18]; 3993 3994 u8 syndrome[0x20]; 3995 3996 u8 reserved_at_40[0xc0]; 3997 3998 struct mlx5_ifc_rqc_bits rq_context; 3999 }; 4000 4001 struct mlx5_ifc_query_rq_in_bits { 4002 u8 opcode[0x10]; 4003 u8 reserved_at_10[0x10]; 4004 4005 u8 reserved_at_20[0x10]; 4006 u8 op_mod[0x10]; 4007 4008 u8 reserved_at_40[0x8]; 4009 u8 rqn[0x18]; 4010 4011 u8 reserved_at_60[0x20]; 4012 }; 4013 4014 struct mlx5_ifc_query_roce_address_out_bits { 4015 u8 status[0x8]; 4016 u8 reserved_at_8[0x18]; 4017 4018 u8 syndrome[0x20]; 4019 4020 u8 reserved_at_40[0x40]; 4021 4022 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4023 }; 4024 4025 struct mlx5_ifc_query_roce_address_in_bits { 4026 u8 opcode[0x10]; 4027 u8 reserved_at_10[0x10]; 4028 4029 u8 reserved_at_20[0x10]; 4030 u8 op_mod[0x10]; 4031 4032 u8 roce_address_index[0x10]; 4033 u8 reserved_at_50[0xc]; 4034 u8 vhca_port_num[0x4]; 4035 4036 u8 reserved_at_60[0x20]; 4037 }; 4038 4039 struct mlx5_ifc_query_rmp_out_bits { 4040 u8 status[0x8]; 4041 u8 reserved_at_8[0x18]; 4042 4043 u8 syndrome[0x20]; 4044 4045 u8 reserved_at_40[0xc0]; 4046 4047 struct mlx5_ifc_rmpc_bits rmp_context; 4048 }; 4049 4050 struct mlx5_ifc_query_rmp_in_bits { 4051 u8 opcode[0x10]; 4052 u8 reserved_at_10[0x10]; 4053 4054 u8 reserved_at_20[0x10]; 4055 u8 op_mod[0x10]; 4056 4057 u8 reserved_at_40[0x8]; 4058 u8 rmpn[0x18]; 4059 4060 u8 reserved_at_60[0x20]; 4061 }; 4062 4063 struct mlx5_ifc_query_qp_out_bits { 4064 u8 status[0x8]; 4065 u8 reserved_at_8[0x18]; 4066 4067 u8 syndrome[0x20]; 4068 4069 u8 reserved_at_40[0x40]; 4070 4071 u8 opt_param_mask[0x20]; 4072 4073 u8 reserved_at_a0[0x20]; 4074 4075 struct mlx5_ifc_qpc_bits qpc; 4076 4077 u8 reserved_at_800[0x80]; 4078 4079 u8 pas[0][0x40]; 4080 }; 4081 4082 struct mlx5_ifc_query_qp_in_bits { 4083 u8 opcode[0x10]; 4084 u8 reserved_at_10[0x10]; 4085 4086 u8 reserved_at_20[0x10]; 4087 u8 op_mod[0x10]; 4088 4089 u8 reserved_at_40[0x8]; 4090 u8 qpn[0x18]; 4091 4092 u8 reserved_at_60[0x20]; 4093 }; 4094 4095 struct mlx5_ifc_query_q_counter_out_bits { 4096 u8 status[0x8]; 4097 u8 reserved_at_8[0x18]; 4098 4099 u8 syndrome[0x20]; 4100 4101 u8 reserved_at_40[0x40]; 4102 4103 u8 rx_write_requests[0x20]; 4104 4105 u8 reserved_at_a0[0x20]; 4106 4107 u8 rx_read_requests[0x20]; 4108 4109 u8 reserved_at_e0[0x20]; 4110 4111 u8 rx_atomic_requests[0x20]; 4112 4113 u8 reserved_at_120[0x20]; 4114 4115 u8 rx_dct_connect[0x20]; 4116 4117 u8 reserved_at_160[0x20]; 4118 4119 u8 out_of_buffer[0x20]; 4120 4121 u8 reserved_at_1a0[0x20]; 4122 4123 u8 out_of_sequence[0x20]; 4124 4125 u8 reserved_at_1e0[0x20]; 4126 4127 u8 duplicate_request[0x20]; 4128 4129 u8 reserved_at_220[0x20]; 4130 4131 u8 rnr_nak_retry_err[0x20]; 4132 4133 u8 reserved_at_260[0x20]; 4134 4135 u8 packet_seq_err[0x20]; 4136 4137 u8 reserved_at_2a0[0x20]; 4138 4139 u8 implied_nak_seq_err[0x20]; 4140 4141 u8 reserved_at_2e0[0x20]; 4142 4143 u8 local_ack_timeout_err[0x20]; 4144 4145 u8 reserved_at_320[0xa0]; 4146 4147 u8 resp_local_length_error[0x20]; 4148 4149 u8 req_local_length_error[0x20]; 4150 4151 u8 resp_local_qp_error[0x20]; 4152 4153 u8 local_operation_error[0x20]; 4154 4155 u8 resp_local_protection[0x20]; 4156 4157 u8 req_local_protection[0x20]; 4158 4159 u8 resp_cqe_error[0x20]; 4160 4161 u8 req_cqe_error[0x20]; 4162 4163 u8 req_mw_binding[0x20]; 4164 4165 u8 req_bad_response[0x20]; 4166 4167 u8 req_remote_invalid_request[0x20]; 4168 4169 u8 resp_remote_invalid_request[0x20]; 4170 4171 u8 req_remote_access_errors[0x20]; 4172 4173 u8 resp_remote_access_errors[0x20]; 4174 4175 u8 req_remote_operation_errors[0x20]; 4176 4177 u8 req_transport_retries_exceeded[0x20]; 4178 4179 u8 cq_overflow[0x20]; 4180 4181 u8 resp_cqe_flush_error[0x20]; 4182 4183 u8 req_cqe_flush_error[0x20]; 4184 4185 u8 reserved_at_620[0x1e0]; 4186 }; 4187 4188 struct mlx5_ifc_query_q_counter_in_bits { 4189 u8 opcode[0x10]; 4190 u8 reserved_at_10[0x10]; 4191 4192 u8 reserved_at_20[0x10]; 4193 u8 op_mod[0x10]; 4194 4195 u8 reserved_at_40[0x80]; 4196 4197 u8 clear[0x1]; 4198 u8 reserved_at_c1[0x1f]; 4199 4200 u8 reserved_at_e0[0x18]; 4201 u8 counter_set_id[0x8]; 4202 }; 4203 4204 struct mlx5_ifc_query_pages_out_bits { 4205 u8 status[0x8]; 4206 u8 reserved_at_8[0x18]; 4207 4208 u8 syndrome[0x20]; 4209 4210 u8 reserved_at_40[0x10]; 4211 u8 function_id[0x10]; 4212 4213 u8 num_pages[0x20]; 4214 }; 4215 4216 enum { 4217 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 4218 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 4219 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 4220 }; 4221 4222 struct mlx5_ifc_query_pages_in_bits { 4223 u8 opcode[0x10]; 4224 u8 reserved_at_10[0x10]; 4225 4226 u8 reserved_at_20[0x10]; 4227 u8 op_mod[0x10]; 4228 4229 u8 reserved_at_40[0x10]; 4230 u8 function_id[0x10]; 4231 4232 u8 reserved_at_60[0x20]; 4233 }; 4234 4235 struct mlx5_ifc_query_nic_vport_context_out_bits { 4236 u8 status[0x8]; 4237 u8 reserved_at_8[0x18]; 4238 4239 u8 syndrome[0x20]; 4240 4241 u8 reserved_at_40[0x40]; 4242 4243 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 4244 }; 4245 4246 struct mlx5_ifc_query_nic_vport_context_in_bits { 4247 u8 opcode[0x10]; 4248 u8 reserved_at_10[0x10]; 4249 4250 u8 reserved_at_20[0x10]; 4251 u8 op_mod[0x10]; 4252 4253 u8 other_vport[0x1]; 4254 u8 reserved_at_41[0xf]; 4255 u8 vport_number[0x10]; 4256 4257 u8 reserved_at_60[0x5]; 4258 u8 allowed_list_type[0x3]; 4259 u8 reserved_at_68[0x18]; 4260 }; 4261 4262 struct mlx5_ifc_query_mkey_out_bits { 4263 u8 status[0x8]; 4264 u8 reserved_at_8[0x18]; 4265 4266 u8 syndrome[0x20]; 4267 4268 u8 reserved_at_40[0x40]; 4269 4270 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 4271 4272 u8 reserved_at_280[0x600]; 4273 4274 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 4275 4276 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 4277 }; 4278 4279 struct mlx5_ifc_query_mkey_in_bits { 4280 u8 opcode[0x10]; 4281 u8 reserved_at_10[0x10]; 4282 4283 u8 reserved_at_20[0x10]; 4284 u8 op_mod[0x10]; 4285 4286 u8 reserved_at_40[0x8]; 4287 u8 mkey_index[0x18]; 4288 4289 u8 pg_access[0x1]; 4290 u8 reserved_at_61[0x1f]; 4291 }; 4292 4293 struct mlx5_ifc_query_mad_demux_out_bits { 4294 u8 status[0x8]; 4295 u8 reserved_at_8[0x18]; 4296 4297 u8 syndrome[0x20]; 4298 4299 u8 reserved_at_40[0x40]; 4300 4301 u8 mad_dumux_parameters_block[0x20]; 4302 }; 4303 4304 struct mlx5_ifc_query_mad_demux_in_bits { 4305 u8 opcode[0x10]; 4306 u8 reserved_at_10[0x10]; 4307 4308 u8 reserved_at_20[0x10]; 4309 u8 op_mod[0x10]; 4310 4311 u8 reserved_at_40[0x40]; 4312 }; 4313 4314 struct mlx5_ifc_query_l2_table_entry_out_bits { 4315 u8 status[0x8]; 4316 u8 reserved_at_8[0x18]; 4317 4318 u8 syndrome[0x20]; 4319 4320 u8 reserved_at_40[0xa0]; 4321 4322 u8 reserved_at_e0[0x13]; 4323 u8 vlan_valid[0x1]; 4324 u8 vlan[0xc]; 4325 4326 struct mlx5_ifc_mac_address_layout_bits mac_address; 4327 4328 u8 reserved_at_140[0xc0]; 4329 }; 4330 4331 struct mlx5_ifc_query_l2_table_entry_in_bits { 4332 u8 opcode[0x10]; 4333 u8 reserved_at_10[0x10]; 4334 4335 u8 reserved_at_20[0x10]; 4336 u8 op_mod[0x10]; 4337 4338 u8 reserved_at_40[0x60]; 4339 4340 u8 reserved_at_a0[0x8]; 4341 u8 table_index[0x18]; 4342 4343 u8 reserved_at_c0[0x140]; 4344 }; 4345 4346 struct mlx5_ifc_query_issi_out_bits { 4347 u8 status[0x8]; 4348 u8 reserved_at_8[0x18]; 4349 4350 u8 syndrome[0x20]; 4351 4352 u8 reserved_at_40[0x10]; 4353 u8 current_issi[0x10]; 4354 4355 u8 reserved_at_60[0xa0]; 4356 4357 u8 reserved_at_100[76][0x8]; 4358 u8 supported_issi_dw0[0x20]; 4359 }; 4360 4361 struct mlx5_ifc_query_issi_in_bits { 4362 u8 opcode[0x10]; 4363 u8 reserved_at_10[0x10]; 4364 4365 u8 reserved_at_20[0x10]; 4366 u8 op_mod[0x10]; 4367 4368 u8 reserved_at_40[0x40]; 4369 }; 4370 4371 struct mlx5_ifc_set_driver_version_out_bits { 4372 u8 status[0x8]; 4373 u8 reserved_0[0x18]; 4374 4375 u8 syndrome[0x20]; 4376 u8 reserved_1[0x40]; 4377 }; 4378 4379 struct mlx5_ifc_set_driver_version_in_bits { 4380 u8 opcode[0x10]; 4381 u8 reserved_0[0x10]; 4382 4383 u8 reserved_1[0x10]; 4384 u8 op_mod[0x10]; 4385 4386 u8 reserved_2[0x40]; 4387 u8 driver_version[64][0x8]; 4388 }; 4389 4390 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 4391 u8 status[0x8]; 4392 u8 reserved_at_8[0x18]; 4393 4394 u8 syndrome[0x20]; 4395 4396 u8 reserved_at_40[0x40]; 4397 4398 struct mlx5_ifc_pkey_bits pkey[0]; 4399 }; 4400 4401 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 4402 u8 opcode[0x10]; 4403 u8 reserved_at_10[0x10]; 4404 4405 u8 reserved_at_20[0x10]; 4406 u8 op_mod[0x10]; 4407 4408 u8 other_vport[0x1]; 4409 u8 reserved_at_41[0xb]; 4410 u8 port_num[0x4]; 4411 u8 vport_number[0x10]; 4412 4413 u8 reserved_at_60[0x10]; 4414 u8 pkey_index[0x10]; 4415 }; 4416 4417 enum { 4418 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 4419 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 4420 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 4421 }; 4422 4423 struct mlx5_ifc_query_hca_vport_gid_out_bits { 4424 u8 status[0x8]; 4425 u8 reserved_at_8[0x18]; 4426 4427 u8 syndrome[0x20]; 4428 4429 u8 reserved_at_40[0x20]; 4430 4431 u8 gids_num[0x10]; 4432 u8 reserved_at_70[0x10]; 4433 4434 struct mlx5_ifc_array128_auto_bits gid[0]; 4435 }; 4436 4437 struct mlx5_ifc_query_hca_vport_gid_in_bits { 4438 u8 opcode[0x10]; 4439 u8 reserved_at_10[0x10]; 4440 4441 u8 reserved_at_20[0x10]; 4442 u8 op_mod[0x10]; 4443 4444 u8 other_vport[0x1]; 4445 u8 reserved_at_41[0xb]; 4446 u8 port_num[0x4]; 4447 u8 vport_number[0x10]; 4448 4449 u8 reserved_at_60[0x10]; 4450 u8 gid_index[0x10]; 4451 }; 4452 4453 struct mlx5_ifc_query_hca_vport_context_out_bits { 4454 u8 status[0x8]; 4455 u8 reserved_at_8[0x18]; 4456 4457 u8 syndrome[0x20]; 4458 4459 u8 reserved_at_40[0x40]; 4460 4461 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 4462 }; 4463 4464 struct mlx5_ifc_query_hca_vport_context_in_bits { 4465 u8 opcode[0x10]; 4466 u8 reserved_at_10[0x10]; 4467 4468 u8 reserved_at_20[0x10]; 4469 u8 op_mod[0x10]; 4470 4471 u8 other_vport[0x1]; 4472 u8 reserved_at_41[0xb]; 4473 u8 port_num[0x4]; 4474 u8 vport_number[0x10]; 4475 4476 u8 reserved_at_60[0x20]; 4477 }; 4478 4479 struct mlx5_ifc_query_hca_cap_out_bits { 4480 u8 status[0x8]; 4481 u8 reserved_at_8[0x18]; 4482 4483 u8 syndrome[0x20]; 4484 4485 u8 reserved_at_40[0x40]; 4486 4487 union mlx5_ifc_hca_cap_union_bits capability; 4488 }; 4489 4490 struct mlx5_ifc_query_hca_cap_in_bits { 4491 u8 opcode[0x10]; 4492 u8 reserved_at_10[0x10]; 4493 4494 u8 reserved_at_20[0x10]; 4495 u8 op_mod[0x10]; 4496 4497 u8 reserved_at_40[0x40]; 4498 }; 4499 4500 struct mlx5_ifc_query_flow_table_out_bits { 4501 u8 status[0x8]; 4502 u8 reserved_at_8[0x18]; 4503 4504 u8 syndrome[0x20]; 4505 4506 u8 reserved_at_40[0x80]; 4507 4508 u8 reserved_at_c0[0x8]; 4509 u8 level[0x8]; 4510 u8 reserved_at_d0[0x8]; 4511 u8 log_size[0x8]; 4512 4513 u8 reserved_at_e0[0x120]; 4514 }; 4515 4516 struct mlx5_ifc_query_flow_table_in_bits { 4517 u8 opcode[0x10]; 4518 u8 reserved_at_10[0x10]; 4519 4520 u8 reserved_at_20[0x10]; 4521 u8 op_mod[0x10]; 4522 4523 u8 reserved_at_40[0x40]; 4524 4525 u8 table_type[0x8]; 4526 u8 reserved_at_88[0x18]; 4527 4528 u8 reserved_at_a0[0x8]; 4529 u8 table_id[0x18]; 4530 4531 u8 reserved_at_c0[0x140]; 4532 }; 4533 4534 struct mlx5_ifc_query_fte_out_bits { 4535 u8 status[0x8]; 4536 u8 reserved_at_8[0x18]; 4537 4538 u8 syndrome[0x20]; 4539 4540 u8 reserved_at_40[0x1c0]; 4541 4542 struct mlx5_ifc_flow_context_bits flow_context; 4543 }; 4544 4545 struct mlx5_ifc_query_fte_in_bits { 4546 u8 opcode[0x10]; 4547 u8 reserved_at_10[0x10]; 4548 4549 u8 reserved_at_20[0x10]; 4550 u8 op_mod[0x10]; 4551 4552 u8 reserved_at_40[0x40]; 4553 4554 u8 table_type[0x8]; 4555 u8 reserved_at_88[0x18]; 4556 4557 u8 reserved_at_a0[0x8]; 4558 u8 table_id[0x18]; 4559 4560 u8 reserved_at_c0[0x40]; 4561 4562 u8 flow_index[0x20]; 4563 4564 u8 reserved_at_120[0xe0]; 4565 }; 4566 4567 enum { 4568 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 4569 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 4570 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 4571 }; 4572 4573 struct mlx5_ifc_query_flow_group_out_bits { 4574 u8 status[0x8]; 4575 u8 reserved_at_8[0x18]; 4576 4577 u8 syndrome[0x20]; 4578 4579 u8 reserved_at_40[0xa0]; 4580 4581 u8 start_flow_index[0x20]; 4582 4583 u8 reserved_at_100[0x20]; 4584 4585 u8 end_flow_index[0x20]; 4586 4587 u8 reserved_at_140[0xa0]; 4588 4589 u8 reserved_at_1e0[0x18]; 4590 u8 match_criteria_enable[0x8]; 4591 4592 struct mlx5_ifc_fte_match_param_bits match_criteria; 4593 4594 u8 reserved_at_1200[0xe00]; 4595 }; 4596 4597 struct mlx5_ifc_query_flow_group_in_bits { 4598 u8 opcode[0x10]; 4599 u8 reserved_at_10[0x10]; 4600 4601 u8 reserved_at_20[0x10]; 4602 u8 op_mod[0x10]; 4603 4604 u8 reserved_at_40[0x40]; 4605 4606 u8 table_type[0x8]; 4607 u8 reserved_at_88[0x18]; 4608 4609 u8 reserved_at_a0[0x8]; 4610 u8 table_id[0x18]; 4611 4612 u8 group_id[0x20]; 4613 4614 u8 reserved_at_e0[0x120]; 4615 }; 4616 4617 struct mlx5_ifc_query_flow_counter_out_bits { 4618 u8 status[0x8]; 4619 u8 reserved_at_8[0x18]; 4620 4621 u8 syndrome[0x20]; 4622 4623 u8 reserved_at_40[0x40]; 4624 4625 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 4626 }; 4627 4628 struct mlx5_ifc_query_flow_counter_in_bits { 4629 u8 opcode[0x10]; 4630 u8 reserved_at_10[0x10]; 4631 4632 u8 reserved_at_20[0x10]; 4633 u8 op_mod[0x10]; 4634 4635 u8 reserved_at_40[0x80]; 4636 4637 u8 clear[0x1]; 4638 u8 reserved_at_c1[0xf]; 4639 u8 num_of_counters[0x10]; 4640 4641 u8 flow_counter_id[0x20]; 4642 }; 4643 4644 struct mlx5_ifc_query_esw_vport_context_out_bits { 4645 u8 status[0x8]; 4646 u8 reserved_at_8[0x18]; 4647 4648 u8 syndrome[0x20]; 4649 4650 u8 reserved_at_40[0x40]; 4651 4652 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4653 }; 4654 4655 struct mlx5_ifc_query_esw_vport_context_in_bits { 4656 u8 opcode[0x10]; 4657 u8 reserved_at_10[0x10]; 4658 4659 u8 reserved_at_20[0x10]; 4660 u8 op_mod[0x10]; 4661 4662 u8 other_vport[0x1]; 4663 u8 reserved_at_41[0xf]; 4664 u8 vport_number[0x10]; 4665 4666 u8 reserved_at_60[0x20]; 4667 }; 4668 4669 struct mlx5_ifc_modify_esw_vport_context_out_bits { 4670 u8 status[0x8]; 4671 u8 reserved_at_8[0x18]; 4672 4673 u8 syndrome[0x20]; 4674 4675 u8 reserved_at_40[0x40]; 4676 }; 4677 4678 struct mlx5_ifc_esw_vport_context_fields_select_bits { 4679 u8 reserved_at_0[0x1c]; 4680 u8 vport_cvlan_insert[0x1]; 4681 u8 vport_svlan_insert[0x1]; 4682 u8 vport_cvlan_strip[0x1]; 4683 u8 vport_svlan_strip[0x1]; 4684 }; 4685 4686 struct mlx5_ifc_modify_esw_vport_context_in_bits { 4687 u8 opcode[0x10]; 4688 u8 reserved_at_10[0x10]; 4689 4690 u8 reserved_at_20[0x10]; 4691 u8 op_mod[0x10]; 4692 4693 u8 other_vport[0x1]; 4694 u8 reserved_at_41[0xf]; 4695 u8 vport_number[0x10]; 4696 4697 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 4698 4699 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 4700 }; 4701 4702 struct mlx5_ifc_query_eq_out_bits { 4703 u8 status[0x8]; 4704 u8 reserved_at_8[0x18]; 4705 4706 u8 syndrome[0x20]; 4707 4708 u8 reserved_at_40[0x40]; 4709 4710 struct mlx5_ifc_eqc_bits eq_context_entry; 4711 4712 u8 reserved_at_280[0x40]; 4713 4714 u8 event_bitmask[0x40]; 4715 4716 u8 reserved_at_300[0x580]; 4717 4718 u8 pas[0][0x40]; 4719 }; 4720 4721 struct mlx5_ifc_query_eq_in_bits { 4722 u8 opcode[0x10]; 4723 u8 reserved_at_10[0x10]; 4724 4725 u8 reserved_at_20[0x10]; 4726 u8 op_mod[0x10]; 4727 4728 u8 reserved_at_40[0x18]; 4729 u8 eq_number[0x8]; 4730 4731 u8 reserved_at_60[0x20]; 4732 }; 4733 4734 struct mlx5_ifc_encap_header_in_bits { 4735 u8 reserved_at_0[0x5]; 4736 u8 header_type[0x3]; 4737 u8 reserved_at_8[0xe]; 4738 u8 encap_header_size[0xa]; 4739 4740 u8 reserved_at_20[0x10]; 4741 u8 encap_header[2][0x8]; 4742 4743 u8 more_encap_header[0][0x8]; 4744 }; 4745 4746 struct mlx5_ifc_query_encap_header_out_bits { 4747 u8 status[0x8]; 4748 u8 reserved_at_8[0x18]; 4749 4750 u8 syndrome[0x20]; 4751 4752 u8 reserved_at_40[0xa0]; 4753 4754 struct mlx5_ifc_encap_header_in_bits encap_header[0]; 4755 }; 4756 4757 struct mlx5_ifc_query_encap_header_in_bits { 4758 u8 opcode[0x10]; 4759 u8 reserved_at_10[0x10]; 4760 4761 u8 reserved_at_20[0x10]; 4762 u8 op_mod[0x10]; 4763 4764 u8 encap_id[0x20]; 4765 4766 u8 reserved_at_60[0xa0]; 4767 }; 4768 4769 struct mlx5_ifc_alloc_encap_header_out_bits { 4770 u8 status[0x8]; 4771 u8 reserved_at_8[0x18]; 4772 4773 u8 syndrome[0x20]; 4774 4775 u8 encap_id[0x20]; 4776 4777 u8 reserved_at_60[0x20]; 4778 }; 4779 4780 struct mlx5_ifc_alloc_encap_header_in_bits { 4781 u8 opcode[0x10]; 4782 u8 reserved_at_10[0x10]; 4783 4784 u8 reserved_at_20[0x10]; 4785 u8 op_mod[0x10]; 4786 4787 u8 reserved_at_40[0xa0]; 4788 4789 struct mlx5_ifc_encap_header_in_bits encap_header; 4790 }; 4791 4792 struct mlx5_ifc_dealloc_encap_header_out_bits { 4793 u8 status[0x8]; 4794 u8 reserved_at_8[0x18]; 4795 4796 u8 syndrome[0x20]; 4797 4798 u8 reserved_at_40[0x40]; 4799 }; 4800 4801 struct mlx5_ifc_dealloc_encap_header_in_bits { 4802 u8 opcode[0x10]; 4803 u8 reserved_at_10[0x10]; 4804 4805 u8 reserved_20[0x10]; 4806 u8 op_mod[0x10]; 4807 4808 u8 encap_id[0x20]; 4809 4810 u8 reserved_60[0x20]; 4811 }; 4812 4813 struct mlx5_ifc_set_action_in_bits { 4814 u8 action_type[0x4]; 4815 u8 field[0xc]; 4816 u8 reserved_at_10[0x3]; 4817 u8 offset[0x5]; 4818 u8 reserved_at_18[0x3]; 4819 u8 length[0x5]; 4820 4821 u8 data[0x20]; 4822 }; 4823 4824 struct mlx5_ifc_add_action_in_bits { 4825 u8 action_type[0x4]; 4826 u8 field[0xc]; 4827 u8 reserved_at_10[0x10]; 4828 4829 u8 data[0x20]; 4830 }; 4831 4832 union mlx5_ifc_set_action_in_add_action_in_auto_bits { 4833 struct mlx5_ifc_set_action_in_bits set_action_in; 4834 struct mlx5_ifc_add_action_in_bits add_action_in; 4835 u8 reserved_at_0[0x40]; 4836 }; 4837 4838 enum { 4839 MLX5_ACTION_TYPE_SET = 0x1, 4840 MLX5_ACTION_TYPE_ADD = 0x2, 4841 }; 4842 4843 enum { 4844 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 4845 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 4846 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 4847 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 4848 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 4849 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 4850 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 4851 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 4852 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 4853 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 4854 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 4855 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 4856 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 4857 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 4858 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 4859 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 4860 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 4861 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 4862 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 4863 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 4864 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 4865 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 4866 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 4867 }; 4868 4869 struct mlx5_ifc_alloc_modify_header_context_out_bits { 4870 u8 status[0x8]; 4871 u8 reserved_at_8[0x18]; 4872 4873 u8 syndrome[0x20]; 4874 4875 u8 modify_header_id[0x20]; 4876 4877 u8 reserved_at_60[0x20]; 4878 }; 4879 4880 struct mlx5_ifc_alloc_modify_header_context_in_bits { 4881 u8 opcode[0x10]; 4882 u8 reserved_at_10[0x10]; 4883 4884 u8 reserved_at_20[0x10]; 4885 u8 op_mod[0x10]; 4886 4887 u8 reserved_at_40[0x20]; 4888 4889 u8 table_type[0x8]; 4890 u8 reserved_at_68[0x10]; 4891 u8 num_of_actions[0x8]; 4892 4893 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; 4894 }; 4895 4896 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 4897 u8 status[0x8]; 4898 u8 reserved_at_8[0x18]; 4899 4900 u8 syndrome[0x20]; 4901 4902 u8 reserved_at_40[0x40]; 4903 }; 4904 4905 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 4906 u8 opcode[0x10]; 4907 u8 reserved_at_10[0x10]; 4908 4909 u8 reserved_at_20[0x10]; 4910 u8 op_mod[0x10]; 4911 4912 u8 modify_header_id[0x20]; 4913 4914 u8 reserved_at_60[0x20]; 4915 }; 4916 4917 struct mlx5_ifc_query_dct_out_bits { 4918 u8 status[0x8]; 4919 u8 reserved_at_8[0x18]; 4920 4921 u8 syndrome[0x20]; 4922 4923 u8 reserved_at_40[0x40]; 4924 4925 struct mlx5_ifc_dctc_bits dct_context_entry; 4926 4927 u8 reserved_at_280[0x180]; 4928 }; 4929 4930 struct mlx5_ifc_query_dct_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_at_10[0x10]; 4933 4934 u8 reserved_at_20[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 reserved_at_40[0x8]; 4938 u8 dctn[0x18]; 4939 4940 u8 reserved_at_60[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_cq_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_at_8[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_at_40[0x40]; 4950 4951 struct mlx5_ifc_cqc_bits cq_context; 4952 4953 u8 reserved_at_280[0x600]; 4954 4955 u8 pas[0][0x40]; 4956 }; 4957 4958 struct mlx5_ifc_query_cq_in_bits { 4959 u8 opcode[0x10]; 4960 u8 reserved_at_10[0x10]; 4961 4962 u8 reserved_at_20[0x10]; 4963 u8 op_mod[0x10]; 4964 4965 u8 reserved_at_40[0x8]; 4966 u8 cqn[0x18]; 4967 4968 u8 reserved_at_60[0x20]; 4969 }; 4970 4971 struct mlx5_ifc_query_cong_status_out_bits { 4972 u8 status[0x8]; 4973 u8 reserved_at_8[0x18]; 4974 4975 u8 syndrome[0x20]; 4976 4977 u8 reserved_at_40[0x20]; 4978 4979 u8 enable[0x1]; 4980 u8 tag_enable[0x1]; 4981 u8 reserved_at_62[0x1e]; 4982 }; 4983 4984 struct mlx5_ifc_query_cong_status_in_bits { 4985 u8 opcode[0x10]; 4986 u8 reserved_at_10[0x10]; 4987 4988 u8 reserved_at_20[0x10]; 4989 u8 op_mod[0x10]; 4990 4991 u8 reserved_at_40[0x18]; 4992 u8 priority[0x4]; 4993 u8 cong_protocol[0x4]; 4994 4995 u8 reserved_at_60[0x20]; 4996 }; 4997 4998 struct mlx5_ifc_query_cong_statistics_out_bits { 4999 u8 status[0x8]; 5000 u8 reserved_at_8[0x18]; 5001 5002 u8 syndrome[0x20]; 5003 5004 u8 reserved_at_40[0x40]; 5005 5006 u8 rp_cur_flows[0x20]; 5007 5008 u8 sum_flows[0x20]; 5009 5010 u8 rp_cnp_ignored_high[0x20]; 5011 5012 u8 rp_cnp_ignored_low[0x20]; 5013 5014 u8 rp_cnp_handled_high[0x20]; 5015 5016 u8 rp_cnp_handled_low[0x20]; 5017 5018 u8 reserved_at_140[0x100]; 5019 5020 u8 time_stamp_high[0x20]; 5021 5022 u8 time_stamp_low[0x20]; 5023 5024 u8 accumulators_period[0x20]; 5025 5026 u8 np_ecn_marked_roce_packets_high[0x20]; 5027 5028 u8 np_ecn_marked_roce_packets_low[0x20]; 5029 5030 u8 np_cnp_sent_high[0x20]; 5031 5032 u8 np_cnp_sent_low[0x20]; 5033 5034 u8 reserved_at_320[0x560]; 5035 }; 5036 5037 struct mlx5_ifc_query_cong_statistics_in_bits { 5038 u8 opcode[0x10]; 5039 u8 reserved_at_10[0x10]; 5040 5041 u8 reserved_at_20[0x10]; 5042 u8 op_mod[0x10]; 5043 5044 u8 clear[0x1]; 5045 u8 reserved_at_41[0x1f]; 5046 5047 u8 reserved_at_60[0x20]; 5048 }; 5049 5050 struct mlx5_ifc_query_cong_params_out_bits { 5051 u8 status[0x8]; 5052 u8 reserved_at_8[0x18]; 5053 5054 u8 syndrome[0x20]; 5055 5056 u8 reserved_at_40[0x40]; 5057 5058 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5059 }; 5060 5061 struct mlx5_ifc_query_cong_params_in_bits { 5062 u8 opcode[0x10]; 5063 u8 reserved_at_10[0x10]; 5064 5065 u8 reserved_at_20[0x10]; 5066 u8 op_mod[0x10]; 5067 5068 u8 reserved_at_40[0x1c]; 5069 u8 cong_protocol[0x4]; 5070 5071 u8 reserved_at_60[0x20]; 5072 }; 5073 5074 struct mlx5_ifc_query_adapter_out_bits { 5075 u8 status[0x8]; 5076 u8 reserved_at_8[0x18]; 5077 5078 u8 syndrome[0x20]; 5079 5080 u8 reserved_at_40[0x40]; 5081 5082 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 5083 }; 5084 5085 struct mlx5_ifc_query_adapter_in_bits { 5086 u8 opcode[0x10]; 5087 u8 reserved_at_10[0x10]; 5088 5089 u8 reserved_at_20[0x10]; 5090 u8 op_mod[0x10]; 5091 5092 u8 reserved_at_40[0x40]; 5093 }; 5094 5095 struct mlx5_ifc_qp_2rst_out_bits { 5096 u8 status[0x8]; 5097 u8 reserved_at_8[0x18]; 5098 5099 u8 syndrome[0x20]; 5100 5101 u8 reserved_at_40[0x40]; 5102 }; 5103 5104 struct mlx5_ifc_qp_2rst_in_bits { 5105 u8 opcode[0x10]; 5106 u8 reserved_at_10[0x10]; 5107 5108 u8 reserved_at_20[0x10]; 5109 u8 op_mod[0x10]; 5110 5111 u8 reserved_at_40[0x8]; 5112 u8 qpn[0x18]; 5113 5114 u8 reserved_at_60[0x20]; 5115 }; 5116 5117 struct mlx5_ifc_qp_2err_out_bits { 5118 u8 status[0x8]; 5119 u8 reserved_at_8[0x18]; 5120 5121 u8 syndrome[0x20]; 5122 5123 u8 reserved_at_40[0x40]; 5124 }; 5125 5126 struct mlx5_ifc_qp_2err_in_bits { 5127 u8 opcode[0x10]; 5128 u8 reserved_at_10[0x10]; 5129 5130 u8 reserved_at_20[0x10]; 5131 u8 op_mod[0x10]; 5132 5133 u8 reserved_at_40[0x8]; 5134 u8 qpn[0x18]; 5135 5136 u8 reserved_at_60[0x20]; 5137 }; 5138 5139 struct mlx5_ifc_page_fault_resume_out_bits { 5140 u8 status[0x8]; 5141 u8 reserved_at_8[0x18]; 5142 5143 u8 syndrome[0x20]; 5144 5145 u8 reserved_at_40[0x40]; 5146 }; 5147 5148 struct mlx5_ifc_page_fault_resume_in_bits { 5149 u8 opcode[0x10]; 5150 u8 reserved_at_10[0x10]; 5151 5152 u8 reserved_at_20[0x10]; 5153 u8 op_mod[0x10]; 5154 5155 u8 error[0x1]; 5156 u8 reserved_at_41[0x4]; 5157 u8 page_fault_type[0x3]; 5158 u8 wq_number[0x18]; 5159 5160 u8 reserved_at_60[0x8]; 5161 u8 token[0x18]; 5162 }; 5163 5164 struct mlx5_ifc_nop_out_bits { 5165 u8 status[0x8]; 5166 u8 reserved_at_8[0x18]; 5167 5168 u8 syndrome[0x20]; 5169 5170 u8 reserved_at_40[0x40]; 5171 }; 5172 5173 struct mlx5_ifc_nop_in_bits { 5174 u8 opcode[0x10]; 5175 u8 reserved_at_10[0x10]; 5176 5177 u8 reserved_at_20[0x10]; 5178 u8 op_mod[0x10]; 5179 5180 u8 reserved_at_40[0x40]; 5181 }; 5182 5183 struct mlx5_ifc_modify_vport_state_out_bits { 5184 u8 status[0x8]; 5185 u8 reserved_at_8[0x18]; 5186 5187 u8 syndrome[0x20]; 5188 5189 u8 reserved_at_40[0x40]; 5190 }; 5191 5192 struct mlx5_ifc_modify_vport_state_in_bits { 5193 u8 opcode[0x10]; 5194 u8 reserved_at_10[0x10]; 5195 5196 u8 reserved_at_20[0x10]; 5197 u8 op_mod[0x10]; 5198 5199 u8 other_vport[0x1]; 5200 u8 reserved_at_41[0xf]; 5201 u8 vport_number[0x10]; 5202 5203 u8 reserved_at_60[0x18]; 5204 u8 admin_state[0x4]; 5205 u8 reserved_at_7c[0x4]; 5206 }; 5207 5208 struct mlx5_ifc_modify_tis_out_bits { 5209 u8 status[0x8]; 5210 u8 reserved_at_8[0x18]; 5211 5212 u8 syndrome[0x20]; 5213 5214 u8 reserved_at_40[0x40]; 5215 }; 5216 5217 struct mlx5_ifc_modify_tis_bitmask_bits { 5218 u8 reserved_at_0[0x20]; 5219 5220 u8 reserved_at_20[0x1d]; 5221 u8 lag_tx_port_affinity[0x1]; 5222 u8 strict_lag_tx_port_affinity[0x1]; 5223 u8 prio[0x1]; 5224 }; 5225 5226 struct mlx5_ifc_modify_tis_in_bits { 5227 u8 opcode[0x10]; 5228 u8 reserved_at_10[0x10]; 5229 5230 u8 reserved_at_20[0x10]; 5231 u8 op_mod[0x10]; 5232 5233 u8 reserved_at_40[0x8]; 5234 u8 tisn[0x18]; 5235 5236 u8 reserved_at_60[0x20]; 5237 5238 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 5239 5240 u8 reserved_at_c0[0x40]; 5241 5242 struct mlx5_ifc_tisc_bits ctx; 5243 }; 5244 5245 struct mlx5_ifc_modify_tir_bitmask_bits { 5246 u8 reserved_at_0[0x20]; 5247 5248 u8 reserved_at_20[0x1b]; 5249 u8 self_lb_en[0x1]; 5250 u8 reserved_at_3c[0x1]; 5251 u8 hash[0x1]; 5252 u8 reserved_at_3e[0x1]; 5253 u8 lro[0x1]; 5254 }; 5255 5256 struct mlx5_ifc_modify_tir_out_bits { 5257 u8 status[0x8]; 5258 u8 reserved_at_8[0x18]; 5259 5260 u8 syndrome[0x20]; 5261 5262 u8 reserved_at_40[0x40]; 5263 }; 5264 5265 struct mlx5_ifc_modify_tir_in_bits { 5266 u8 opcode[0x10]; 5267 u8 reserved_at_10[0x10]; 5268 5269 u8 reserved_at_20[0x10]; 5270 u8 op_mod[0x10]; 5271 5272 u8 reserved_at_40[0x8]; 5273 u8 tirn[0x18]; 5274 5275 u8 reserved_at_60[0x20]; 5276 5277 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 5278 5279 u8 reserved_at_c0[0x40]; 5280 5281 struct mlx5_ifc_tirc_bits ctx; 5282 }; 5283 5284 struct mlx5_ifc_modify_sq_out_bits { 5285 u8 status[0x8]; 5286 u8 reserved_at_8[0x18]; 5287 5288 u8 syndrome[0x20]; 5289 5290 u8 reserved_at_40[0x40]; 5291 }; 5292 5293 struct mlx5_ifc_modify_sq_in_bits { 5294 u8 opcode[0x10]; 5295 u8 reserved_at_10[0x10]; 5296 5297 u8 reserved_at_20[0x10]; 5298 u8 op_mod[0x10]; 5299 5300 u8 sq_state[0x4]; 5301 u8 reserved_at_44[0x4]; 5302 u8 sqn[0x18]; 5303 5304 u8 reserved_at_60[0x20]; 5305 5306 u8 modify_bitmask[0x40]; 5307 5308 u8 reserved_at_c0[0x40]; 5309 5310 struct mlx5_ifc_sqc_bits ctx; 5311 }; 5312 5313 struct mlx5_ifc_modify_scheduling_element_out_bits { 5314 u8 status[0x8]; 5315 u8 reserved_at_8[0x18]; 5316 5317 u8 syndrome[0x20]; 5318 5319 u8 reserved_at_40[0x1c0]; 5320 }; 5321 5322 enum { 5323 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 5324 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 5325 }; 5326 5327 struct mlx5_ifc_modify_scheduling_element_in_bits { 5328 u8 opcode[0x10]; 5329 u8 reserved_at_10[0x10]; 5330 5331 u8 reserved_at_20[0x10]; 5332 u8 op_mod[0x10]; 5333 5334 u8 scheduling_hierarchy[0x8]; 5335 u8 reserved_at_48[0x18]; 5336 5337 u8 scheduling_element_id[0x20]; 5338 5339 u8 reserved_at_80[0x20]; 5340 5341 u8 modify_bitmask[0x20]; 5342 5343 u8 reserved_at_c0[0x40]; 5344 5345 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5346 5347 u8 reserved_at_300[0x100]; 5348 }; 5349 5350 struct mlx5_ifc_modify_rqt_out_bits { 5351 u8 status[0x8]; 5352 u8 reserved_at_8[0x18]; 5353 5354 u8 syndrome[0x20]; 5355 5356 u8 reserved_at_40[0x40]; 5357 }; 5358 5359 struct mlx5_ifc_rqt_bitmask_bits { 5360 u8 reserved_at_0[0x20]; 5361 5362 u8 reserved_at_20[0x1f]; 5363 u8 rqn_list[0x1]; 5364 }; 5365 5366 struct mlx5_ifc_modify_rqt_in_bits { 5367 u8 opcode[0x10]; 5368 u8 reserved_at_10[0x10]; 5369 5370 u8 reserved_at_20[0x10]; 5371 u8 op_mod[0x10]; 5372 5373 u8 reserved_at_40[0x8]; 5374 u8 rqtn[0x18]; 5375 5376 u8 reserved_at_60[0x20]; 5377 5378 struct mlx5_ifc_rqt_bitmask_bits bitmask; 5379 5380 u8 reserved_at_c0[0x40]; 5381 5382 struct mlx5_ifc_rqtc_bits ctx; 5383 }; 5384 5385 struct mlx5_ifc_modify_rq_out_bits { 5386 u8 status[0x8]; 5387 u8 reserved_at_8[0x18]; 5388 5389 u8 syndrome[0x20]; 5390 5391 u8 reserved_at_40[0x40]; 5392 }; 5393 5394 enum { 5395 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 5396 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 5397 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 5398 }; 5399 5400 struct mlx5_ifc_modify_rq_in_bits { 5401 u8 opcode[0x10]; 5402 u8 reserved_at_10[0x10]; 5403 5404 u8 reserved_at_20[0x10]; 5405 u8 op_mod[0x10]; 5406 5407 u8 rq_state[0x4]; 5408 u8 reserved_at_44[0x4]; 5409 u8 rqn[0x18]; 5410 5411 u8 reserved_at_60[0x20]; 5412 5413 u8 modify_bitmask[0x40]; 5414 5415 u8 reserved_at_c0[0x40]; 5416 5417 struct mlx5_ifc_rqc_bits ctx; 5418 }; 5419 5420 struct mlx5_ifc_modify_rmp_out_bits { 5421 u8 status[0x8]; 5422 u8 reserved_at_8[0x18]; 5423 5424 u8 syndrome[0x20]; 5425 5426 u8 reserved_at_40[0x40]; 5427 }; 5428 5429 struct mlx5_ifc_rmp_bitmask_bits { 5430 u8 reserved_at_0[0x20]; 5431 5432 u8 reserved_at_20[0x1f]; 5433 u8 lwm[0x1]; 5434 }; 5435 5436 struct mlx5_ifc_modify_rmp_in_bits { 5437 u8 opcode[0x10]; 5438 u8 reserved_at_10[0x10]; 5439 5440 u8 reserved_at_20[0x10]; 5441 u8 op_mod[0x10]; 5442 5443 u8 rmp_state[0x4]; 5444 u8 reserved_at_44[0x4]; 5445 u8 rmpn[0x18]; 5446 5447 u8 reserved_at_60[0x20]; 5448 5449 struct mlx5_ifc_rmp_bitmask_bits bitmask; 5450 5451 u8 reserved_at_c0[0x40]; 5452 5453 struct mlx5_ifc_rmpc_bits ctx; 5454 }; 5455 5456 struct mlx5_ifc_modify_nic_vport_context_out_bits { 5457 u8 status[0x8]; 5458 u8 reserved_at_8[0x18]; 5459 5460 u8 syndrome[0x20]; 5461 5462 u8 reserved_at_40[0x40]; 5463 }; 5464 5465 struct mlx5_ifc_modify_nic_vport_field_select_bits { 5466 u8 reserved_at_0[0x12]; 5467 u8 affiliation[0x1]; 5468 u8 reserved_at_e[0x1]; 5469 u8 disable_uc_local_lb[0x1]; 5470 u8 disable_mc_local_lb[0x1]; 5471 u8 node_guid[0x1]; 5472 u8 port_guid[0x1]; 5473 u8 min_inline[0x1]; 5474 u8 mtu[0x1]; 5475 u8 change_event[0x1]; 5476 u8 promisc[0x1]; 5477 u8 permanent_address[0x1]; 5478 u8 addresses_list[0x1]; 5479 u8 roce_en[0x1]; 5480 u8 reserved_at_1f[0x1]; 5481 }; 5482 5483 struct mlx5_ifc_modify_nic_vport_context_in_bits { 5484 u8 opcode[0x10]; 5485 u8 reserved_at_10[0x10]; 5486 5487 u8 reserved_at_20[0x10]; 5488 u8 op_mod[0x10]; 5489 5490 u8 other_vport[0x1]; 5491 u8 reserved_at_41[0xf]; 5492 u8 vport_number[0x10]; 5493 5494 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 5495 5496 u8 reserved_at_80[0x780]; 5497 5498 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5499 }; 5500 5501 struct mlx5_ifc_modify_hca_vport_context_out_bits { 5502 u8 status[0x8]; 5503 u8 reserved_at_8[0x18]; 5504 5505 u8 syndrome[0x20]; 5506 5507 u8 reserved_at_40[0x40]; 5508 }; 5509 5510 struct mlx5_ifc_modify_hca_vport_context_in_bits { 5511 u8 opcode[0x10]; 5512 u8 reserved_at_10[0x10]; 5513 5514 u8 reserved_at_20[0x10]; 5515 u8 op_mod[0x10]; 5516 5517 u8 other_vport[0x1]; 5518 u8 reserved_at_41[0xb]; 5519 u8 port_num[0x4]; 5520 u8 vport_number[0x10]; 5521 5522 u8 reserved_at_60[0x20]; 5523 5524 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5525 }; 5526 5527 struct mlx5_ifc_modify_cq_out_bits { 5528 u8 status[0x8]; 5529 u8 reserved_at_8[0x18]; 5530 5531 u8 syndrome[0x20]; 5532 5533 u8 reserved_at_40[0x40]; 5534 }; 5535 5536 enum { 5537 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 5538 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 5539 }; 5540 5541 struct mlx5_ifc_modify_cq_in_bits { 5542 u8 opcode[0x10]; 5543 u8 reserved_at_10[0x10]; 5544 5545 u8 reserved_at_20[0x10]; 5546 u8 op_mod[0x10]; 5547 5548 u8 reserved_at_40[0x8]; 5549 u8 cqn[0x18]; 5550 5551 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 5552 5553 struct mlx5_ifc_cqc_bits cq_context; 5554 5555 u8 reserved_at_280[0x600]; 5556 5557 u8 pas[0][0x40]; 5558 }; 5559 5560 struct mlx5_ifc_modify_cong_status_out_bits { 5561 u8 status[0x8]; 5562 u8 reserved_at_8[0x18]; 5563 5564 u8 syndrome[0x20]; 5565 5566 u8 reserved_at_40[0x40]; 5567 }; 5568 5569 struct mlx5_ifc_modify_cong_status_in_bits { 5570 u8 opcode[0x10]; 5571 u8 reserved_at_10[0x10]; 5572 5573 u8 reserved_at_20[0x10]; 5574 u8 op_mod[0x10]; 5575 5576 u8 reserved_at_40[0x18]; 5577 u8 priority[0x4]; 5578 u8 cong_protocol[0x4]; 5579 5580 u8 enable[0x1]; 5581 u8 tag_enable[0x1]; 5582 u8 reserved_at_62[0x1e]; 5583 }; 5584 5585 struct mlx5_ifc_modify_cong_params_out_bits { 5586 u8 status[0x8]; 5587 u8 reserved_at_8[0x18]; 5588 5589 u8 syndrome[0x20]; 5590 5591 u8 reserved_at_40[0x40]; 5592 }; 5593 5594 struct mlx5_ifc_modify_cong_params_in_bits { 5595 u8 opcode[0x10]; 5596 u8 reserved_at_10[0x10]; 5597 5598 u8 reserved_at_20[0x10]; 5599 u8 op_mod[0x10]; 5600 5601 u8 reserved_at_40[0x1c]; 5602 u8 cong_protocol[0x4]; 5603 5604 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 5605 5606 u8 reserved_at_80[0x80]; 5607 5608 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 5609 }; 5610 5611 struct mlx5_ifc_manage_pages_out_bits { 5612 u8 status[0x8]; 5613 u8 reserved_at_8[0x18]; 5614 5615 u8 syndrome[0x20]; 5616 5617 u8 output_num_entries[0x20]; 5618 5619 u8 reserved_at_60[0x20]; 5620 5621 u8 pas[0][0x40]; 5622 }; 5623 5624 enum { 5625 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 5626 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 5627 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 5628 }; 5629 5630 struct mlx5_ifc_manage_pages_in_bits { 5631 u8 opcode[0x10]; 5632 u8 reserved_at_10[0x10]; 5633 5634 u8 reserved_at_20[0x10]; 5635 u8 op_mod[0x10]; 5636 5637 u8 reserved_at_40[0x10]; 5638 u8 function_id[0x10]; 5639 5640 u8 input_num_entries[0x20]; 5641 5642 u8 pas[0][0x40]; 5643 }; 5644 5645 struct mlx5_ifc_mad_ifc_out_bits { 5646 u8 status[0x8]; 5647 u8 reserved_at_8[0x18]; 5648 5649 u8 syndrome[0x20]; 5650 5651 u8 reserved_at_40[0x40]; 5652 5653 u8 response_mad_packet[256][0x8]; 5654 }; 5655 5656 struct mlx5_ifc_mad_ifc_in_bits { 5657 u8 opcode[0x10]; 5658 u8 reserved_at_10[0x10]; 5659 5660 u8 reserved_at_20[0x10]; 5661 u8 op_mod[0x10]; 5662 5663 u8 remote_lid[0x10]; 5664 u8 reserved_at_50[0x8]; 5665 u8 port[0x8]; 5666 5667 u8 reserved_at_60[0x20]; 5668 5669 u8 mad[256][0x8]; 5670 }; 5671 5672 struct mlx5_ifc_init_hca_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 reserved_at_40[0x40]; 5679 }; 5680 5681 struct mlx5_ifc_init_hca_in_bits { 5682 u8 opcode[0x10]; 5683 u8 reserved_at_10[0x10]; 5684 5685 u8 reserved_at_20[0x10]; 5686 u8 op_mod[0x10]; 5687 5688 u8 reserved_at_40[0x40]; 5689 u8 sw_owner_id[4][0x20]; 5690 }; 5691 5692 struct mlx5_ifc_init2rtr_qp_out_bits { 5693 u8 status[0x8]; 5694 u8 reserved_at_8[0x18]; 5695 5696 u8 syndrome[0x20]; 5697 5698 u8 reserved_at_40[0x40]; 5699 }; 5700 5701 struct mlx5_ifc_init2rtr_qp_in_bits { 5702 u8 opcode[0x10]; 5703 u8 reserved_at_10[0x10]; 5704 5705 u8 reserved_at_20[0x10]; 5706 u8 op_mod[0x10]; 5707 5708 u8 reserved_at_40[0x8]; 5709 u8 qpn[0x18]; 5710 5711 u8 reserved_at_60[0x20]; 5712 5713 u8 opt_param_mask[0x20]; 5714 5715 u8 reserved_at_a0[0x20]; 5716 5717 struct mlx5_ifc_qpc_bits qpc; 5718 5719 u8 reserved_at_800[0x80]; 5720 }; 5721 5722 struct mlx5_ifc_init2init_qp_out_bits { 5723 u8 status[0x8]; 5724 u8 reserved_at_8[0x18]; 5725 5726 u8 syndrome[0x20]; 5727 5728 u8 reserved_at_40[0x40]; 5729 }; 5730 5731 struct mlx5_ifc_init2init_qp_in_bits { 5732 u8 opcode[0x10]; 5733 u8 reserved_at_10[0x10]; 5734 5735 u8 reserved_at_20[0x10]; 5736 u8 op_mod[0x10]; 5737 5738 u8 reserved_at_40[0x8]; 5739 u8 qpn[0x18]; 5740 5741 u8 reserved_at_60[0x20]; 5742 5743 u8 opt_param_mask[0x20]; 5744 5745 u8 reserved_at_a0[0x20]; 5746 5747 struct mlx5_ifc_qpc_bits qpc; 5748 5749 u8 reserved_at_800[0x80]; 5750 }; 5751 5752 struct mlx5_ifc_get_dropped_packet_log_out_bits { 5753 u8 status[0x8]; 5754 u8 reserved_at_8[0x18]; 5755 5756 u8 syndrome[0x20]; 5757 5758 u8 reserved_at_40[0x40]; 5759 5760 u8 packet_headers_log[128][0x8]; 5761 5762 u8 packet_syndrome[64][0x8]; 5763 }; 5764 5765 struct mlx5_ifc_get_dropped_packet_log_in_bits { 5766 u8 opcode[0x10]; 5767 u8 reserved_at_10[0x10]; 5768 5769 u8 reserved_at_20[0x10]; 5770 u8 op_mod[0x10]; 5771 5772 u8 reserved_at_40[0x40]; 5773 }; 5774 5775 struct mlx5_ifc_gen_eqe_in_bits { 5776 u8 opcode[0x10]; 5777 u8 reserved_at_10[0x10]; 5778 5779 u8 reserved_at_20[0x10]; 5780 u8 op_mod[0x10]; 5781 5782 u8 reserved_at_40[0x18]; 5783 u8 eq_number[0x8]; 5784 5785 u8 reserved_at_60[0x20]; 5786 5787 u8 eqe[64][0x8]; 5788 }; 5789 5790 struct mlx5_ifc_gen_eq_out_bits { 5791 u8 status[0x8]; 5792 u8 reserved_at_8[0x18]; 5793 5794 u8 syndrome[0x20]; 5795 5796 u8 reserved_at_40[0x40]; 5797 }; 5798 5799 struct mlx5_ifc_enable_hca_out_bits { 5800 u8 status[0x8]; 5801 u8 reserved_at_8[0x18]; 5802 5803 u8 syndrome[0x20]; 5804 5805 u8 reserved_at_40[0x20]; 5806 }; 5807 5808 struct mlx5_ifc_enable_hca_in_bits { 5809 u8 opcode[0x10]; 5810 u8 reserved_at_10[0x10]; 5811 5812 u8 reserved_at_20[0x10]; 5813 u8 op_mod[0x10]; 5814 5815 u8 reserved_at_40[0x10]; 5816 u8 function_id[0x10]; 5817 5818 u8 reserved_at_60[0x20]; 5819 }; 5820 5821 struct mlx5_ifc_drain_dct_out_bits { 5822 u8 status[0x8]; 5823 u8 reserved_at_8[0x18]; 5824 5825 u8 syndrome[0x20]; 5826 5827 u8 reserved_at_40[0x40]; 5828 }; 5829 5830 struct mlx5_ifc_drain_dct_in_bits { 5831 u8 opcode[0x10]; 5832 u8 reserved_at_10[0x10]; 5833 5834 u8 reserved_at_20[0x10]; 5835 u8 op_mod[0x10]; 5836 5837 u8 reserved_at_40[0x8]; 5838 u8 dctn[0x18]; 5839 5840 u8 reserved_at_60[0x20]; 5841 }; 5842 5843 struct mlx5_ifc_disable_hca_out_bits { 5844 u8 status[0x8]; 5845 u8 reserved_at_8[0x18]; 5846 5847 u8 syndrome[0x20]; 5848 5849 u8 reserved_at_40[0x20]; 5850 }; 5851 5852 struct mlx5_ifc_disable_hca_in_bits { 5853 u8 opcode[0x10]; 5854 u8 reserved_at_10[0x10]; 5855 5856 u8 reserved_at_20[0x10]; 5857 u8 op_mod[0x10]; 5858 5859 u8 reserved_at_40[0x10]; 5860 u8 function_id[0x10]; 5861 5862 u8 reserved_at_60[0x20]; 5863 }; 5864 5865 struct mlx5_ifc_detach_from_mcg_out_bits { 5866 u8 status[0x8]; 5867 u8 reserved_at_8[0x18]; 5868 5869 u8 syndrome[0x20]; 5870 5871 u8 reserved_at_40[0x40]; 5872 }; 5873 5874 struct mlx5_ifc_detach_from_mcg_in_bits { 5875 u8 opcode[0x10]; 5876 u8 reserved_at_10[0x10]; 5877 5878 u8 reserved_at_20[0x10]; 5879 u8 op_mod[0x10]; 5880 5881 u8 reserved_at_40[0x8]; 5882 u8 qpn[0x18]; 5883 5884 u8 reserved_at_60[0x20]; 5885 5886 u8 multicast_gid[16][0x8]; 5887 }; 5888 5889 struct mlx5_ifc_destroy_xrq_out_bits { 5890 u8 status[0x8]; 5891 u8 reserved_at_8[0x18]; 5892 5893 u8 syndrome[0x20]; 5894 5895 u8 reserved_at_40[0x40]; 5896 }; 5897 5898 struct mlx5_ifc_destroy_xrq_in_bits { 5899 u8 opcode[0x10]; 5900 u8 reserved_at_10[0x10]; 5901 5902 u8 reserved_at_20[0x10]; 5903 u8 op_mod[0x10]; 5904 5905 u8 reserved_at_40[0x8]; 5906 u8 xrqn[0x18]; 5907 5908 u8 reserved_at_60[0x20]; 5909 }; 5910 5911 struct mlx5_ifc_destroy_xrc_srq_out_bits { 5912 u8 status[0x8]; 5913 u8 reserved_at_8[0x18]; 5914 5915 u8 syndrome[0x20]; 5916 5917 u8 reserved_at_40[0x40]; 5918 }; 5919 5920 struct mlx5_ifc_destroy_xrc_srq_in_bits { 5921 u8 opcode[0x10]; 5922 u8 reserved_at_10[0x10]; 5923 5924 u8 reserved_at_20[0x10]; 5925 u8 op_mod[0x10]; 5926 5927 u8 reserved_at_40[0x8]; 5928 u8 xrc_srqn[0x18]; 5929 5930 u8 reserved_at_60[0x20]; 5931 }; 5932 5933 struct mlx5_ifc_destroy_tis_out_bits { 5934 u8 status[0x8]; 5935 u8 reserved_at_8[0x18]; 5936 5937 u8 syndrome[0x20]; 5938 5939 u8 reserved_at_40[0x40]; 5940 }; 5941 5942 struct mlx5_ifc_destroy_tis_in_bits { 5943 u8 opcode[0x10]; 5944 u8 reserved_at_10[0x10]; 5945 5946 u8 reserved_at_20[0x10]; 5947 u8 op_mod[0x10]; 5948 5949 u8 reserved_at_40[0x8]; 5950 u8 tisn[0x18]; 5951 5952 u8 reserved_at_60[0x20]; 5953 }; 5954 5955 struct mlx5_ifc_destroy_tir_out_bits { 5956 u8 status[0x8]; 5957 u8 reserved_at_8[0x18]; 5958 5959 u8 syndrome[0x20]; 5960 5961 u8 reserved_at_40[0x40]; 5962 }; 5963 5964 struct mlx5_ifc_destroy_tir_in_bits { 5965 u8 opcode[0x10]; 5966 u8 reserved_at_10[0x10]; 5967 5968 u8 reserved_at_20[0x10]; 5969 u8 op_mod[0x10]; 5970 5971 u8 reserved_at_40[0x8]; 5972 u8 tirn[0x18]; 5973 5974 u8 reserved_at_60[0x20]; 5975 }; 5976 5977 struct mlx5_ifc_destroy_srq_out_bits { 5978 u8 status[0x8]; 5979 u8 reserved_at_8[0x18]; 5980 5981 u8 syndrome[0x20]; 5982 5983 u8 reserved_at_40[0x40]; 5984 }; 5985 5986 struct mlx5_ifc_destroy_srq_in_bits { 5987 u8 opcode[0x10]; 5988 u8 reserved_at_10[0x10]; 5989 5990 u8 reserved_at_20[0x10]; 5991 u8 op_mod[0x10]; 5992 5993 u8 reserved_at_40[0x8]; 5994 u8 srqn[0x18]; 5995 5996 u8 reserved_at_60[0x20]; 5997 }; 5998 5999 struct mlx5_ifc_destroy_sq_out_bits { 6000 u8 status[0x8]; 6001 u8 reserved_at_8[0x18]; 6002 6003 u8 syndrome[0x20]; 6004 6005 u8 reserved_at_40[0x40]; 6006 }; 6007 6008 struct mlx5_ifc_destroy_sq_in_bits { 6009 u8 opcode[0x10]; 6010 u8 reserved_at_10[0x10]; 6011 6012 u8 reserved_at_20[0x10]; 6013 u8 op_mod[0x10]; 6014 6015 u8 reserved_at_40[0x8]; 6016 u8 sqn[0x18]; 6017 6018 u8 reserved_at_60[0x20]; 6019 }; 6020 6021 struct mlx5_ifc_destroy_scheduling_element_out_bits { 6022 u8 status[0x8]; 6023 u8 reserved_at_8[0x18]; 6024 6025 u8 syndrome[0x20]; 6026 6027 u8 reserved_at_40[0x1c0]; 6028 }; 6029 6030 struct mlx5_ifc_destroy_scheduling_element_in_bits { 6031 u8 opcode[0x10]; 6032 u8 reserved_at_10[0x10]; 6033 6034 u8 reserved_at_20[0x10]; 6035 u8 op_mod[0x10]; 6036 6037 u8 scheduling_hierarchy[0x8]; 6038 u8 reserved_at_48[0x18]; 6039 6040 u8 scheduling_element_id[0x20]; 6041 6042 u8 reserved_at_80[0x180]; 6043 }; 6044 6045 struct mlx5_ifc_destroy_rqt_out_bits { 6046 u8 status[0x8]; 6047 u8 reserved_at_8[0x18]; 6048 6049 u8 syndrome[0x20]; 6050 6051 u8 reserved_at_40[0x40]; 6052 }; 6053 6054 struct mlx5_ifc_destroy_rqt_in_bits { 6055 u8 opcode[0x10]; 6056 u8 reserved_at_10[0x10]; 6057 6058 u8 reserved_at_20[0x10]; 6059 u8 op_mod[0x10]; 6060 6061 u8 reserved_at_40[0x8]; 6062 u8 rqtn[0x18]; 6063 6064 u8 reserved_at_60[0x20]; 6065 }; 6066 6067 struct mlx5_ifc_destroy_rq_out_bits { 6068 u8 status[0x8]; 6069 u8 reserved_at_8[0x18]; 6070 6071 u8 syndrome[0x20]; 6072 6073 u8 reserved_at_40[0x40]; 6074 }; 6075 6076 struct mlx5_ifc_destroy_rq_in_bits { 6077 u8 opcode[0x10]; 6078 u8 reserved_at_10[0x10]; 6079 6080 u8 reserved_at_20[0x10]; 6081 u8 op_mod[0x10]; 6082 6083 u8 reserved_at_40[0x8]; 6084 u8 rqn[0x18]; 6085 6086 u8 reserved_at_60[0x20]; 6087 }; 6088 6089 struct mlx5_ifc_set_delay_drop_params_in_bits { 6090 u8 opcode[0x10]; 6091 u8 reserved_at_10[0x10]; 6092 6093 u8 reserved_at_20[0x10]; 6094 u8 op_mod[0x10]; 6095 6096 u8 reserved_at_40[0x20]; 6097 6098 u8 reserved_at_60[0x10]; 6099 u8 delay_drop_timeout[0x10]; 6100 }; 6101 6102 struct mlx5_ifc_set_delay_drop_params_out_bits { 6103 u8 status[0x8]; 6104 u8 reserved_at_8[0x18]; 6105 6106 u8 syndrome[0x20]; 6107 6108 u8 reserved_at_40[0x40]; 6109 }; 6110 6111 struct mlx5_ifc_destroy_rmp_out_bits { 6112 u8 status[0x8]; 6113 u8 reserved_at_8[0x18]; 6114 6115 u8 syndrome[0x20]; 6116 6117 u8 reserved_at_40[0x40]; 6118 }; 6119 6120 struct mlx5_ifc_destroy_rmp_in_bits { 6121 u8 opcode[0x10]; 6122 u8 reserved_at_10[0x10]; 6123 6124 u8 reserved_at_20[0x10]; 6125 u8 op_mod[0x10]; 6126 6127 u8 reserved_at_40[0x8]; 6128 u8 rmpn[0x18]; 6129 6130 u8 reserved_at_60[0x20]; 6131 }; 6132 6133 struct mlx5_ifc_destroy_qp_out_bits { 6134 u8 status[0x8]; 6135 u8 reserved_at_8[0x18]; 6136 6137 u8 syndrome[0x20]; 6138 6139 u8 reserved_at_40[0x40]; 6140 }; 6141 6142 struct mlx5_ifc_destroy_qp_in_bits { 6143 u8 opcode[0x10]; 6144 u8 reserved_at_10[0x10]; 6145 6146 u8 reserved_at_20[0x10]; 6147 u8 op_mod[0x10]; 6148 6149 u8 reserved_at_40[0x8]; 6150 u8 qpn[0x18]; 6151 6152 u8 reserved_at_60[0x20]; 6153 }; 6154 6155 struct mlx5_ifc_destroy_psv_out_bits { 6156 u8 status[0x8]; 6157 u8 reserved_at_8[0x18]; 6158 6159 u8 syndrome[0x20]; 6160 6161 u8 reserved_at_40[0x40]; 6162 }; 6163 6164 struct mlx5_ifc_destroy_psv_in_bits { 6165 u8 opcode[0x10]; 6166 u8 reserved_at_10[0x10]; 6167 6168 u8 reserved_at_20[0x10]; 6169 u8 op_mod[0x10]; 6170 6171 u8 reserved_at_40[0x8]; 6172 u8 psvn[0x18]; 6173 6174 u8 reserved_at_60[0x20]; 6175 }; 6176 6177 struct mlx5_ifc_destroy_mkey_out_bits { 6178 u8 status[0x8]; 6179 u8 reserved_at_8[0x18]; 6180 6181 u8 syndrome[0x20]; 6182 6183 u8 reserved_at_40[0x40]; 6184 }; 6185 6186 struct mlx5_ifc_destroy_mkey_in_bits { 6187 u8 opcode[0x10]; 6188 u8 reserved_at_10[0x10]; 6189 6190 u8 reserved_at_20[0x10]; 6191 u8 op_mod[0x10]; 6192 6193 u8 reserved_at_40[0x8]; 6194 u8 mkey_index[0x18]; 6195 6196 u8 reserved_at_60[0x20]; 6197 }; 6198 6199 struct mlx5_ifc_destroy_flow_table_out_bits { 6200 u8 status[0x8]; 6201 u8 reserved_at_8[0x18]; 6202 6203 u8 syndrome[0x20]; 6204 6205 u8 reserved_at_40[0x40]; 6206 }; 6207 6208 struct mlx5_ifc_destroy_flow_table_in_bits { 6209 u8 opcode[0x10]; 6210 u8 reserved_at_10[0x10]; 6211 6212 u8 reserved_at_20[0x10]; 6213 u8 op_mod[0x10]; 6214 6215 u8 other_vport[0x1]; 6216 u8 reserved_at_41[0xf]; 6217 u8 vport_number[0x10]; 6218 6219 u8 reserved_at_60[0x20]; 6220 6221 u8 table_type[0x8]; 6222 u8 reserved_at_88[0x18]; 6223 6224 u8 reserved_at_a0[0x8]; 6225 u8 table_id[0x18]; 6226 6227 u8 reserved_at_c0[0x140]; 6228 }; 6229 6230 struct mlx5_ifc_destroy_flow_group_out_bits { 6231 u8 status[0x8]; 6232 u8 reserved_at_8[0x18]; 6233 6234 u8 syndrome[0x20]; 6235 6236 u8 reserved_at_40[0x40]; 6237 }; 6238 6239 struct mlx5_ifc_destroy_flow_group_in_bits { 6240 u8 opcode[0x10]; 6241 u8 reserved_at_10[0x10]; 6242 6243 u8 reserved_at_20[0x10]; 6244 u8 op_mod[0x10]; 6245 6246 u8 other_vport[0x1]; 6247 u8 reserved_at_41[0xf]; 6248 u8 vport_number[0x10]; 6249 6250 u8 reserved_at_60[0x20]; 6251 6252 u8 table_type[0x8]; 6253 u8 reserved_at_88[0x18]; 6254 6255 u8 reserved_at_a0[0x8]; 6256 u8 table_id[0x18]; 6257 6258 u8 group_id[0x20]; 6259 6260 u8 reserved_at_e0[0x120]; 6261 }; 6262 6263 struct mlx5_ifc_destroy_eq_out_bits { 6264 u8 status[0x8]; 6265 u8 reserved_at_8[0x18]; 6266 6267 u8 syndrome[0x20]; 6268 6269 u8 reserved_at_40[0x40]; 6270 }; 6271 6272 struct mlx5_ifc_destroy_eq_in_bits { 6273 u8 opcode[0x10]; 6274 u8 reserved_at_10[0x10]; 6275 6276 u8 reserved_at_20[0x10]; 6277 u8 op_mod[0x10]; 6278 6279 u8 reserved_at_40[0x18]; 6280 u8 eq_number[0x8]; 6281 6282 u8 reserved_at_60[0x20]; 6283 }; 6284 6285 struct mlx5_ifc_destroy_dct_out_bits { 6286 u8 status[0x8]; 6287 u8 reserved_at_8[0x18]; 6288 6289 u8 syndrome[0x20]; 6290 6291 u8 reserved_at_40[0x40]; 6292 }; 6293 6294 struct mlx5_ifc_destroy_dct_in_bits { 6295 u8 opcode[0x10]; 6296 u8 reserved_at_10[0x10]; 6297 6298 u8 reserved_at_20[0x10]; 6299 u8 op_mod[0x10]; 6300 6301 u8 reserved_at_40[0x8]; 6302 u8 dctn[0x18]; 6303 6304 u8 reserved_at_60[0x20]; 6305 }; 6306 6307 struct mlx5_ifc_destroy_cq_out_bits { 6308 u8 status[0x8]; 6309 u8 reserved_at_8[0x18]; 6310 6311 u8 syndrome[0x20]; 6312 6313 u8 reserved_at_40[0x40]; 6314 }; 6315 6316 struct mlx5_ifc_destroy_cq_in_bits { 6317 u8 opcode[0x10]; 6318 u8 reserved_at_10[0x10]; 6319 6320 u8 reserved_at_20[0x10]; 6321 u8 op_mod[0x10]; 6322 6323 u8 reserved_at_40[0x8]; 6324 u8 cqn[0x18]; 6325 6326 u8 reserved_at_60[0x20]; 6327 }; 6328 6329 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 6330 u8 status[0x8]; 6331 u8 reserved_at_8[0x18]; 6332 6333 u8 syndrome[0x20]; 6334 6335 u8 reserved_at_40[0x40]; 6336 }; 6337 6338 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 6339 u8 opcode[0x10]; 6340 u8 reserved_at_10[0x10]; 6341 6342 u8 reserved_at_20[0x10]; 6343 u8 op_mod[0x10]; 6344 6345 u8 reserved_at_40[0x20]; 6346 6347 u8 reserved_at_60[0x10]; 6348 u8 vxlan_udp_port[0x10]; 6349 }; 6350 6351 struct mlx5_ifc_delete_l2_table_entry_out_bits { 6352 u8 status[0x8]; 6353 u8 reserved_at_8[0x18]; 6354 6355 u8 syndrome[0x20]; 6356 6357 u8 reserved_at_40[0x40]; 6358 }; 6359 6360 struct mlx5_ifc_delete_l2_table_entry_in_bits { 6361 u8 opcode[0x10]; 6362 u8 reserved_at_10[0x10]; 6363 6364 u8 reserved_at_20[0x10]; 6365 u8 op_mod[0x10]; 6366 6367 u8 reserved_at_40[0x60]; 6368 6369 u8 reserved_at_a0[0x8]; 6370 u8 table_index[0x18]; 6371 6372 u8 reserved_at_c0[0x140]; 6373 }; 6374 6375 struct mlx5_ifc_delete_fte_out_bits { 6376 u8 status[0x8]; 6377 u8 reserved_at_8[0x18]; 6378 6379 u8 syndrome[0x20]; 6380 6381 u8 reserved_at_40[0x40]; 6382 }; 6383 6384 struct mlx5_ifc_delete_fte_in_bits { 6385 u8 opcode[0x10]; 6386 u8 reserved_at_10[0x10]; 6387 6388 u8 reserved_at_20[0x10]; 6389 u8 op_mod[0x10]; 6390 6391 u8 other_vport[0x1]; 6392 u8 reserved_at_41[0xf]; 6393 u8 vport_number[0x10]; 6394 6395 u8 reserved_at_60[0x20]; 6396 6397 u8 table_type[0x8]; 6398 u8 reserved_at_88[0x18]; 6399 6400 u8 reserved_at_a0[0x8]; 6401 u8 table_id[0x18]; 6402 6403 u8 reserved_at_c0[0x40]; 6404 6405 u8 flow_index[0x20]; 6406 6407 u8 reserved_at_120[0xe0]; 6408 }; 6409 6410 struct mlx5_ifc_dealloc_xrcd_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_at_8[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_at_40[0x40]; 6417 }; 6418 6419 struct mlx5_ifc_dealloc_xrcd_in_bits { 6420 u8 opcode[0x10]; 6421 u8 reserved_at_10[0x10]; 6422 6423 u8 reserved_at_20[0x10]; 6424 u8 op_mod[0x10]; 6425 6426 u8 reserved_at_40[0x8]; 6427 u8 xrcd[0x18]; 6428 6429 u8 reserved_at_60[0x20]; 6430 }; 6431 6432 struct mlx5_ifc_dealloc_uar_out_bits { 6433 u8 status[0x8]; 6434 u8 reserved_at_8[0x18]; 6435 6436 u8 syndrome[0x20]; 6437 6438 u8 reserved_at_40[0x40]; 6439 }; 6440 6441 struct mlx5_ifc_dealloc_uar_in_bits { 6442 u8 opcode[0x10]; 6443 u8 reserved_at_10[0x10]; 6444 6445 u8 reserved_at_20[0x10]; 6446 u8 op_mod[0x10]; 6447 6448 u8 reserved_at_40[0x8]; 6449 u8 uar[0x18]; 6450 6451 u8 reserved_at_60[0x20]; 6452 }; 6453 6454 struct mlx5_ifc_dealloc_transport_domain_out_bits { 6455 u8 status[0x8]; 6456 u8 reserved_at_8[0x18]; 6457 6458 u8 syndrome[0x20]; 6459 6460 u8 reserved_at_40[0x40]; 6461 }; 6462 6463 struct mlx5_ifc_dealloc_transport_domain_in_bits { 6464 u8 opcode[0x10]; 6465 u8 reserved_at_10[0x10]; 6466 6467 u8 reserved_at_20[0x10]; 6468 u8 op_mod[0x10]; 6469 6470 u8 reserved_at_40[0x8]; 6471 u8 transport_domain[0x18]; 6472 6473 u8 reserved_at_60[0x20]; 6474 }; 6475 6476 struct mlx5_ifc_dealloc_q_counter_out_bits { 6477 u8 status[0x8]; 6478 u8 reserved_at_8[0x18]; 6479 6480 u8 syndrome[0x20]; 6481 6482 u8 reserved_at_40[0x40]; 6483 }; 6484 6485 struct mlx5_ifc_dealloc_q_counter_in_bits { 6486 u8 opcode[0x10]; 6487 u8 reserved_at_10[0x10]; 6488 6489 u8 reserved_at_20[0x10]; 6490 u8 op_mod[0x10]; 6491 6492 u8 reserved_at_40[0x18]; 6493 u8 counter_set_id[0x8]; 6494 6495 u8 reserved_at_60[0x20]; 6496 }; 6497 6498 struct mlx5_ifc_dealloc_pd_out_bits { 6499 u8 status[0x8]; 6500 u8 reserved_at_8[0x18]; 6501 6502 u8 syndrome[0x20]; 6503 6504 u8 reserved_at_40[0x40]; 6505 }; 6506 6507 struct mlx5_ifc_dealloc_pd_in_bits { 6508 u8 opcode[0x10]; 6509 u8 reserved_at_10[0x10]; 6510 6511 u8 reserved_at_20[0x10]; 6512 u8 op_mod[0x10]; 6513 6514 u8 reserved_at_40[0x8]; 6515 u8 pd[0x18]; 6516 6517 u8 reserved_at_60[0x20]; 6518 }; 6519 6520 struct mlx5_ifc_dealloc_flow_counter_out_bits { 6521 u8 status[0x8]; 6522 u8 reserved_at_8[0x18]; 6523 6524 u8 syndrome[0x20]; 6525 6526 u8 reserved_at_40[0x40]; 6527 }; 6528 6529 struct mlx5_ifc_dealloc_flow_counter_in_bits { 6530 u8 opcode[0x10]; 6531 u8 reserved_at_10[0x10]; 6532 6533 u8 reserved_at_20[0x10]; 6534 u8 op_mod[0x10]; 6535 6536 u8 flow_counter_id[0x20]; 6537 6538 u8 reserved_at_60[0x20]; 6539 }; 6540 6541 struct mlx5_ifc_create_xrq_out_bits { 6542 u8 status[0x8]; 6543 u8 reserved_at_8[0x18]; 6544 6545 u8 syndrome[0x20]; 6546 6547 u8 reserved_at_40[0x8]; 6548 u8 xrqn[0x18]; 6549 6550 u8 reserved_at_60[0x20]; 6551 }; 6552 6553 struct mlx5_ifc_create_xrq_in_bits { 6554 u8 opcode[0x10]; 6555 u8 reserved_at_10[0x10]; 6556 6557 u8 reserved_at_20[0x10]; 6558 u8 op_mod[0x10]; 6559 6560 u8 reserved_at_40[0x40]; 6561 6562 struct mlx5_ifc_xrqc_bits xrq_context; 6563 }; 6564 6565 struct mlx5_ifc_create_xrc_srq_out_bits { 6566 u8 status[0x8]; 6567 u8 reserved_at_8[0x18]; 6568 6569 u8 syndrome[0x20]; 6570 6571 u8 reserved_at_40[0x8]; 6572 u8 xrc_srqn[0x18]; 6573 6574 u8 reserved_at_60[0x20]; 6575 }; 6576 6577 struct mlx5_ifc_create_xrc_srq_in_bits { 6578 u8 opcode[0x10]; 6579 u8 reserved_at_10[0x10]; 6580 6581 u8 reserved_at_20[0x10]; 6582 u8 op_mod[0x10]; 6583 6584 u8 reserved_at_40[0x40]; 6585 6586 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 6587 6588 u8 reserved_at_280[0x600]; 6589 6590 u8 pas[0][0x40]; 6591 }; 6592 6593 struct mlx5_ifc_create_tis_out_bits { 6594 u8 status[0x8]; 6595 u8 reserved_at_8[0x18]; 6596 6597 u8 syndrome[0x20]; 6598 6599 u8 reserved_at_40[0x8]; 6600 u8 tisn[0x18]; 6601 6602 u8 reserved_at_60[0x20]; 6603 }; 6604 6605 struct mlx5_ifc_create_tis_in_bits { 6606 u8 opcode[0x10]; 6607 u8 reserved_at_10[0x10]; 6608 6609 u8 reserved_at_20[0x10]; 6610 u8 op_mod[0x10]; 6611 6612 u8 reserved_at_40[0xc0]; 6613 6614 struct mlx5_ifc_tisc_bits ctx; 6615 }; 6616 6617 struct mlx5_ifc_create_tir_out_bits { 6618 u8 status[0x8]; 6619 u8 reserved_at_8[0x18]; 6620 6621 u8 syndrome[0x20]; 6622 6623 u8 reserved_at_40[0x8]; 6624 u8 tirn[0x18]; 6625 6626 u8 reserved_at_60[0x20]; 6627 }; 6628 6629 struct mlx5_ifc_create_tir_in_bits { 6630 u8 opcode[0x10]; 6631 u8 reserved_at_10[0x10]; 6632 6633 u8 reserved_at_20[0x10]; 6634 u8 op_mod[0x10]; 6635 6636 u8 reserved_at_40[0xc0]; 6637 6638 struct mlx5_ifc_tirc_bits ctx; 6639 }; 6640 6641 struct mlx5_ifc_create_srq_out_bits { 6642 u8 status[0x8]; 6643 u8 reserved_at_8[0x18]; 6644 6645 u8 syndrome[0x20]; 6646 6647 u8 reserved_at_40[0x8]; 6648 u8 srqn[0x18]; 6649 6650 u8 reserved_at_60[0x20]; 6651 }; 6652 6653 struct mlx5_ifc_create_srq_in_bits { 6654 u8 opcode[0x10]; 6655 u8 reserved_at_10[0x10]; 6656 6657 u8 reserved_at_20[0x10]; 6658 u8 op_mod[0x10]; 6659 6660 u8 reserved_at_40[0x40]; 6661 6662 struct mlx5_ifc_srqc_bits srq_context_entry; 6663 6664 u8 reserved_at_280[0x600]; 6665 6666 u8 pas[0][0x40]; 6667 }; 6668 6669 struct mlx5_ifc_create_sq_out_bits { 6670 u8 status[0x8]; 6671 u8 reserved_at_8[0x18]; 6672 6673 u8 syndrome[0x20]; 6674 6675 u8 reserved_at_40[0x8]; 6676 u8 sqn[0x18]; 6677 6678 u8 reserved_at_60[0x20]; 6679 }; 6680 6681 struct mlx5_ifc_create_sq_in_bits { 6682 u8 opcode[0x10]; 6683 u8 reserved_at_10[0x10]; 6684 6685 u8 reserved_at_20[0x10]; 6686 u8 op_mod[0x10]; 6687 6688 u8 reserved_at_40[0xc0]; 6689 6690 struct mlx5_ifc_sqc_bits ctx; 6691 }; 6692 6693 struct mlx5_ifc_create_scheduling_element_out_bits { 6694 u8 status[0x8]; 6695 u8 reserved_at_8[0x18]; 6696 6697 u8 syndrome[0x20]; 6698 6699 u8 reserved_at_40[0x40]; 6700 6701 u8 scheduling_element_id[0x20]; 6702 6703 u8 reserved_at_a0[0x160]; 6704 }; 6705 6706 struct mlx5_ifc_create_scheduling_element_in_bits { 6707 u8 opcode[0x10]; 6708 u8 reserved_at_10[0x10]; 6709 6710 u8 reserved_at_20[0x10]; 6711 u8 op_mod[0x10]; 6712 6713 u8 scheduling_hierarchy[0x8]; 6714 u8 reserved_at_48[0x18]; 6715 6716 u8 reserved_at_60[0xa0]; 6717 6718 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6719 6720 u8 reserved_at_300[0x100]; 6721 }; 6722 6723 struct mlx5_ifc_create_rqt_out_bits { 6724 u8 status[0x8]; 6725 u8 reserved_at_8[0x18]; 6726 6727 u8 syndrome[0x20]; 6728 6729 u8 reserved_at_40[0x8]; 6730 u8 rqtn[0x18]; 6731 6732 u8 reserved_at_60[0x20]; 6733 }; 6734 6735 struct mlx5_ifc_create_rqt_in_bits { 6736 u8 opcode[0x10]; 6737 u8 reserved_at_10[0x10]; 6738 6739 u8 reserved_at_20[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_at_40[0xc0]; 6743 6744 struct mlx5_ifc_rqtc_bits rqt_context; 6745 }; 6746 6747 struct mlx5_ifc_create_rq_out_bits { 6748 u8 status[0x8]; 6749 u8 reserved_at_8[0x18]; 6750 6751 u8 syndrome[0x20]; 6752 6753 u8 reserved_at_40[0x8]; 6754 u8 rqn[0x18]; 6755 6756 u8 reserved_at_60[0x20]; 6757 }; 6758 6759 struct mlx5_ifc_create_rq_in_bits { 6760 u8 opcode[0x10]; 6761 u8 reserved_at_10[0x10]; 6762 6763 u8 reserved_at_20[0x10]; 6764 u8 op_mod[0x10]; 6765 6766 u8 reserved_at_40[0xc0]; 6767 6768 struct mlx5_ifc_rqc_bits ctx; 6769 }; 6770 6771 struct mlx5_ifc_create_rmp_out_bits { 6772 u8 status[0x8]; 6773 u8 reserved_at_8[0x18]; 6774 6775 u8 syndrome[0x20]; 6776 6777 u8 reserved_at_40[0x8]; 6778 u8 rmpn[0x18]; 6779 6780 u8 reserved_at_60[0x20]; 6781 }; 6782 6783 struct mlx5_ifc_create_rmp_in_bits { 6784 u8 opcode[0x10]; 6785 u8 reserved_at_10[0x10]; 6786 6787 u8 reserved_at_20[0x10]; 6788 u8 op_mod[0x10]; 6789 6790 u8 reserved_at_40[0xc0]; 6791 6792 struct mlx5_ifc_rmpc_bits ctx; 6793 }; 6794 6795 struct mlx5_ifc_create_qp_out_bits { 6796 u8 status[0x8]; 6797 u8 reserved_at_8[0x18]; 6798 6799 u8 syndrome[0x20]; 6800 6801 u8 reserved_at_40[0x8]; 6802 u8 qpn[0x18]; 6803 6804 u8 reserved_at_60[0x20]; 6805 }; 6806 6807 struct mlx5_ifc_create_qp_in_bits { 6808 u8 opcode[0x10]; 6809 u8 reserved_at_10[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 reserved_at_40[0x40]; 6815 6816 u8 opt_param_mask[0x20]; 6817 6818 u8 reserved_at_a0[0x20]; 6819 6820 struct mlx5_ifc_qpc_bits qpc; 6821 6822 u8 reserved_at_800[0x80]; 6823 6824 u8 pas[0][0x40]; 6825 }; 6826 6827 struct mlx5_ifc_create_psv_out_bits { 6828 u8 status[0x8]; 6829 u8 reserved_at_8[0x18]; 6830 6831 u8 syndrome[0x20]; 6832 6833 u8 reserved_at_40[0x40]; 6834 6835 u8 reserved_at_80[0x8]; 6836 u8 psv0_index[0x18]; 6837 6838 u8 reserved_at_a0[0x8]; 6839 u8 psv1_index[0x18]; 6840 6841 u8 reserved_at_c0[0x8]; 6842 u8 psv2_index[0x18]; 6843 6844 u8 reserved_at_e0[0x8]; 6845 u8 psv3_index[0x18]; 6846 }; 6847 6848 struct mlx5_ifc_create_psv_in_bits { 6849 u8 opcode[0x10]; 6850 u8 reserved_at_10[0x10]; 6851 6852 u8 reserved_at_20[0x10]; 6853 u8 op_mod[0x10]; 6854 6855 u8 num_psv[0x4]; 6856 u8 reserved_at_44[0x4]; 6857 u8 pd[0x18]; 6858 6859 u8 reserved_at_60[0x20]; 6860 }; 6861 6862 struct mlx5_ifc_create_mkey_out_bits { 6863 u8 status[0x8]; 6864 u8 reserved_at_8[0x18]; 6865 6866 u8 syndrome[0x20]; 6867 6868 u8 reserved_at_40[0x8]; 6869 u8 mkey_index[0x18]; 6870 6871 u8 reserved_at_60[0x20]; 6872 }; 6873 6874 struct mlx5_ifc_create_mkey_in_bits { 6875 u8 opcode[0x10]; 6876 u8 reserved_at_10[0x10]; 6877 6878 u8 reserved_at_20[0x10]; 6879 u8 op_mod[0x10]; 6880 6881 u8 reserved_at_40[0x20]; 6882 6883 u8 pg_access[0x1]; 6884 u8 reserved_at_61[0x1f]; 6885 6886 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 6887 6888 u8 reserved_at_280[0x80]; 6889 6890 u8 translations_octword_actual_size[0x20]; 6891 6892 u8 reserved_at_320[0x560]; 6893 6894 u8 klm_pas_mtt[0][0x20]; 6895 }; 6896 6897 struct mlx5_ifc_create_flow_table_out_bits { 6898 u8 status[0x8]; 6899 u8 reserved_at_8[0x18]; 6900 6901 u8 syndrome[0x20]; 6902 6903 u8 reserved_at_40[0x8]; 6904 u8 table_id[0x18]; 6905 6906 u8 reserved_at_60[0x20]; 6907 }; 6908 6909 struct mlx5_ifc_flow_table_context_bits { 6910 u8 encap_en[0x1]; 6911 u8 decap_en[0x1]; 6912 u8 reserved_at_2[0x2]; 6913 u8 table_miss_action[0x4]; 6914 u8 level[0x8]; 6915 u8 reserved_at_10[0x8]; 6916 u8 log_size[0x8]; 6917 6918 u8 reserved_at_20[0x8]; 6919 u8 table_miss_id[0x18]; 6920 6921 u8 reserved_at_40[0x8]; 6922 u8 lag_master_next_table_id[0x18]; 6923 6924 u8 reserved_at_60[0xe0]; 6925 }; 6926 6927 struct mlx5_ifc_create_flow_table_in_bits { 6928 u8 opcode[0x10]; 6929 u8 reserved_at_10[0x10]; 6930 6931 u8 reserved_at_20[0x10]; 6932 u8 op_mod[0x10]; 6933 6934 u8 other_vport[0x1]; 6935 u8 reserved_at_41[0xf]; 6936 u8 vport_number[0x10]; 6937 6938 u8 reserved_at_60[0x20]; 6939 6940 u8 table_type[0x8]; 6941 u8 reserved_at_88[0x18]; 6942 6943 u8 reserved_at_a0[0x20]; 6944 6945 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6946 }; 6947 6948 struct mlx5_ifc_create_flow_group_out_bits { 6949 u8 status[0x8]; 6950 u8 reserved_at_8[0x18]; 6951 6952 u8 syndrome[0x20]; 6953 6954 u8 reserved_at_40[0x8]; 6955 u8 group_id[0x18]; 6956 6957 u8 reserved_at_60[0x20]; 6958 }; 6959 6960 enum { 6961 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6962 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6963 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6964 }; 6965 6966 struct mlx5_ifc_create_flow_group_in_bits { 6967 u8 opcode[0x10]; 6968 u8 reserved_at_10[0x10]; 6969 6970 u8 reserved_at_20[0x10]; 6971 u8 op_mod[0x10]; 6972 6973 u8 other_vport[0x1]; 6974 u8 reserved_at_41[0xf]; 6975 u8 vport_number[0x10]; 6976 6977 u8 reserved_at_60[0x20]; 6978 6979 u8 table_type[0x8]; 6980 u8 reserved_at_88[0x18]; 6981 6982 u8 reserved_at_a0[0x8]; 6983 u8 table_id[0x18]; 6984 6985 u8 source_eswitch_owner_vhca_id_valid[0x1]; 6986 6987 u8 reserved_at_c1[0x1f]; 6988 6989 u8 start_flow_index[0x20]; 6990 6991 u8 reserved_at_100[0x20]; 6992 6993 u8 end_flow_index[0x20]; 6994 6995 u8 reserved_at_140[0xa0]; 6996 6997 u8 reserved_at_1e0[0x18]; 6998 u8 match_criteria_enable[0x8]; 6999 7000 struct mlx5_ifc_fte_match_param_bits match_criteria; 7001 7002 u8 reserved_at_1200[0xe00]; 7003 }; 7004 7005 struct mlx5_ifc_create_eq_out_bits { 7006 u8 status[0x8]; 7007 u8 reserved_at_8[0x18]; 7008 7009 u8 syndrome[0x20]; 7010 7011 u8 reserved_at_40[0x18]; 7012 u8 eq_number[0x8]; 7013 7014 u8 reserved_at_60[0x20]; 7015 }; 7016 7017 struct mlx5_ifc_create_eq_in_bits { 7018 u8 opcode[0x10]; 7019 u8 reserved_at_10[0x10]; 7020 7021 u8 reserved_at_20[0x10]; 7022 u8 op_mod[0x10]; 7023 7024 u8 reserved_at_40[0x40]; 7025 7026 struct mlx5_ifc_eqc_bits eq_context_entry; 7027 7028 u8 reserved_at_280[0x40]; 7029 7030 u8 event_bitmask[0x40]; 7031 7032 u8 reserved_at_300[0x580]; 7033 7034 u8 pas[0][0x40]; 7035 }; 7036 7037 struct mlx5_ifc_create_dct_out_bits { 7038 u8 status[0x8]; 7039 u8 reserved_at_8[0x18]; 7040 7041 u8 syndrome[0x20]; 7042 7043 u8 reserved_at_40[0x8]; 7044 u8 dctn[0x18]; 7045 7046 u8 reserved_at_60[0x20]; 7047 }; 7048 7049 struct mlx5_ifc_create_dct_in_bits { 7050 u8 opcode[0x10]; 7051 u8 reserved_at_10[0x10]; 7052 7053 u8 reserved_at_20[0x10]; 7054 u8 op_mod[0x10]; 7055 7056 u8 reserved_at_40[0x40]; 7057 7058 struct mlx5_ifc_dctc_bits dct_context_entry; 7059 7060 u8 reserved_at_280[0x180]; 7061 }; 7062 7063 struct mlx5_ifc_create_cq_out_bits { 7064 u8 status[0x8]; 7065 u8 reserved_at_8[0x18]; 7066 7067 u8 syndrome[0x20]; 7068 7069 u8 reserved_at_40[0x8]; 7070 u8 cqn[0x18]; 7071 7072 u8 reserved_at_60[0x20]; 7073 }; 7074 7075 struct mlx5_ifc_create_cq_in_bits { 7076 u8 opcode[0x10]; 7077 u8 reserved_at_10[0x10]; 7078 7079 u8 reserved_at_20[0x10]; 7080 u8 op_mod[0x10]; 7081 7082 u8 reserved_at_40[0x40]; 7083 7084 struct mlx5_ifc_cqc_bits cq_context; 7085 7086 u8 reserved_at_280[0x600]; 7087 7088 u8 pas[0][0x40]; 7089 }; 7090 7091 struct mlx5_ifc_config_int_moderation_out_bits { 7092 u8 status[0x8]; 7093 u8 reserved_at_8[0x18]; 7094 7095 u8 syndrome[0x20]; 7096 7097 u8 reserved_at_40[0x4]; 7098 u8 min_delay[0xc]; 7099 u8 int_vector[0x10]; 7100 7101 u8 reserved_at_60[0x20]; 7102 }; 7103 7104 enum { 7105 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 7106 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 7107 }; 7108 7109 struct mlx5_ifc_config_int_moderation_in_bits { 7110 u8 opcode[0x10]; 7111 u8 reserved_at_10[0x10]; 7112 7113 u8 reserved_at_20[0x10]; 7114 u8 op_mod[0x10]; 7115 7116 u8 reserved_at_40[0x4]; 7117 u8 min_delay[0xc]; 7118 u8 int_vector[0x10]; 7119 7120 u8 reserved_at_60[0x20]; 7121 }; 7122 7123 struct mlx5_ifc_attach_to_mcg_out_bits { 7124 u8 status[0x8]; 7125 u8 reserved_at_8[0x18]; 7126 7127 u8 syndrome[0x20]; 7128 7129 u8 reserved_at_40[0x40]; 7130 }; 7131 7132 struct mlx5_ifc_attach_to_mcg_in_bits { 7133 u8 opcode[0x10]; 7134 u8 reserved_at_10[0x10]; 7135 7136 u8 reserved_at_20[0x10]; 7137 u8 op_mod[0x10]; 7138 7139 u8 reserved_at_40[0x8]; 7140 u8 qpn[0x18]; 7141 7142 u8 reserved_at_60[0x20]; 7143 7144 u8 multicast_gid[16][0x8]; 7145 }; 7146 7147 struct mlx5_ifc_arm_xrq_out_bits { 7148 u8 status[0x8]; 7149 u8 reserved_at_8[0x18]; 7150 7151 u8 syndrome[0x20]; 7152 7153 u8 reserved_at_40[0x40]; 7154 }; 7155 7156 struct mlx5_ifc_arm_xrq_in_bits { 7157 u8 opcode[0x10]; 7158 u8 reserved_at_10[0x10]; 7159 7160 u8 reserved_at_20[0x10]; 7161 u8 op_mod[0x10]; 7162 7163 u8 reserved_at_40[0x8]; 7164 u8 xrqn[0x18]; 7165 7166 u8 reserved_at_60[0x10]; 7167 u8 lwm[0x10]; 7168 }; 7169 7170 struct mlx5_ifc_arm_xrc_srq_out_bits { 7171 u8 status[0x8]; 7172 u8 reserved_at_8[0x18]; 7173 7174 u8 syndrome[0x20]; 7175 7176 u8 reserved_at_40[0x40]; 7177 }; 7178 7179 enum { 7180 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 7181 }; 7182 7183 struct mlx5_ifc_arm_xrc_srq_in_bits { 7184 u8 opcode[0x10]; 7185 u8 reserved_at_10[0x10]; 7186 7187 u8 reserved_at_20[0x10]; 7188 u8 op_mod[0x10]; 7189 7190 u8 reserved_at_40[0x8]; 7191 u8 xrc_srqn[0x18]; 7192 7193 u8 reserved_at_60[0x10]; 7194 u8 lwm[0x10]; 7195 }; 7196 7197 struct mlx5_ifc_arm_rq_out_bits { 7198 u8 status[0x8]; 7199 u8 reserved_at_8[0x18]; 7200 7201 u8 syndrome[0x20]; 7202 7203 u8 reserved_at_40[0x40]; 7204 }; 7205 7206 enum { 7207 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 7208 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 7209 }; 7210 7211 struct mlx5_ifc_arm_rq_in_bits { 7212 u8 opcode[0x10]; 7213 u8 reserved_at_10[0x10]; 7214 7215 u8 reserved_at_20[0x10]; 7216 u8 op_mod[0x10]; 7217 7218 u8 reserved_at_40[0x8]; 7219 u8 srq_number[0x18]; 7220 7221 u8 reserved_at_60[0x10]; 7222 u8 lwm[0x10]; 7223 }; 7224 7225 struct mlx5_ifc_arm_dct_out_bits { 7226 u8 status[0x8]; 7227 u8 reserved_at_8[0x18]; 7228 7229 u8 syndrome[0x20]; 7230 7231 u8 reserved_at_40[0x40]; 7232 }; 7233 7234 struct mlx5_ifc_arm_dct_in_bits { 7235 u8 opcode[0x10]; 7236 u8 reserved_at_10[0x10]; 7237 7238 u8 reserved_at_20[0x10]; 7239 u8 op_mod[0x10]; 7240 7241 u8 reserved_at_40[0x8]; 7242 u8 dct_number[0x18]; 7243 7244 u8 reserved_at_60[0x20]; 7245 }; 7246 7247 struct mlx5_ifc_alloc_xrcd_out_bits { 7248 u8 status[0x8]; 7249 u8 reserved_at_8[0x18]; 7250 7251 u8 syndrome[0x20]; 7252 7253 u8 reserved_at_40[0x8]; 7254 u8 xrcd[0x18]; 7255 7256 u8 reserved_at_60[0x20]; 7257 }; 7258 7259 struct mlx5_ifc_alloc_xrcd_in_bits { 7260 u8 opcode[0x10]; 7261 u8 reserved_at_10[0x10]; 7262 7263 u8 reserved_at_20[0x10]; 7264 u8 op_mod[0x10]; 7265 7266 u8 reserved_at_40[0x40]; 7267 }; 7268 7269 struct mlx5_ifc_alloc_uar_out_bits { 7270 u8 status[0x8]; 7271 u8 reserved_at_8[0x18]; 7272 7273 u8 syndrome[0x20]; 7274 7275 u8 reserved_at_40[0x8]; 7276 u8 uar[0x18]; 7277 7278 u8 reserved_at_60[0x20]; 7279 }; 7280 7281 struct mlx5_ifc_alloc_uar_in_bits { 7282 u8 opcode[0x10]; 7283 u8 reserved_at_10[0x10]; 7284 7285 u8 reserved_at_20[0x10]; 7286 u8 op_mod[0x10]; 7287 7288 u8 reserved_at_40[0x40]; 7289 }; 7290 7291 struct mlx5_ifc_alloc_transport_domain_out_bits { 7292 u8 status[0x8]; 7293 u8 reserved_at_8[0x18]; 7294 7295 u8 syndrome[0x20]; 7296 7297 u8 reserved_at_40[0x8]; 7298 u8 transport_domain[0x18]; 7299 7300 u8 reserved_at_60[0x20]; 7301 }; 7302 7303 struct mlx5_ifc_alloc_transport_domain_in_bits { 7304 u8 opcode[0x10]; 7305 u8 reserved_at_10[0x10]; 7306 7307 u8 reserved_at_20[0x10]; 7308 u8 op_mod[0x10]; 7309 7310 u8 reserved_at_40[0x40]; 7311 }; 7312 7313 struct mlx5_ifc_alloc_q_counter_out_bits { 7314 u8 status[0x8]; 7315 u8 reserved_at_8[0x18]; 7316 7317 u8 syndrome[0x20]; 7318 7319 u8 reserved_at_40[0x18]; 7320 u8 counter_set_id[0x8]; 7321 7322 u8 reserved_at_60[0x20]; 7323 }; 7324 7325 struct mlx5_ifc_alloc_q_counter_in_bits { 7326 u8 opcode[0x10]; 7327 u8 reserved_at_10[0x10]; 7328 7329 u8 reserved_at_20[0x10]; 7330 u8 op_mod[0x10]; 7331 7332 u8 reserved_at_40[0x40]; 7333 }; 7334 7335 struct mlx5_ifc_alloc_pd_out_bits { 7336 u8 status[0x8]; 7337 u8 reserved_at_8[0x18]; 7338 7339 u8 syndrome[0x20]; 7340 7341 u8 reserved_at_40[0x8]; 7342 u8 pd[0x18]; 7343 7344 u8 reserved_at_60[0x20]; 7345 }; 7346 7347 struct mlx5_ifc_alloc_pd_in_bits { 7348 u8 opcode[0x10]; 7349 u8 reserved_at_10[0x10]; 7350 7351 u8 reserved_at_20[0x10]; 7352 u8 op_mod[0x10]; 7353 7354 u8 reserved_at_40[0x40]; 7355 }; 7356 7357 struct mlx5_ifc_alloc_flow_counter_out_bits { 7358 u8 status[0x8]; 7359 u8 reserved_at_8[0x18]; 7360 7361 u8 syndrome[0x20]; 7362 7363 u8 flow_counter_id[0x20]; 7364 7365 u8 reserved_at_60[0x20]; 7366 }; 7367 7368 struct mlx5_ifc_alloc_flow_counter_in_bits { 7369 u8 opcode[0x10]; 7370 u8 reserved_at_10[0x10]; 7371 7372 u8 reserved_at_20[0x10]; 7373 u8 op_mod[0x10]; 7374 7375 u8 reserved_at_40[0x40]; 7376 }; 7377 7378 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 7379 u8 status[0x8]; 7380 u8 reserved_at_8[0x18]; 7381 7382 u8 syndrome[0x20]; 7383 7384 u8 reserved_at_40[0x40]; 7385 }; 7386 7387 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 7388 u8 opcode[0x10]; 7389 u8 reserved_at_10[0x10]; 7390 7391 u8 reserved_at_20[0x10]; 7392 u8 op_mod[0x10]; 7393 7394 u8 reserved_at_40[0x20]; 7395 7396 u8 reserved_at_60[0x10]; 7397 u8 vxlan_udp_port[0x10]; 7398 }; 7399 7400 struct mlx5_ifc_set_pp_rate_limit_out_bits { 7401 u8 status[0x8]; 7402 u8 reserved_at_8[0x18]; 7403 7404 u8 syndrome[0x20]; 7405 7406 u8 reserved_at_40[0x40]; 7407 }; 7408 7409 struct mlx5_ifc_set_pp_rate_limit_in_bits { 7410 u8 opcode[0x10]; 7411 u8 reserved_at_10[0x10]; 7412 7413 u8 reserved_at_20[0x10]; 7414 u8 op_mod[0x10]; 7415 7416 u8 reserved_at_40[0x10]; 7417 u8 rate_limit_index[0x10]; 7418 7419 u8 reserved_at_60[0x20]; 7420 7421 u8 rate_limit[0x20]; 7422 7423 u8 burst_upper_bound[0x20]; 7424 7425 u8 reserved_at_c0[0x10]; 7426 u8 typical_packet_size[0x10]; 7427 7428 u8 reserved_at_e0[0x120]; 7429 }; 7430 7431 struct mlx5_ifc_access_register_out_bits { 7432 u8 status[0x8]; 7433 u8 reserved_at_8[0x18]; 7434 7435 u8 syndrome[0x20]; 7436 7437 u8 reserved_at_40[0x40]; 7438 7439 u8 register_data[0][0x20]; 7440 }; 7441 7442 enum { 7443 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 7444 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 7445 }; 7446 7447 struct mlx5_ifc_access_register_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_at_10[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x10]; 7455 u8 register_id[0x10]; 7456 7457 u8 argument[0x20]; 7458 7459 u8 register_data[0][0x20]; 7460 }; 7461 7462 struct mlx5_ifc_sltp_reg_bits { 7463 u8 status[0x4]; 7464 u8 version[0x4]; 7465 u8 local_port[0x8]; 7466 u8 pnat[0x2]; 7467 u8 reserved_at_12[0x2]; 7468 u8 lane[0x4]; 7469 u8 reserved_at_18[0x8]; 7470 7471 u8 reserved_at_20[0x20]; 7472 7473 u8 reserved_at_40[0x7]; 7474 u8 polarity[0x1]; 7475 u8 ob_tap0[0x8]; 7476 u8 ob_tap1[0x8]; 7477 u8 ob_tap2[0x8]; 7478 7479 u8 reserved_at_60[0xc]; 7480 u8 ob_preemp_mode[0x4]; 7481 u8 ob_reg[0x8]; 7482 u8 ob_bias[0x8]; 7483 7484 u8 reserved_at_80[0x20]; 7485 }; 7486 7487 struct mlx5_ifc_slrg_reg_bits { 7488 u8 status[0x4]; 7489 u8 version[0x4]; 7490 u8 local_port[0x8]; 7491 u8 pnat[0x2]; 7492 u8 reserved_at_12[0x2]; 7493 u8 lane[0x4]; 7494 u8 reserved_at_18[0x8]; 7495 7496 u8 time_to_link_up[0x10]; 7497 u8 reserved_at_30[0xc]; 7498 u8 grade_lane_speed[0x4]; 7499 7500 u8 grade_version[0x8]; 7501 u8 grade[0x18]; 7502 7503 u8 reserved_at_60[0x4]; 7504 u8 height_grade_type[0x4]; 7505 u8 height_grade[0x18]; 7506 7507 u8 height_dz[0x10]; 7508 u8 height_dv[0x10]; 7509 7510 u8 reserved_at_a0[0x10]; 7511 u8 height_sigma[0x10]; 7512 7513 u8 reserved_at_c0[0x20]; 7514 7515 u8 reserved_at_e0[0x4]; 7516 u8 phase_grade_type[0x4]; 7517 u8 phase_grade[0x18]; 7518 7519 u8 reserved_at_100[0x8]; 7520 u8 phase_eo_pos[0x8]; 7521 u8 reserved_at_110[0x8]; 7522 u8 phase_eo_neg[0x8]; 7523 7524 u8 ffe_set_tested[0x10]; 7525 u8 test_errors_per_lane[0x10]; 7526 }; 7527 7528 struct mlx5_ifc_pvlc_reg_bits { 7529 u8 reserved_at_0[0x8]; 7530 u8 local_port[0x8]; 7531 u8 reserved_at_10[0x10]; 7532 7533 u8 reserved_at_20[0x1c]; 7534 u8 vl_hw_cap[0x4]; 7535 7536 u8 reserved_at_40[0x1c]; 7537 u8 vl_admin[0x4]; 7538 7539 u8 reserved_at_60[0x1c]; 7540 u8 vl_operational[0x4]; 7541 }; 7542 7543 struct mlx5_ifc_pude_reg_bits { 7544 u8 swid[0x8]; 7545 u8 local_port[0x8]; 7546 u8 reserved_at_10[0x4]; 7547 u8 admin_status[0x4]; 7548 u8 reserved_at_18[0x4]; 7549 u8 oper_status[0x4]; 7550 7551 u8 reserved_at_20[0x60]; 7552 }; 7553 7554 struct mlx5_ifc_ptys_reg_bits { 7555 u8 reserved_at_0[0x1]; 7556 u8 an_disable_admin[0x1]; 7557 u8 an_disable_cap[0x1]; 7558 u8 reserved_at_3[0x5]; 7559 u8 local_port[0x8]; 7560 u8 reserved_at_10[0xd]; 7561 u8 proto_mask[0x3]; 7562 7563 u8 an_status[0x4]; 7564 u8 reserved_at_24[0x3c]; 7565 7566 u8 eth_proto_capability[0x20]; 7567 7568 u8 ib_link_width_capability[0x10]; 7569 u8 ib_proto_capability[0x10]; 7570 7571 u8 reserved_at_a0[0x20]; 7572 7573 u8 eth_proto_admin[0x20]; 7574 7575 u8 ib_link_width_admin[0x10]; 7576 u8 ib_proto_admin[0x10]; 7577 7578 u8 reserved_at_100[0x20]; 7579 7580 u8 eth_proto_oper[0x20]; 7581 7582 u8 ib_link_width_oper[0x10]; 7583 u8 ib_proto_oper[0x10]; 7584 7585 u8 reserved_at_160[0x1c]; 7586 u8 connector_type[0x4]; 7587 7588 u8 eth_proto_lp_advertise[0x20]; 7589 7590 u8 reserved_at_1a0[0x60]; 7591 }; 7592 7593 struct mlx5_ifc_mlcr_reg_bits { 7594 u8 reserved_at_0[0x8]; 7595 u8 local_port[0x8]; 7596 u8 reserved_at_10[0x20]; 7597 7598 u8 beacon_duration[0x10]; 7599 u8 reserved_at_40[0x10]; 7600 7601 u8 beacon_remain[0x10]; 7602 }; 7603 7604 struct mlx5_ifc_ptas_reg_bits { 7605 u8 reserved_at_0[0x20]; 7606 7607 u8 algorithm_options[0x10]; 7608 u8 reserved_at_30[0x4]; 7609 u8 repetitions_mode[0x4]; 7610 u8 num_of_repetitions[0x8]; 7611 7612 u8 grade_version[0x8]; 7613 u8 height_grade_type[0x4]; 7614 u8 phase_grade_type[0x4]; 7615 u8 height_grade_weight[0x8]; 7616 u8 phase_grade_weight[0x8]; 7617 7618 u8 gisim_measure_bits[0x10]; 7619 u8 adaptive_tap_measure_bits[0x10]; 7620 7621 u8 ber_bath_high_error_threshold[0x10]; 7622 u8 ber_bath_mid_error_threshold[0x10]; 7623 7624 u8 ber_bath_low_error_threshold[0x10]; 7625 u8 one_ratio_high_threshold[0x10]; 7626 7627 u8 one_ratio_high_mid_threshold[0x10]; 7628 u8 one_ratio_low_mid_threshold[0x10]; 7629 7630 u8 one_ratio_low_threshold[0x10]; 7631 u8 ndeo_error_threshold[0x10]; 7632 7633 u8 mixer_offset_step_size[0x10]; 7634 u8 reserved_at_110[0x8]; 7635 u8 mix90_phase_for_voltage_bath[0x8]; 7636 7637 u8 mixer_offset_start[0x10]; 7638 u8 mixer_offset_end[0x10]; 7639 7640 u8 reserved_at_140[0x15]; 7641 u8 ber_test_time[0xb]; 7642 }; 7643 7644 struct mlx5_ifc_pspa_reg_bits { 7645 u8 swid[0x8]; 7646 u8 local_port[0x8]; 7647 u8 sub_port[0x8]; 7648 u8 reserved_at_18[0x8]; 7649 7650 u8 reserved_at_20[0x20]; 7651 }; 7652 7653 struct mlx5_ifc_pqdr_reg_bits { 7654 u8 reserved_at_0[0x8]; 7655 u8 local_port[0x8]; 7656 u8 reserved_at_10[0x5]; 7657 u8 prio[0x3]; 7658 u8 reserved_at_18[0x6]; 7659 u8 mode[0x2]; 7660 7661 u8 reserved_at_20[0x20]; 7662 7663 u8 reserved_at_40[0x10]; 7664 u8 min_threshold[0x10]; 7665 7666 u8 reserved_at_60[0x10]; 7667 u8 max_threshold[0x10]; 7668 7669 u8 reserved_at_80[0x10]; 7670 u8 mark_probability_denominator[0x10]; 7671 7672 u8 reserved_at_a0[0x60]; 7673 }; 7674 7675 struct mlx5_ifc_ppsc_reg_bits { 7676 u8 reserved_at_0[0x8]; 7677 u8 local_port[0x8]; 7678 u8 reserved_at_10[0x10]; 7679 7680 u8 reserved_at_20[0x60]; 7681 7682 u8 reserved_at_80[0x1c]; 7683 u8 wrps_admin[0x4]; 7684 7685 u8 reserved_at_a0[0x1c]; 7686 u8 wrps_status[0x4]; 7687 7688 u8 reserved_at_c0[0x8]; 7689 u8 up_threshold[0x8]; 7690 u8 reserved_at_d0[0x8]; 7691 u8 down_threshold[0x8]; 7692 7693 u8 reserved_at_e0[0x20]; 7694 7695 u8 reserved_at_100[0x1c]; 7696 u8 srps_admin[0x4]; 7697 7698 u8 reserved_at_120[0x1c]; 7699 u8 srps_status[0x4]; 7700 7701 u8 reserved_at_140[0x40]; 7702 }; 7703 7704 struct mlx5_ifc_pplr_reg_bits { 7705 u8 reserved_at_0[0x8]; 7706 u8 local_port[0x8]; 7707 u8 reserved_at_10[0x10]; 7708 7709 u8 reserved_at_20[0x8]; 7710 u8 lb_cap[0x8]; 7711 u8 reserved_at_30[0x8]; 7712 u8 lb_en[0x8]; 7713 }; 7714 7715 struct mlx5_ifc_pplm_reg_bits { 7716 u8 reserved_at_0[0x8]; 7717 u8 local_port[0x8]; 7718 u8 reserved_at_10[0x10]; 7719 7720 u8 reserved_at_20[0x20]; 7721 7722 u8 port_profile_mode[0x8]; 7723 u8 static_port_profile[0x8]; 7724 u8 active_port_profile[0x8]; 7725 u8 reserved_at_58[0x8]; 7726 7727 u8 retransmission_active[0x8]; 7728 u8 fec_mode_active[0x18]; 7729 7730 u8 reserved_at_80[0x20]; 7731 }; 7732 7733 struct mlx5_ifc_ppcnt_reg_bits { 7734 u8 swid[0x8]; 7735 u8 local_port[0x8]; 7736 u8 pnat[0x2]; 7737 u8 reserved_at_12[0x8]; 7738 u8 grp[0x6]; 7739 7740 u8 clr[0x1]; 7741 u8 reserved_at_21[0x1c]; 7742 u8 prio_tc[0x3]; 7743 7744 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 7745 }; 7746 7747 struct mlx5_ifc_mpcnt_reg_bits { 7748 u8 reserved_at_0[0x8]; 7749 u8 pcie_index[0x8]; 7750 u8 reserved_at_10[0xa]; 7751 u8 grp[0x6]; 7752 7753 u8 clr[0x1]; 7754 u8 reserved_at_21[0x1f]; 7755 7756 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 7757 }; 7758 7759 struct mlx5_ifc_ppad_reg_bits { 7760 u8 reserved_at_0[0x3]; 7761 u8 single_mac[0x1]; 7762 u8 reserved_at_4[0x4]; 7763 u8 local_port[0x8]; 7764 u8 mac_47_32[0x10]; 7765 7766 u8 mac_31_0[0x20]; 7767 7768 u8 reserved_at_40[0x40]; 7769 }; 7770 7771 struct mlx5_ifc_pmtu_reg_bits { 7772 u8 reserved_at_0[0x8]; 7773 u8 local_port[0x8]; 7774 u8 reserved_at_10[0x10]; 7775 7776 u8 max_mtu[0x10]; 7777 u8 reserved_at_30[0x10]; 7778 7779 u8 admin_mtu[0x10]; 7780 u8 reserved_at_50[0x10]; 7781 7782 u8 oper_mtu[0x10]; 7783 u8 reserved_at_70[0x10]; 7784 }; 7785 7786 struct mlx5_ifc_pmpr_reg_bits { 7787 u8 reserved_at_0[0x8]; 7788 u8 module[0x8]; 7789 u8 reserved_at_10[0x10]; 7790 7791 u8 reserved_at_20[0x18]; 7792 u8 attenuation_5g[0x8]; 7793 7794 u8 reserved_at_40[0x18]; 7795 u8 attenuation_7g[0x8]; 7796 7797 u8 reserved_at_60[0x18]; 7798 u8 attenuation_12g[0x8]; 7799 }; 7800 7801 struct mlx5_ifc_pmpe_reg_bits { 7802 u8 reserved_at_0[0x8]; 7803 u8 module[0x8]; 7804 u8 reserved_at_10[0xc]; 7805 u8 module_status[0x4]; 7806 7807 u8 reserved_at_20[0x60]; 7808 }; 7809 7810 struct mlx5_ifc_pmpc_reg_bits { 7811 u8 module_state_updated[32][0x8]; 7812 }; 7813 7814 struct mlx5_ifc_pmlpn_reg_bits { 7815 u8 reserved_at_0[0x4]; 7816 u8 mlpn_status[0x4]; 7817 u8 local_port[0x8]; 7818 u8 reserved_at_10[0x10]; 7819 7820 u8 e[0x1]; 7821 u8 reserved_at_21[0x1f]; 7822 }; 7823 7824 struct mlx5_ifc_pmlp_reg_bits { 7825 u8 rxtx[0x1]; 7826 u8 reserved_at_1[0x7]; 7827 u8 local_port[0x8]; 7828 u8 reserved_at_10[0x8]; 7829 u8 width[0x8]; 7830 7831 u8 lane0_module_mapping[0x20]; 7832 7833 u8 lane1_module_mapping[0x20]; 7834 7835 u8 lane2_module_mapping[0x20]; 7836 7837 u8 lane3_module_mapping[0x20]; 7838 7839 u8 reserved_at_a0[0x160]; 7840 }; 7841 7842 struct mlx5_ifc_pmaos_reg_bits { 7843 u8 reserved_at_0[0x8]; 7844 u8 module[0x8]; 7845 u8 reserved_at_10[0x4]; 7846 u8 admin_status[0x4]; 7847 u8 reserved_at_18[0x4]; 7848 u8 oper_status[0x4]; 7849 7850 u8 ase[0x1]; 7851 u8 ee[0x1]; 7852 u8 reserved_at_22[0x1c]; 7853 u8 e[0x2]; 7854 7855 u8 reserved_at_40[0x40]; 7856 }; 7857 7858 struct mlx5_ifc_plpc_reg_bits { 7859 u8 reserved_at_0[0x4]; 7860 u8 profile_id[0xc]; 7861 u8 reserved_at_10[0x4]; 7862 u8 proto_mask[0x4]; 7863 u8 reserved_at_18[0x8]; 7864 7865 u8 reserved_at_20[0x10]; 7866 u8 lane_speed[0x10]; 7867 7868 u8 reserved_at_40[0x17]; 7869 u8 lpbf[0x1]; 7870 u8 fec_mode_policy[0x8]; 7871 7872 u8 retransmission_capability[0x8]; 7873 u8 fec_mode_capability[0x18]; 7874 7875 u8 retransmission_support_admin[0x8]; 7876 u8 fec_mode_support_admin[0x18]; 7877 7878 u8 retransmission_request_admin[0x8]; 7879 u8 fec_mode_request_admin[0x18]; 7880 7881 u8 reserved_at_c0[0x80]; 7882 }; 7883 7884 struct mlx5_ifc_plib_reg_bits { 7885 u8 reserved_at_0[0x8]; 7886 u8 local_port[0x8]; 7887 u8 reserved_at_10[0x8]; 7888 u8 ib_port[0x8]; 7889 7890 u8 reserved_at_20[0x60]; 7891 }; 7892 7893 struct mlx5_ifc_plbf_reg_bits { 7894 u8 reserved_at_0[0x8]; 7895 u8 local_port[0x8]; 7896 u8 reserved_at_10[0xd]; 7897 u8 lbf_mode[0x3]; 7898 7899 u8 reserved_at_20[0x20]; 7900 }; 7901 7902 struct mlx5_ifc_pipg_reg_bits { 7903 u8 reserved_at_0[0x8]; 7904 u8 local_port[0x8]; 7905 u8 reserved_at_10[0x10]; 7906 7907 u8 dic[0x1]; 7908 u8 reserved_at_21[0x19]; 7909 u8 ipg[0x4]; 7910 u8 reserved_at_3e[0x2]; 7911 }; 7912 7913 struct mlx5_ifc_pifr_reg_bits { 7914 u8 reserved_at_0[0x8]; 7915 u8 local_port[0x8]; 7916 u8 reserved_at_10[0x10]; 7917 7918 u8 reserved_at_20[0xe0]; 7919 7920 u8 port_filter[8][0x20]; 7921 7922 u8 port_filter_update_en[8][0x20]; 7923 }; 7924 7925 struct mlx5_ifc_pfcc_reg_bits { 7926 u8 reserved_at_0[0x8]; 7927 u8 local_port[0x8]; 7928 u8 reserved_at_10[0xb]; 7929 u8 ppan_mask_n[0x1]; 7930 u8 minor_stall_mask[0x1]; 7931 u8 critical_stall_mask[0x1]; 7932 u8 reserved_at_1e[0x2]; 7933 7934 u8 ppan[0x4]; 7935 u8 reserved_at_24[0x4]; 7936 u8 prio_mask_tx[0x8]; 7937 u8 reserved_at_30[0x8]; 7938 u8 prio_mask_rx[0x8]; 7939 7940 u8 pptx[0x1]; 7941 u8 aptx[0x1]; 7942 u8 pptx_mask_n[0x1]; 7943 u8 reserved_at_43[0x5]; 7944 u8 pfctx[0x8]; 7945 u8 reserved_at_50[0x10]; 7946 7947 u8 pprx[0x1]; 7948 u8 aprx[0x1]; 7949 u8 pprx_mask_n[0x1]; 7950 u8 reserved_at_63[0x5]; 7951 u8 pfcrx[0x8]; 7952 u8 reserved_at_70[0x10]; 7953 7954 u8 device_stall_minor_watermark[0x10]; 7955 u8 device_stall_critical_watermark[0x10]; 7956 7957 u8 reserved_at_a0[0x60]; 7958 }; 7959 7960 struct mlx5_ifc_pelc_reg_bits { 7961 u8 op[0x4]; 7962 u8 reserved_at_4[0x4]; 7963 u8 local_port[0x8]; 7964 u8 reserved_at_10[0x10]; 7965 7966 u8 op_admin[0x8]; 7967 u8 op_capability[0x8]; 7968 u8 op_request[0x8]; 7969 u8 op_active[0x8]; 7970 7971 u8 admin[0x40]; 7972 7973 u8 capability[0x40]; 7974 7975 u8 request[0x40]; 7976 7977 u8 active[0x40]; 7978 7979 u8 reserved_at_140[0x80]; 7980 }; 7981 7982 struct mlx5_ifc_peir_reg_bits { 7983 u8 reserved_at_0[0x8]; 7984 u8 local_port[0x8]; 7985 u8 reserved_at_10[0x10]; 7986 7987 u8 reserved_at_20[0xc]; 7988 u8 error_count[0x4]; 7989 u8 reserved_at_30[0x10]; 7990 7991 u8 reserved_at_40[0xc]; 7992 u8 lane[0x4]; 7993 u8 reserved_at_50[0x8]; 7994 u8 error_type[0x8]; 7995 }; 7996 7997 struct mlx5_ifc_pcam_enhanced_features_bits { 7998 u8 reserved_at_0[0x76]; 7999 8000 u8 pfcc_mask[0x1]; 8001 u8 reserved_at_77[0x4]; 8002 u8 rx_buffer_fullness_counters[0x1]; 8003 u8 ptys_connector_type[0x1]; 8004 u8 reserved_at_7d[0x1]; 8005 u8 ppcnt_discard_group[0x1]; 8006 u8 ppcnt_statistical_group[0x1]; 8007 }; 8008 8009 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 8010 u8 port_access_reg_cap_mask_127_to_96[0x20]; 8011 u8 port_access_reg_cap_mask_95_to_64[0x20]; 8012 u8 port_access_reg_cap_mask_63_to_32[0x20]; 8013 8014 u8 port_access_reg_cap_mask_31_to_13[0x13]; 8015 u8 pbmc[0x1]; 8016 u8 pptb[0x1]; 8017 u8 port_access_reg_cap_mask_10_to_0[0xb]; 8018 }; 8019 8020 struct mlx5_ifc_pcam_reg_bits { 8021 u8 reserved_at_0[0x8]; 8022 u8 feature_group[0x8]; 8023 u8 reserved_at_10[0x8]; 8024 u8 access_reg_group[0x8]; 8025 8026 u8 reserved_at_20[0x20]; 8027 8028 union { 8029 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 8030 u8 reserved_at_0[0x80]; 8031 } port_access_reg_cap_mask; 8032 8033 u8 reserved_at_c0[0x80]; 8034 8035 union { 8036 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 8037 u8 reserved_at_0[0x80]; 8038 } feature_cap_mask; 8039 8040 u8 reserved_at_1c0[0xc0]; 8041 }; 8042 8043 struct mlx5_ifc_mcam_enhanced_features_bits { 8044 u8 reserved_at_0[0x7b]; 8045 u8 pcie_outbound_stalled[0x1]; 8046 u8 tx_overflow_buffer_pkt[0x1]; 8047 u8 mtpps_enh_out_per_adj[0x1]; 8048 u8 mtpps_fs[0x1]; 8049 u8 pcie_performance_group[0x1]; 8050 }; 8051 8052 struct mlx5_ifc_mcam_access_reg_bits { 8053 u8 reserved_at_0[0x1c]; 8054 u8 mcda[0x1]; 8055 u8 mcc[0x1]; 8056 u8 mcqi[0x1]; 8057 u8 reserved_at_1f[0x1]; 8058 8059 u8 regs_95_to_64[0x20]; 8060 u8 regs_63_to_32[0x20]; 8061 u8 regs_31_to_0[0x20]; 8062 }; 8063 8064 struct mlx5_ifc_mcam_reg_bits { 8065 u8 reserved_at_0[0x8]; 8066 u8 feature_group[0x8]; 8067 u8 reserved_at_10[0x8]; 8068 u8 access_reg_group[0x8]; 8069 8070 u8 reserved_at_20[0x20]; 8071 8072 union { 8073 struct mlx5_ifc_mcam_access_reg_bits access_regs; 8074 u8 reserved_at_0[0x80]; 8075 } mng_access_reg_cap_mask; 8076 8077 u8 reserved_at_c0[0x80]; 8078 8079 union { 8080 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 8081 u8 reserved_at_0[0x80]; 8082 } mng_feature_cap_mask; 8083 8084 u8 reserved_at_1c0[0x80]; 8085 }; 8086 8087 struct mlx5_ifc_qcam_access_reg_cap_mask { 8088 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 8089 u8 qpdpm[0x1]; 8090 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 8091 u8 qdpm[0x1]; 8092 u8 qpts[0x1]; 8093 u8 qcap[0x1]; 8094 u8 qcam_access_reg_cap_mask_0[0x1]; 8095 }; 8096 8097 struct mlx5_ifc_qcam_qos_feature_cap_mask { 8098 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 8099 u8 qpts_trust_both[0x1]; 8100 }; 8101 8102 struct mlx5_ifc_qcam_reg_bits { 8103 u8 reserved_at_0[0x8]; 8104 u8 feature_group[0x8]; 8105 u8 reserved_at_10[0x8]; 8106 u8 access_reg_group[0x8]; 8107 u8 reserved_at_20[0x20]; 8108 8109 union { 8110 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 8111 u8 reserved_at_0[0x80]; 8112 } qos_access_reg_cap_mask; 8113 8114 u8 reserved_at_c0[0x80]; 8115 8116 union { 8117 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 8118 u8 reserved_at_0[0x80]; 8119 } qos_feature_cap_mask; 8120 8121 u8 reserved_at_1c0[0x80]; 8122 }; 8123 8124 struct mlx5_ifc_pcap_reg_bits { 8125 u8 reserved_at_0[0x8]; 8126 u8 local_port[0x8]; 8127 u8 reserved_at_10[0x10]; 8128 8129 u8 port_capability_mask[4][0x20]; 8130 }; 8131 8132 struct mlx5_ifc_paos_reg_bits { 8133 u8 swid[0x8]; 8134 u8 local_port[0x8]; 8135 u8 reserved_at_10[0x4]; 8136 u8 admin_status[0x4]; 8137 u8 reserved_at_18[0x4]; 8138 u8 oper_status[0x4]; 8139 8140 u8 ase[0x1]; 8141 u8 ee[0x1]; 8142 u8 reserved_at_22[0x1c]; 8143 u8 e[0x2]; 8144 8145 u8 reserved_at_40[0x40]; 8146 }; 8147 8148 struct mlx5_ifc_pamp_reg_bits { 8149 u8 reserved_at_0[0x8]; 8150 u8 opamp_group[0x8]; 8151 u8 reserved_at_10[0xc]; 8152 u8 opamp_group_type[0x4]; 8153 8154 u8 start_index[0x10]; 8155 u8 reserved_at_30[0x4]; 8156 u8 num_of_indices[0xc]; 8157 8158 u8 index_data[18][0x10]; 8159 }; 8160 8161 struct mlx5_ifc_pcmr_reg_bits { 8162 u8 reserved_at_0[0x8]; 8163 u8 local_port[0x8]; 8164 u8 reserved_at_10[0x2e]; 8165 u8 fcs_cap[0x1]; 8166 u8 reserved_at_3f[0x1f]; 8167 u8 fcs_chk[0x1]; 8168 u8 reserved_at_5f[0x1]; 8169 }; 8170 8171 struct mlx5_ifc_lane_2_module_mapping_bits { 8172 u8 reserved_at_0[0x6]; 8173 u8 rx_lane[0x2]; 8174 u8 reserved_at_8[0x6]; 8175 u8 tx_lane[0x2]; 8176 u8 reserved_at_10[0x8]; 8177 u8 module[0x8]; 8178 }; 8179 8180 struct mlx5_ifc_bufferx_reg_bits { 8181 u8 reserved_at_0[0x6]; 8182 u8 lossy[0x1]; 8183 u8 epsb[0x1]; 8184 u8 reserved_at_8[0xc]; 8185 u8 size[0xc]; 8186 8187 u8 xoff_threshold[0x10]; 8188 u8 xon_threshold[0x10]; 8189 }; 8190 8191 struct mlx5_ifc_set_node_in_bits { 8192 u8 node_description[64][0x8]; 8193 }; 8194 8195 struct mlx5_ifc_register_power_settings_bits { 8196 u8 reserved_at_0[0x18]; 8197 u8 power_settings_level[0x8]; 8198 8199 u8 reserved_at_20[0x60]; 8200 }; 8201 8202 struct mlx5_ifc_register_host_endianness_bits { 8203 u8 he[0x1]; 8204 u8 reserved_at_1[0x1f]; 8205 8206 u8 reserved_at_20[0x60]; 8207 }; 8208 8209 struct mlx5_ifc_umr_pointer_desc_argument_bits { 8210 u8 reserved_at_0[0x20]; 8211 8212 u8 mkey[0x20]; 8213 8214 u8 addressh_63_32[0x20]; 8215 8216 u8 addressl_31_0[0x20]; 8217 }; 8218 8219 struct mlx5_ifc_ud_adrs_vector_bits { 8220 u8 dc_key[0x40]; 8221 8222 u8 ext[0x1]; 8223 u8 reserved_at_41[0x7]; 8224 u8 destination_qp_dct[0x18]; 8225 8226 u8 static_rate[0x4]; 8227 u8 sl_eth_prio[0x4]; 8228 u8 fl[0x1]; 8229 u8 mlid[0x7]; 8230 u8 rlid_udp_sport[0x10]; 8231 8232 u8 reserved_at_80[0x20]; 8233 8234 u8 rmac_47_16[0x20]; 8235 8236 u8 rmac_15_0[0x10]; 8237 u8 tclass[0x8]; 8238 u8 hop_limit[0x8]; 8239 8240 u8 reserved_at_e0[0x1]; 8241 u8 grh[0x1]; 8242 u8 reserved_at_e2[0x2]; 8243 u8 src_addr_index[0x8]; 8244 u8 flow_label[0x14]; 8245 8246 u8 rgid_rip[16][0x8]; 8247 }; 8248 8249 struct mlx5_ifc_pages_req_event_bits { 8250 u8 reserved_at_0[0x10]; 8251 u8 function_id[0x10]; 8252 8253 u8 num_pages[0x20]; 8254 8255 u8 reserved_at_40[0xa0]; 8256 }; 8257 8258 struct mlx5_ifc_eqe_bits { 8259 u8 reserved_at_0[0x8]; 8260 u8 event_type[0x8]; 8261 u8 reserved_at_10[0x8]; 8262 u8 event_sub_type[0x8]; 8263 8264 u8 reserved_at_20[0xe0]; 8265 8266 union mlx5_ifc_event_auto_bits event_data; 8267 8268 u8 reserved_at_1e0[0x10]; 8269 u8 signature[0x8]; 8270 u8 reserved_at_1f8[0x7]; 8271 u8 owner[0x1]; 8272 }; 8273 8274 enum { 8275 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 8276 }; 8277 8278 struct mlx5_ifc_cmd_queue_entry_bits { 8279 u8 type[0x8]; 8280 u8 reserved_at_8[0x18]; 8281 8282 u8 input_length[0x20]; 8283 8284 u8 input_mailbox_pointer_63_32[0x20]; 8285 8286 u8 input_mailbox_pointer_31_9[0x17]; 8287 u8 reserved_at_77[0x9]; 8288 8289 u8 command_input_inline_data[16][0x8]; 8290 8291 u8 command_output_inline_data[16][0x8]; 8292 8293 u8 output_mailbox_pointer_63_32[0x20]; 8294 8295 u8 output_mailbox_pointer_31_9[0x17]; 8296 u8 reserved_at_1b7[0x9]; 8297 8298 u8 output_length[0x20]; 8299 8300 u8 token[0x8]; 8301 u8 signature[0x8]; 8302 u8 reserved_at_1f0[0x8]; 8303 u8 status[0x7]; 8304 u8 ownership[0x1]; 8305 }; 8306 8307 struct mlx5_ifc_cmd_out_bits { 8308 u8 status[0x8]; 8309 u8 reserved_at_8[0x18]; 8310 8311 u8 syndrome[0x20]; 8312 8313 u8 command_output[0x20]; 8314 }; 8315 8316 struct mlx5_ifc_cmd_in_bits { 8317 u8 opcode[0x10]; 8318 u8 reserved_at_10[0x10]; 8319 8320 u8 reserved_at_20[0x10]; 8321 u8 op_mod[0x10]; 8322 8323 u8 command[0][0x20]; 8324 }; 8325 8326 struct mlx5_ifc_cmd_if_box_bits { 8327 u8 mailbox_data[512][0x8]; 8328 8329 u8 reserved_at_1000[0x180]; 8330 8331 u8 next_pointer_63_32[0x20]; 8332 8333 u8 next_pointer_31_10[0x16]; 8334 u8 reserved_at_11b6[0xa]; 8335 8336 u8 block_number[0x20]; 8337 8338 u8 reserved_at_11e0[0x8]; 8339 u8 token[0x8]; 8340 u8 ctrl_signature[0x8]; 8341 u8 signature[0x8]; 8342 }; 8343 8344 struct mlx5_ifc_mtt_bits { 8345 u8 ptag_63_32[0x20]; 8346 8347 u8 ptag_31_8[0x18]; 8348 u8 reserved_at_38[0x6]; 8349 u8 wr_en[0x1]; 8350 u8 rd_en[0x1]; 8351 }; 8352 8353 struct mlx5_ifc_query_wol_rol_out_bits { 8354 u8 status[0x8]; 8355 u8 reserved_at_8[0x18]; 8356 8357 u8 syndrome[0x20]; 8358 8359 u8 reserved_at_40[0x10]; 8360 u8 rol_mode[0x8]; 8361 u8 wol_mode[0x8]; 8362 8363 u8 reserved_at_60[0x20]; 8364 }; 8365 8366 struct mlx5_ifc_query_wol_rol_in_bits { 8367 u8 opcode[0x10]; 8368 u8 reserved_at_10[0x10]; 8369 8370 u8 reserved_at_20[0x10]; 8371 u8 op_mod[0x10]; 8372 8373 u8 reserved_at_40[0x40]; 8374 }; 8375 8376 struct mlx5_ifc_set_wol_rol_out_bits { 8377 u8 status[0x8]; 8378 u8 reserved_at_8[0x18]; 8379 8380 u8 syndrome[0x20]; 8381 8382 u8 reserved_at_40[0x40]; 8383 }; 8384 8385 struct mlx5_ifc_set_wol_rol_in_bits { 8386 u8 opcode[0x10]; 8387 u8 reserved_at_10[0x10]; 8388 8389 u8 reserved_at_20[0x10]; 8390 u8 op_mod[0x10]; 8391 8392 u8 rol_mode_valid[0x1]; 8393 u8 wol_mode_valid[0x1]; 8394 u8 reserved_at_42[0xe]; 8395 u8 rol_mode[0x8]; 8396 u8 wol_mode[0x8]; 8397 8398 u8 reserved_at_60[0x20]; 8399 }; 8400 8401 enum { 8402 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 8403 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 8404 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 8405 }; 8406 8407 enum { 8408 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 8409 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 8410 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 8411 }; 8412 8413 enum { 8414 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 8415 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 8416 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 8417 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 8418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 8419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 8420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 8421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 8422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 8423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 8424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 8425 }; 8426 8427 struct mlx5_ifc_initial_seg_bits { 8428 u8 fw_rev_minor[0x10]; 8429 u8 fw_rev_major[0x10]; 8430 8431 u8 cmd_interface_rev[0x10]; 8432 u8 fw_rev_subminor[0x10]; 8433 8434 u8 reserved_at_40[0x40]; 8435 8436 u8 cmdq_phy_addr_63_32[0x20]; 8437 8438 u8 cmdq_phy_addr_31_12[0x14]; 8439 u8 reserved_at_b4[0x2]; 8440 u8 nic_interface[0x2]; 8441 u8 log_cmdq_size[0x4]; 8442 u8 log_cmdq_stride[0x4]; 8443 8444 u8 command_doorbell_vector[0x20]; 8445 8446 u8 reserved_at_e0[0xf00]; 8447 8448 u8 initializing[0x1]; 8449 u8 reserved_at_fe1[0x4]; 8450 u8 nic_interface_supported[0x3]; 8451 u8 reserved_at_fe8[0x18]; 8452 8453 struct mlx5_ifc_health_buffer_bits health_buffer; 8454 8455 u8 no_dram_nic_offset[0x20]; 8456 8457 u8 reserved_at_1220[0x6e40]; 8458 8459 u8 reserved_at_8060[0x1f]; 8460 u8 clear_int[0x1]; 8461 8462 u8 health_syndrome[0x8]; 8463 u8 health_counter[0x18]; 8464 8465 u8 reserved_at_80a0[0x17fc0]; 8466 }; 8467 8468 struct mlx5_ifc_mtpps_reg_bits { 8469 u8 reserved_at_0[0xc]; 8470 u8 cap_number_of_pps_pins[0x4]; 8471 u8 reserved_at_10[0x4]; 8472 u8 cap_max_num_of_pps_in_pins[0x4]; 8473 u8 reserved_at_18[0x4]; 8474 u8 cap_max_num_of_pps_out_pins[0x4]; 8475 8476 u8 reserved_at_20[0x24]; 8477 u8 cap_pin_3_mode[0x4]; 8478 u8 reserved_at_48[0x4]; 8479 u8 cap_pin_2_mode[0x4]; 8480 u8 reserved_at_50[0x4]; 8481 u8 cap_pin_1_mode[0x4]; 8482 u8 reserved_at_58[0x4]; 8483 u8 cap_pin_0_mode[0x4]; 8484 8485 u8 reserved_at_60[0x4]; 8486 u8 cap_pin_7_mode[0x4]; 8487 u8 reserved_at_68[0x4]; 8488 u8 cap_pin_6_mode[0x4]; 8489 u8 reserved_at_70[0x4]; 8490 u8 cap_pin_5_mode[0x4]; 8491 u8 reserved_at_78[0x4]; 8492 u8 cap_pin_4_mode[0x4]; 8493 8494 u8 field_select[0x20]; 8495 u8 reserved_at_a0[0x60]; 8496 8497 u8 enable[0x1]; 8498 u8 reserved_at_101[0xb]; 8499 u8 pattern[0x4]; 8500 u8 reserved_at_110[0x4]; 8501 u8 pin_mode[0x4]; 8502 u8 pin[0x8]; 8503 8504 u8 reserved_at_120[0x20]; 8505 8506 u8 time_stamp[0x40]; 8507 8508 u8 out_pulse_duration[0x10]; 8509 u8 out_periodic_adjustment[0x10]; 8510 u8 enhanced_out_periodic_adjustment[0x20]; 8511 8512 u8 reserved_at_1c0[0x20]; 8513 }; 8514 8515 struct mlx5_ifc_mtppse_reg_bits { 8516 u8 reserved_at_0[0x18]; 8517 u8 pin[0x8]; 8518 u8 event_arm[0x1]; 8519 u8 reserved_at_21[0x1b]; 8520 u8 event_generation_mode[0x4]; 8521 u8 reserved_at_40[0x40]; 8522 }; 8523 8524 struct mlx5_ifc_mcqi_cap_bits { 8525 u8 supported_info_bitmask[0x20]; 8526 8527 u8 component_size[0x20]; 8528 8529 u8 max_component_size[0x20]; 8530 8531 u8 log_mcda_word_size[0x4]; 8532 u8 reserved_at_64[0xc]; 8533 u8 mcda_max_write_size[0x10]; 8534 8535 u8 rd_en[0x1]; 8536 u8 reserved_at_81[0x1]; 8537 u8 match_chip_id[0x1]; 8538 u8 match_psid[0x1]; 8539 u8 check_user_timestamp[0x1]; 8540 u8 match_base_guid_mac[0x1]; 8541 u8 reserved_at_86[0x1a]; 8542 }; 8543 8544 struct mlx5_ifc_mcqi_reg_bits { 8545 u8 read_pending_component[0x1]; 8546 u8 reserved_at_1[0xf]; 8547 u8 component_index[0x10]; 8548 8549 u8 reserved_at_20[0x20]; 8550 8551 u8 reserved_at_40[0x1b]; 8552 u8 info_type[0x5]; 8553 8554 u8 info_size[0x20]; 8555 8556 u8 offset[0x20]; 8557 8558 u8 reserved_at_a0[0x10]; 8559 u8 data_size[0x10]; 8560 8561 u8 data[0][0x20]; 8562 }; 8563 8564 struct mlx5_ifc_mcc_reg_bits { 8565 u8 reserved_at_0[0x4]; 8566 u8 time_elapsed_since_last_cmd[0xc]; 8567 u8 reserved_at_10[0x8]; 8568 u8 instruction[0x8]; 8569 8570 u8 reserved_at_20[0x10]; 8571 u8 component_index[0x10]; 8572 8573 u8 reserved_at_40[0x8]; 8574 u8 update_handle[0x18]; 8575 8576 u8 handle_owner_type[0x4]; 8577 u8 handle_owner_host_id[0x4]; 8578 u8 reserved_at_68[0x1]; 8579 u8 control_progress[0x7]; 8580 u8 error_code[0x8]; 8581 u8 reserved_at_78[0x4]; 8582 u8 control_state[0x4]; 8583 8584 u8 component_size[0x20]; 8585 8586 u8 reserved_at_a0[0x60]; 8587 }; 8588 8589 struct mlx5_ifc_mcda_reg_bits { 8590 u8 reserved_at_0[0x8]; 8591 u8 update_handle[0x18]; 8592 8593 u8 offset[0x20]; 8594 8595 u8 reserved_at_40[0x10]; 8596 u8 size[0x10]; 8597 8598 u8 reserved_at_60[0x20]; 8599 8600 u8 data[0][0x20]; 8601 }; 8602 8603 union mlx5_ifc_ports_control_registers_document_bits { 8604 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 8605 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 8606 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 8607 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 8608 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 8609 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 8610 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 8611 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; 8612 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 8613 struct mlx5_ifc_pamp_reg_bits pamp_reg; 8614 struct mlx5_ifc_paos_reg_bits paos_reg; 8615 struct mlx5_ifc_pcap_reg_bits pcap_reg; 8616 struct mlx5_ifc_peir_reg_bits peir_reg; 8617 struct mlx5_ifc_pelc_reg_bits pelc_reg; 8618 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 8619 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 8620 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 8621 struct mlx5_ifc_pifr_reg_bits pifr_reg; 8622 struct mlx5_ifc_pipg_reg_bits pipg_reg; 8623 struct mlx5_ifc_plbf_reg_bits plbf_reg; 8624 struct mlx5_ifc_plib_reg_bits plib_reg; 8625 struct mlx5_ifc_plpc_reg_bits plpc_reg; 8626 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 8627 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 8628 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 8629 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 8630 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 8631 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 8632 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 8633 struct mlx5_ifc_ppad_reg_bits ppad_reg; 8634 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 8635 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 8636 struct mlx5_ifc_pplm_reg_bits pplm_reg; 8637 struct mlx5_ifc_pplr_reg_bits pplr_reg; 8638 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 8639 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 8640 struct mlx5_ifc_pspa_reg_bits pspa_reg; 8641 struct mlx5_ifc_ptas_reg_bits ptas_reg; 8642 struct mlx5_ifc_ptys_reg_bits ptys_reg; 8643 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 8644 struct mlx5_ifc_pude_reg_bits pude_reg; 8645 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 8646 struct mlx5_ifc_slrg_reg_bits slrg_reg; 8647 struct mlx5_ifc_sltp_reg_bits sltp_reg; 8648 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 8649 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 8650 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 8651 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 8652 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 8653 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 8654 struct mlx5_ifc_mcc_reg_bits mcc_reg; 8655 struct mlx5_ifc_mcda_reg_bits mcda_reg; 8656 u8 reserved_at_0[0x60e0]; 8657 }; 8658 8659 union mlx5_ifc_debug_enhancements_document_bits { 8660 struct mlx5_ifc_health_buffer_bits health_buffer; 8661 u8 reserved_at_0[0x200]; 8662 }; 8663 8664 union mlx5_ifc_uplink_pci_interface_document_bits { 8665 struct mlx5_ifc_initial_seg_bits initial_seg; 8666 u8 reserved_at_0[0x20060]; 8667 }; 8668 8669 struct mlx5_ifc_set_flow_table_root_out_bits { 8670 u8 status[0x8]; 8671 u8 reserved_at_8[0x18]; 8672 8673 u8 syndrome[0x20]; 8674 8675 u8 reserved_at_40[0x40]; 8676 }; 8677 8678 struct mlx5_ifc_set_flow_table_root_in_bits { 8679 u8 opcode[0x10]; 8680 u8 reserved_at_10[0x10]; 8681 8682 u8 reserved_at_20[0x10]; 8683 u8 op_mod[0x10]; 8684 8685 u8 other_vport[0x1]; 8686 u8 reserved_at_41[0xf]; 8687 u8 vport_number[0x10]; 8688 8689 u8 reserved_at_60[0x20]; 8690 8691 u8 table_type[0x8]; 8692 u8 reserved_at_88[0x18]; 8693 8694 u8 reserved_at_a0[0x8]; 8695 u8 table_id[0x18]; 8696 8697 u8 reserved_at_c0[0x8]; 8698 u8 underlay_qpn[0x18]; 8699 u8 reserved_at_e0[0x120]; 8700 }; 8701 8702 enum { 8703 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 8704 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 8705 }; 8706 8707 struct mlx5_ifc_modify_flow_table_out_bits { 8708 u8 status[0x8]; 8709 u8 reserved_at_8[0x18]; 8710 8711 u8 syndrome[0x20]; 8712 8713 u8 reserved_at_40[0x40]; 8714 }; 8715 8716 struct mlx5_ifc_modify_flow_table_in_bits { 8717 u8 opcode[0x10]; 8718 u8 reserved_at_10[0x10]; 8719 8720 u8 reserved_at_20[0x10]; 8721 u8 op_mod[0x10]; 8722 8723 u8 other_vport[0x1]; 8724 u8 reserved_at_41[0xf]; 8725 u8 vport_number[0x10]; 8726 8727 u8 reserved_at_60[0x10]; 8728 u8 modify_field_select[0x10]; 8729 8730 u8 table_type[0x8]; 8731 u8 reserved_at_88[0x18]; 8732 8733 u8 reserved_at_a0[0x8]; 8734 u8 table_id[0x18]; 8735 8736 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8737 }; 8738 8739 struct mlx5_ifc_ets_tcn_config_reg_bits { 8740 u8 g[0x1]; 8741 u8 b[0x1]; 8742 u8 r[0x1]; 8743 u8 reserved_at_3[0x9]; 8744 u8 group[0x4]; 8745 u8 reserved_at_10[0x9]; 8746 u8 bw_allocation[0x7]; 8747 8748 u8 reserved_at_20[0xc]; 8749 u8 max_bw_units[0x4]; 8750 u8 reserved_at_30[0x8]; 8751 u8 max_bw_value[0x8]; 8752 }; 8753 8754 struct mlx5_ifc_ets_global_config_reg_bits { 8755 u8 reserved_at_0[0x2]; 8756 u8 r[0x1]; 8757 u8 reserved_at_3[0x1d]; 8758 8759 u8 reserved_at_20[0xc]; 8760 u8 max_bw_units[0x4]; 8761 u8 reserved_at_30[0x8]; 8762 u8 max_bw_value[0x8]; 8763 }; 8764 8765 struct mlx5_ifc_qetc_reg_bits { 8766 u8 reserved_at_0[0x8]; 8767 u8 port_number[0x8]; 8768 u8 reserved_at_10[0x30]; 8769 8770 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 8771 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 8772 }; 8773 8774 struct mlx5_ifc_qpdpm_dscp_reg_bits { 8775 u8 e[0x1]; 8776 u8 reserved_at_01[0x0b]; 8777 u8 prio[0x04]; 8778 }; 8779 8780 struct mlx5_ifc_qpdpm_reg_bits { 8781 u8 reserved_at_0[0x8]; 8782 u8 local_port[0x8]; 8783 u8 reserved_at_10[0x10]; 8784 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 8785 }; 8786 8787 struct mlx5_ifc_qpts_reg_bits { 8788 u8 reserved_at_0[0x8]; 8789 u8 local_port[0x8]; 8790 u8 reserved_at_10[0x2d]; 8791 u8 trust_state[0x3]; 8792 }; 8793 8794 struct mlx5_ifc_pptb_reg_bits { 8795 u8 reserved_at_0[0x2]; 8796 u8 mm[0x2]; 8797 u8 reserved_at_4[0x4]; 8798 u8 local_port[0x8]; 8799 u8 reserved_at_10[0x6]; 8800 u8 cm[0x1]; 8801 u8 um[0x1]; 8802 u8 pm[0x8]; 8803 8804 u8 prio_x_buff[0x20]; 8805 8806 u8 pm_msb[0x8]; 8807 u8 reserved_at_48[0x10]; 8808 u8 ctrl_buff[0x4]; 8809 u8 untagged_buff[0x4]; 8810 }; 8811 8812 struct mlx5_ifc_pbmc_reg_bits { 8813 u8 reserved_at_0[0x8]; 8814 u8 local_port[0x8]; 8815 u8 reserved_at_10[0x10]; 8816 8817 u8 xoff_timer_value[0x10]; 8818 u8 xoff_refresh[0x10]; 8819 8820 u8 reserved_at_40[0x9]; 8821 u8 fullness_threshold[0x7]; 8822 u8 port_buffer_size[0x10]; 8823 8824 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 8825 8826 u8 reserved_at_2e0[0x40]; 8827 }; 8828 8829 struct mlx5_ifc_qtct_reg_bits { 8830 u8 reserved_at_0[0x8]; 8831 u8 port_number[0x8]; 8832 u8 reserved_at_10[0xd]; 8833 u8 prio[0x3]; 8834 8835 u8 reserved_at_20[0x1d]; 8836 u8 tclass[0x3]; 8837 }; 8838 8839 struct mlx5_ifc_mcia_reg_bits { 8840 u8 l[0x1]; 8841 u8 reserved_at_1[0x7]; 8842 u8 module[0x8]; 8843 u8 reserved_at_10[0x8]; 8844 u8 status[0x8]; 8845 8846 u8 i2c_device_address[0x8]; 8847 u8 page_number[0x8]; 8848 u8 device_address[0x10]; 8849 8850 u8 reserved_at_40[0x10]; 8851 u8 size[0x10]; 8852 8853 u8 reserved_at_60[0x20]; 8854 8855 u8 dword_0[0x20]; 8856 u8 dword_1[0x20]; 8857 u8 dword_2[0x20]; 8858 u8 dword_3[0x20]; 8859 u8 dword_4[0x20]; 8860 u8 dword_5[0x20]; 8861 u8 dword_6[0x20]; 8862 u8 dword_7[0x20]; 8863 u8 dword_8[0x20]; 8864 u8 dword_9[0x20]; 8865 u8 dword_10[0x20]; 8866 u8 dword_11[0x20]; 8867 }; 8868 8869 struct mlx5_ifc_dcbx_param_bits { 8870 u8 dcbx_cee_cap[0x1]; 8871 u8 dcbx_ieee_cap[0x1]; 8872 u8 dcbx_standby_cap[0x1]; 8873 u8 reserved_at_0[0x5]; 8874 u8 port_number[0x8]; 8875 u8 reserved_at_10[0xa]; 8876 u8 max_application_table_size[6]; 8877 u8 reserved_at_20[0x15]; 8878 u8 version_oper[0x3]; 8879 u8 reserved_at_38[5]; 8880 u8 version_admin[0x3]; 8881 u8 willing_admin[0x1]; 8882 u8 reserved_at_41[0x3]; 8883 u8 pfc_cap_oper[0x4]; 8884 u8 reserved_at_48[0x4]; 8885 u8 pfc_cap_admin[0x4]; 8886 u8 reserved_at_50[0x4]; 8887 u8 num_of_tc_oper[0x4]; 8888 u8 reserved_at_58[0x4]; 8889 u8 num_of_tc_admin[0x4]; 8890 u8 remote_willing[0x1]; 8891 u8 reserved_at_61[3]; 8892 u8 remote_pfc_cap[4]; 8893 u8 reserved_at_68[0x14]; 8894 u8 remote_num_of_tc[0x4]; 8895 u8 reserved_at_80[0x18]; 8896 u8 error[0x8]; 8897 u8 reserved_at_a0[0x160]; 8898 }; 8899 8900 struct mlx5_ifc_lagc_bits { 8901 u8 reserved_at_0[0x1d]; 8902 u8 lag_state[0x3]; 8903 8904 u8 reserved_at_20[0x14]; 8905 u8 tx_remap_affinity_2[0x4]; 8906 u8 reserved_at_38[0x4]; 8907 u8 tx_remap_affinity_1[0x4]; 8908 }; 8909 8910 struct mlx5_ifc_create_lag_out_bits { 8911 u8 status[0x8]; 8912 u8 reserved_at_8[0x18]; 8913 8914 u8 syndrome[0x20]; 8915 8916 u8 reserved_at_40[0x40]; 8917 }; 8918 8919 struct mlx5_ifc_create_lag_in_bits { 8920 u8 opcode[0x10]; 8921 u8 reserved_at_10[0x10]; 8922 8923 u8 reserved_at_20[0x10]; 8924 u8 op_mod[0x10]; 8925 8926 struct mlx5_ifc_lagc_bits ctx; 8927 }; 8928 8929 struct mlx5_ifc_modify_lag_out_bits { 8930 u8 status[0x8]; 8931 u8 reserved_at_8[0x18]; 8932 8933 u8 syndrome[0x20]; 8934 8935 u8 reserved_at_40[0x40]; 8936 }; 8937 8938 struct mlx5_ifc_modify_lag_in_bits { 8939 u8 opcode[0x10]; 8940 u8 reserved_at_10[0x10]; 8941 8942 u8 reserved_at_20[0x10]; 8943 u8 op_mod[0x10]; 8944 8945 u8 reserved_at_40[0x20]; 8946 u8 field_select[0x20]; 8947 8948 struct mlx5_ifc_lagc_bits ctx; 8949 }; 8950 8951 struct mlx5_ifc_query_lag_out_bits { 8952 u8 status[0x8]; 8953 u8 reserved_at_8[0x18]; 8954 8955 u8 syndrome[0x20]; 8956 8957 u8 reserved_at_40[0x40]; 8958 8959 struct mlx5_ifc_lagc_bits ctx; 8960 }; 8961 8962 struct mlx5_ifc_query_lag_in_bits { 8963 u8 opcode[0x10]; 8964 u8 reserved_at_10[0x10]; 8965 8966 u8 reserved_at_20[0x10]; 8967 u8 op_mod[0x10]; 8968 8969 u8 reserved_at_40[0x40]; 8970 }; 8971 8972 struct mlx5_ifc_destroy_lag_out_bits { 8973 u8 status[0x8]; 8974 u8 reserved_at_8[0x18]; 8975 8976 u8 syndrome[0x20]; 8977 8978 u8 reserved_at_40[0x40]; 8979 }; 8980 8981 struct mlx5_ifc_destroy_lag_in_bits { 8982 u8 opcode[0x10]; 8983 u8 reserved_at_10[0x10]; 8984 8985 u8 reserved_at_20[0x10]; 8986 u8 op_mod[0x10]; 8987 8988 u8 reserved_at_40[0x40]; 8989 }; 8990 8991 struct mlx5_ifc_create_vport_lag_out_bits { 8992 u8 status[0x8]; 8993 u8 reserved_at_8[0x18]; 8994 8995 u8 syndrome[0x20]; 8996 8997 u8 reserved_at_40[0x40]; 8998 }; 8999 9000 struct mlx5_ifc_create_vport_lag_in_bits { 9001 u8 opcode[0x10]; 9002 u8 reserved_at_10[0x10]; 9003 9004 u8 reserved_at_20[0x10]; 9005 u8 op_mod[0x10]; 9006 9007 u8 reserved_at_40[0x40]; 9008 }; 9009 9010 struct mlx5_ifc_destroy_vport_lag_out_bits { 9011 u8 status[0x8]; 9012 u8 reserved_at_8[0x18]; 9013 9014 u8 syndrome[0x20]; 9015 9016 u8 reserved_at_40[0x40]; 9017 }; 9018 9019 struct mlx5_ifc_destroy_vport_lag_in_bits { 9020 u8 opcode[0x10]; 9021 u8 reserved_at_10[0x10]; 9022 9023 u8 reserved_at_20[0x10]; 9024 u8 op_mod[0x10]; 9025 9026 u8 reserved_at_40[0x40]; 9027 }; 9028 9029 struct mlx5_ifc_alloc_memic_in_bits { 9030 u8 opcode[0x10]; 9031 u8 reserved_at_10[0x10]; 9032 9033 u8 reserved_at_20[0x10]; 9034 u8 op_mod[0x10]; 9035 9036 u8 reserved_at_30[0x20]; 9037 9038 u8 reserved_at_40[0x18]; 9039 u8 log_memic_addr_alignment[0x8]; 9040 9041 u8 range_start_addr[0x40]; 9042 9043 u8 range_size[0x20]; 9044 9045 u8 memic_size[0x20]; 9046 }; 9047 9048 struct mlx5_ifc_alloc_memic_out_bits { 9049 u8 status[0x8]; 9050 u8 reserved_at_8[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 memic_start_addr[0x40]; 9055 }; 9056 9057 struct mlx5_ifc_dealloc_memic_in_bits { 9058 u8 opcode[0x10]; 9059 u8 reserved_at_10[0x10]; 9060 9061 u8 reserved_at_20[0x10]; 9062 u8 op_mod[0x10]; 9063 9064 u8 reserved_at_40[0x40]; 9065 9066 u8 memic_start_addr[0x40]; 9067 9068 u8 memic_size[0x20]; 9069 9070 u8 reserved_at_e0[0x20]; 9071 }; 9072 9073 struct mlx5_ifc_dealloc_memic_out_bits { 9074 u8 status[0x8]; 9075 u8 reserved_at_8[0x18]; 9076 9077 u8 syndrome[0x20]; 9078 9079 u8 reserved_at_40[0x40]; 9080 }; 9081 9082 #endif /* MLX5_IFC_H */ 9083