1 /* 2 * GXBB clock tree IDs 3 */ 4 5 #ifndef __GXBB_CLKC_H 6 #define __GXBB_CLKC_H 7 8 #define CLKID_CPUCLK 1 9 #define CLKID_HDMI_PLL 2 10 #define CLKID_FCLK_DIV2 4 11 #define CLKID_FCLK_DIV3 5 12 #define CLKID_FCLK_DIV4 6 13 #define CLKID_CLK81 12 14 #define CLKID_ETH 36 15 #define CLKID_SD_EMMC_A 94 16 #define CLKID_SD_EMMC_B 95 17 #define CLKID_SD_EMMC_C 96 18 19 #endif /* __GXBB_CLKC_H */ 20