1 /* 2 * Copyright © 2008 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #ifndef _DRM_DP_HELPER_H_ 24 #define _DRM_DP_HELPER_H_ 25 26 #include <linux/delay.h> 27 #include <linux/i2c.h> 28 29 #include <drm/display/drm_dp.h> 30 #include <drm/drm_connector.h> 31 32 struct drm_device; 33 struct drm_dp_aux; 34 struct drm_panel; 35 36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 37 int lane_count); 38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 39 int lane_count); 40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 41 int lane); 42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 43 int lane); 44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 45 int lane); 46 47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 48 enum drm_dp_phy dp_phy, bool uhbr); 49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 50 enum drm_dp_phy dp_phy, bool uhbr); 51 52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 54 void drm_dp_lttpr_link_train_clock_recovery_delay(void); 55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 59 60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux); 61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 62 int lane_count); 63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 64 int lane_count); 65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]); 67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]); 68 69 u8 drm_dp_link_rate_to_bw_code(int link_rate); 70 int drm_dp_bw_code_to_link_rate(u8 link_bw); 71 72 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy); 73 74 /** 75 * struct drm_dp_vsc_sdp - drm DP VSC SDP 76 * 77 * This structure represents a DP VSC SDP of drm 78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and 79 * [Table 2-117: VSC SDP Payload for DB16 through DB18] 80 * 81 * @sdp_type: secondary-data packet type 82 * @revision: revision number 83 * @length: number of valid data bytes 84 * @pixelformat: pixel encoding format 85 * @colorimetry: colorimetry format 86 * @bpc: bit per color 87 * @dynamic_range: dynamic range information 88 * @content_type: CTA-861-G defines content types and expected processing by a sink device 89 */ 90 struct drm_dp_vsc_sdp { 91 unsigned char sdp_type; 92 unsigned char revision; 93 unsigned char length; 94 enum dp_pixelformat pixelformat; 95 enum dp_colorimetry colorimetry; 96 int bpc; 97 enum dp_dynamic_range dynamic_range; 98 enum dp_content_type content_type; 99 }; 100 101 /** 102 * struct drm_dp_as_sdp - drm DP Adaptive Sync SDP 103 * 104 * This structure represents a DP AS SDP of drm 105 * It is based on DP 2.1 spec [Table 2-126: Adaptive-Sync SDP Header Bytes] and 106 * [Table 2-127: Adaptive-Sync SDP Payload for DB0 through DB8] 107 * 108 * @sdp_type: Secondary-data packet type 109 * @revision: Revision Number 110 * @length: Number of valid data bytes 111 * @vtotal: Minimum Vertical Vtotal 112 * @target_rr: Target Refresh 113 * @duration_incr_ms: Successive frame duration increase 114 * @duration_decr_ms: Successive frame duration decrease 115 * @target_rr_divider: Target refresh rate divider 116 * @mode: Adaptive Sync Operation Mode 117 */ 118 struct drm_dp_as_sdp { 119 unsigned char sdp_type; 120 unsigned char revision; 121 unsigned char length; 122 int vtotal; 123 int target_rr; 124 int duration_incr_ms; 125 int duration_decr_ms; 126 bool target_rr_divider; 127 enum operation_mode mode; 128 }; 129 130 void drm_dp_as_sdp_log(struct drm_printer *p, 131 const struct drm_dp_as_sdp *as_sdp); 132 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc); 133 134 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 135 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]); 136 137 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]); 138 139 static inline int 140 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 141 { 142 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); 143 } 144 145 static inline u8 146 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 147 { 148 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; 149 } 150 151 static inline bool 152 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 153 { 154 return dpcd[DP_DPCD_REV] >= 0x11 && 155 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP); 156 } 157 158 static inline bool 159 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 160 { 161 return dpcd[DP_DPCD_REV] >= 0x11 && 162 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING); 163 } 164 165 static inline bool 166 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 167 { 168 return dpcd[DP_DPCD_REV] >= 0x12 && 169 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED; 170 } 171 172 static inline bool 173 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 174 { 175 return dpcd[DP_DPCD_REV] >= 0x11 || 176 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5; 177 } 178 179 static inline bool 180 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 181 { 182 return dpcd[DP_DPCD_REV] >= 0x14 && 183 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED; 184 } 185 186 static inline u8 187 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 188 { 189 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 : 190 DP_TRAINING_PATTERN_MASK; 191 } 192 193 static inline bool 194 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 195 { 196 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT; 197 } 198 199 /* DP/eDP DSC support */ 200 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 201 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 202 bool is_edp); 203 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); 204 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], 205 u8 dsc_bpc[3]); 206 207 static inline bool 208 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 209 { 210 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & 211 DP_DSC_DECOMPRESSION_IS_SUPPORTED; 212 } 213 214 static inline u16 215 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 216 { 217 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] | 218 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] & 219 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK) << 8); 220 } 221 222 static inline u32 223 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 224 { 225 /* Max Slicewidth = Number of Pixels * 320 */ 226 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 227 DP_DSC_SLICE_WIDTH_MULTIPLIER; 228 } 229 230 /** 231 * drm_dp_dsc_sink_supports_format() - check if sink supports DSC with given output format 232 * @dsc_dpcd : DSC-capability DPCDs of the sink 233 * @output_format: output_format which is to be checked 234 * 235 * Returns true if the sink supports DSC with the given output_format, false otherwise. 236 */ 237 static inline bool 238 drm_dp_dsc_sink_supports_format(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 output_format) 239 { 240 return dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & output_format; 241 } 242 243 /* Forward Error Correction Support on DP 1.4 */ 244 static inline bool 245 drm_dp_sink_supports_fec(const u8 fec_capable) 246 { 247 return fec_capable & DP_FEC_CAPABLE; 248 } 249 250 static inline bool 251 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 252 { 253 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; 254 } 255 256 static inline bool 257 drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 258 { 259 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; 260 } 261 262 static inline bool 263 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 264 { 265 return dpcd[DP_EDP_CONFIGURATION_CAP] & 266 DP_ALTERNATE_SCRAMBLER_RESET_CAP; 267 } 268 269 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */ 270 static inline bool 271 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 272 { 273 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & 274 DP_MSA_TIMING_PAR_IGNORED; 275 } 276 277 /** 278 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support 279 * @edp_dpcd: The DPCD to check 280 * 281 * Note that currently this function will return %false for panels which support various DPCD 282 * backlight features but which require the brightness be set through PWM, and don't support setting 283 * the brightness level via the DPCD. 284 * 285 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false 286 * otherwise 287 */ 288 static inline bool 289 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 290 { 291 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP); 292 } 293 294 /** 295 * drm_dp_is_uhbr_rate - Determine if a link rate is UHBR 296 * @link_rate: link rate in 10kbits/s units 297 * 298 * Determine if the provided link rate is an UHBR rate. 299 * 300 * Returns: %True if @link_rate is an UHBR rate. 301 */ 302 static inline bool drm_dp_is_uhbr_rate(int link_rate) 303 { 304 return link_rate >= 1000000; 305 } 306 307 /* 308 * DisplayPort AUX channel 309 */ 310 311 /** 312 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction 313 * @address: address of the (first) register to access 314 * @request: contains the type of transaction (see DP_AUX_* macros) 315 * @reply: upon completion, contains the reply type of the transaction 316 * @buffer: pointer to a transmission or reception buffer 317 * @size: size of @buffer 318 */ 319 struct drm_dp_aux_msg { 320 unsigned int address; 321 u8 request; 322 u8 reply; 323 void *buffer; 324 size_t size; 325 }; 326 327 struct cec_adapter; 328 struct drm_connector; 329 struct drm_edid; 330 331 /** 332 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX 333 * @lock: mutex protecting this struct 334 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support. 335 * @connector: the connector this CEC adapter is associated with 336 * @unregister_work: unregister the CEC adapter 337 */ 338 struct drm_dp_aux_cec { 339 struct mutex lock; 340 struct cec_adapter *adap; 341 struct drm_connector *connector; 342 struct delayed_work unregister_work; 343 }; 344 345 /** 346 * struct drm_dp_aux - DisplayPort AUX channel 347 * 348 * An AUX channel can also be used to transport I2C messages to a sink. A 349 * typical application of that is to access an EDID that's present in the sink 350 * device. The @transfer() function can also be used to execute such 351 * transactions. The drm_dp_aux_register() function registers an I2C adapter 352 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call 353 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long 354 * transfers by default; if a partial response is received, the adapter will 355 * drop down to the size given by the partial response for this transaction 356 * only. 357 */ 358 struct drm_dp_aux { 359 /** 360 * @name: user-visible name of this AUX channel and the 361 * I2C-over-AUX adapter. 362 * 363 * It's also used to specify the name of the I2C adapter. If set 364 * to %NULL, dev_name() of @dev will be used. 365 */ 366 const char *name; 367 368 /** 369 * @ddc: I2C adapter that can be used for I2C-over-AUX 370 * communication 371 */ 372 struct i2c_adapter ddc; 373 374 /** 375 * @dev: pointer to struct device that is the parent for this 376 * AUX channel. 377 */ 378 struct device *dev; 379 380 /** 381 * @drm_dev: pointer to the &drm_device that owns this AUX channel. 382 * Beware, this may be %NULL before drm_dp_aux_register() has been 383 * called. 384 * 385 * It should be set to the &drm_device that will be using this AUX 386 * channel as early as possible. For many graphics drivers this should 387 * happen before drm_dp_aux_init(), however it's perfectly fine to set 388 * this field later so long as it's assigned before calling 389 * drm_dp_aux_register(). 390 */ 391 struct drm_device *drm_dev; 392 393 /** 394 * @crtc: backpointer to the crtc that is currently using this 395 * AUX channel 396 */ 397 struct drm_crtc *crtc; 398 399 /** 400 * @hw_mutex: internal mutex used for locking transfers. 401 * 402 * Note that if the underlying hardware is shared among multiple 403 * channels, the driver needs to do additional locking to 404 * prevent concurrent access. 405 */ 406 struct mutex hw_mutex; 407 408 /** 409 * @crc_work: worker that captures CRCs for each frame 410 */ 411 struct work_struct crc_work; 412 413 /** 414 * @crc_count: counter of captured frame CRCs 415 */ 416 u8 crc_count; 417 418 /** 419 * @transfer: transfers a message representing a single AUX 420 * transaction. 421 * 422 * This is a hardware-specific implementation of how 423 * transactions are executed that the drivers must provide. 424 * 425 * A pointer to a &drm_dp_aux_msg structure describing the 426 * transaction is passed into this function. Upon success, the 427 * implementation should return the number of payload bytes that 428 * were transferred, or a negative error-code on failure. 429 * 430 * Helpers will propagate these errors, with the exception of 431 * the %-EBUSY error, which causes a transaction to be retried. 432 * On a short, helpers will return %-EPROTO to make it simpler 433 * to check for failure. 434 * 435 * The @transfer() function must only modify the reply field of 436 * the &drm_dp_aux_msg structure. The retry logic and i2c 437 * helpers assume this is the case. 438 * 439 * Also note that this callback can be called no matter the 440 * state @dev is in and also no matter what state the panel is 441 * in. It's expected: 442 * 443 * - If the @dev providing the AUX bus is currently unpowered then 444 * it will power itself up for the transfer. 445 * 446 * - If we're on eDP (using a drm_panel) and the panel is not in a 447 * state where it can respond (it's not powered or it's in a 448 * low power state) then this function may return an error, but 449 * not crash. It's up to the caller of this code to make sure that 450 * the panel is powered on if getting an error back is not OK. If a 451 * drm_panel driver is initiating a DP AUX transfer it may power 452 * itself up however it wants. All other code should ensure that 453 * the pre_enable() bridge chain (which eventually calls the 454 * drm_panel prepare function) has powered the panel. 455 */ 456 ssize_t (*transfer)(struct drm_dp_aux *aux, 457 struct drm_dp_aux_msg *msg); 458 459 /** 460 * @wait_hpd_asserted: wait for HPD to be asserted 461 * 462 * This is mainly useful for eDP panels drivers to wait for an eDP 463 * panel to finish powering on. It is optional for DP AUX controllers 464 * to implement this function. It is required for DP AUX endpoints 465 * (panel drivers) to call this function after powering up but before 466 * doing AUX transfers unless the DP AUX endpoint driver knows that 467 * we're not using the AUX controller's HPD. One example of the panel 468 * driver not needing to call this is if HPD is hooked up to a GPIO 469 * that the panel driver can read directly. 470 * 471 * If a DP AUX controller does not implement this function then it 472 * may still support eDP panels that use the AUX controller's built-in 473 * HPD signal by implementing a long wait for HPD in the transfer() 474 * callback, though this is deprecated. 475 * 476 * This function will efficiently wait for the HPD signal to be 477 * asserted. The `wait_us` parameter that is passed in says that we 478 * know that the HPD signal is expected to be asserted within `wait_us` 479 * microseconds. This function could wait for longer than `wait_us` if 480 * the logic in the DP controller has a long debouncing time. The 481 * important thing is that if this function returns success that the 482 * DP controller is ready to send AUX transactions. 483 * 484 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time 485 * expired and HPD wasn't asserted. This function should not print 486 * timeout errors to the log. 487 * 488 * The semantics of this function are designed to match the 489 * readx_poll_timeout() function. That means a `wait_us` of 0 means 490 * to wait forever. Like readx_poll_timeout(), this function may sleep. 491 * 492 * NOTE: this function specifically reports the state of the HPD pin 493 * that's associated with the DP AUX channel. This is different from 494 * the HPD concept in much of the rest of DRM which is more about 495 * physical presence of a display. For eDP, for instance, a display is 496 * assumed always present even if the HPD pin is deasserted. 497 */ 498 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us); 499 500 /** 501 * @i2c_nack_count: Counts I2C NACKs, used for DP validation. 502 */ 503 unsigned i2c_nack_count; 504 /** 505 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation. 506 */ 507 unsigned i2c_defer_count; 508 /** 509 * @cec: struct containing fields used for CEC-Tunneling-over-AUX. 510 */ 511 struct drm_dp_aux_cec cec; 512 /** 513 * @is_remote: Is this AUX CH actually using sideband messaging. 514 */ 515 bool is_remote; 516 517 /** 518 * @powered_down: If true then the remote endpoint is powered down. 519 */ 520 bool powered_down; 521 }; 522 523 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset); 524 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered); 525 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 526 void *buffer, size_t size); 527 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 528 void *buffer, size_t size); 529 530 /** 531 * drm_dp_dpcd_read_data() - read a series of bytes from the DPCD 532 * @aux: DisplayPort AUX channel (SST or MST) 533 * @offset: address of the (first) register to read 534 * @buffer: buffer to store the register values 535 * @size: number of bytes in @buffer 536 * 537 * Returns zero (0) on success, or a negative error 538 * code on failure. -EIO is returned if the request was NAKed by the sink or 539 * if the retry count was exceeded. If not all bytes were transferred, this 540 * function returns -EPROTO. Errors from the underlying AUX channel transfer 541 * function, with the exception of -EBUSY (which causes the transaction to 542 * be retried), are propagated to the caller. 543 */ 544 static inline int drm_dp_dpcd_read_data(struct drm_dp_aux *aux, 545 unsigned int offset, 546 void *buffer, size_t size) 547 { 548 int ret; 549 550 ret = drm_dp_dpcd_read(aux, offset, buffer, size); 551 if (ret < 0) 552 return ret; 553 if (ret < size) 554 return -EPROTO; 555 556 return 0; 557 } 558 559 /** 560 * drm_dp_dpcd_write_data() - write a series of bytes to the DPCD 561 * @aux: DisplayPort AUX channel (SST or MST) 562 * @offset: address of the (first) register to write 563 * @buffer: buffer containing the values to write 564 * @size: number of bytes in @buffer 565 * 566 * Returns zero (0) on success, or a negative error 567 * code on failure. -EIO is returned if the request was NAKed by the sink or 568 * if the retry count was exceeded. If not all bytes were transferred, this 569 * function returns -EPROTO. Errors from the underlying AUX channel transfer 570 * function, with the exception of -EBUSY (which causes the transaction to 571 * be retried), are propagated to the caller. 572 */ 573 static inline int drm_dp_dpcd_write_data(struct drm_dp_aux *aux, 574 unsigned int offset, 575 void *buffer, size_t size) 576 { 577 int ret; 578 579 ret = drm_dp_dpcd_write(aux, offset, buffer, size); 580 if (ret < 0) 581 return ret; 582 if (ret < size) 583 return -EPROTO; 584 585 return 0; 586 } 587 588 /** 589 * drm_dp_dpcd_readb() - read a single byte from the DPCD 590 * @aux: DisplayPort AUX channel 591 * @offset: address of the register to read 592 * @valuep: location where the value of the register will be stored 593 * 594 * Returns the number of bytes transferred (1) on success, or a negative 595 * error code on failure. In most of the cases you should be using 596 * drm_dp_dpcd_read_byte() instead. 597 */ 598 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux, 599 unsigned int offset, u8 *valuep) 600 { 601 return drm_dp_dpcd_read(aux, offset, valuep, 1); 602 } 603 604 /** 605 * drm_dp_dpcd_writeb() - write a single byte to the DPCD 606 * @aux: DisplayPort AUX channel 607 * @offset: address of the register to write 608 * @value: value to write to the register 609 * 610 * Returns the number of bytes transferred (1) on success, or a negative 611 * error code on failure. In most of the cases you should be using 612 * drm_dp_dpcd_write_byte() instead. 613 */ 614 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux, 615 unsigned int offset, u8 value) 616 { 617 return drm_dp_dpcd_write(aux, offset, &value, 1); 618 } 619 620 /** 621 * drm_dp_dpcd_read_byte() - read a single byte from the DPCD 622 * @aux: DisplayPort AUX channel 623 * @offset: address of the register to read 624 * @valuep: location where the value of the register will be stored 625 * 626 * Returns zero (0) on success, or a negative error code on failure. 627 */ 628 static inline int drm_dp_dpcd_read_byte(struct drm_dp_aux *aux, 629 unsigned int offset, u8 *valuep) 630 { 631 return drm_dp_dpcd_read_data(aux, offset, valuep, 1); 632 } 633 634 /** 635 * drm_dp_dpcd_write_byte() - write a single byte to the DPCD 636 * @aux: DisplayPort AUX channel 637 * @offset: address of the register to write 638 * @value: value to write to the register 639 * 640 * Returns zero (0) on success, or a negative error code on failure. 641 */ 642 static inline int drm_dp_dpcd_write_byte(struct drm_dp_aux *aux, 643 unsigned int offset, u8 value) 644 { 645 return drm_dp_dpcd_write_data(aux, offset, &value, 1); 646 } 647 648 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 649 u8 dpcd[DP_RECEIVER_CAP_SIZE]); 650 651 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 652 u8 status[DP_LINK_STATUS_SIZE]); 653 654 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 655 enum drm_dp_phy dp_phy, 656 u8 link_status[DP_LINK_STATUS_SIZE]); 657 int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision); 658 int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision); 659 660 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 661 int vcpid, u8 start_time_slot, u8 time_slot_count); 662 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux); 663 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms); 664 665 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 666 u8 real_edid_checksum); 667 668 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 669 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 670 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]); 671 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 672 const u8 port_cap[4], u8 type); 673 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 674 const u8 port_cap[4], 675 const struct drm_edid *drm_edid); 676 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 677 const u8 port_cap[4]); 678 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 679 const u8 port_cap[4], 680 const struct drm_edid *drm_edid); 681 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 682 const u8 port_cap[4], 683 const struct drm_edid *drm_edid); 684 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 685 const u8 port_cap[4], 686 const struct drm_edid *drm_edid); 687 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 688 const u8 port_cap[4]); 689 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 690 const u8 port_cap[4]); 691 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev, 692 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 693 const u8 port_cap[4]); 694 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]); 695 void drm_dp_downstream_debug(struct seq_file *m, 696 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 697 const u8 port_cap[4], 698 const struct drm_edid *drm_edid, 699 struct drm_dp_aux *aux); 700 enum drm_mode_subconnector 701 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 702 const u8 port_cap[4]); 703 void drm_dp_set_subconnector_property(struct drm_connector *connector, 704 enum drm_connector_status status, 705 const u8 *dpcd, 706 const u8 port_cap[4]); 707 708 struct drm_dp_desc; 709 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 710 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 711 const struct drm_dp_desc *desc); 712 int drm_dp_read_sink_count(struct drm_dp_aux *aux); 713 714 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 715 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 716 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 717 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 718 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 719 enum drm_dp_phy dp_phy, 720 u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 721 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]); 722 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 723 int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable); 724 int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count); 725 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]); 726 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 727 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]); 728 void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode); 729 730 void drm_dp_remote_aux_init(struct drm_dp_aux *aux); 731 void drm_dp_aux_init(struct drm_dp_aux *aux); 732 int drm_dp_aux_register(struct drm_dp_aux *aux); 733 void drm_dp_aux_unregister(struct drm_dp_aux *aux); 734 735 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc); 736 int drm_dp_stop_crc(struct drm_dp_aux *aux); 737 738 struct drm_dp_dpcd_ident { 739 u8 oui[3]; 740 u8 device_id[6]; 741 u8 hw_rev; 742 u8 sw_major_rev; 743 u8 sw_minor_rev; 744 } __packed; 745 746 /** 747 * struct drm_dp_desc - DP branch/sink device descriptor 748 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch). 749 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks. 750 */ 751 struct drm_dp_desc { 752 struct drm_dp_dpcd_ident ident; 753 u32 quirks; 754 }; 755 756 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 757 bool is_branch); 758 759 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy); 760 761 /** 762 * enum drm_dp_quirk - Display Port sink/branch device specific quirks 763 * 764 * Display Port sink and branch devices in the wild have a variety of bugs, try 765 * to collect them here. The quirks are shared, but it's up to the drivers to 766 * implement workarounds for them. 767 */ 768 enum drm_dp_quirk { 769 /** 770 * @DP_DPCD_QUIRK_CONSTANT_N: 771 * 772 * The device requires main link attributes Mvid and Nvid to be limited 773 * to 16 bits. So will give a constant value (0x8000) for compatability. 774 */ 775 DP_DPCD_QUIRK_CONSTANT_N, 776 /** 777 * @DP_DPCD_QUIRK_NO_PSR: 778 * 779 * The device does not support PSR even if reports that it supports or 780 * driver still need to implement proper handling for such device. 781 */ 782 DP_DPCD_QUIRK_NO_PSR, 783 /** 784 * @DP_DPCD_QUIRK_NO_SINK_COUNT: 785 * 786 * The device does not set SINK_COUNT to a non-zero value. 787 * The driver should ignore SINK_COUNT during detection. Note that 788 * drm_dp_read_sink_count_cap() automatically checks for this quirk. 789 */ 790 DP_DPCD_QUIRK_NO_SINK_COUNT, 791 /** 792 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD: 793 * 794 * The device supports MST DSC despite not supporting Virtual DPCD. 795 * The DSC caps can be read from the physical aux instead. 796 */ 797 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD, 798 /** 799 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS: 800 * 801 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite 802 * the DP_MAX_LINK_RATE register reporting a lower max multiplier. 803 */ 804 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS, 805 /** 806 * @DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC: 807 * 808 * The device applies HBLANK expansion for some modes, but this 809 * requires enabling DSC. 810 */ 811 DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC, 812 }; 813 814 /** 815 * drm_dp_has_quirk() - does the DP device have a specific quirk 816 * @desc: Device descriptor filled by drm_dp_read_desc() 817 * @quirk: Quirk to query for 818 * 819 * Return true if DP device identified by @desc has @quirk. 820 */ 821 static inline bool 822 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk) 823 { 824 return desc->quirks & BIT(quirk); 825 } 826 827 /** 828 * struct drm_edp_backlight_info - Probed eDP backlight info struct 829 * @pwmgen_bit_count: The pwmgen bit count 830 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any 831 * @max: The maximum backlight level that may be set 832 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register? 833 * @aux_enable: Does the panel support the AUX enable cap? 834 * @aux_set: Does the panel support setting the brightness through AUX? 835 * 836 * This structure contains various data about an eDP backlight, which can be populated by using 837 * drm_edp_backlight_init(). 838 */ 839 struct drm_edp_backlight_info { 840 u8 pwmgen_bit_count; 841 u8 pwm_freq_pre_divider; 842 u16 max; 843 844 bool lsb_reg_used : 1; 845 bool aux_enable : 1; 846 bool aux_set : 1; 847 }; 848 849 int 850 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 851 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 852 u16 *current_level, u8 *current_mode); 853 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 854 u16 level); 855 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 856 u16 level); 857 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl); 858 859 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 860 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))) 861 862 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux); 863 864 #else 865 866 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel, 867 struct drm_dp_aux *aux) 868 { 869 return 0; 870 } 871 872 #endif 873 874 #ifdef CONFIG_DRM_DISPLAY_DP_AUX_CEC 875 void drm_dp_cec_irq(struct drm_dp_aux *aux); 876 void drm_dp_cec_register_connector(struct drm_dp_aux *aux, 877 struct drm_connector *connector); 878 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux); 879 void drm_dp_cec_attach(struct drm_dp_aux *aux, u16 source_physical_address); 880 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid); 881 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux); 882 #else 883 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux) 884 { 885 } 886 887 static inline void 888 drm_dp_cec_register_connector(struct drm_dp_aux *aux, 889 struct drm_connector *connector) 890 { 891 } 892 893 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) 894 { 895 } 896 897 static inline void drm_dp_cec_attach(struct drm_dp_aux *aux, 898 u16 source_physical_address) 899 { 900 } 901 902 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux, 903 const struct edid *edid) 904 { 905 } 906 907 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux) 908 { 909 } 910 911 #endif 912 913 /** 914 * struct drm_dp_phy_test_params - DP Phy Compliance parameters 915 * @link_rate: Requested Link rate from DPCD 0x219 916 * @num_lanes: Number of lanes requested by sing through DPCD 0x220 917 * @phy_pattern: DP Phy test pattern from DPCD 0x248 918 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B 919 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259 920 * @enhanced_frame_cap: flag for enhanced frame capability. 921 */ 922 struct drm_dp_phy_test_params { 923 int link_rate; 924 u8 num_lanes; 925 u8 phy_pattern; 926 u8 hbr2_reset[2]; 927 u8 custom80[10]; 928 bool enhanced_frame_cap; 929 }; 930 931 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 932 struct drm_dp_phy_test_params *data); 933 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 934 struct drm_dp_phy_test_params *data, u8 dp_rev); 935 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 936 const u8 port_cap[4]); 937 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd); 938 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux); 939 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 940 u8 frl_mode); 941 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 942 u8 frl_type); 943 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux); 944 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux); 945 946 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux); 947 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask); 948 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 949 struct drm_connector *connector); 950 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 951 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 952 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 953 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]); 954 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux); 955 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]); 956 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]); 957 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 958 const u8 port_cap[4], u8 color_spc); 959 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc); 960 961 #define DRM_DP_BW_OVERHEAD_MST BIT(0) 962 #define DRM_DP_BW_OVERHEAD_UHBR BIT(1) 963 #define DRM_DP_BW_OVERHEAD_SSC_REF_CLK BIT(2) 964 #define DRM_DP_BW_OVERHEAD_FEC BIT(3) 965 #define DRM_DP_BW_OVERHEAD_DSC BIT(4) 966 967 int drm_dp_bw_overhead(int lane_count, int hactive, 968 int dsc_slice_count, 969 int bpp_x16, unsigned long flags); 970 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr); 971 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes); 972 973 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, struct dp_sdp *sdp); 974 975 #endif /* _DRM_DP_HELPER_H_ */ 976