163f77a71SBrett Creeley /* SPDX-License-Identifier: GPL-2.0 */ 263f77a71SBrett Creeley /* Copyright(c) 2023 Advanced Micro Devices, Inc. */ 363f77a71SBrett Creeley 463f77a71SBrett Creeley #ifndef _CMDS_H_ 563f77a71SBrett Creeley #define _CMDS_H_ 663f77a71SBrett Creeley 763f77a71SBrett Creeley int pds_vfio_register_client_cmd(struct pds_vfio_pci_device *pds_vfio); 863f77a71SBrett Creeley void pds_vfio_unregister_client_cmd(struct pds_vfio_pci_device *pds_vfio); 9bb500dbeSBrett Creeley int pds_vfio_suspend_device_cmd(struct pds_vfio_pci_device *pds_vfio, u8 type); 10bb500dbeSBrett Creeley int pds_vfio_resume_device_cmd(struct pds_vfio_pci_device *pds_vfio, u8 type); 11bb500dbeSBrett Creeley int pds_vfio_get_lm_state_size_cmd(struct pds_vfio_pci_device *pds_vfio, u64 *size); 12bb500dbeSBrett Creeley int pds_vfio_get_lm_state_cmd(struct pds_vfio_pci_device *pds_vfio); 13bb500dbeSBrett Creeley int pds_vfio_set_lm_state_cmd(struct pds_vfio_pci_device *pds_vfio); 14bb500dbeSBrett Creeley void pds_vfio_send_host_vf_lm_status_cmd(struct pds_vfio_pci_device *pds_vfio, 15bb500dbeSBrett Creeley enum pds_lm_host_vf_status vf_status); 16*f232836aSBrett Creeley int pds_vfio_dirty_status_cmd(struct pds_vfio_pci_device *pds_vfio, 17*f232836aSBrett Creeley u64 regions_dma, u8 *max_regions, 18*f232836aSBrett Creeley u8 *num_regions); 19*f232836aSBrett Creeley int pds_vfio_dirty_enable_cmd(struct pds_vfio_pci_device *pds_vfio, 20*f232836aSBrett Creeley u64 regions_dma, u8 num_regions); 21*f232836aSBrett Creeley int pds_vfio_dirty_disable_cmd(struct pds_vfio_pci_device *pds_vfio); 22*f232836aSBrett Creeley int pds_vfio_dirty_seq_ack_cmd(struct pds_vfio_pci_device *pds_vfio, 23*f232836aSBrett Creeley u64 sgl_dma, u16 num_sge, u32 offset, 24*f232836aSBrett Creeley u32 total_len, bool read_seq); 2563f77a71SBrett Creeley #endif /* _CMDS_H_ */ 26