1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * xHCI host controller driver 5 * 6 * Copyright (C) 2008 Intel Corp. 7 * 8 * Author: Sarah Sharp 9 * Some code borrowed from the Linux EHCI driver. 10 */ 11 12 #ifndef __LINUX_XHCI_HCD_H 13 #define __LINUX_XHCI_HCD_H 14 15 #include <linux/usb.h> 16 #include <linux/timer.h> 17 #include <linux/kernel.h> 18 #include <linux/usb/hcd.h> 19 #include <linux/io-64-nonatomic-lo-hi.h> 20 21 /* Code sharing between pci-quirks and xhci hcd */ 22 #include "xhci-ext-caps.h" 23 #include "pci-quirks.h" 24 25 /* xHCI PCI Configuration Registers */ 26 #define XHCI_SBRN_OFFSET (0x60) 27 28 /* Max number of USB devices for any host controller - limit in section 6.1 */ 29 #define MAX_HC_SLOTS 256 30 /* Section 5.3.3 - MaxPorts */ 31 #define MAX_HC_PORTS 127 32 33 /* 34 * xHCI register interface. 35 * This corresponds to the eXtensible Host Controller Interface (xHCI) 36 * Revision 0.95 specification 37 */ 38 39 /** 40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers. 41 * @hc_capbase: length of the capabilities register and HC version number 42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1 43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2 44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3 45 * @hcc_params: HCCPARAMS - Capability Parameters 46 * @db_off: DBOFF - Doorbell array offset 47 * @run_regs_off: RTSOFF - Runtime register space offset 48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only 49 */ 50 struct xhci_cap_regs { 51 __le32 hc_capbase; 52 __le32 hcs_params1; 53 __le32 hcs_params2; 54 __le32 hcs_params3; 55 __le32 hcc_params; 56 __le32 db_off; 57 __le32 run_regs_off; 58 __le32 hcc_params2; /* xhci 1.1 */ 59 /* Reserved up to (CAPLENGTH - 0x1C) */ 60 }; 61 62 /* hc_capbase bitmasks */ 63 /* bits 7:0 - how long is the Capabilities register */ 64 #define HC_LENGTH(p) XHCI_HC_LENGTH(p) 65 /* bits 31:16 */ 66 #define HC_VERSION(p) (((p) >> 16) & 0xffff) 67 68 /* HCSPARAMS1 - hcs_params1 - bitmasks */ 69 /* bits 0:7, Max Device Slots */ 70 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff) 71 #define HCS_SLOTS_MASK 0xff 72 /* bits 8:18, Max Interrupters */ 73 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) 74 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ 75 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f) 76 77 /* HCSPARAMS2 - hcs_params2 - bitmasks */ 78 /* bits 0:3, frames or uframes that SW needs to queue transactions 79 * ahead of the HW to meet periodic deadlines */ 80 #define HCS_IST(p) (((p) >> 0) & 0xf) 81 /* bits 4:7, max number of Event Ring segments */ 82 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf) 83 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */ 84 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */ 85 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */ 86 #define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f)) 87 88 /* HCSPARAMS3 - hcs_params3 - bitmasks */ 89 /* bits 0:7, Max U1 to U0 latency for the roothub ports */ 90 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff) 91 /* bits 16:31, Max U2 to U0 latency for the roothub ports */ 92 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff) 93 94 /* HCCPARAMS - hcc_params - bitmasks */ 95 /* true: HC can use 64-bit address pointers */ 96 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0)) 97 /* true: HC can do bandwidth negotiation */ 98 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1)) 99 /* true: HC uses 64-byte Device Context structures 100 * FIXME 64-byte context structures aren't supported yet. 101 */ 102 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2)) 103 /* true: HC has port power switches */ 104 #define HCC_PPC(p) ((p) & (1 << 3)) 105 /* true: HC has port indicators */ 106 #define HCS_INDICATOR(p) ((p) & (1 << 4)) 107 /* true: HC has Light HC Reset Capability */ 108 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5)) 109 /* true: HC supports latency tolerance messaging */ 110 #define HCC_LTC(p) ((p) & (1 << 6)) 111 /* true: no secondary Stream ID Support */ 112 #define HCC_NSS(p) ((p) & (1 << 7)) 113 /* true: HC supports Stopped - Short Packet */ 114 #define HCC_SPC(p) ((p) & (1 << 9)) 115 /* true: HC has Contiguous Frame ID Capability */ 116 #define HCC_CFC(p) ((p) & (1 << 11)) 117 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */ 118 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1)) 119 /* Extended Capabilities pointer from PCI base - section 5.3.6 */ 120 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p) 121 122 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32) 123 124 /* db_off bitmask - bits 0:1 reserved */ 125 #define DBOFF_MASK (~0x3) 126 127 /* run_regs_off bitmask - bits 0:4 reserved */ 128 #define RTSOFF_MASK (~0x1f) 129 130 /* HCCPARAMS2 - hcc_params2 - bitmasks */ 131 /* true: HC supports U3 entry Capability */ 132 #define HCC2_U3C(p) ((p) & (1 << 0)) 133 /* true: HC supports Configure endpoint command Max exit latency too large */ 134 #define HCC2_CMC(p) ((p) & (1 << 1)) 135 /* true: HC supports Force Save context Capability */ 136 #define HCC2_FSC(p) ((p) & (1 << 2)) 137 /* true: HC supports Compliance Transition Capability */ 138 #define HCC2_CTC(p) ((p) & (1 << 3)) 139 /* true: HC support Large ESIT payload Capability > 48k */ 140 #define HCC2_LEC(p) ((p) & (1 << 4)) 141 /* true: HC support Configuration Information Capability */ 142 #define HCC2_CIC(p) ((p) & (1 << 5)) 143 /* true: HC support Extended TBC Capability, Isoc burst count > 65535 */ 144 #define HCC2_ETC(p) ((p) & (1 << 6)) 145 146 /* Number of registers per port */ 147 #define NUM_PORT_REGS 4 148 149 #define PORTSC 0 150 #define PORTPMSC 1 151 #define PORTLI 2 152 #define PORTHLPMC 3 153 154 /** 155 * struct xhci_op_regs - xHCI Host Controller Operational Registers. 156 * @command: USBCMD - xHC command register 157 * @status: USBSTS - xHC status register 158 * @page_size: This indicates the page size that the host controller 159 * supports. If bit n is set, the HC supports a page size 160 * of 2^(n+12), up to a 128MB page size. 161 * 4K is the minimum page size. 162 * @cmd_ring: CRP - 64-bit Command Ring Pointer 163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer 164 * @config_reg: CONFIG - Configure Register 165 * @port_status_base: PORTSCn - base address for Port Status and Control 166 * Each port has a Port Status and Control register, 167 * followed by a Port Power Management Status and Control 168 * register, a Port Link Info register, and a reserved 169 * register. 170 * @port_power_base: PORTPMSCn - base address for 171 * Port Power Management Status and Control 172 * @port_link_base: PORTLIn - base address for Port Link Info (current 173 * Link PM state and control) for USB 2.1 and USB 3.0 174 * devices. 175 */ 176 struct xhci_op_regs { 177 __le32 command; 178 __le32 status; 179 __le32 page_size; 180 __le32 reserved1; 181 __le32 reserved2; 182 __le32 dev_notification; 183 __le64 cmd_ring; 184 /* rsvd: offset 0x20-2F */ 185 __le32 reserved3[4]; 186 __le64 dcbaa_ptr; 187 __le32 config_reg; 188 /* rsvd: offset 0x3C-3FF */ 189 __le32 reserved4[241]; 190 /* port 1 registers, which serve as a base address for other ports */ 191 __le32 port_status_base; 192 __le32 port_power_base; 193 __le32 port_link_base; 194 __le32 reserved5; 195 /* registers for ports 2-255 */ 196 __le32 reserved6[NUM_PORT_REGS*254]; 197 }; 198 199 /* USBCMD - USB command - command bitmasks */ 200 /* start/stop HC execution - do not write unless HC is halted*/ 201 #define CMD_RUN XHCI_CMD_RUN 202 /* Reset HC - resets internal HC state machine and all registers (except 203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports. 204 * The xHCI driver must reinitialize the xHC after setting this bit. 205 */ 206 #define CMD_RESET (1 << 1) 207 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */ 208 #define CMD_EIE XHCI_CMD_EIE 209 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */ 210 #define CMD_HSEIE XHCI_CMD_HSEIE 211 /* bits 4:6 are reserved (and should be preserved on writes). */ 212 /* light reset (port status stays unchanged) - reset completed when this is 0 */ 213 #define CMD_LRESET (1 << 7) 214 /* host controller save/restore state. */ 215 #define CMD_CSS (1 << 8) 216 #define CMD_CRS (1 << 9) 217 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */ 218 #define CMD_EWE XHCI_CMD_EWE 219 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root 220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off. 221 * '0' means the xHC can power it off if all ports are in the disconnect, 222 * disabled, or powered-off state. 223 */ 224 #define CMD_PM_INDEX (1 << 11) 225 /* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */ 226 #define CMD_ETE (1 << 14) 227 /* bits 15:31 are reserved (and should be preserved on writes). */ 228 229 /* IMAN - Interrupt Management Register */ 230 #define IMAN_IE (1 << 1) 231 #define IMAN_IP (1 << 0) 232 233 /* USBSTS - USB status - status bitmasks */ 234 /* HC not running - set to 1 when run/stop bit is cleared. */ 235 #define STS_HALT XHCI_STS_HALT 236 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */ 237 #define STS_FATAL (1 << 2) 238 /* event interrupt - clear this prior to clearing any IP flags in IR set*/ 239 #define STS_EINT (1 << 3) 240 /* port change detect */ 241 #define STS_PORT (1 << 4) 242 /* bits 5:7 reserved and zeroed */ 243 /* save state status - '1' means xHC is saving state */ 244 #define STS_SAVE (1 << 8) 245 /* restore state status - '1' means xHC is restoring state */ 246 #define STS_RESTORE (1 << 9) 247 /* true: save or restore error */ 248 #define STS_SRE (1 << 10) 249 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */ 250 #define STS_CNR XHCI_STS_CNR 251 /* true: internal Host Controller Error - SW needs to reset and reinitialize */ 252 #define STS_HCE (1 << 12) 253 /* bits 13:31 reserved and should be preserved */ 254 255 /* 256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks 257 * Generate a device notification event when the HC sees a transaction with a 258 * notification type that matches a bit set in this bit field. 259 */ 260 #define DEV_NOTE_MASK (0xffff) 261 #define ENABLE_DEV_NOTE(x) (1 << (x)) 262 /* Most of the device notification types should only be used for debug. 263 * SW does need to pay attention to function wake notifications. 264 */ 265 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1) 266 267 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */ 268 /* bit 0 is the command ring cycle state */ 269 /* stop ring operation after completion of the currently executing command */ 270 #define CMD_RING_PAUSE (1 << 1) 271 /* stop ring immediately - abort the currently executing command */ 272 #define CMD_RING_ABORT (1 << 2) 273 /* true: command ring is running */ 274 #define CMD_RING_RUNNING (1 << 3) 275 /* bits 4:5 reserved and should be preserved */ 276 /* Command Ring pointer - bit mask for the lower 32 bits. */ 277 #define CMD_RING_RSVD_BITS (0x3f) 278 279 /* CONFIG - Configure Register - config_reg bitmasks */ 280 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */ 281 #define MAX_DEVS(p) ((p) & 0xff) 282 /* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */ 283 #define CONFIG_U3E (1 << 8) 284 /* bit 9: Configuration Information Enable, xhci 1.1 */ 285 #define CONFIG_CIE (1 << 9) 286 /* bits 10:31 - reserved and should be preserved */ 287 288 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */ 289 /* true: device connected */ 290 #define PORT_CONNECT (1 << 0) 291 /* true: port enabled */ 292 #define PORT_PE (1 << 1) 293 /* bit 2 reserved and zeroed */ 294 /* true: port has an over-current condition */ 295 #define PORT_OC (1 << 3) 296 /* true: port reset signaling asserted */ 297 #define PORT_RESET (1 << 4) 298 /* Port Link State - bits 5:8 299 * A read gives the current link PM state of the port, 300 * a write with Link State Write Strobe set sets the link state. 301 */ 302 #define PORT_PLS_MASK (0xf << 5) 303 #define XDEV_U0 (0x0 << 5) 304 #define XDEV_U1 (0x1 << 5) 305 #define XDEV_U2 (0x2 << 5) 306 #define XDEV_U3 (0x3 << 5) 307 #define XDEV_DISABLED (0x4 << 5) 308 #define XDEV_RXDETECT (0x5 << 5) 309 #define XDEV_INACTIVE (0x6 << 5) 310 #define XDEV_POLLING (0x7 << 5) 311 #define XDEV_RECOVERY (0x8 << 5) 312 #define XDEV_HOT_RESET (0x9 << 5) 313 #define XDEV_COMP_MODE (0xa << 5) 314 #define XDEV_TEST_MODE (0xb << 5) 315 #define XDEV_RESUME (0xf << 5) 316 317 /* true: port has power (see HCC_PPC) */ 318 #define PORT_POWER (1 << 9) 319 /* bits 10:13 indicate device speed: 320 * 0 - undefined speed - port hasn't be initialized by a reset yet 321 * 1 - full speed 322 * 2 - low speed 323 * 3 - high speed 324 * 4 - super speed 325 * 5-15 reserved 326 */ 327 #define DEV_SPEED_MASK (0xf << 10) 328 #define XDEV_FS (0x1 << 10) 329 #define XDEV_LS (0x2 << 10) 330 #define XDEV_HS (0x3 << 10) 331 #define XDEV_SS (0x4 << 10) 332 #define XDEV_SSP (0x5 << 10) 333 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10)) 334 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS) 335 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS) 336 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS) 337 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS) 338 #define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP) 339 #define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS) 340 #define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f) 341 342 /* Bits 20:23 in the Slot Context are the speed for the device */ 343 #define SLOT_SPEED_FS (XDEV_FS << 10) 344 #define SLOT_SPEED_LS (XDEV_LS << 10) 345 #define SLOT_SPEED_HS (XDEV_HS << 10) 346 #define SLOT_SPEED_SS (XDEV_SS << 10) 347 #define SLOT_SPEED_SSP (XDEV_SSP << 10) 348 /* Port Indicator Control */ 349 #define PORT_LED_OFF (0 << 14) 350 #define PORT_LED_AMBER (1 << 14) 351 #define PORT_LED_GREEN (2 << 14) 352 #define PORT_LED_MASK (3 << 14) 353 /* Port Link State Write Strobe - set this when changing link state */ 354 #define PORT_LINK_STROBE (1 << 16) 355 /* true: connect status change */ 356 #define PORT_CSC (1 << 17) 357 /* true: port enable change */ 358 #define PORT_PEC (1 << 18) 359 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port 360 * into an enabled state, and the device into the default state. A "warm" reset 361 * also resets the link, forcing the device through the link training sequence. 362 * SW can also look at the Port Reset register to see when warm reset is done. 363 */ 364 #define PORT_WRC (1 << 19) 365 /* true: over-current change */ 366 #define PORT_OCC (1 << 20) 367 /* true: reset change - 1 to 0 transition of PORT_RESET */ 368 #define PORT_RC (1 << 21) 369 /* port link status change - set on some port link state transitions: 370 * Transition Reason 371 * ------------------------------------------------------------------------------ 372 * - U3 to Resume Wakeup signaling from a device 373 * - Resume to Recovery to U0 USB 3.0 device resume 374 * - Resume to U0 USB 2.0 device resume 375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete 376 * - U3 to U0 Software resume of USB 2.0 device complete 377 * - U2 to U0 L1 resume of USB 2.1 device complete 378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device 379 * - U0 to disabled L1 entry error with USB 2.1 device 380 * - Any state to inactive Error on USB 3.0 port 381 */ 382 #define PORT_PLC (1 << 22) 383 /* port configure error change - port failed to configure its link partner */ 384 #define PORT_CEC (1 << 23) 385 /* Cold Attach Status - xHC can set this bit to report device attached during 386 * Sx state. Warm port reset should be perfomed to clear this bit and move port 387 * to connected state. 388 */ 389 #define PORT_CAS (1 << 24) 390 /* wake on connect (enable) */ 391 #define PORT_WKCONN_E (1 << 25) 392 /* wake on disconnect (enable) */ 393 #define PORT_WKDISC_E (1 << 26) 394 /* wake on over-current (enable) */ 395 #define PORT_WKOC_E (1 << 27) 396 /* bits 28:29 reserved */ 397 /* true: device is non-removable - for USB 3.0 roothub emulation */ 398 #define PORT_DEV_REMOVE (1 << 30) 399 /* Initiate a warm port reset - complete when PORT_WRC is '1' */ 400 #define PORT_WR (1 << 31) 401 402 /* We mark duplicate entries with -1 */ 403 #define DUPLICATE_ENTRY ((u8)(-1)) 404 405 /* Port Power Management Status and Control - port_power_base bitmasks */ 406 /* Inactivity timer value for transitions into U1, in microseconds. 407 * Timeout can be up to 127us. 0xFF means an infinite timeout. 408 */ 409 #define PORT_U1_TIMEOUT(p) ((p) & 0xff) 410 #define PORT_U1_TIMEOUT_MASK 0xff 411 /* Inactivity timer value for transitions into U2 */ 412 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8) 413 #define PORT_U2_TIMEOUT_MASK (0xff << 8) 414 /* Bits 24:31 for port testing */ 415 416 /* USB2 Protocol PORTSPMSC */ 417 #define PORT_L1S_MASK 7 418 #define PORT_L1S_SUCCESS 1 419 #define PORT_RWE (1 << 3) 420 #define PORT_HIRD(p) (((p) & 0xf) << 4) 421 #define PORT_HIRD_MASK (0xf << 4) 422 #define PORT_L1DS_MASK (0xff << 8) 423 #define PORT_L1DS(p) (((p) & 0xff) << 8) 424 #define PORT_HLE (1 << 16) 425 #define PORT_TEST_MODE_SHIFT 28 426 427 /* USB3 Protocol PORTLI Port Link Information */ 428 #define PORT_RX_LANES(p) (((p) >> 16) & 0xf) 429 #define PORT_TX_LANES(p) (((p) >> 20) & 0xf) 430 431 /* USB2 Protocol PORTHLPMC */ 432 #define PORT_HIRDM(p)((p) & 3) 433 #define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2) 434 #define PORT_BESLD(p)(((p) & 0xf) << 10) 435 436 /* use 512 microseconds as USB2 LPM L1 default timeout. */ 437 #define XHCI_L1_TIMEOUT 512 438 439 /* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency. 440 * Safe to use with mixed HIRD and BESL systems (host and device) and is used 441 * by other operating systems. 442 * 443 * XHCI 1.0 errata 8/14/12 Table 13 notes: 444 * "Software should choose xHC BESL/BESLD field values that do not violate a 445 * device's resume latency requirements, 446 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached, 447 * or not program values < '4' if BLC = '0' and a BESL device is attached. 448 */ 449 #define XHCI_DEFAULT_BESL 4 450 451 /** 452 * struct xhci_intr_reg - Interrupt Register Set 453 * @irq_pending: IMAN - Interrupt Management Register. Used to enable 454 * interrupts and check for pending interrupts. 455 * @irq_control: IMOD - Interrupt Moderation Register. 456 * Used to throttle interrupts. 457 * @erst_size: Number of segments in the Event Ring Segment Table (ERST). 458 * @erst_base: ERST base address. 459 * @erst_dequeue: Event ring dequeue pointer. 460 * 461 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event 462 * Ring Segment Table (ERST) associated with it. The event ring is comprised of 463 * multiple segments of the same size. The HC places events on the ring and 464 * "updates the Cycle bit in the TRBs to indicate to software the current 465 * position of the Enqueue Pointer." The HCD (Linux) processes those events and 466 * updates the dequeue pointer. 467 */ 468 struct xhci_intr_reg { 469 __le32 irq_pending; 470 __le32 irq_control; 471 __le32 erst_size; 472 __le32 rsvd; 473 __le64 erst_base; 474 __le64 erst_dequeue; 475 }; 476 477 /* irq_pending bitmasks */ 478 #define ER_IRQ_PENDING(p) ((p) & 0x1) 479 /* bits 2:31 need to be preserved */ 480 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */ 481 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe) 482 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2) 483 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2)) 484 485 /* irq_control bitmasks */ 486 /* Minimum interval between interrupts (in 250ns intervals). The interval 487 * between interrupts will be longer if there are no events on the event ring. 488 * Default is 4000 (1 ms). 489 */ 490 #define ER_IRQ_INTERVAL_MASK (0xffff) 491 /* Counter used to count down the time to the next interrupt - HW use only */ 492 #define ER_IRQ_COUNTER_MASK (0xffff << 16) 493 494 /* erst_size bitmasks */ 495 /* Preserve bits 16:31 of erst_size */ 496 #define ERST_SIZE_MASK (0xffff << 16) 497 498 /* erst_dequeue bitmasks */ 499 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias) 500 * where the current dequeue pointer lies. This is an optional HW hint. 501 */ 502 #define ERST_DESI_MASK (0x7) 503 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by 504 * a work queue (or delayed service routine)? 505 */ 506 #define ERST_EHB (1 << 3) 507 #define ERST_PTR_MASK (0xf) 508 509 /** 510 * struct xhci_run_regs 511 * @microframe_index: 512 * MFINDEX - current microframe number 513 * 514 * Section 5.5 Host Controller Runtime Registers: 515 * "Software should read and write these registers using only Dword (32 bit) 516 * or larger accesses" 517 */ 518 struct xhci_run_regs { 519 __le32 microframe_index; 520 __le32 rsvd[7]; 521 struct xhci_intr_reg ir_set[128]; 522 }; 523 524 /** 525 * struct doorbell_array 526 * 527 * Bits 0 - 7: Endpoint target 528 * Bits 8 - 15: RsvdZ 529 * Bits 16 - 31: Stream ID 530 * 531 * Section 5.6 532 */ 533 struct xhci_doorbell_array { 534 __le32 doorbell[256]; 535 }; 536 537 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16)) 538 #define DB_VALUE_HOST 0x00000000 539 540 /** 541 * struct xhci_protocol_caps 542 * @revision: major revision, minor revision, capability ID, 543 * and next capability pointer. 544 * @name_string: Four ASCII characters to say which spec this xHC 545 * follows, typically "USB ". 546 * @port_info: Port offset, count, and protocol-defined information. 547 */ 548 struct xhci_protocol_caps { 549 u32 revision; 550 u32 name_string; 551 u32 port_info; 552 }; 553 554 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff) 555 #define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff) 556 #define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f) 557 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff) 558 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff) 559 560 #define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f) 561 #define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03) 562 #define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03) 563 #define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01) 564 #define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03) 565 #define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff) 566 567 #define PLT_MASK (0x03 << 6) 568 #define PLT_SYM (0x00 << 6) 569 #define PLT_ASYM_RX (0x02 << 6) 570 #define PLT_ASYM_TX (0x03 << 6) 571 572 /** 573 * struct xhci_container_ctx 574 * @type: Type of context. Used to calculated offsets to contained contexts. 575 * @size: Size of the context data 576 * @bytes: The raw context data given to HW 577 * @dma: dma address of the bytes 578 * 579 * Represents either a Device or Input context. Holds a pointer to the raw 580 * memory used for the context (bytes) and dma address of it (dma). 581 */ 582 struct xhci_container_ctx { 583 unsigned type; 584 #define XHCI_CTX_TYPE_DEVICE 0x1 585 #define XHCI_CTX_TYPE_INPUT 0x2 586 587 int size; 588 589 u8 *bytes; 590 dma_addr_t dma; 591 }; 592 593 /** 594 * struct xhci_slot_ctx 595 * @dev_info: Route string, device speed, hub info, and last valid endpoint 596 * @dev_info2: Max exit latency for device number, root hub port number 597 * @tt_info: tt_info is used to construct split transaction tokens 598 * @dev_state: slot state and device address 599 * 600 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context 601 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 602 * reserved at the end of the slot context for HC internal use. 603 */ 604 struct xhci_slot_ctx { 605 __le32 dev_info; 606 __le32 dev_info2; 607 __le32 tt_info; 608 __le32 dev_state; 609 /* offset 0x10 to 0x1f reserved for HC internal use */ 610 __le32 reserved[4]; 611 }; 612 613 /* dev_info bitmasks */ 614 /* Route String - 0:19 */ 615 #define ROUTE_STRING_MASK (0xfffff) 616 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */ 617 #define DEV_SPEED (0xf << 20) 618 #define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20) 619 /* bit 24 reserved */ 620 /* Is this LS/FS device connected through a HS hub? - bit 25 */ 621 #define DEV_MTT (0x1 << 25) 622 /* Set if the device is a hub - bit 26 */ 623 #define DEV_HUB (0x1 << 26) 624 /* Index of the last valid endpoint context in this device context - 27:31 */ 625 #define LAST_CTX_MASK (0x1f << 27) 626 #define LAST_CTX(p) ((p) << 27) 627 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1) 628 #define SLOT_FLAG (1 << 0) 629 #define EP0_FLAG (1 << 1) 630 631 /* dev_info2 bitmasks */ 632 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */ 633 #define MAX_EXIT (0xffff) 634 /* Root hub port number that is needed to access the USB device */ 635 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16) 636 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff) 637 /* Maximum number of ports under a hub device */ 638 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24) 639 #define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24) 640 641 /* tt_info bitmasks */ 642 /* 643 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub 644 * The Slot ID of the hub that isolates the high speed signaling from 645 * this low or full-speed device. '0' if attached to root hub port. 646 */ 647 #define TT_SLOT (0xff) 648 /* 649 * The number of the downstream facing port of the high-speed hub 650 * '0' if the device is not low or full speed. 651 */ 652 #define TT_PORT (0xff << 8) 653 #define TT_THINK_TIME(p) (((p) & 0x3) << 16) 654 #define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16) 655 656 /* dev_state bitmasks */ 657 /* USB device address - assigned by the HC */ 658 #define DEV_ADDR_MASK (0xff) 659 /* bits 8:26 reserved */ 660 /* Slot state */ 661 #define SLOT_STATE (0x1f << 27) 662 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27) 663 664 #define SLOT_STATE_DISABLED 0 665 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED 666 #define SLOT_STATE_DEFAULT 1 667 #define SLOT_STATE_ADDRESSED 2 668 #define SLOT_STATE_CONFIGURED 3 669 670 /** 671 * struct xhci_ep_ctx 672 * @ep_info: endpoint state, streams, mult, and interval information. 673 * @ep_info2: information on endpoint type, max packet size, max burst size, 674 * error count, and whether the HC will force an event for all 675 * transactions. 676 * @deq: 64-bit ring dequeue pointer address. If the endpoint only 677 * defines one stream, this points to the endpoint transfer ring. 678 * Otherwise, it points to a stream context array, which has a 679 * ring pointer for each flow. 680 * @tx_info: 681 * Average TRB lengths for the endpoint ring and 682 * max payload within an Endpoint Service Interval Time (ESIT). 683 * 684 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context 685 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes 686 * reserved at the end of the endpoint context for HC internal use. 687 */ 688 struct xhci_ep_ctx { 689 __le32 ep_info; 690 __le32 ep_info2; 691 __le64 deq; 692 __le32 tx_info; 693 /* offset 0x14 - 0x1f reserved for HC internal use */ 694 __le32 reserved[3]; 695 }; 696 697 /* ep_info bitmasks */ 698 /* 699 * Endpoint State - bits 0:2 700 * 0 - disabled 701 * 1 - running 702 * 2 - halted due to halt condition - ok to manipulate endpoint ring 703 * 3 - stopped 704 * 4 - TRB error 705 * 5-7 - reserved 706 */ 707 #define EP_STATE_MASK (0xf) 708 #define EP_STATE_DISABLED 0 709 #define EP_STATE_RUNNING 1 710 #define EP_STATE_HALTED 2 711 #define EP_STATE_STOPPED 3 712 #define EP_STATE_ERROR 4 713 #define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK) 714 715 /* Mult - Max number of burtst within an interval, in EP companion desc. */ 716 #define EP_MULT(p) (((p) & 0x3) << 8) 717 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3) 718 /* bits 10:14 are Max Primary Streams */ 719 /* bit 15 is Linear Stream Array */ 720 /* Interval - period between requests to an endpoint - 125u increments. */ 721 #define EP_INTERVAL(p) (((p) & 0xff) << 16) 722 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff)) 723 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff) 724 #define EP_MAXPSTREAMS_MASK (0x1f << 10) 725 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK) 726 #define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10) 727 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */ 728 #define EP_HAS_LSA (1 << 15) 729 /* hosts with LEC=1 use bits 31:24 as ESIT high bits. */ 730 #define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff) 731 732 /* ep_info2 bitmasks */ 733 /* 734 * Force Event - generate transfer events for all TRBs for this endpoint 735 * This will tell the HC to ignore the IOC and ISP flags (for debugging only). 736 */ 737 #define FORCE_EVENT (0x1) 738 #define ERROR_COUNT(p) (((p) & 0x3) << 1) 739 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) 740 #define EP_TYPE(p) ((p) << 3) 741 #define ISOC_OUT_EP 1 742 #define BULK_OUT_EP 2 743 #define INT_OUT_EP 3 744 #define CTRL_EP 4 745 #define ISOC_IN_EP 5 746 #define BULK_IN_EP 6 747 #define INT_IN_EP 7 748 /* bit 6 reserved */ 749 /* bit 7 is Host Initiate Disable - for disabling stream selection */ 750 #define MAX_BURST(p) (((p)&0xff) << 8) 751 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) 752 #define MAX_PACKET(p) (((p)&0xffff) << 16) 753 #define MAX_PACKET_MASK (0xffff << 16) 754 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) 755 756 /* tx_info bitmasks */ 757 #define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff) 758 #define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16) 759 #define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24) 760 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff) 761 762 /* deq bitmasks */ 763 #define EP_CTX_CYCLE_MASK (1 << 0) 764 #define SCTX_DEQ_MASK (~0xfL) 765 766 767 /** 768 * struct xhci_input_control_context 769 * Input control context; see section 6.2.5. 770 * 771 * @drop_context: set the bit of the endpoint context you want to disable 772 * @add_context: set the bit of the endpoint context you want to enable 773 */ 774 struct xhci_input_control_ctx { 775 __le32 drop_flags; 776 __le32 add_flags; 777 __le32 rsvd2[6]; 778 }; 779 780 #define EP_IS_ADDED(ctrl_ctx, i) \ 781 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))) 782 #define EP_IS_DROPPED(ctrl_ctx, i) \ 783 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) 784 785 /* Represents everything that is needed to issue a command on the command ring. 786 * It's useful to pre-allocate these for commands that cannot fail due to 787 * out-of-memory errors, like freeing streams. 788 */ 789 struct xhci_command { 790 /* Input context for changing device state */ 791 struct xhci_container_ctx *in_ctx; 792 u32 status; 793 int slot_id; 794 /* If completion is null, no one is waiting on this command 795 * and the structure can be freed after the command completes. 796 */ 797 struct completion *completion; 798 union xhci_trb *command_trb; 799 struct list_head cmd_list; 800 }; 801 802 /* drop context bitmasks */ 803 #define DROP_EP(x) (0x1 << x) 804 /* add context bitmasks */ 805 #define ADD_EP(x) (0x1 << x) 806 807 struct xhci_stream_ctx { 808 /* 64-bit stream ring address, cycle state, and stream type */ 809 __le64 stream_ring; 810 /* offset 0x14 - 0x1f reserved for HC internal use */ 811 __le32 reserved[2]; 812 }; 813 814 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */ 815 #define SCT_FOR_CTX(p) (((p) & 0x7) << 1) 816 /* Secondary stream array type, dequeue pointer is to a transfer ring */ 817 #define SCT_SEC_TR 0 818 /* Primary stream array type, dequeue pointer is to a transfer ring */ 819 #define SCT_PRI_TR 1 820 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */ 821 #define SCT_SSA_8 2 822 #define SCT_SSA_16 3 823 #define SCT_SSA_32 4 824 #define SCT_SSA_64 5 825 #define SCT_SSA_128 6 826 #define SCT_SSA_256 7 827 828 /* Assume no secondary streams for now */ 829 struct xhci_stream_info { 830 struct xhci_ring **stream_rings; 831 /* Number of streams, including stream 0 (which drivers can't use) */ 832 unsigned int num_streams; 833 /* The stream context array may be bigger than 834 * the number of streams the driver asked for 835 */ 836 struct xhci_stream_ctx *stream_ctx_array; 837 unsigned int num_stream_ctxs; 838 dma_addr_t ctx_array_dma; 839 /* For mapping physical TRB addresses to segments in stream rings */ 840 struct radix_tree_root trb_address_map; 841 struct xhci_command *free_streams_command; 842 }; 843 844 #define SMALL_STREAM_ARRAY_SIZE 256 845 #define MEDIUM_STREAM_ARRAY_SIZE 1024 846 847 /* Some Intel xHCI host controllers need software to keep track of the bus 848 * bandwidth. Keep track of endpoint info here. Each root port is allocated 849 * the full bus bandwidth. We must also treat TTs (including each port under a 850 * multi-TT hub) as a separate bandwidth domain. The direct memory interface 851 * (DMI) also limits the total bandwidth (across all domains) that can be used. 852 */ 853 struct xhci_bw_info { 854 /* ep_interval is zero-based */ 855 unsigned int ep_interval; 856 /* mult and num_packets are one-based */ 857 unsigned int mult; 858 unsigned int num_packets; 859 unsigned int max_packet_size; 860 unsigned int max_esit_payload; 861 unsigned int type; 862 }; 863 864 /* "Block" sizes in bytes the hardware uses for different device speeds. 865 * The logic in this part of the hardware limits the number of bits the hardware 866 * can use, so must represent bandwidth in a less precise manner to mimic what 867 * the scheduler hardware computes. 868 */ 869 #define FS_BLOCK 1 870 #define HS_BLOCK 4 871 #define SS_BLOCK 16 872 #define DMI_BLOCK 32 873 874 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated 875 * with each byte transferred. SuperSpeed devices have an initial overhead to 876 * set up bursts. These are in blocks, see above. LS overhead has already been 877 * translated into FS blocks. 878 */ 879 #define DMI_OVERHEAD 8 880 #define DMI_OVERHEAD_BURST 4 881 #define SS_OVERHEAD 8 882 #define SS_OVERHEAD_BURST 32 883 #define HS_OVERHEAD 26 884 #define FS_OVERHEAD 20 885 #define LS_OVERHEAD 128 886 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per 887 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because 888 * of overhead associated with split transfers crossing microframe boundaries. 889 * 31 blocks is pure protocol overhead. 890 */ 891 #define TT_HS_OVERHEAD (31 + 94) 892 #define TT_DMI_OVERHEAD (25 + 12) 893 894 /* Bandwidth limits in blocks */ 895 #define FS_BW_LIMIT 1285 896 #define TT_BW_LIMIT 1320 897 #define HS_BW_LIMIT 1607 898 #define SS_BW_LIMIT_IN 3906 899 #define DMI_BW_LIMIT_IN 3906 900 #define SS_BW_LIMIT_OUT 3906 901 #define DMI_BW_LIMIT_OUT 3906 902 903 /* Percentage of bus bandwidth reserved for non-periodic transfers */ 904 #define FS_BW_RESERVED 10 905 #define HS_BW_RESERVED 20 906 #define SS_BW_RESERVED 10 907 908 struct xhci_virt_ep { 909 struct xhci_ring *ring; 910 /* Related to endpoints that are configured to use stream IDs only */ 911 struct xhci_stream_info *stream_info; 912 /* Temporary storage in case the configure endpoint command fails and we 913 * have to restore the device state to the previous state 914 */ 915 struct xhci_ring *new_ring; 916 unsigned int ep_state; 917 #define SET_DEQ_PENDING (1 << 0) 918 #define EP_HALTED (1 << 1) /* For stall handling */ 919 #define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */ 920 /* Transitioning the endpoint to using streams, don't enqueue URBs */ 921 #define EP_GETTING_STREAMS (1 << 3) 922 #define EP_HAS_STREAMS (1 << 4) 923 /* Transitioning the endpoint to not using streams, don't enqueue URBs */ 924 #define EP_GETTING_NO_STREAMS (1 << 5) 925 #define EP_HARD_CLEAR_TOGGLE (1 << 6) 926 #define EP_SOFT_CLEAR_TOGGLE (1 << 7) 927 /* ---- Related to URB cancellation ---- */ 928 struct list_head cancelled_td_list; 929 /* Watchdog timer for stop endpoint command to cancel URBs */ 930 struct timer_list stop_cmd_timer; 931 struct xhci_hcd *xhci; 932 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue 933 * command. We'll need to update the ring's dequeue segment and dequeue 934 * pointer after the command completes. 935 */ 936 struct xhci_segment *queued_deq_seg; 937 union xhci_trb *queued_deq_ptr; 938 /* 939 * Sometimes the xHC can not process isochronous endpoint ring quickly 940 * enough, and it will miss some isoc tds on the ring and generate 941 * a Missed Service Error Event. 942 * Set skip flag when receive a Missed Service Error Event and 943 * process the missed tds on the endpoint ring. 944 */ 945 bool skip; 946 /* Bandwidth checking storage */ 947 struct xhci_bw_info bw_info; 948 struct list_head bw_endpoint_list; 949 /* Isoch Frame ID checking storage */ 950 int next_frame_id; 951 /* Use new Isoch TRB layout needed for extended TBC support */ 952 bool use_extended_tbc; 953 }; 954 955 enum xhci_overhead_type { 956 LS_OVERHEAD_TYPE = 0, 957 FS_OVERHEAD_TYPE, 958 HS_OVERHEAD_TYPE, 959 }; 960 961 struct xhci_interval_bw { 962 unsigned int num_packets; 963 /* Sorted by max packet size. 964 * Head of the list is the greatest max packet size. 965 */ 966 struct list_head endpoints; 967 /* How many endpoints of each speed are present. */ 968 unsigned int overhead[3]; 969 }; 970 971 #define XHCI_MAX_INTERVAL 16 972 973 struct xhci_interval_bw_table { 974 unsigned int interval0_esit_payload; 975 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL]; 976 /* Includes reserved bandwidth for async endpoints */ 977 unsigned int bw_used; 978 unsigned int ss_bw_in; 979 unsigned int ss_bw_out; 980 }; 981 982 983 struct xhci_virt_device { 984 struct usb_device *udev; 985 /* 986 * Commands to the hardware are passed an "input context" that 987 * tells the hardware what to change in its data structures. 988 * The hardware will return changes in an "output context" that 989 * software must allocate for the hardware. We need to keep 990 * track of input and output contexts separately because 991 * these commands might fail and we don't trust the hardware. 992 */ 993 struct xhci_container_ctx *out_ctx; 994 /* Used for addressing devices and configuration changes */ 995 struct xhci_container_ctx *in_ctx; 996 struct xhci_virt_ep eps[31]; 997 u8 fake_port; 998 u8 real_port; 999 struct xhci_interval_bw_table *bw_table; 1000 struct xhci_tt_bw_info *tt_info; 1001 /* The current max exit latency for the enabled USB3 link states. */ 1002 u16 current_mel; 1003 /* Used for the debugfs interfaces. */ 1004 void *debugfs_private; 1005 }; 1006 1007 /* 1008 * For each roothub, keep track of the bandwidth information for each periodic 1009 * interval. 1010 * 1011 * If a high speed hub is attached to the roothub, each TT associated with that 1012 * hub is a separate bandwidth domain. The interval information for the 1013 * endpoints on the devices under that TT will appear in the TT structure. 1014 */ 1015 struct xhci_root_port_bw_info { 1016 struct list_head tts; 1017 unsigned int num_active_tts; 1018 struct xhci_interval_bw_table bw_table; 1019 }; 1020 1021 struct xhci_tt_bw_info { 1022 struct list_head tt_list; 1023 int slot_id; 1024 int ttport; 1025 struct xhci_interval_bw_table bw_table; 1026 int active_eps; 1027 }; 1028 1029 1030 /** 1031 * struct xhci_device_context_array 1032 * @dev_context_ptr array of 64-bit DMA addresses for device contexts 1033 */ 1034 struct xhci_device_context_array { 1035 /* 64-bit device addresses; we only write 32-bit addresses */ 1036 __le64 dev_context_ptrs[MAX_HC_SLOTS]; 1037 /* private xHCD pointers */ 1038 dma_addr_t dma; 1039 }; 1040 /* TODO: write function to set the 64-bit device DMA address */ 1041 /* 1042 * TODO: change this to be dynamically sized at HC mem init time since the HC 1043 * might not be able to handle the maximum number of devices possible. 1044 */ 1045 1046 1047 struct xhci_transfer_event { 1048 /* 64-bit buffer address, or immediate data */ 1049 __le64 buffer; 1050 __le32 transfer_len; 1051 /* This field is interpreted differently based on the type of TRB */ 1052 __le32 flags; 1053 }; 1054 1055 /* Transfer event TRB length bit mask */ 1056 /* bits 0:23 */ 1057 #define EVENT_TRB_LEN(p) ((p) & 0xffffff) 1058 1059 /** Transfer Event bit fields **/ 1060 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f) 1061 1062 /* Completion Code - only applicable for some types of TRBs */ 1063 #define COMP_CODE_MASK (0xff << 24) 1064 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24) 1065 #define COMP_INVALID 0 1066 #define COMP_SUCCESS 1 1067 #define COMP_DATA_BUFFER_ERROR 2 1068 #define COMP_BABBLE_DETECTED_ERROR 3 1069 #define COMP_USB_TRANSACTION_ERROR 4 1070 #define COMP_TRB_ERROR 5 1071 #define COMP_STALL_ERROR 6 1072 #define COMP_RESOURCE_ERROR 7 1073 #define COMP_BANDWIDTH_ERROR 8 1074 #define COMP_NO_SLOTS_AVAILABLE_ERROR 9 1075 #define COMP_INVALID_STREAM_TYPE_ERROR 10 1076 #define COMP_SLOT_NOT_ENABLED_ERROR 11 1077 #define COMP_ENDPOINT_NOT_ENABLED_ERROR 12 1078 #define COMP_SHORT_PACKET 13 1079 #define COMP_RING_UNDERRUN 14 1080 #define COMP_RING_OVERRUN 15 1081 #define COMP_VF_EVENT_RING_FULL_ERROR 16 1082 #define COMP_PARAMETER_ERROR 17 1083 #define COMP_BANDWIDTH_OVERRUN_ERROR 18 1084 #define COMP_CONTEXT_STATE_ERROR 19 1085 #define COMP_NO_PING_RESPONSE_ERROR 20 1086 #define COMP_EVENT_RING_FULL_ERROR 21 1087 #define COMP_INCOMPATIBLE_DEVICE_ERROR 22 1088 #define COMP_MISSED_SERVICE_ERROR 23 1089 #define COMP_COMMAND_RING_STOPPED 24 1090 #define COMP_COMMAND_ABORTED 25 1091 #define COMP_STOPPED 26 1092 #define COMP_STOPPED_LENGTH_INVALID 27 1093 #define COMP_STOPPED_SHORT_PACKET 28 1094 #define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29 1095 #define COMP_ISOCH_BUFFER_OVERRUN 31 1096 #define COMP_EVENT_LOST_ERROR 32 1097 #define COMP_UNDEFINED_ERROR 33 1098 #define COMP_INVALID_STREAM_ID_ERROR 34 1099 #define COMP_SECONDARY_BANDWIDTH_ERROR 35 1100 #define COMP_SPLIT_TRANSACTION_ERROR 36 1101 1102 static inline const char *xhci_trb_comp_code_string(u8 status) 1103 { 1104 switch (status) { 1105 case COMP_INVALID: 1106 return "Invalid"; 1107 case COMP_SUCCESS: 1108 return "Success"; 1109 case COMP_DATA_BUFFER_ERROR: 1110 return "Data Buffer Error"; 1111 case COMP_BABBLE_DETECTED_ERROR: 1112 return "Babble Detected"; 1113 case COMP_USB_TRANSACTION_ERROR: 1114 return "USB Transaction Error"; 1115 case COMP_TRB_ERROR: 1116 return "TRB Error"; 1117 case COMP_STALL_ERROR: 1118 return "Stall Error"; 1119 case COMP_RESOURCE_ERROR: 1120 return "Resource Error"; 1121 case COMP_BANDWIDTH_ERROR: 1122 return "Bandwidth Error"; 1123 case COMP_NO_SLOTS_AVAILABLE_ERROR: 1124 return "No Slots Available Error"; 1125 case COMP_INVALID_STREAM_TYPE_ERROR: 1126 return "Invalid Stream Type Error"; 1127 case COMP_SLOT_NOT_ENABLED_ERROR: 1128 return "Slot Not Enabled Error"; 1129 case COMP_ENDPOINT_NOT_ENABLED_ERROR: 1130 return "Endpoint Not Enabled Error"; 1131 case COMP_SHORT_PACKET: 1132 return "Short Packet"; 1133 case COMP_RING_UNDERRUN: 1134 return "Ring Underrun"; 1135 case COMP_RING_OVERRUN: 1136 return "Ring Overrun"; 1137 case COMP_VF_EVENT_RING_FULL_ERROR: 1138 return "VF Event Ring Full Error"; 1139 case COMP_PARAMETER_ERROR: 1140 return "Parameter Error"; 1141 case COMP_BANDWIDTH_OVERRUN_ERROR: 1142 return "Bandwidth Overrun Error"; 1143 case COMP_CONTEXT_STATE_ERROR: 1144 return "Context State Error"; 1145 case COMP_NO_PING_RESPONSE_ERROR: 1146 return "No Ping Response Error"; 1147 case COMP_EVENT_RING_FULL_ERROR: 1148 return "Event Ring Full Error"; 1149 case COMP_INCOMPATIBLE_DEVICE_ERROR: 1150 return "Incompatible Device Error"; 1151 case COMP_MISSED_SERVICE_ERROR: 1152 return "Missed Service Error"; 1153 case COMP_COMMAND_RING_STOPPED: 1154 return "Command Ring Stopped"; 1155 case COMP_COMMAND_ABORTED: 1156 return "Command Aborted"; 1157 case COMP_STOPPED: 1158 return "Stopped"; 1159 case COMP_STOPPED_LENGTH_INVALID: 1160 return "Stopped - Length Invalid"; 1161 case COMP_STOPPED_SHORT_PACKET: 1162 return "Stopped - Short Packet"; 1163 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: 1164 return "Max Exit Latency Too Large Error"; 1165 case COMP_ISOCH_BUFFER_OVERRUN: 1166 return "Isoch Buffer Overrun"; 1167 case COMP_EVENT_LOST_ERROR: 1168 return "Event Lost Error"; 1169 case COMP_UNDEFINED_ERROR: 1170 return "Undefined Error"; 1171 case COMP_INVALID_STREAM_ID_ERROR: 1172 return "Invalid Stream ID Error"; 1173 case COMP_SECONDARY_BANDWIDTH_ERROR: 1174 return "Secondary Bandwidth Error"; 1175 case COMP_SPLIT_TRANSACTION_ERROR: 1176 return "Split Transaction Error"; 1177 default: 1178 return "Unknown!!"; 1179 } 1180 } 1181 1182 struct xhci_link_trb { 1183 /* 64-bit segment pointer*/ 1184 __le64 segment_ptr; 1185 __le32 intr_target; 1186 __le32 control; 1187 }; 1188 1189 /* control bitfields */ 1190 #define LINK_TOGGLE (0x1<<1) 1191 1192 /* Command completion event TRB */ 1193 struct xhci_event_cmd { 1194 /* Pointer to command TRB, or the value passed by the event data trb */ 1195 __le64 cmd_trb; 1196 __le32 status; 1197 __le32 flags; 1198 }; 1199 1200 /* flags bitmasks */ 1201 1202 /* Address device - disable SetAddress */ 1203 #define TRB_BSR (1<<9) 1204 1205 /* Configure Endpoint - Deconfigure */ 1206 #define TRB_DC (1<<9) 1207 1208 /* Stop Ring - Transfer State Preserve */ 1209 #define TRB_TSP (1<<9) 1210 1211 enum xhci_ep_reset_type { 1212 EP_HARD_RESET, 1213 EP_SOFT_RESET, 1214 }; 1215 1216 /* Force Event */ 1217 #define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22) 1218 #define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16) 1219 1220 /* Set Latency Tolerance Value */ 1221 #define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16) 1222 1223 /* Get Port Bandwidth */ 1224 #define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16) 1225 1226 /* Force Header */ 1227 #define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f) 1228 #define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24) 1229 1230 enum xhci_setup_dev { 1231 SETUP_CONTEXT_ONLY, 1232 SETUP_CONTEXT_ADDRESS, 1233 }; 1234 1235 /* bits 16:23 are the virtual function ID */ 1236 /* bits 24:31 are the slot ID */ 1237 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24) 1238 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24) 1239 1240 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */ 1241 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1) 1242 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16) 1243 1244 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23) 1245 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23) 1246 #define LAST_EP_INDEX 30 1247 1248 /* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */ 1249 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16)) 1250 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16) 1251 #define SCT_FOR_TRB(p) (((p) << 1) & 0x7) 1252 1253 /* Link TRB specific fields */ 1254 #define TRB_TC (1<<1) 1255 1256 /* Port Status Change Event TRB fields */ 1257 /* Port ID - bits 31:24 */ 1258 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24) 1259 1260 #define EVENT_DATA (1 << 2) 1261 1262 /* Normal TRB fields */ 1263 /* transfer_len bitmasks - bits 0:16 */ 1264 #define TRB_LEN(p) ((p) & 0x1ffff) 1265 /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ 1266 #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) 1267 #define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17) 1268 /* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */ 1269 #define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17) 1270 /* Interrupter Target - which MSI-X vector to target the completion event at */ 1271 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) 1272 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) 1273 /* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */ 1274 #define TRB_TBC(p) (((p) & 0x3) << 7) 1275 #define TRB_TLBPC(p) (((p) & 0xf) << 16) 1276 1277 /* Cycle bit - indicates TRB ownership by HC or HCD */ 1278 #define TRB_CYCLE (1<<0) 1279 /* 1280 * Force next event data TRB to be evaluated before task switch. 1281 * Used to pass OS data back after a TD completes. 1282 */ 1283 #define TRB_ENT (1<<1) 1284 /* Interrupt on short packet */ 1285 #define TRB_ISP (1<<2) 1286 /* Set PCIe no snoop attribute */ 1287 #define TRB_NO_SNOOP (1<<3) 1288 /* Chain multiple TRBs into a TD */ 1289 #define TRB_CHAIN (1<<4) 1290 /* Interrupt on completion */ 1291 #define TRB_IOC (1<<5) 1292 /* The buffer pointer contains immediate data */ 1293 #define TRB_IDT (1<<6) 1294 1295 /* Block Event Interrupt */ 1296 #define TRB_BEI (1<<9) 1297 1298 /* Control transfer TRB specific fields */ 1299 #define TRB_DIR_IN (1<<16) 1300 #define TRB_TX_TYPE(p) ((p) << 16) 1301 #define TRB_DATA_OUT 2 1302 #define TRB_DATA_IN 3 1303 1304 /* Isochronous TRB specific fields */ 1305 #define TRB_SIA (1<<31) 1306 #define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20) 1307 1308 struct xhci_generic_trb { 1309 __le32 field[4]; 1310 }; 1311 1312 union xhci_trb { 1313 struct xhci_link_trb link; 1314 struct xhci_transfer_event trans_event; 1315 struct xhci_event_cmd event_cmd; 1316 struct xhci_generic_trb generic; 1317 }; 1318 1319 /* TRB bit mask */ 1320 #define TRB_TYPE_BITMASK (0xfc00) 1321 #define TRB_TYPE(p) ((p) << 10) 1322 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 1323 /* TRB type IDs */ 1324 /* bulk, interrupt, isoc scatter/gather, and control data stage */ 1325 #define TRB_NORMAL 1 1326 /* setup stage for control transfers */ 1327 #define TRB_SETUP 2 1328 /* data stage for control transfers */ 1329 #define TRB_DATA 3 1330 /* status stage for control transfers */ 1331 #define TRB_STATUS 4 1332 /* isoc transfers */ 1333 #define TRB_ISOC 5 1334 /* TRB for linking ring segments */ 1335 #define TRB_LINK 6 1336 #define TRB_EVENT_DATA 7 1337 /* Transfer Ring No-op (not for the command ring) */ 1338 #define TRB_TR_NOOP 8 1339 /* Command TRBs */ 1340 /* Enable Slot Command */ 1341 #define TRB_ENABLE_SLOT 9 1342 /* Disable Slot Command */ 1343 #define TRB_DISABLE_SLOT 10 1344 /* Address Device Command */ 1345 #define TRB_ADDR_DEV 11 1346 /* Configure Endpoint Command */ 1347 #define TRB_CONFIG_EP 12 1348 /* Evaluate Context Command */ 1349 #define TRB_EVAL_CONTEXT 13 1350 /* Reset Endpoint Command */ 1351 #define TRB_RESET_EP 14 1352 /* Stop Transfer Ring Command */ 1353 #define TRB_STOP_RING 15 1354 /* Set Transfer Ring Dequeue Pointer Command */ 1355 #define TRB_SET_DEQ 16 1356 /* Reset Device Command */ 1357 #define TRB_RESET_DEV 17 1358 /* Force Event Command (opt) */ 1359 #define TRB_FORCE_EVENT 18 1360 /* Negotiate Bandwidth Command (opt) */ 1361 #define TRB_NEG_BANDWIDTH 19 1362 /* Set Latency Tolerance Value Command (opt) */ 1363 #define TRB_SET_LT 20 1364 /* Get port bandwidth Command */ 1365 #define TRB_GET_BW 21 1366 /* Force Header Command - generate a transaction or link management packet */ 1367 #define TRB_FORCE_HEADER 22 1368 /* No-op Command - not for transfer rings */ 1369 #define TRB_CMD_NOOP 23 1370 /* TRB IDs 24-31 reserved */ 1371 /* Event TRBS */ 1372 /* Transfer Event */ 1373 #define TRB_TRANSFER 32 1374 /* Command Completion Event */ 1375 #define TRB_COMPLETION 33 1376 /* Port Status Change Event */ 1377 #define TRB_PORT_STATUS 34 1378 /* Bandwidth Request Event (opt) */ 1379 #define TRB_BANDWIDTH_EVENT 35 1380 /* Doorbell Event (opt) */ 1381 #define TRB_DOORBELL 36 1382 /* Host Controller Event */ 1383 #define TRB_HC_EVENT 37 1384 /* Device Notification Event - device sent function wake notification */ 1385 #define TRB_DEV_NOTE 38 1386 /* MFINDEX Wrap Event - microframe counter wrapped */ 1387 #define TRB_MFINDEX_WRAP 39 1388 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */ 1389 1390 /* Nec vendor-specific command completion event. */ 1391 #define TRB_NEC_CMD_COMP 48 1392 /* Get NEC firmware revision. */ 1393 #define TRB_NEC_GET_FW 49 1394 1395 static inline const char *xhci_trb_type_string(u8 type) 1396 { 1397 switch (type) { 1398 case TRB_NORMAL: 1399 return "Normal"; 1400 case TRB_SETUP: 1401 return "Setup Stage"; 1402 case TRB_DATA: 1403 return "Data Stage"; 1404 case TRB_STATUS: 1405 return "Status Stage"; 1406 case TRB_ISOC: 1407 return "Isoch"; 1408 case TRB_LINK: 1409 return "Link"; 1410 case TRB_EVENT_DATA: 1411 return "Event Data"; 1412 case TRB_TR_NOOP: 1413 return "No-Op"; 1414 case TRB_ENABLE_SLOT: 1415 return "Enable Slot Command"; 1416 case TRB_DISABLE_SLOT: 1417 return "Disable Slot Command"; 1418 case TRB_ADDR_DEV: 1419 return "Address Device Command"; 1420 case TRB_CONFIG_EP: 1421 return "Configure Endpoint Command"; 1422 case TRB_EVAL_CONTEXT: 1423 return "Evaluate Context Command"; 1424 case TRB_RESET_EP: 1425 return "Reset Endpoint Command"; 1426 case TRB_STOP_RING: 1427 return "Stop Ring Command"; 1428 case TRB_SET_DEQ: 1429 return "Set TR Dequeue Pointer Command"; 1430 case TRB_RESET_DEV: 1431 return "Reset Device Command"; 1432 case TRB_FORCE_EVENT: 1433 return "Force Event Command"; 1434 case TRB_NEG_BANDWIDTH: 1435 return "Negotiate Bandwidth Command"; 1436 case TRB_SET_LT: 1437 return "Set Latency Tolerance Value Command"; 1438 case TRB_GET_BW: 1439 return "Get Port Bandwidth Command"; 1440 case TRB_FORCE_HEADER: 1441 return "Force Header Command"; 1442 case TRB_CMD_NOOP: 1443 return "No-Op Command"; 1444 case TRB_TRANSFER: 1445 return "Transfer Event"; 1446 case TRB_COMPLETION: 1447 return "Command Completion Event"; 1448 case TRB_PORT_STATUS: 1449 return "Port Status Change Event"; 1450 case TRB_BANDWIDTH_EVENT: 1451 return "Bandwidth Request Event"; 1452 case TRB_DOORBELL: 1453 return "Doorbell Event"; 1454 case TRB_HC_EVENT: 1455 return "Host Controller Event"; 1456 case TRB_DEV_NOTE: 1457 return "Device Notification Event"; 1458 case TRB_MFINDEX_WRAP: 1459 return "MFINDEX Wrap Event"; 1460 case TRB_NEC_CMD_COMP: 1461 return "NEC Command Completion Event"; 1462 case TRB_NEC_GET_FW: 1463 return "NET Get Firmware Revision Command"; 1464 default: 1465 return "UNKNOWN"; 1466 } 1467 } 1468 1469 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK)) 1470 /* Above, but for __le32 types -- can avoid work by swapping constants: */ 1471 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1472 cpu_to_le32(TRB_TYPE(TRB_LINK))) 1473 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \ 1474 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP))) 1475 1476 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff) 1477 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff) 1478 1479 /* 1480 * TRBS_PER_SEGMENT must be a multiple of 4, 1481 * since the command ring is 64-byte aligned. 1482 * It must also be greater than 16. 1483 */ 1484 #define TRBS_PER_SEGMENT 256 1485 /* Allow two commands + a link TRB, along with any reserved command TRBs */ 1486 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3) 1487 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16) 1488 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE)) 1489 /* TRB buffer pointers can't cross 64KB boundaries */ 1490 #define TRB_MAX_BUFF_SHIFT 16 1491 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT) 1492 /* How much data is left before the 64KB boundary? */ 1493 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \ 1494 (addr & (TRB_MAX_BUFF_SIZE - 1))) 1495 1496 struct xhci_segment { 1497 union xhci_trb *trbs; 1498 /* private to HCD */ 1499 struct xhci_segment *next; 1500 dma_addr_t dma; 1501 /* Max packet sized bounce buffer for td-fragmant alignment */ 1502 dma_addr_t bounce_dma; 1503 void *bounce_buf; 1504 unsigned int bounce_offs; 1505 unsigned int bounce_len; 1506 }; 1507 1508 struct xhci_td { 1509 struct list_head td_list; 1510 struct list_head cancelled_td_list; 1511 struct urb *urb; 1512 struct xhci_segment *start_seg; 1513 union xhci_trb *first_trb; 1514 union xhci_trb *last_trb; 1515 struct xhci_segment *bounce_seg; 1516 /* actual_length of the URB has already been set */ 1517 bool urb_length_set; 1518 }; 1519 1520 /* xHCI command default timeout value */ 1521 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ) 1522 1523 /* command descriptor */ 1524 struct xhci_cd { 1525 struct xhci_command *command; 1526 union xhci_trb *cmd_trb; 1527 }; 1528 1529 struct xhci_dequeue_state { 1530 struct xhci_segment *new_deq_seg; 1531 union xhci_trb *new_deq_ptr; 1532 int new_cycle_state; 1533 unsigned int stream_id; 1534 }; 1535 1536 enum xhci_ring_type { 1537 TYPE_CTRL = 0, 1538 TYPE_ISOC, 1539 TYPE_BULK, 1540 TYPE_INTR, 1541 TYPE_STREAM, 1542 TYPE_COMMAND, 1543 TYPE_EVENT, 1544 }; 1545 1546 static inline const char *xhci_ring_type_string(enum xhci_ring_type type) 1547 { 1548 switch (type) { 1549 case TYPE_CTRL: 1550 return "CTRL"; 1551 case TYPE_ISOC: 1552 return "ISOC"; 1553 case TYPE_BULK: 1554 return "BULK"; 1555 case TYPE_INTR: 1556 return "INTR"; 1557 case TYPE_STREAM: 1558 return "STREAM"; 1559 case TYPE_COMMAND: 1560 return "CMD"; 1561 case TYPE_EVENT: 1562 return "EVENT"; 1563 } 1564 1565 return "UNKNOWN"; 1566 } 1567 1568 struct xhci_ring { 1569 struct xhci_segment *first_seg; 1570 struct xhci_segment *last_seg; 1571 union xhci_trb *enqueue; 1572 struct xhci_segment *enq_seg; 1573 union xhci_trb *dequeue; 1574 struct xhci_segment *deq_seg; 1575 struct list_head td_list; 1576 /* 1577 * Write the cycle state into the TRB cycle field to give ownership of 1578 * the TRB to the host controller (if we are the producer), or to check 1579 * if we own the TRB (if we are the consumer). See section 4.9.1. 1580 */ 1581 u32 cycle_state; 1582 unsigned int stream_id; 1583 unsigned int num_segs; 1584 unsigned int num_trbs_free; 1585 unsigned int num_trbs_free_temp; 1586 unsigned int bounce_buf_len; 1587 enum xhci_ring_type type; 1588 bool last_td_was_short; 1589 struct radix_tree_root *trb_address_map; 1590 }; 1591 1592 struct xhci_erst_entry { 1593 /* 64-bit event ring segment address */ 1594 __le64 seg_addr; 1595 __le32 seg_size; 1596 /* Set to zero */ 1597 __le32 rsvd; 1598 }; 1599 1600 struct xhci_erst { 1601 struct xhci_erst_entry *entries; 1602 unsigned int num_entries; 1603 /* xhci->event_ring keeps track of segment dma addresses */ 1604 dma_addr_t erst_dma_addr; 1605 /* Num entries the ERST can contain */ 1606 unsigned int erst_size; 1607 }; 1608 1609 struct xhci_scratchpad { 1610 u64 *sp_array; 1611 dma_addr_t sp_dma; 1612 void **sp_buffers; 1613 }; 1614 1615 struct urb_priv { 1616 int num_tds; 1617 int num_tds_done; 1618 struct xhci_td td[0]; 1619 }; 1620 1621 /* 1622 * Each segment table entry is 4*32bits long. 1K seems like an ok size: 1623 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table, 1624 * meaning 64 ring segments. 1625 * Initial allocated size of the ERST, in number of entries */ 1626 #define ERST_NUM_SEGS 1 1627 /* Initial allocated size of the ERST, in number of entries */ 1628 #define ERST_SIZE 64 1629 /* Initial number of event segment rings allocated */ 1630 #define ERST_ENTRIES 1 1631 /* Poll every 60 seconds */ 1632 #define POLL_TIMEOUT 60 1633 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */ 1634 #define XHCI_STOP_EP_CMD_TIMEOUT 5 1635 /* XXX: Make these module parameters */ 1636 1637 struct s3_save { 1638 u32 command; 1639 u32 dev_nt; 1640 u64 dcbaa_ptr; 1641 u32 config_reg; 1642 u32 irq_pending; 1643 u32 irq_control; 1644 u32 erst_size; 1645 u64 erst_base; 1646 u64 erst_dequeue; 1647 }; 1648 1649 /* Use for lpm */ 1650 struct dev_info { 1651 u32 dev_id; 1652 struct list_head list; 1653 }; 1654 1655 struct xhci_bus_state { 1656 unsigned long bus_suspended; 1657 unsigned long next_statechange; 1658 1659 /* Port suspend arrays are indexed by the portnum of the fake roothub */ 1660 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */ 1661 u32 port_c_suspend; 1662 u32 suspended_ports; 1663 u32 port_remote_wakeup; 1664 unsigned long resume_done[USB_MAXCHILDREN]; 1665 /* which ports have started to resume */ 1666 unsigned long resuming_ports; 1667 /* Which ports are waiting on RExit to U0 transition. */ 1668 unsigned long rexit_ports; 1669 struct completion rexit_done[USB_MAXCHILDREN]; 1670 }; 1671 1672 1673 /* 1674 * It can take up to 20 ms to transition from RExit to U0 on the 1675 * Intel Lynx Point LP xHCI host. 1676 */ 1677 #define XHCI_MAX_REXIT_TIMEOUT (20 * 1000) 1678 1679 static inline unsigned int hcd_index(struct usb_hcd *hcd) 1680 { 1681 if (hcd->speed >= HCD_USB3) 1682 return 0; 1683 else 1684 return 1; 1685 } 1686 1687 struct xhci_hub { 1688 u8 maj_rev; 1689 u8 min_rev; 1690 u32 *psi; /* array of protocol speed ID entries */ 1691 u8 psi_count; 1692 u8 psi_uid_count; 1693 }; 1694 1695 /* There is one xhci_hcd structure per controller */ 1696 struct xhci_hcd { 1697 struct usb_hcd *main_hcd; 1698 struct usb_hcd *shared_hcd; 1699 /* glue to PCI and HCD framework */ 1700 struct xhci_cap_regs __iomem *cap_regs; 1701 struct xhci_op_regs __iomem *op_regs; 1702 struct xhci_run_regs __iomem *run_regs; 1703 struct xhci_doorbell_array __iomem *dba; 1704 /* Our HCD's current interrupter register set */ 1705 struct xhci_intr_reg __iomem *ir_set; 1706 1707 /* Cached register copies of read-only HC data */ 1708 __u32 hcs_params1; 1709 __u32 hcs_params2; 1710 __u32 hcs_params3; 1711 __u32 hcc_params; 1712 __u32 hcc_params2; 1713 1714 spinlock_t lock; 1715 1716 /* packed release number */ 1717 u8 sbrn; 1718 u16 hci_version; 1719 u8 max_slots; 1720 u8 max_interrupters; 1721 u8 max_ports; 1722 u8 isoc_threshold; 1723 /* imod_interval in ns (I * 250ns) */ 1724 u32 imod_interval; 1725 int event_ring_max; 1726 /* 4KB min, 128MB max */ 1727 int page_size; 1728 /* Valid values are 12 to 20, inclusive */ 1729 int page_shift; 1730 /* msi-x vectors */ 1731 int msix_count; 1732 /* optional clock */ 1733 struct clk *clk; 1734 /* data structures */ 1735 struct xhci_device_context_array *dcbaa; 1736 struct xhci_ring *cmd_ring; 1737 unsigned int cmd_ring_state; 1738 #define CMD_RING_STATE_RUNNING (1 << 0) 1739 #define CMD_RING_STATE_ABORTED (1 << 1) 1740 #define CMD_RING_STATE_STOPPED (1 << 2) 1741 struct list_head cmd_list; 1742 unsigned int cmd_ring_reserved_trbs; 1743 struct delayed_work cmd_timer; 1744 struct completion cmd_ring_stop_completion; 1745 struct xhci_command *current_cmd; 1746 struct xhci_ring *event_ring; 1747 struct xhci_erst erst; 1748 /* Scratchpad */ 1749 struct xhci_scratchpad *scratchpad; 1750 /* Store LPM test failed devices' information */ 1751 struct list_head lpm_failed_devs; 1752 1753 /* slot enabling and address device helpers */ 1754 /* these are not thread safe so use mutex */ 1755 struct mutex mutex; 1756 /* For USB 3.0 LPM enable/disable. */ 1757 struct xhci_command *lpm_command; 1758 /* Internal mirror of the HW's dcbaa */ 1759 struct xhci_virt_device *devs[MAX_HC_SLOTS]; 1760 /* For keeping track of bandwidth domains per roothub. */ 1761 struct xhci_root_port_bw_info *rh_bw; 1762 1763 /* DMA pools */ 1764 struct dma_pool *device_pool; 1765 struct dma_pool *segment_pool; 1766 struct dma_pool *small_streams_pool; 1767 struct dma_pool *medium_streams_pool; 1768 1769 /* Host controller watchdog timer structures */ 1770 unsigned int xhc_state; 1771 1772 u32 command; 1773 struct s3_save s3; 1774 /* Host controller is dying - not responding to commands. "I'm not dead yet!" 1775 * 1776 * xHC interrupts have been disabled and a watchdog timer will (or has already) 1777 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code 1778 * that sees this status (other than the timer that set it) should stop touching 1779 * hardware immediately. Interrupt handlers should return immediately when 1780 * they see this status (any time they drop and re-acquire xhci->lock). 1781 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without 1782 * putting the TD on the canceled list, etc. 1783 * 1784 * There are no reports of xHCI host controllers that display this issue. 1785 */ 1786 #define XHCI_STATE_DYING (1 << 0) 1787 #define XHCI_STATE_HALTED (1 << 1) 1788 #define XHCI_STATE_REMOVING (1 << 2) 1789 unsigned int quirks; 1790 #define XHCI_LINK_TRB_QUIRK (1 << 0) 1791 #define XHCI_RESET_EP_QUIRK (1 << 1) 1792 #define XHCI_NEC_HOST (1 << 2) 1793 #define XHCI_AMD_PLL_FIX (1 << 3) 1794 #define XHCI_SPURIOUS_SUCCESS (1 << 4) 1795 /* 1796 * Certain Intel host controllers have a limit to the number of endpoint 1797 * contexts they can handle. Ideally, they would signal that they can't handle 1798 * anymore endpoint contexts by returning a Resource Error for the Configure 1799 * Endpoint command, but they don't. Instead they expect software to keep track 1800 * of the number of active endpoints for them, across configure endpoint 1801 * commands, reset device commands, disable slot commands, and address device 1802 * commands. 1803 */ 1804 #define XHCI_EP_LIMIT_QUIRK (1 << 5) 1805 #define XHCI_BROKEN_MSI (1 << 6) 1806 #define XHCI_RESET_ON_RESUME (1 << 7) 1807 #define XHCI_SW_BW_CHECKING (1 << 8) 1808 #define XHCI_AMD_0x96_HOST (1 << 9) 1809 #define XHCI_TRUST_TX_LENGTH (1 << 10) 1810 #define XHCI_LPM_SUPPORT (1 << 11) 1811 #define XHCI_INTEL_HOST (1 << 12) 1812 #define XHCI_SPURIOUS_REBOOT (1 << 13) 1813 #define XHCI_COMP_MODE_QUIRK (1 << 14) 1814 #define XHCI_AVOID_BEI (1 << 15) 1815 #define XHCI_PLAT (1 << 16) 1816 #define XHCI_SLOW_SUSPEND (1 << 17) 1817 #define XHCI_SPURIOUS_WAKEUP (1 << 18) 1818 /* For controllers with a broken beyond repair streams implementation */ 1819 #define XHCI_BROKEN_STREAMS (1 << 19) 1820 #define XHCI_PME_STUCK_QUIRK (1 << 20) 1821 #define XHCI_MTK_HOST (1 << 21) 1822 #define XHCI_SSIC_PORT_UNUSED (1 << 22) 1823 #define XHCI_NO_64BIT_SUPPORT (1 << 23) 1824 #define XHCI_MISSING_CAS (1 << 24) 1825 /* For controller with a broken Port Disable implementation */ 1826 #define XHCI_BROKEN_PORT_PED (1 << 25) 1827 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) 1828 #define XHCI_U2_DISABLE_WAKE (1 << 27) 1829 #define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) 1830 #define XHCI_HW_LPM_DISABLE (1 << 29) 1831 #define XHCI_SUSPEND_DELAY (1 << 30) 1832 #define XHCI_INTEL_USB_ROLE_SW (1 << 31) 1833 1834 unsigned int num_active_eps; 1835 unsigned int limit_active_eps; 1836 /* There are two roothubs to keep track of bus suspend info for */ 1837 struct xhci_bus_state bus_state[2]; 1838 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */ 1839 u8 *port_array; 1840 /* Array of pointers to USB 3.0 PORTSC registers */ 1841 __le32 __iomem **usb3_ports; 1842 unsigned int num_usb3_ports; 1843 /* Array of pointers to USB 2.0 PORTSC registers */ 1844 __le32 __iomem **usb2_ports; 1845 struct xhci_hub usb2_rhub; 1846 struct xhci_hub usb3_rhub; 1847 unsigned int num_usb2_ports; 1848 /* support xHCI 0.96 spec USB2 software LPM */ 1849 unsigned sw_lpm_support:1; 1850 /* support xHCI 1.0 spec USB2 hardware LPM */ 1851 unsigned hw_lpm_support:1; 1852 /* cached usb2 extened protocol capabilites */ 1853 u32 *ext_caps; 1854 unsigned int num_ext_caps; 1855 /* Compliance Mode Recovery Data */ 1856 struct timer_list comp_mode_recovery_timer; 1857 u32 port_status_u0; 1858 u16 test_mode; 1859 /* Compliance Mode Timer Triggered every 2 seconds */ 1860 #define COMP_MODE_RCVRY_MSECS 2000 1861 1862 struct dentry *debugfs_root; 1863 struct dentry *debugfs_slots; 1864 struct list_head regset_list; 1865 1866 void *dbc; 1867 /* platform-specific data -- must come last */ 1868 unsigned long priv[0] __aligned(sizeof(s64)); 1869 }; 1870 1871 /* Platform specific overrides to generic XHCI hc_driver ops */ 1872 struct xhci_driver_overrides { 1873 size_t extra_priv_size; 1874 int (*reset)(struct usb_hcd *hcd); 1875 int (*start)(struct usb_hcd *hcd); 1876 }; 1877 1878 #define XHCI_CFC_DELAY 10 1879 1880 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 1881 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd) 1882 { 1883 struct usb_hcd *primary_hcd; 1884 1885 if (usb_hcd_is_primary_hcd(hcd)) 1886 primary_hcd = hcd; 1887 else 1888 primary_hcd = hcd->primary_hcd; 1889 1890 return (struct xhci_hcd *) (primary_hcd->hcd_priv); 1891 } 1892 1893 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci) 1894 { 1895 return xhci->main_hcd; 1896 } 1897 1898 #define xhci_dbg(xhci, fmt, args...) \ 1899 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1900 #define xhci_err(xhci, fmt, args...) \ 1901 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1902 #define xhci_warn(xhci, fmt, args...) \ 1903 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1904 #define xhci_warn_ratelimited(xhci, fmt, args...) \ 1905 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1906 #define xhci_info(xhci, fmt, args...) \ 1907 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args) 1908 1909 /* 1910 * Registers should always be accessed with double word or quad word accesses. 1911 * 1912 * Some xHCI implementations may support 64-bit address pointers. Registers 1913 * with 64-bit address pointers should be written to with dword accesses by 1914 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second. 1915 * xHCI implementations that do not support 64-bit address pointers will ignore 1916 * the high dword, and write order is irrelevant. 1917 */ 1918 static inline u64 xhci_read_64(const struct xhci_hcd *xhci, 1919 __le64 __iomem *regs) 1920 { 1921 return lo_hi_readq(regs); 1922 } 1923 static inline void xhci_write_64(struct xhci_hcd *xhci, 1924 const u64 val, __le64 __iomem *regs) 1925 { 1926 lo_hi_writeq(val, regs); 1927 } 1928 1929 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci) 1930 { 1931 return xhci->quirks & XHCI_LINK_TRB_QUIRK; 1932 } 1933 1934 /* xHCI debugging */ 1935 char *xhci_get_slot_state(struct xhci_hcd *xhci, 1936 struct xhci_container_ctx *ctx); 1937 void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *), 1938 const char *fmt, ...); 1939 1940 /* xHCI memory management */ 1941 void xhci_mem_cleanup(struct xhci_hcd *xhci); 1942 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags); 1943 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id); 1944 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags); 1945 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev); 1946 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci, 1947 struct usb_device *udev); 1948 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc); 1949 unsigned int xhci_get_endpoint_address(unsigned int ep_index); 1950 unsigned int xhci_last_valid_endpoint(u32 added_ctxs); 1951 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep); 1952 void xhci_update_tt_active_eps(struct xhci_hcd *xhci, 1953 struct xhci_virt_device *virt_dev, 1954 int old_active_eps); 1955 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info); 1956 void xhci_update_bw_info(struct xhci_hcd *xhci, 1957 struct xhci_container_ctx *in_ctx, 1958 struct xhci_input_control_ctx *ctrl_ctx, 1959 struct xhci_virt_device *virt_dev); 1960 void xhci_endpoint_copy(struct xhci_hcd *xhci, 1961 struct xhci_container_ctx *in_ctx, 1962 struct xhci_container_ctx *out_ctx, 1963 unsigned int ep_index); 1964 void xhci_slot_copy(struct xhci_hcd *xhci, 1965 struct xhci_container_ctx *in_ctx, 1966 struct xhci_container_ctx *out_ctx); 1967 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, 1968 struct usb_device *udev, struct usb_host_endpoint *ep, 1969 gfp_t mem_flags); 1970 struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci, 1971 unsigned int num_segs, unsigned int cycle_state, 1972 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags); 1973 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring); 1974 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring, 1975 unsigned int num_trbs, gfp_t flags); 1976 int xhci_alloc_erst(struct xhci_hcd *xhci, 1977 struct xhci_ring *evt_ring, 1978 struct xhci_erst *erst, 1979 gfp_t flags); 1980 void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst); 1981 void xhci_free_endpoint_ring(struct xhci_hcd *xhci, 1982 struct xhci_virt_device *virt_dev, 1983 unsigned int ep_index); 1984 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci, 1985 unsigned int num_stream_ctxs, 1986 unsigned int num_streams, 1987 unsigned int max_packet, gfp_t flags); 1988 void xhci_free_stream_info(struct xhci_hcd *xhci, 1989 struct xhci_stream_info *stream_info); 1990 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci, 1991 struct xhci_ep_ctx *ep_ctx, 1992 struct xhci_stream_info *stream_info); 1993 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx, 1994 struct xhci_virt_ep *ep); 1995 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci, 1996 struct xhci_virt_device *virt_dev, bool drop_control_ep); 1997 struct xhci_ring *xhci_dma_to_transfer_ring( 1998 struct xhci_virt_ep *ep, 1999 u64 address); 2000 struct xhci_ring *xhci_stream_id_to_ring( 2001 struct xhci_virt_device *dev, 2002 unsigned int ep_index, 2003 unsigned int stream_id); 2004 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci, 2005 bool allocate_completion, gfp_t mem_flags); 2006 struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci, 2007 bool allocate_completion, gfp_t mem_flags); 2008 void xhci_urb_free_priv(struct urb_priv *urb_priv); 2009 void xhci_free_command(struct xhci_hcd *xhci, 2010 struct xhci_command *command); 2011 struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci, 2012 int type, gfp_t flags); 2013 void xhci_free_container_ctx(struct xhci_hcd *xhci, 2014 struct xhci_container_ctx *ctx); 2015 2016 /* xHCI host controller glue */ 2017 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *); 2018 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec); 2019 void xhci_quiesce(struct xhci_hcd *xhci); 2020 int xhci_halt(struct xhci_hcd *xhci); 2021 int xhci_start(struct xhci_hcd *xhci); 2022 int xhci_reset(struct xhci_hcd *xhci); 2023 int xhci_run(struct usb_hcd *hcd); 2024 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks); 2025 void xhci_init_driver(struct hc_driver *drv, 2026 const struct xhci_driver_overrides *over); 2027 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id); 2028 int xhci_ext_cap_init(struct xhci_hcd *xhci); 2029 2030 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup); 2031 int xhci_resume(struct xhci_hcd *xhci, bool hibernated); 2032 2033 irqreturn_t xhci_irq(struct usb_hcd *hcd); 2034 irqreturn_t xhci_msi_irq(int irq, void *hcd); 2035 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev); 2036 int xhci_alloc_tt_info(struct xhci_hcd *xhci, 2037 struct xhci_virt_device *virt_dev, 2038 struct usb_device *hdev, 2039 struct usb_tt *tt, gfp_t mem_flags); 2040 2041 /* xHCI ring, segment, TRB, and TD functions */ 2042 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb); 2043 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci, 2044 struct xhci_segment *start_seg, union xhci_trb *start_trb, 2045 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug); 2046 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code); 2047 void xhci_ring_cmd_db(struct xhci_hcd *xhci); 2048 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd, 2049 u32 trb_type, u32 slot_id); 2050 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2051 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev); 2052 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd, 2053 u32 field1, u32 field2, u32 field3, u32 field4); 2054 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd, 2055 int slot_id, unsigned int ep_index, int suspend); 2056 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2057 int slot_id, unsigned int ep_index); 2058 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2059 int slot_id, unsigned int ep_index); 2060 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb, 2061 int slot_id, unsigned int ep_index); 2062 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags, 2063 struct urb *urb, int slot_id, unsigned int ep_index); 2064 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, 2065 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id, 2066 bool command_must_succeed); 2067 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd, 2068 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed); 2069 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd, 2070 int slot_id, unsigned int ep_index, 2071 enum xhci_ep_reset_type reset_type); 2072 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd, 2073 u32 slot_id); 2074 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci, 2075 unsigned int slot_id, unsigned int ep_index, 2076 unsigned int stream_id, struct xhci_td *cur_td, 2077 struct xhci_dequeue_state *state); 2078 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci, 2079 unsigned int slot_id, unsigned int ep_index, 2080 struct xhci_dequeue_state *deq_state); 2081 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index, 2082 unsigned int stream_id, struct xhci_td *td); 2083 void xhci_stop_endpoint_command_watchdog(struct timer_list *t); 2084 void xhci_handle_command_timeout(struct work_struct *work); 2085 2086 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id, 2087 unsigned int ep_index, unsigned int stream_id); 2088 void xhci_cleanup_command_queue(struct xhci_hcd *xhci); 2089 void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring); 2090 unsigned int count_trbs(u64 addr, u64 len); 2091 2092 /* xHCI roothub code */ 2093 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2094 int port_id, u32 link_state); 2095 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array, 2096 int port_id, u32 port_bit); 2097 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, 2098 char *buf, u16 wLength); 2099 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf); 2100 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1); 2101 void xhci_hc_died(struct xhci_hcd *xhci); 2102 2103 #ifdef CONFIG_PM 2104 int xhci_bus_suspend(struct usb_hcd *hcd); 2105 int xhci_bus_resume(struct usb_hcd *hcd); 2106 #else 2107 #define xhci_bus_suspend NULL 2108 #define xhci_bus_resume NULL 2109 #endif /* CONFIG_PM */ 2110 2111 u32 xhci_port_state_to_neutral(u32 state); 2112 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci, 2113 u16 port); 2114 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id); 2115 2116 /* xHCI contexts */ 2117 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx); 2118 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx); 2119 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index); 2120 2121 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci, 2122 unsigned int slot_id, unsigned int ep_index, 2123 unsigned int stream_id); 2124 2125 static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci, 2126 struct urb *urb) 2127 { 2128 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id, 2129 xhci_get_endpoint_index(&urb->ep->desc), 2130 urb->stream_id); 2131 } 2132 2133 static inline char *xhci_slot_state_string(u32 state) 2134 { 2135 switch (state) { 2136 case SLOT_STATE_ENABLED: 2137 return "enabled/disabled"; 2138 case SLOT_STATE_DEFAULT: 2139 return "default"; 2140 case SLOT_STATE_ADDRESSED: 2141 return "addressed"; 2142 case SLOT_STATE_CONFIGURED: 2143 return "configured"; 2144 default: 2145 return "reserved"; 2146 } 2147 } 2148 2149 static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2, 2150 u32 field3) 2151 { 2152 static char str[256]; 2153 int type = TRB_FIELD_TO_TYPE(field3); 2154 2155 switch (type) { 2156 case TRB_LINK: 2157 sprintf(str, 2158 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c", 2159 field1, field0, GET_INTR_TARGET(field2), 2160 xhci_trb_type_string(type), 2161 field3 & TRB_IOC ? 'I' : 'i', 2162 field3 & TRB_CHAIN ? 'C' : 'c', 2163 field3 & TRB_TC ? 'T' : 't', 2164 field3 & TRB_CYCLE ? 'C' : 'c'); 2165 break; 2166 case TRB_TRANSFER: 2167 case TRB_COMPLETION: 2168 case TRB_PORT_STATUS: 2169 case TRB_BANDWIDTH_EVENT: 2170 case TRB_DOORBELL: 2171 case TRB_HC_EVENT: 2172 case TRB_DEV_NOTE: 2173 case TRB_MFINDEX_WRAP: 2174 sprintf(str, 2175 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c", 2176 field1, field0, 2177 xhci_trb_comp_code_string(GET_COMP_CODE(field2)), 2178 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3), 2179 /* Macro decrements 1, maybe it shouldn't?!? */ 2180 TRB_TO_EP_INDEX(field3) + 1, 2181 xhci_trb_type_string(type), 2182 field3 & EVENT_DATA ? 'E' : 'e', 2183 field3 & TRB_CYCLE ? 'C' : 'c'); 2184 2185 break; 2186 case TRB_SETUP: 2187 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c", 2188 field0 & 0xff, 2189 (field0 & 0xff00) >> 8, 2190 (field0 & 0xff000000) >> 24, 2191 (field0 & 0xff0000) >> 16, 2192 (field1 & 0xff00) >> 8, 2193 field1 & 0xff, 2194 (field1 & 0xff000000) >> 16 | 2195 (field1 & 0xff0000) >> 16, 2196 TRB_LEN(field2), GET_TD_SIZE(field2), 2197 GET_INTR_TARGET(field2), 2198 xhci_trb_type_string(type), 2199 field3 & TRB_IDT ? 'I' : 'i', 2200 field3 & TRB_IOC ? 'I' : 'i', 2201 field3 & TRB_CYCLE ? 'C' : 'c'); 2202 break; 2203 case TRB_DATA: 2204 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c", 2205 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2206 GET_INTR_TARGET(field2), 2207 xhci_trb_type_string(type), 2208 field3 & TRB_IDT ? 'I' : 'i', 2209 field3 & TRB_IOC ? 'I' : 'i', 2210 field3 & TRB_CHAIN ? 'C' : 'c', 2211 field3 & TRB_NO_SNOOP ? 'S' : 's', 2212 field3 & TRB_ISP ? 'I' : 'i', 2213 field3 & TRB_ENT ? 'E' : 'e', 2214 field3 & TRB_CYCLE ? 'C' : 'c'); 2215 break; 2216 case TRB_STATUS: 2217 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c", 2218 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2219 GET_INTR_TARGET(field2), 2220 xhci_trb_type_string(type), 2221 field3 & TRB_IOC ? 'I' : 'i', 2222 field3 & TRB_CHAIN ? 'C' : 'c', 2223 field3 & TRB_ENT ? 'E' : 'e', 2224 field3 & TRB_CYCLE ? 'C' : 'c'); 2225 break; 2226 case TRB_NORMAL: 2227 case TRB_ISOC: 2228 case TRB_EVENT_DATA: 2229 case TRB_TR_NOOP: 2230 sprintf(str, 2231 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c", 2232 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2), 2233 GET_INTR_TARGET(field2), 2234 xhci_trb_type_string(type), 2235 field3 & TRB_BEI ? 'B' : 'b', 2236 field3 & TRB_IDT ? 'I' : 'i', 2237 field3 & TRB_IOC ? 'I' : 'i', 2238 field3 & TRB_CHAIN ? 'C' : 'c', 2239 field3 & TRB_NO_SNOOP ? 'S' : 's', 2240 field3 & TRB_ISP ? 'I' : 'i', 2241 field3 & TRB_ENT ? 'E' : 'e', 2242 field3 & TRB_CYCLE ? 'C' : 'c'); 2243 break; 2244 2245 case TRB_CMD_NOOP: 2246 case TRB_ENABLE_SLOT: 2247 sprintf(str, 2248 "%s: flags %c", 2249 xhci_trb_type_string(type), 2250 field3 & TRB_CYCLE ? 'C' : 'c'); 2251 break; 2252 case TRB_DISABLE_SLOT: 2253 case TRB_NEG_BANDWIDTH: 2254 sprintf(str, 2255 "%s: slot %d flags %c", 2256 xhci_trb_type_string(type), 2257 TRB_TO_SLOT_ID(field3), 2258 field3 & TRB_CYCLE ? 'C' : 'c'); 2259 break; 2260 case TRB_ADDR_DEV: 2261 sprintf(str, 2262 "%s: ctx %08x%08x slot %d flags %c:%c", 2263 xhci_trb_type_string(type), 2264 field1, field0, 2265 TRB_TO_SLOT_ID(field3), 2266 field3 & TRB_BSR ? 'B' : 'b', 2267 field3 & TRB_CYCLE ? 'C' : 'c'); 2268 break; 2269 case TRB_CONFIG_EP: 2270 sprintf(str, 2271 "%s: ctx %08x%08x slot %d flags %c:%c", 2272 xhci_trb_type_string(type), 2273 field1, field0, 2274 TRB_TO_SLOT_ID(field3), 2275 field3 & TRB_DC ? 'D' : 'd', 2276 field3 & TRB_CYCLE ? 'C' : 'c'); 2277 break; 2278 case TRB_EVAL_CONTEXT: 2279 sprintf(str, 2280 "%s: ctx %08x%08x slot %d flags %c", 2281 xhci_trb_type_string(type), 2282 field1, field0, 2283 TRB_TO_SLOT_ID(field3), 2284 field3 & TRB_CYCLE ? 'C' : 'c'); 2285 break; 2286 case TRB_RESET_EP: 2287 sprintf(str, 2288 "%s: ctx %08x%08x slot %d ep %d flags %c", 2289 xhci_trb_type_string(type), 2290 field1, field0, 2291 TRB_TO_SLOT_ID(field3), 2292 /* Macro decrements 1, maybe it shouldn't?!? */ 2293 TRB_TO_EP_INDEX(field3) + 1, 2294 field3 & TRB_CYCLE ? 'C' : 'c'); 2295 break; 2296 case TRB_STOP_RING: 2297 sprintf(str, 2298 "%s: slot %d sp %d ep %d flags %c", 2299 xhci_trb_type_string(type), 2300 TRB_TO_SLOT_ID(field3), 2301 TRB_TO_SUSPEND_PORT(field3), 2302 /* Macro decrements 1, maybe it shouldn't?!? */ 2303 TRB_TO_EP_INDEX(field3) + 1, 2304 field3 & TRB_CYCLE ? 'C' : 'c'); 2305 break; 2306 case TRB_SET_DEQ: 2307 sprintf(str, 2308 "%s: deq %08x%08x stream %d slot %d ep %d flags %c", 2309 xhci_trb_type_string(type), 2310 field1, field0, 2311 TRB_TO_STREAM_ID(field2), 2312 TRB_TO_SLOT_ID(field3), 2313 /* Macro decrements 1, maybe it shouldn't?!? */ 2314 TRB_TO_EP_INDEX(field3) + 1, 2315 field3 & TRB_CYCLE ? 'C' : 'c'); 2316 break; 2317 case TRB_RESET_DEV: 2318 sprintf(str, 2319 "%s: slot %d flags %c", 2320 xhci_trb_type_string(type), 2321 TRB_TO_SLOT_ID(field3), 2322 field3 & TRB_CYCLE ? 'C' : 'c'); 2323 break; 2324 case TRB_FORCE_EVENT: 2325 sprintf(str, 2326 "%s: event %08x%08x vf intr %d vf id %d flags %c", 2327 xhci_trb_type_string(type), 2328 field1, field0, 2329 TRB_TO_VF_INTR_TARGET(field2), 2330 TRB_TO_VF_ID(field3), 2331 field3 & TRB_CYCLE ? 'C' : 'c'); 2332 break; 2333 case TRB_SET_LT: 2334 sprintf(str, 2335 "%s: belt %d flags %c", 2336 xhci_trb_type_string(type), 2337 TRB_TO_BELT(field3), 2338 field3 & TRB_CYCLE ? 'C' : 'c'); 2339 break; 2340 case TRB_GET_BW: 2341 sprintf(str, 2342 "%s: ctx %08x%08x slot %d speed %d flags %c", 2343 xhci_trb_type_string(type), 2344 field1, field0, 2345 TRB_TO_SLOT_ID(field3), 2346 TRB_TO_DEV_SPEED(field3), 2347 field3 & TRB_CYCLE ? 'C' : 'c'); 2348 break; 2349 case TRB_FORCE_HEADER: 2350 sprintf(str, 2351 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c", 2352 xhci_trb_type_string(type), 2353 field2, field1, field0 & 0xffffffe0, 2354 TRB_TO_PACKET_TYPE(field0), 2355 TRB_TO_ROOTHUB_PORT(field3), 2356 field3 & TRB_CYCLE ? 'C' : 'c'); 2357 break; 2358 default: 2359 sprintf(str, 2360 "type '%s' -> raw %08x %08x %08x %08x", 2361 xhci_trb_type_string(type), 2362 field0, field1, field2, field3); 2363 } 2364 2365 return str; 2366 } 2367 2368 static inline const char *xhci_decode_slot_context(u32 info, u32 info2, 2369 u32 tt_info, u32 state) 2370 { 2371 static char str[1024]; 2372 u32 speed; 2373 u32 hub; 2374 u32 mtt; 2375 int ret = 0; 2376 2377 speed = info & DEV_SPEED; 2378 hub = info & DEV_HUB; 2379 mtt = info & DEV_MTT; 2380 2381 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d", 2382 info & ROUTE_STRING_MASK, 2383 ({ char *s; 2384 switch (speed) { 2385 case SLOT_SPEED_FS: 2386 s = "full-speed"; 2387 break; 2388 case SLOT_SPEED_LS: 2389 s = "low-speed"; 2390 break; 2391 case SLOT_SPEED_HS: 2392 s = "high-speed"; 2393 break; 2394 case SLOT_SPEED_SS: 2395 s = "super-speed"; 2396 break; 2397 case SLOT_SPEED_SSP: 2398 s = "super-speed plus"; 2399 break; 2400 default: 2401 s = "UNKNOWN speed"; 2402 } s; }), 2403 mtt ? " multi-TT" : "", 2404 hub ? " Hub" : "", 2405 (info & LAST_CTX_MASK) >> 27, 2406 info2 & MAX_EXIT, 2407 DEVINFO_TO_ROOT_HUB_PORT(info2), 2408 DEVINFO_TO_MAX_PORTS(info2)); 2409 2410 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s", 2411 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8, 2412 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info), 2413 state & DEV_ADDR_MASK, 2414 xhci_slot_state_string(GET_SLOT_STATE(state))); 2415 2416 return str; 2417 } 2418 2419 2420 static inline const char *xhci_portsc_link_state_string(u32 portsc) 2421 { 2422 switch (portsc & PORT_PLS_MASK) { 2423 case XDEV_U0: 2424 return "U0"; 2425 case XDEV_U1: 2426 return "U1"; 2427 case XDEV_U2: 2428 return "U2"; 2429 case XDEV_U3: 2430 return "U3"; 2431 case XDEV_DISABLED: 2432 return "Disabled"; 2433 case XDEV_RXDETECT: 2434 return "RxDetect"; 2435 case XDEV_INACTIVE: 2436 return "Inactive"; 2437 case XDEV_POLLING: 2438 return "Polling"; 2439 case XDEV_RECOVERY: 2440 return "Recovery"; 2441 case XDEV_HOT_RESET: 2442 return "Hot Reset"; 2443 case XDEV_COMP_MODE: 2444 return "Compliance mode"; 2445 case XDEV_TEST_MODE: 2446 return "Test mode"; 2447 case XDEV_RESUME: 2448 return "Resume"; 2449 default: 2450 break; 2451 } 2452 return "Unknown"; 2453 } 2454 2455 static inline const char *xhci_decode_portsc(u32 portsc) 2456 { 2457 static char str[256]; 2458 int ret; 2459 2460 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ", 2461 portsc & PORT_POWER ? "Powered" : "Powered-off", 2462 portsc & PORT_CONNECT ? "Connected" : "Not-connected", 2463 portsc & PORT_PE ? "Enabled" : "Disabled", 2464 xhci_portsc_link_state_string(portsc), 2465 DEV_PORT_SPEED(portsc)); 2466 2467 if (portsc & PORT_OC) 2468 ret += sprintf(str + ret, "OverCurrent "); 2469 if (portsc & PORT_RESET) 2470 ret += sprintf(str + ret, "In-Reset "); 2471 2472 ret += sprintf(str + ret, "Change: "); 2473 if (portsc & PORT_CSC) 2474 ret += sprintf(str + ret, "CSC "); 2475 if (portsc & PORT_PEC) 2476 ret += sprintf(str + ret, "PEC "); 2477 if (portsc & PORT_WRC) 2478 ret += sprintf(str + ret, "WRC "); 2479 if (portsc & PORT_OCC) 2480 ret += sprintf(str + ret, "OCC "); 2481 if (portsc & PORT_RC) 2482 ret += sprintf(str + ret, "PRC "); 2483 if (portsc & PORT_PLC) 2484 ret += sprintf(str + ret, "PLC "); 2485 if (portsc & PORT_CEC) 2486 ret += sprintf(str + ret, "CEC "); 2487 if (portsc & PORT_CAS) 2488 ret += sprintf(str + ret, "CAS "); 2489 2490 ret += sprintf(str + ret, "Wake: "); 2491 if (portsc & PORT_WKCONN_E) 2492 ret += sprintf(str + ret, "WCE "); 2493 if (portsc & PORT_WKDISC_E) 2494 ret += sprintf(str + ret, "WDE "); 2495 if (portsc & PORT_WKOC_E) 2496 ret += sprintf(str + ret, "WOE "); 2497 2498 return str; 2499 } 2500 2501 static inline const char *xhci_ep_state_string(u8 state) 2502 { 2503 switch (state) { 2504 case EP_STATE_DISABLED: 2505 return "disabled"; 2506 case EP_STATE_RUNNING: 2507 return "running"; 2508 case EP_STATE_HALTED: 2509 return "halted"; 2510 case EP_STATE_STOPPED: 2511 return "stopped"; 2512 case EP_STATE_ERROR: 2513 return "error"; 2514 default: 2515 return "INVALID"; 2516 } 2517 } 2518 2519 static inline const char *xhci_ep_type_string(u8 type) 2520 { 2521 switch (type) { 2522 case ISOC_OUT_EP: 2523 return "Isoc OUT"; 2524 case BULK_OUT_EP: 2525 return "Bulk OUT"; 2526 case INT_OUT_EP: 2527 return "Int OUT"; 2528 case CTRL_EP: 2529 return "Ctrl"; 2530 case ISOC_IN_EP: 2531 return "Isoc IN"; 2532 case BULK_IN_EP: 2533 return "Bulk IN"; 2534 case INT_IN_EP: 2535 return "Int IN"; 2536 default: 2537 return "INVALID"; 2538 } 2539 } 2540 2541 static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq, 2542 u32 tx_info) 2543 { 2544 static char str[1024]; 2545 int ret; 2546 2547 u32 esit; 2548 u16 maxp; 2549 u16 avg; 2550 2551 u8 max_pstr; 2552 u8 ep_state; 2553 u8 interval; 2554 u8 ep_type; 2555 u8 burst; 2556 u8 cerr; 2557 u8 mult; 2558 2559 bool lsa; 2560 bool hid; 2561 2562 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 | 2563 CTX_TO_MAX_ESIT_PAYLOAD(tx_info); 2564 2565 ep_state = info & EP_STATE_MASK; 2566 max_pstr = CTX_TO_EP_MAXPSTREAMS(info); 2567 interval = CTX_TO_EP_INTERVAL(info); 2568 mult = CTX_TO_EP_MULT(info) + 1; 2569 lsa = !!(info & EP_HAS_LSA); 2570 2571 cerr = (info2 & (3 << 1)) >> 1; 2572 ep_type = CTX_TO_EP_TYPE(info2); 2573 hid = !!(info2 & (1 << 7)); 2574 burst = CTX_TO_MAX_BURST(info2); 2575 maxp = MAX_PACKET_DECODED(info2); 2576 2577 avg = EP_AVG_TRB_LENGTH(tx_info); 2578 2579 ret = sprintf(str, "State %s mult %d max P. Streams %d %s", 2580 xhci_ep_state_string(ep_state), mult, 2581 max_pstr, lsa ? "LSA " : ""); 2582 2583 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ", 2584 (1 << interval) * 125, esit, cerr); 2585 2586 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ", 2587 xhci_ep_type_string(ep_type), hid ? "HID" : "", 2588 burst, maxp, deq); 2589 2590 ret += sprintf(str + ret, "avg trb len %d", avg); 2591 2592 return str; 2593 } 2594 2595 #endif /* __LINUX_XHCI_HCD_H */ 2596