1 /* 2 * MediaTek xHCI Host Controller Driver 3 * 4 * Copyright (c) 2015 MediaTek Inc. 5 * Author: 6 * Chunfeng Yun <chunfeng.yun@mediatek.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/iopoll.h> 22 #include <linux/kernel.h> 23 #include <linux/mfd/syscon.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/phy/phy.h> 27 #include <linux/platform_device.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regmap.h> 30 #include <linux/regulator/consumer.h> 31 32 #include "xhci.h" 33 #include "xhci-mtk.h" 34 35 /* ip_pw_ctrl0 register */ 36 #define CTRL0_IP_SW_RST BIT(0) 37 38 /* ip_pw_ctrl1 register */ 39 #define CTRL1_IP_HOST_PDN BIT(0) 40 41 /* ip_pw_ctrl2 register */ 42 #define CTRL2_IP_DEV_PDN BIT(0) 43 44 /* ip_pw_sts1 register */ 45 #define STS1_IP_SLEEP_STS BIT(30) 46 #define STS1_XHCI_RST BIT(11) 47 #define STS1_SYS125_RST BIT(10) 48 #define STS1_REF_RST BIT(8) 49 #define STS1_SYSPLL_STABLE BIT(0) 50 51 /* ip_xhci_cap register */ 52 #define CAP_U3_PORT_NUM(p) ((p) & 0xff) 53 #define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff) 54 55 /* u3_ctrl_p register */ 56 #define CTRL_U3_PORT_HOST_SEL BIT(2) 57 #define CTRL_U3_PORT_PDN BIT(1) 58 #define CTRL_U3_PORT_DIS BIT(0) 59 60 /* u2_ctrl_p register */ 61 #define CTRL_U2_PORT_HOST_SEL BIT(2) 62 #define CTRL_U2_PORT_PDN BIT(1) 63 #define CTRL_U2_PORT_DIS BIT(0) 64 65 /* u2_phy_pll register */ 66 #define CTRL_U2_FORCE_PLL_STB BIT(28) 67 68 #define PERI_WK_CTRL0 0x400 69 #define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */ 70 #define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/ 71 #define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1) 72 #define UWK_CTL1_1P_LS_E BIT(0) 73 74 #define PERI_WK_CTRL1 0x404 75 #define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26) 76 #define UWK_CTL1_IS_E BIT(25) 77 #define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21) 78 #define UWK_CTL1_0P_LS_E BIT(20) 79 #define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */ 80 #define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */ 81 #define UWK_CTL1_IDDIG_P BIT(9) /* polarity */ 82 #define UWK_CTL1_0P_LS_P BIT(7) 83 #define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */ 84 85 enum ssusb_wakeup_src { 86 SSUSB_WK_IP_SLEEP = 1, 87 SSUSB_WK_LINE_STATE = 2, 88 }; 89 90 static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk) 91 { 92 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 93 u32 value, check_val; 94 int ret; 95 int i; 96 97 if (!mtk->has_ippc) 98 return 0; 99 100 /* power on host ip */ 101 value = readl(&ippc->ip_pw_ctr1); 102 value &= ~CTRL1_IP_HOST_PDN; 103 writel(value, &ippc->ip_pw_ctr1); 104 105 /* power on and enable all u3 ports */ 106 for (i = 0; i < mtk->num_u3_ports; i++) { 107 value = readl(&ippc->u3_ctrl_p[i]); 108 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); 109 value |= CTRL_U3_PORT_HOST_SEL; 110 writel(value, &ippc->u3_ctrl_p[i]); 111 } 112 113 /* power on and enable all u2 ports */ 114 for (i = 0; i < mtk->num_u2_ports; i++) { 115 value = readl(&ippc->u2_ctrl_p[i]); 116 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); 117 value |= CTRL_U2_PORT_HOST_SEL; 118 writel(value, &ippc->u2_ctrl_p[i]); 119 } 120 121 /* 122 * wait for clocks to be stable, and clock domains reset to 123 * be inactive after power on and enable ports 124 */ 125 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST | 126 STS1_SYS125_RST | STS1_XHCI_RST; 127 128 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 129 (check_val == (value & check_val)), 100, 20000); 130 if (ret) { 131 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value); 132 return ret; 133 } 134 135 return 0; 136 } 137 138 static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk) 139 { 140 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 141 u32 value; 142 int ret; 143 int i; 144 145 if (!mtk->has_ippc) 146 return 0; 147 148 /* power down all u3 ports */ 149 for (i = 0; i < mtk->num_u3_ports; i++) { 150 value = readl(&ippc->u3_ctrl_p[i]); 151 value |= CTRL_U3_PORT_PDN; 152 writel(value, &ippc->u3_ctrl_p[i]); 153 } 154 155 /* power down all u2 ports */ 156 for (i = 0; i < mtk->num_u2_ports; i++) { 157 value = readl(&ippc->u2_ctrl_p[i]); 158 value |= CTRL_U2_PORT_PDN; 159 writel(value, &ippc->u2_ctrl_p[i]); 160 } 161 162 /* power down host ip */ 163 value = readl(&ippc->ip_pw_ctr1); 164 value |= CTRL1_IP_HOST_PDN; 165 writel(value, &ippc->ip_pw_ctr1); 166 167 /* wait for host ip to sleep */ 168 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value, 169 (value & STS1_IP_SLEEP_STS), 100, 100000); 170 if (ret) { 171 dev_err(mtk->dev, "ip sleep failed!!!\n"); 172 return ret; 173 } 174 return 0; 175 } 176 177 static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk) 178 { 179 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs; 180 u32 value; 181 182 if (!mtk->has_ippc) 183 return 0; 184 185 /* reset whole ip */ 186 value = readl(&ippc->ip_pw_ctr0); 187 value |= CTRL0_IP_SW_RST; 188 writel(value, &ippc->ip_pw_ctr0); 189 udelay(1); 190 value = readl(&ippc->ip_pw_ctr0); 191 value &= ~CTRL0_IP_SW_RST; 192 writel(value, &ippc->ip_pw_ctr0); 193 194 /* 195 * device ip is default power-on in fact 196 * power down device ip, otherwise ip-sleep will fail 197 */ 198 value = readl(&ippc->ip_pw_ctr2); 199 value |= CTRL2_IP_DEV_PDN; 200 writel(value, &ippc->ip_pw_ctr2); 201 202 value = readl(&ippc->ip_xhci_cap); 203 mtk->num_u3_ports = CAP_U3_PORT_NUM(value); 204 mtk->num_u2_ports = CAP_U2_PORT_NUM(value); 205 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__, 206 mtk->num_u2_ports, mtk->num_u3_ports); 207 208 return xhci_mtk_host_enable(mtk); 209 } 210 211 static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk) 212 { 213 int ret; 214 215 ret = clk_prepare_enable(mtk->sys_clk); 216 if (ret) { 217 dev_err(mtk->dev, "failed to enable sys_clk\n"); 218 goto sys_clk_err; 219 } 220 221 if (mtk->wakeup_src) { 222 ret = clk_prepare_enable(mtk->wk_deb_p0); 223 if (ret) { 224 dev_err(mtk->dev, "failed to enable wk_deb_p0\n"); 225 goto usb_p0_err; 226 } 227 228 ret = clk_prepare_enable(mtk->wk_deb_p1); 229 if (ret) { 230 dev_err(mtk->dev, "failed to enable wk_deb_p1\n"); 231 goto usb_p1_err; 232 } 233 } 234 return 0; 235 236 usb_p1_err: 237 clk_disable_unprepare(mtk->wk_deb_p0); 238 usb_p0_err: 239 clk_disable_unprepare(mtk->sys_clk); 240 sys_clk_err: 241 return -EINVAL; 242 } 243 244 static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk) 245 { 246 if (mtk->wakeup_src) { 247 clk_disable_unprepare(mtk->wk_deb_p1); 248 clk_disable_unprepare(mtk->wk_deb_p0); 249 } 250 clk_disable_unprepare(mtk->sys_clk); 251 } 252 253 /* only clocks can be turn off for ip-sleep wakeup mode */ 254 static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk) 255 { 256 u32 tmp; 257 struct regmap *pericfg = mtk->pericfg; 258 259 regmap_read(pericfg, PERI_WK_CTRL1, &tmp); 260 tmp &= ~UWK_CTL1_IS_P; 261 tmp &= ~(UWK_CTL1_IS_C(0xf)); 262 tmp |= UWK_CTL1_IS_C(0x8); 263 regmap_write(pericfg, PERI_WK_CTRL1, tmp); 264 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E); 265 266 regmap_read(pericfg, PERI_WK_CTRL1, &tmp); 267 dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n", 268 __func__, tmp); 269 } 270 271 static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk) 272 { 273 u32 tmp; 274 275 regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp); 276 tmp &= ~UWK_CTL1_IS_E; 277 regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp); 278 } 279 280 /* 281 * for line-state wakeup mode, phy's power should not power-down 282 * and only support cable plug in/out 283 */ 284 static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk) 285 { 286 u32 tmp; 287 struct regmap *pericfg = mtk->pericfg; 288 289 /* line-state of u2-port0 */ 290 regmap_read(pericfg, PERI_WK_CTRL1, &tmp); 291 tmp &= ~UWK_CTL1_0P_LS_P; 292 tmp &= ~(UWK_CTL1_0P_LS_C(0xf)); 293 tmp |= UWK_CTL1_0P_LS_C(0x8); 294 regmap_write(pericfg, PERI_WK_CTRL1, tmp); 295 regmap_read(pericfg, PERI_WK_CTRL1, &tmp); 296 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E); 297 298 /* line-state of u2-port1 */ 299 regmap_read(pericfg, PERI_WK_CTRL0, &tmp); 300 tmp &= ~(UWK_CTL1_1P_LS_C(0xf)); 301 tmp |= UWK_CTL1_1P_LS_C(0x8); 302 regmap_write(pericfg, PERI_WK_CTRL0, tmp); 303 regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E); 304 } 305 306 static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk) 307 { 308 u32 tmp; 309 struct regmap *pericfg = mtk->pericfg; 310 311 /* line-state of u2-port0 */ 312 regmap_read(pericfg, PERI_WK_CTRL1, &tmp); 313 tmp &= ~UWK_CTL1_0P_LS_E; 314 regmap_write(pericfg, PERI_WK_CTRL1, tmp); 315 316 /* line-state of u2-port1 */ 317 regmap_read(pericfg, PERI_WK_CTRL0, &tmp); 318 tmp &= ~UWK_CTL1_1P_LS_E; 319 regmap_write(pericfg, PERI_WK_CTRL0, tmp); 320 } 321 322 static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk) 323 { 324 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) 325 usb_wakeup_ip_sleep_en(mtk); 326 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) 327 usb_wakeup_line_state_en(mtk); 328 } 329 330 static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk) 331 { 332 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP) 333 usb_wakeup_ip_sleep_dis(mtk); 334 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE) 335 usb_wakeup_line_state_dis(mtk); 336 } 337 338 static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk, 339 struct device_node *dn) 340 { 341 struct device *dev = mtk->dev; 342 343 /* 344 * wakeup function is optional, so it is not an error if this property 345 * does not exist, and in such case, no need to get relative 346 * properties anymore. 347 */ 348 of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src); 349 if (!mtk->wakeup_src) 350 return 0; 351 352 mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0"); 353 if (IS_ERR(mtk->wk_deb_p0)) { 354 dev_err(dev, "fail to get wakeup_deb_p0\n"); 355 return PTR_ERR(mtk->wk_deb_p0); 356 } 357 358 mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1"); 359 if (IS_ERR(mtk->wk_deb_p1)) { 360 dev_err(dev, "fail to get wakeup_deb_p1\n"); 361 return PTR_ERR(mtk->wk_deb_p1); 362 } 363 364 mtk->pericfg = syscon_regmap_lookup_by_phandle(dn, 365 "mediatek,syscon-wakeup"); 366 if (IS_ERR(mtk->pericfg)) { 367 dev_err(dev, "fail to get pericfg regs\n"); 368 return PTR_ERR(mtk->pericfg); 369 } 370 371 return 0; 372 } 373 374 static int xhci_mtk_setup(struct usb_hcd *hcd); 375 static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = { 376 .extra_priv_size = sizeof(struct xhci_hcd), 377 .reset = xhci_mtk_setup, 378 }; 379 380 static struct hc_driver __read_mostly xhci_mtk_hc_driver; 381 382 static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk) 383 { 384 int i; 385 int ret; 386 387 for (i = 0; i < mtk->num_phys; i++) { 388 ret = phy_init(mtk->phys[i]); 389 if (ret) 390 goto exit_phy; 391 } 392 return 0; 393 394 exit_phy: 395 for (; i > 0; i--) 396 phy_exit(mtk->phys[i - 1]); 397 398 return ret; 399 } 400 401 static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk) 402 { 403 int i; 404 405 for (i = 0; i < mtk->num_phys; i++) 406 phy_exit(mtk->phys[i]); 407 408 return 0; 409 } 410 411 static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk) 412 { 413 int i; 414 int ret; 415 416 for (i = 0; i < mtk->num_phys; i++) { 417 ret = phy_power_on(mtk->phys[i]); 418 if (ret) 419 goto power_off_phy; 420 } 421 return 0; 422 423 power_off_phy: 424 for (; i > 0; i--) 425 phy_power_off(mtk->phys[i - 1]); 426 427 return ret; 428 } 429 430 static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk) 431 { 432 unsigned int i; 433 434 for (i = 0; i < mtk->num_phys; i++) 435 phy_power_off(mtk->phys[i]); 436 } 437 438 static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk) 439 { 440 int ret; 441 442 ret = regulator_enable(mtk->vbus); 443 if (ret) { 444 dev_err(mtk->dev, "failed to enable vbus\n"); 445 return ret; 446 } 447 448 ret = regulator_enable(mtk->vusb33); 449 if (ret) { 450 dev_err(mtk->dev, "failed to enable vusb33\n"); 451 regulator_disable(mtk->vbus); 452 return ret; 453 } 454 return 0; 455 } 456 457 static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk) 458 { 459 regulator_disable(mtk->vbus); 460 regulator_disable(mtk->vusb33); 461 } 462 463 static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci) 464 { 465 struct usb_hcd *hcd = xhci_to_hcd(xhci); 466 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 467 468 /* 469 * As of now platform drivers don't provide MSI support so we ensure 470 * here that the generic code does not try to make a pci_dev from our 471 * dev struct in order to setup MSI 472 */ 473 xhci->quirks |= XHCI_PLAT; 474 xhci->quirks |= XHCI_MTK_HOST; 475 /* 476 * MTK host controller gives a spurious successful event after a 477 * short transfer. Ignore it. 478 */ 479 xhci->quirks |= XHCI_SPURIOUS_SUCCESS; 480 if (mtk->lpm_support) 481 xhci->quirks |= XHCI_LPM_SUPPORT; 482 } 483 484 /* called during probe() after chip reset completes */ 485 static int xhci_mtk_setup(struct usb_hcd *hcd) 486 { 487 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 488 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); 489 int ret; 490 491 if (usb_hcd_is_primary_hcd(hcd)) { 492 ret = xhci_mtk_ssusb_config(mtk); 493 if (ret) 494 return ret; 495 } 496 497 ret = xhci_gen_setup(hcd, xhci_mtk_quirks); 498 if (ret) 499 return ret; 500 501 if (usb_hcd_is_primary_hcd(hcd)) { 502 mtk->num_u3_ports = xhci->num_usb3_ports; 503 mtk->num_u2_ports = xhci->num_usb2_ports; 504 ret = xhci_mtk_sch_init(mtk); 505 if (ret) 506 return ret; 507 } 508 509 return ret; 510 } 511 512 static int xhci_mtk_probe(struct platform_device *pdev) 513 { 514 struct device *dev = &pdev->dev; 515 struct device_node *node = dev->of_node; 516 struct xhci_hcd_mtk *mtk; 517 const struct hc_driver *driver; 518 struct xhci_hcd *xhci; 519 struct resource *res; 520 struct usb_hcd *hcd; 521 struct phy *phy; 522 int phy_num; 523 int ret = -ENODEV; 524 int irq; 525 526 if (usb_disabled()) 527 return -ENODEV; 528 529 driver = &xhci_mtk_hc_driver; 530 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 531 if (!mtk) 532 return -ENOMEM; 533 534 mtk->dev = dev; 535 mtk->vbus = devm_regulator_get(dev, "vbus"); 536 if (IS_ERR(mtk->vbus)) { 537 dev_err(dev, "fail to get vbus\n"); 538 return PTR_ERR(mtk->vbus); 539 } 540 541 mtk->vusb33 = devm_regulator_get(dev, "vusb33"); 542 if (IS_ERR(mtk->vusb33)) { 543 dev_err(dev, "fail to get vusb33\n"); 544 return PTR_ERR(mtk->vusb33); 545 } 546 547 mtk->sys_clk = devm_clk_get(dev, "sys_ck"); 548 if (IS_ERR(mtk->sys_clk)) { 549 dev_err(dev, "fail to get sys_ck\n"); 550 return PTR_ERR(mtk->sys_clk); 551 } 552 553 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable"); 554 555 ret = usb_wakeup_of_property_parse(mtk, node); 556 if (ret) 557 return ret; 558 559 mtk->num_phys = of_count_phandle_with_args(node, 560 "phys", "#phy-cells"); 561 if (mtk->num_phys > 0) { 562 mtk->phys = devm_kcalloc(dev, mtk->num_phys, 563 sizeof(*mtk->phys), GFP_KERNEL); 564 if (!mtk->phys) 565 return -ENOMEM; 566 } else { 567 mtk->num_phys = 0; 568 } 569 pm_runtime_enable(dev); 570 pm_runtime_get_sync(dev); 571 device_enable_async_suspend(dev); 572 573 ret = xhci_mtk_ldos_enable(mtk); 574 if (ret) 575 goto disable_pm; 576 577 ret = xhci_mtk_clks_enable(mtk); 578 if (ret) 579 goto disable_ldos; 580 581 irq = platform_get_irq(pdev, 0); 582 if (irq < 0) 583 goto disable_clk; 584 585 /* Initialize dma_mask and coherent_dma_mask to 32-bits */ 586 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); 587 if (ret) 588 goto disable_clk; 589 590 if (!dev->dma_mask) 591 dev->dma_mask = &dev->coherent_dma_mask; 592 else 593 dma_set_mask(dev, DMA_BIT_MASK(32)); 594 595 hcd = usb_create_hcd(driver, dev, dev_name(dev)); 596 if (!hcd) { 597 ret = -ENOMEM; 598 goto disable_clk; 599 } 600 601 /* 602 * USB 2.0 roothub is stored in the platform_device. 603 * Swap it with mtk HCD. 604 */ 605 mtk->hcd = platform_get_drvdata(pdev); 606 platform_set_drvdata(pdev, mtk); 607 608 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac"); 609 hcd->regs = devm_ioremap_resource(dev, res); 610 if (IS_ERR(hcd->regs)) { 611 ret = PTR_ERR(hcd->regs); 612 goto put_usb2_hcd; 613 } 614 hcd->rsrc_start = res->start; 615 hcd->rsrc_len = resource_size(res); 616 617 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); 618 if (res) { /* ippc register is optional */ 619 mtk->ippc_regs = devm_ioremap_resource(dev, res); 620 if (IS_ERR(mtk->ippc_regs)) { 621 ret = PTR_ERR(mtk->ippc_regs); 622 goto put_usb2_hcd; 623 } 624 mtk->has_ippc = true; 625 } else { 626 mtk->has_ippc = false; 627 } 628 629 for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) { 630 phy = devm_of_phy_get_by_index(dev, node, phy_num); 631 if (IS_ERR(phy)) { 632 ret = PTR_ERR(phy); 633 goto put_usb2_hcd; 634 } 635 mtk->phys[phy_num] = phy; 636 } 637 638 ret = xhci_mtk_phy_init(mtk); 639 if (ret) 640 goto put_usb2_hcd; 641 642 ret = xhci_mtk_phy_power_on(mtk); 643 if (ret) 644 goto exit_phys; 645 646 device_init_wakeup(dev, true); 647 648 xhci = hcd_to_xhci(hcd); 649 xhci->main_hcd = hcd; 650 xhci->shared_hcd = usb_create_shared_hcd(driver, dev, 651 dev_name(dev), hcd); 652 if (!xhci->shared_hcd) { 653 ret = -ENOMEM; 654 goto power_off_phys; 655 } 656 657 if (HCC_MAX_PSA(xhci->hcc_params) >= 4) 658 xhci->shared_hcd->can_do_streams = 1; 659 660 ret = usb_add_hcd(hcd, irq, IRQF_SHARED); 661 if (ret) 662 goto put_usb3_hcd; 663 664 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED); 665 if (ret) 666 goto dealloc_usb2_hcd; 667 668 return 0; 669 670 dealloc_usb2_hcd: 671 usb_remove_hcd(hcd); 672 673 put_usb3_hcd: 674 xhci_mtk_sch_exit(mtk); 675 usb_put_hcd(xhci->shared_hcd); 676 677 power_off_phys: 678 xhci_mtk_phy_power_off(mtk); 679 device_init_wakeup(dev, false); 680 681 exit_phys: 682 xhci_mtk_phy_exit(mtk); 683 684 put_usb2_hcd: 685 usb_put_hcd(hcd); 686 687 disable_clk: 688 xhci_mtk_clks_disable(mtk); 689 690 disable_ldos: 691 xhci_mtk_ldos_disable(mtk); 692 693 disable_pm: 694 pm_runtime_put_sync(dev); 695 pm_runtime_disable(dev); 696 return ret; 697 } 698 699 static int xhci_mtk_remove(struct platform_device *dev) 700 { 701 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev); 702 struct usb_hcd *hcd = mtk->hcd; 703 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 704 705 usb_remove_hcd(xhci->shared_hcd); 706 xhci_mtk_phy_power_off(mtk); 707 xhci_mtk_phy_exit(mtk); 708 device_init_wakeup(&dev->dev, false); 709 710 usb_remove_hcd(hcd); 711 usb_put_hcd(xhci->shared_hcd); 712 usb_put_hcd(hcd); 713 xhci_mtk_sch_exit(mtk); 714 xhci_mtk_clks_disable(mtk); 715 xhci_mtk_ldos_disable(mtk); 716 pm_runtime_put_sync(&dev->dev); 717 pm_runtime_disable(&dev->dev); 718 719 return 0; 720 } 721 722 /* 723 * if ip sleep fails, and all clocks are disabled, access register will hang 724 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend. 725 * and no need to check whether ip sleep failed or not; this will cause SPM 726 * to wake up system immediately after system suspend complete if ip sleep 727 * fails, it is what we wanted. 728 */ 729 static int __maybe_unused xhci_mtk_suspend(struct device *dev) 730 { 731 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 732 struct usb_hcd *hcd = mtk->hcd; 733 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 734 735 xhci_dbg(xhci, "%s: stop port polling\n", __func__); 736 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags); 737 del_timer_sync(&hcd->rh_timer); 738 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 739 del_timer_sync(&xhci->shared_hcd->rh_timer); 740 741 xhci_mtk_host_disable(mtk); 742 xhci_mtk_phy_power_off(mtk); 743 xhci_mtk_clks_disable(mtk); 744 usb_wakeup_enable(mtk); 745 return 0; 746 } 747 748 static int __maybe_unused xhci_mtk_resume(struct device *dev) 749 { 750 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev); 751 struct usb_hcd *hcd = mtk->hcd; 752 struct xhci_hcd *xhci = hcd_to_xhci(hcd); 753 754 usb_wakeup_disable(mtk); 755 xhci_mtk_clks_enable(mtk); 756 xhci_mtk_phy_power_on(mtk); 757 xhci_mtk_host_enable(mtk); 758 759 xhci_dbg(xhci, "%s: restart port polling\n", __func__); 760 set_bit(HCD_FLAG_POLL_RH, &hcd->flags); 761 usb_hcd_poll_rh_status(hcd); 762 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags); 763 usb_hcd_poll_rh_status(xhci->shared_hcd); 764 return 0; 765 } 766 767 static const struct dev_pm_ops xhci_mtk_pm_ops = { 768 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume) 769 }; 770 #define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL 771 772 #ifdef CONFIG_OF 773 static const struct of_device_id mtk_xhci_of_match[] = { 774 { .compatible = "mediatek,mt8173-xhci"}, 775 { }, 776 }; 777 MODULE_DEVICE_TABLE(of, mtk_xhci_of_match); 778 #endif 779 780 static struct platform_driver mtk_xhci_driver = { 781 .probe = xhci_mtk_probe, 782 .remove = xhci_mtk_remove, 783 .driver = { 784 .name = "xhci-mtk", 785 .pm = DEV_PM_OPS, 786 .of_match_table = of_match_ptr(mtk_xhci_of_match), 787 }, 788 }; 789 MODULE_ALIAS("platform:xhci-mtk"); 790 791 static int __init xhci_mtk_init(void) 792 { 793 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides); 794 return platform_driver_register(&mtk_xhci_driver); 795 } 796 module_init(xhci_mtk_init); 797 798 static void __exit xhci_mtk_exit(void) 799 { 800 platform_driver_unregister(&mtk_xhci_driver); 801 } 802 module_exit(xhci_mtk_exit); 803 804 MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 805 MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver"); 806 MODULE_LICENSE("GPL v2"); 807