1e443b333SAlexander Shishkin /* 2e443b333SAlexander Shishkin * bits.h - register bits of the ChipIdea USB IP core 3e443b333SAlexander Shishkin * 4e443b333SAlexander Shishkin * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved. 5e443b333SAlexander Shishkin * 6e443b333SAlexander Shishkin * Author: David Lopo 7e443b333SAlexander Shishkin * 8e443b333SAlexander Shishkin * This program is free software; you can redistribute it and/or modify 9e443b333SAlexander Shishkin * it under the terms of the GNU General Public License version 2 as 10e443b333SAlexander Shishkin * published by the Free Software Foundation. 11e443b333SAlexander Shishkin */ 12e443b333SAlexander Shishkin 13e443b333SAlexander Shishkin #ifndef __DRIVERS_USB_CHIPIDEA_BITS_H 14e443b333SAlexander Shishkin #define __DRIVERS_USB_CHIPIDEA_BITS_H 15e443b333SAlexander Shishkin 16e443b333SAlexander Shishkin /* HCCPARAMS */ 17e443b333SAlexander Shishkin #define HCCPARAMS_LEN BIT(17) 18e443b333SAlexander Shishkin 19e443b333SAlexander Shishkin /* DCCPARAMS */ 20e443b333SAlexander Shishkin #define DCCPARAMS_DEN (0x1F << 0) 21e443b333SAlexander Shishkin #define DCCPARAMS_DC BIT(7) 22e443b333SAlexander Shishkin 23e443b333SAlexander Shishkin /* TESTMODE */ 24e443b333SAlexander Shishkin #define TESTMODE_FORCE BIT(0) 25e443b333SAlexander Shishkin 26e443b333SAlexander Shishkin /* USBCMD */ 27e443b333SAlexander Shishkin #define USBCMD_RS BIT(0) 28e443b333SAlexander Shishkin #define USBCMD_RST BIT(1) 29e443b333SAlexander Shishkin #define USBCMD_SUTW BIT(13) 30e443b333SAlexander Shishkin #define USBCMD_ATDTW BIT(14) 31e443b333SAlexander Shishkin 32e443b333SAlexander Shishkin /* USBSTS & USBINTR */ 33e443b333SAlexander Shishkin #define USBi_UI BIT(0) 34e443b333SAlexander Shishkin #define USBi_UEI BIT(1) 35e443b333SAlexander Shishkin #define USBi_PCI BIT(2) 36e443b333SAlexander Shishkin #define USBi_URI BIT(6) 37e443b333SAlexander Shishkin #define USBi_SLI BIT(8) 38e443b333SAlexander Shishkin 39e443b333SAlexander Shishkin /* DEVICEADDR */ 40e443b333SAlexander Shishkin #define DEVICEADDR_USBADRA BIT(24) 41e443b333SAlexander Shishkin #define DEVICEADDR_USBADR (0x7FUL << 25) 42e443b333SAlexander Shishkin 43e443b333SAlexander Shishkin /* PORTSC */ 44e443b333SAlexander Shishkin #define PORTSC_FPR BIT(6) 45e443b333SAlexander Shishkin #define PORTSC_SUSP BIT(7) 46e443b333SAlexander Shishkin #define PORTSC_HSP BIT(9) 47e443b333SAlexander Shishkin #define PORTSC_PTC (0x0FUL << 16) 48e443b333SAlexander Shishkin 49e443b333SAlexander Shishkin /* DEVLC */ 50e443b333SAlexander Shishkin #define DEVLC_PSPD (0x03UL << 25) 51e443b333SAlexander Shishkin #define DEVLC_PSPD_HS (0x02UL << 25) 52e443b333SAlexander Shishkin 53*5f36e231SAlexander Shishkin /* OTGSC */ 54*5f36e231SAlexander Shishkin #define OTGSC_IDPU BIT(5) 55*5f36e231SAlexander Shishkin #define OTGSC_ID BIT(8) 56*5f36e231SAlexander Shishkin #define OTGSC_AVV BIT(9) 57*5f36e231SAlexander Shishkin #define OTGSC_ASV BIT(10) 58*5f36e231SAlexander Shishkin #define OTGSC_BSV BIT(11) 59*5f36e231SAlexander Shishkin #define OTGSC_BSE BIT(12) 60*5f36e231SAlexander Shishkin #define OTGSC_IDIS BIT(16) 61*5f36e231SAlexander Shishkin #define OTGSC_AVVIS BIT(17) 62*5f36e231SAlexander Shishkin #define OTGSC_ASVIS BIT(18) 63*5f36e231SAlexander Shishkin #define OTGSC_BSVIS BIT(19) 64*5f36e231SAlexander Shishkin #define OTGSC_BSEIS BIT(20) 65*5f36e231SAlexander Shishkin #define OTGSC_IDIE BIT(24) 66*5f36e231SAlexander Shishkin #define OTGSC_AVVIE BIT(25) 67*5f36e231SAlexander Shishkin #define OTGSC_ASVIE BIT(26) 68*5f36e231SAlexander Shishkin #define OTGSC_BSVIE BIT(27) 69*5f36e231SAlexander Shishkin #define OTGSC_BSEIE BIT(28) 70*5f36e231SAlexander Shishkin 71e443b333SAlexander Shishkin /* USBMODE */ 72e443b333SAlexander Shishkin #define USBMODE_CM (0x03UL << 0) 73e443b333SAlexander Shishkin #define USBMODE_CM_IDLE (0x00UL << 0) 74e443b333SAlexander Shishkin #define USBMODE_CM_DEVICE (0x02UL << 0) 75e443b333SAlexander Shishkin #define USBMODE_CM_HOST (0x03UL << 0) 76e443b333SAlexander Shishkin #define USBMODE_SLOM BIT(3) 77e443b333SAlexander Shishkin #define USBMODE_SDIS BIT(4) 78e443b333SAlexander Shishkin 79e443b333SAlexander Shishkin /* ENDPTCTRL */ 80e443b333SAlexander Shishkin #define ENDPTCTRL_RXS BIT(0) 81e443b333SAlexander Shishkin #define ENDPTCTRL_RXT (0x03UL << 2) 82e443b333SAlexander Shishkin #define ENDPTCTRL_RXR BIT(6) /* reserved for port 0 */ 83e443b333SAlexander Shishkin #define ENDPTCTRL_RXE BIT(7) 84e443b333SAlexander Shishkin #define ENDPTCTRL_TXS BIT(16) 85e443b333SAlexander Shishkin #define ENDPTCTRL_TXT (0x03UL << 18) 86e443b333SAlexander Shishkin #define ENDPTCTRL_TXR BIT(22) /* reserved for port 0 */ 87e443b333SAlexander Shishkin #define ENDPTCTRL_TXE BIT(23) 88e443b333SAlexander Shishkin 89e443b333SAlexander Shishkin #endif /* __DRIVERS_USB_CHIPIDEA_BITS_H */ 90