1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller driver Core 4 * Copyright (C) 2011-2013 Samsung India Software Operations 5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <linux/async.h> 13 #include <linux/devfreq.h> 14 #include <linux/nls.h> 15 #include <linux/of.h> 16 #include <linux/bitfield.h> 17 #include <linux/blk-pm.h> 18 #include <linux/blkdev.h> 19 #include <linux/clk.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/pm_opp.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/sched/clock.h> 26 #include <linux/iopoll.h> 27 #include <scsi/scsi_cmnd.h> 28 #include <scsi/scsi_dbg.h> 29 #include <scsi/scsi_driver.h> 30 #include <scsi/scsi_eh.h> 31 #include "ufshcd-priv.h" 32 #include <ufs/ufs_quirks.h> 33 #include <ufs/unipro.h> 34 #include "ufs-sysfs.h" 35 #include "ufs-debugfs.h" 36 #include "ufs-fault-injection.h" 37 #include "ufs_bsg.h" 38 #include "ufshcd-crypto.h" 39 #include <asm/unaligned.h> 40 41 #define CREATE_TRACE_POINTS 42 #include <trace/events/ufs.h> 43 44 #define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\ 45 UTP_TASK_REQ_COMPL |\ 46 UFSHCD_ERROR_MASK) 47 48 #define UFSHCD_ENABLE_MCQ_INTRS (UTP_TASK_REQ_COMPL |\ 49 UFSHCD_ERROR_MASK |\ 50 MCQ_CQ_EVENT_STATUS) 51 52 53 /* UIC command timeout, unit: ms */ 54 #define UIC_CMD_TIMEOUT 500 55 56 /* NOP OUT retries waiting for NOP IN response */ 57 #define NOP_OUT_RETRIES 10 58 /* Timeout after 50 msecs if NOP OUT hangs without response */ 59 #define NOP_OUT_TIMEOUT 50 /* msecs */ 60 61 /* Query request retries */ 62 #define QUERY_REQ_RETRIES 3 63 /* Query request timeout */ 64 #define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */ 65 66 /* Advanced RPMB request timeout */ 67 #define ADVANCED_RPMB_REQ_TIMEOUT 3000 /* 3 seconds */ 68 69 /* Task management command timeout */ 70 #define TM_CMD_TIMEOUT 100 /* msecs */ 71 72 /* maximum number of retries for a general UIC command */ 73 #define UFS_UIC_COMMAND_RETRIES 3 74 75 /* maximum number of link-startup retries */ 76 #define DME_LINKSTARTUP_RETRIES 3 77 78 /* maximum number of reset retries before giving up */ 79 #define MAX_HOST_RESET_RETRIES 5 80 81 /* Maximum number of error handler retries before giving up */ 82 #define MAX_ERR_HANDLER_RETRIES 5 83 84 /* Expose the flag value from utp_upiu_query.value */ 85 #define MASK_QUERY_UPIU_FLAG_LOC 0xFF 86 87 /* Interrupt aggregation default timeout, unit: 40us */ 88 #define INT_AGGR_DEF_TO 0x02 89 90 /* default delay of autosuspend: 2000 ms */ 91 #define RPM_AUTOSUSPEND_DELAY_MS 2000 92 93 /* Default delay of RPM device flush delayed work */ 94 #define RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS 5000 95 96 /* Default value of wait time before gating device ref clock */ 97 #define UFSHCD_REF_CLK_GATING_WAIT_US 0xFF /* microsecs */ 98 99 /* Polling time to wait for fDeviceInit */ 100 #define FDEVICEINIT_COMPL_TIMEOUT 1500 /* millisecs */ 101 102 /* UFSHC 4.0 compliant HC support this mode. */ 103 static bool use_mcq_mode = true; 104 105 static bool is_mcq_supported(struct ufs_hba *hba) 106 { 107 return hba->mcq_sup && use_mcq_mode; 108 } 109 110 module_param(use_mcq_mode, bool, 0644); 111 MODULE_PARM_DESC(use_mcq_mode, "Control MCQ mode for controllers starting from UFSHCI 4.0. 1 - enable MCQ, 0 - disable MCQ. MCQ is enabled by default"); 112 113 #define ufshcd_toggle_vreg(_dev, _vreg, _on) \ 114 ({ \ 115 int _ret; \ 116 if (_on) \ 117 _ret = ufshcd_enable_vreg(_dev, _vreg); \ 118 else \ 119 _ret = ufshcd_disable_vreg(_dev, _vreg); \ 120 _ret; \ 121 }) 122 123 #define ufshcd_hex_dump(prefix_str, buf, len) do { \ 124 size_t __len = (len); \ 125 print_hex_dump(KERN_ERR, prefix_str, \ 126 __len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE,\ 127 16, 4, buf, __len, false); \ 128 } while (0) 129 130 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, 131 const char *prefix) 132 { 133 u32 *regs; 134 size_t pos; 135 136 if (offset % 4 != 0 || len % 4 != 0) /* keep readl happy */ 137 return -EINVAL; 138 139 regs = kzalloc(len, GFP_ATOMIC); 140 if (!regs) 141 return -ENOMEM; 142 143 for (pos = 0; pos < len; pos += 4) { 144 if (offset == 0 && 145 pos >= REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER && 146 pos <= REG_UIC_ERROR_CODE_DME) 147 continue; 148 regs[pos / 4] = ufshcd_readl(hba, offset + pos); 149 } 150 151 ufshcd_hex_dump(prefix, regs, len); 152 kfree(regs); 153 154 return 0; 155 } 156 EXPORT_SYMBOL_GPL(ufshcd_dump_regs); 157 158 enum { 159 UFSHCD_MAX_CHANNEL = 0, 160 UFSHCD_MAX_ID = 1, 161 UFSHCD_CMD_PER_LUN = 32 - UFSHCD_NUM_RESERVED, 162 UFSHCD_CAN_QUEUE = 32 - UFSHCD_NUM_RESERVED, 163 }; 164 165 static const char *const ufshcd_state_name[] = { 166 [UFSHCD_STATE_RESET] = "reset", 167 [UFSHCD_STATE_OPERATIONAL] = "operational", 168 [UFSHCD_STATE_ERROR] = "error", 169 [UFSHCD_STATE_EH_SCHEDULED_FATAL] = "eh_fatal", 170 [UFSHCD_STATE_EH_SCHEDULED_NON_FATAL] = "eh_non_fatal", 171 }; 172 173 /* UFSHCD error handling flags */ 174 enum { 175 UFSHCD_EH_IN_PROGRESS = (1 << 0), 176 }; 177 178 /* UFSHCD UIC layer error flags */ 179 enum { 180 UFSHCD_UIC_DL_PA_INIT_ERROR = (1 << 0), /* Data link layer error */ 181 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR = (1 << 1), /* Data link layer error */ 182 UFSHCD_UIC_DL_TCx_REPLAY_ERROR = (1 << 2), /* Data link layer error */ 183 UFSHCD_UIC_NL_ERROR = (1 << 3), /* Network layer error */ 184 UFSHCD_UIC_TL_ERROR = (1 << 4), /* Transport Layer error */ 185 UFSHCD_UIC_DME_ERROR = (1 << 5), /* DME error */ 186 UFSHCD_UIC_PA_GENERIC_ERROR = (1 << 6), /* Generic PA error */ 187 }; 188 189 #define ufshcd_set_eh_in_progress(h) \ 190 ((h)->eh_flags |= UFSHCD_EH_IN_PROGRESS) 191 #define ufshcd_eh_in_progress(h) \ 192 ((h)->eh_flags & UFSHCD_EH_IN_PROGRESS) 193 #define ufshcd_clear_eh_in_progress(h) \ 194 ((h)->eh_flags &= ~UFSHCD_EH_IN_PROGRESS) 195 196 const struct ufs_pm_lvl_states ufs_pm_lvl_states[] = { 197 [UFS_PM_LVL_0] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 198 [UFS_PM_LVL_1] = {UFS_ACTIVE_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 199 [UFS_PM_LVL_2] = {UFS_SLEEP_PWR_MODE, UIC_LINK_ACTIVE_STATE}, 200 [UFS_PM_LVL_3] = {UFS_SLEEP_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 201 [UFS_PM_LVL_4] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_HIBERN8_STATE}, 202 [UFS_PM_LVL_5] = {UFS_POWERDOWN_PWR_MODE, UIC_LINK_OFF_STATE}, 203 /* 204 * For DeepSleep, the link is first put in hibern8 and then off. 205 * Leaving the link in hibern8 is not supported. 206 */ 207 [UFS_PM_LVL_6] = {UFS_DEEPSLEEP_PWR_MODE, UIC_LINK_OFF_STATE}, 208 }; 209 210 static inline enum ufs_dev_pwr_mode 211 ufs_get_pm_lvl_to_dev_pwr_mode(enum ufs_pm_level lvl) 212 { 213 return ufs_pm_lvl_states[lvl].dev_state; 214 } 215 216 static inline enum uic_link_state 217 ufs_get_pm_lvl_to_link_pwr_state(enum ufs_pm_level lvl) 218 { 219 return ufs_pm_lvl_states[lvl].link_state; 220 } 221 222 static inline enum ufs_pm_level 223 ufs_get_desired_pm_lvl_for_dev_link_state(enum ufs_dev_pwr_mode dev_state, 224 enum uic_link_state link_state) 225 { 226 enum ufs_pm_level lvl; 227 228 for (lvl = UFS_PM_LVL_0; lvl < UFS_PM_LVL_MAX; lvl++) { 229 if ((ufs_pm_lvl_states[lvl].dev_state == dev_state) && 230 (ufs_pm_lvl_states[lvl].link_state == link_state)) 231 return lvl; 232 } 233 234 /* if no match found, return the level 0 */ 235 return UFS_PM_LVL_0; 236 } 237 238 static const struct ufs_dev_quirk ufs_fixups[] = { 239 /* UFS cards deviations table */ 240 { .wmanufacturerid = UFS_VENDOR_MICRON, 241 .model = UFS_ANY_MODEL, 242 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 243 { .wmanufacturerid = UFS_VENDOR_SAMSUNG, 244 .model = UFS_ANY_MODEL, 245 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM | 246 UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE | 247 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS }, 248 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 249 .model = UFS_ANY_MODEL, 250 .quirk = UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME }, 251 { .wmanufacturerid = UFS_VENDOR_SKHYNIX, 252 .model = "hB8aL1" /*H28U62301AMR*/, 253 .quirk = UFS_DEVICE_QUIRK_HOST_VS_DEBUGSAVECONFIGTIME }, 254 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 255 .model = UFS_ANY_MODEL, 256 .quirk = UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM }, 257 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 258 .model = "THGLF2G9C8KBADG", 259 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 260 { .wmanufacturerid = UFS_VENDOR_TOSHIBA, 261 .model = "THGLF2G9D8KBADG", 262 .quirk = UFS_DEVICE_QUIRK_PA_TACTIVATE }, 263 {} 264 }; 265 266 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba); 267 static void ufshcd_async_scan(void *data, async_cookie_t cookie); 268 static int ufshcd_reset_and_restore(struct ufs_hba *hba); 269 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd); 270 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag); 271 static void ufshcd_hba_exit(struct ufs_hba *hba); 272 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params); 273 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on); 274 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba); 275 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba); 276 static void ufshcd_resume_clkscaling(struct ufs_hba *hba); 277 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba); 278 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 279 bool scale_up); 280 static irqreturn_t ufshcd_intr(int irq, void *__hba); 281 static int ufshcd_change_power_mode(struct ufs_hba *hba, 282 struct ufs_pa_layer_attr *pwr_mode); 283 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on); 284 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on); 285 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 286 struct ufs_vreg *vreg); 287 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 288 bool enable); 289 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba); 290 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba); 291 292 static inline void ufshcd_enable_irq(struct ufs_hba *hba) 293 { 294 if (!hba->is_irq_enabled) { 295 enable_irq(hba->irq); 296 hba->is_irq_enabled = true; 297 } 298 } 299 300 static inline void ufshcd_disable_irq(struct ufs_hba *hba) 301 { 302 if (hba->is_irq_enabled) { 303 disable_irq(hba->irq); 304 hba->is_irq_enabled = false; 305 } 306 } 307 308 static void ufshcd_configure_wb(struct ufs_hba *hba) 309 { 310 if (!ufshcd_is_wb_allowed(hba)) 311 return; 312 313 ufshcd_wb_toggle(hba, true); 314 315 ufshcd_wb_toggle_buf_flush_during_h8(hba, true); 316 317 if (ufshcd_is_wb_buf_flush_allowed(hba)) 318 ufshcd_wb_toggle_buf_flush(hba, true); 319 } 320 321 static void ufshcd_scsi_unblock_requests(struct ufs_hba *hba) 322 { 323 if (atomic_dec_and_test(&hba->scsi_block_reqs_cnt)) 324 scsi_unblock_requests(hba->host); 325 } 326 327 static void ufshcd_scsi_block_requests(struct ufs_hba *hba) 328 { 329 if (atomic_inc_return(&hba->scsi_block_reqs_cnt) == 1) 330 scsi_block_requests(hba->host); 331 } 332 333 static void ufshcd_add_cmd_upiu_trace(struct ufs_hba *hba, unsigned int tag, 334 enum ufs_trace_str_t str_t) 335 { 336 struct utp_upiu_req *rq = hba->lrb[tag].ucd_req_ptr; 337 struct utp_upiu_header *header; 338 339 if (!trace_ufshcd_upiu_enabled()) 340 return; 341 342 if (str_t == UFS_CMD_SEND) 343 header = &rq->header; 344 else 345 header = &hba->lrb[tag].ucd_rsp_ptr->header; 346 347 trace_ufshcd_upiu(dev_name(hba->dev), str_t, header, &rq->sc.cdb, 348 UFS_TSF_CDB); 349 } 350 351 static void ufshcd_add_query_upiu_trace(struct ufs_hba *hba, 352 enum ufs_trace_str_t str_t, 353 struct utp_upiu_req *rq_rsp) 354 { 355 if (!trace_ufshcd_upiu_enabled()) 356 return; 357 358 trace_ufshcd_upiu(dev_name(hba->dev), str_t, &rq_rsp->header, 359 &rq_rsp->qr, UFS_TSF_OSF); 360 } 361 362 static void ufshcd_add_tm_upiu_trace(struct ufs_hba *hba, unsigned int tag, 363 enum ufs_trace_str_t str_t) 364 { 365 struct utp_task_req_desc *descp = &hba->utmrdl_base_addr[tag]; 366 367 if (!trace_ufshcd_upiu_enabled()) 368 return; 369 370 if (str_t == UFS_TM_SEND) 371 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 372 &descp->upiu_req.req_header, 373 &descp->upiu_req.input_param1, 374 UFS_TSF_TM_INPUT); 375 else 376 trace_ufshcd_upiu(dev_name(hba->dev), str_t, 377 &descp->upiu_rsp.rsp_header, 378 &descp->upiu_rsp.output_param1, 379 UFS_TSF_TM_OUTPUT); 380 } 381 382 static void ufshcd_add_uic_command_trace(struct ufs_hba *hba, 383 const struct uic_command *ucmd, 384 enum ufs_trace_str_t str_t) 385 { 386 u32 cmd; 387 388 if (!trace_ufshcd_uic_command_enabled()) 389 return; 390 391 if (str_t == UFS_CMD_SEND) 392 cmd = ucmd->command; 393 else 394 cmd = ufshcd_readl(hba, REG_UIC_COMMAND); 395 396 trace_ufshcd_uic_command(dev_name(hba->dev), str_t, cmd, 397 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_1), 398 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2), 399 ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3)); 400 } 401 402 static void ufshcd_add_command_trace(struct ufs_hba *hba, unsigned int tag, 403 enum ufs_trace_str_t str_t) 404 { 405 u64 lba = 0; 406 u8 opcode = 0, group_id = 0; 407 u32 doorbell = 0; 408 u32 intr; 409 int hwq_id = -1; 410 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 411 struct scsi_cmnd *cmd = lrbp->cmd; 412 struct request *rq = scsi_cmd_to_rq(cmd); 413 int transfer_len = -1; 414 415 if (!cmd) 416 return; 417 418 /* trace UPIU also */ 419 ufshcd_add_cmd_upiu_trace(hba, tag, str_t); 420 if (!trace_ufshcd_command_enabled()) 421 return; 422 423 opcode = cmd->cmnd[0]; 424 425 if (opcode == READ_10 || opcode == WRITE_10) { 426 /* 427 * Currently we only fully trace read(10) and write(10) commands 428 */ 429 transfer_len = 430 be32_to_cpu(lrbp->ucd_req_ptr->sc.exp_data_transfer_len); 431 lba = scsi_get_lba(cmd); 432 if (opcode == WRITE_10) 433 group_id = lrbp->cmd->cmnd[6]; 434 } else if (opcode == UNMAP) { 435 /* 436 * The number of Bytes to be unmapped beginning with the lba. 437 */ 438 transfer_len = blk_rq_bytes(rq); 439 lba = scsi_get_lba(cmd); 440 } 441 442 intr = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 443 444 if (is_mcq_enabled(hba)) { 445 struct ufs_hw_queue *hwq = ufshcd_mcq_req_to_hwq(hba, rq); 446 447 hwq_id = hwq->id; 448 } else { 449 doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 450 } 451 trace_ufshcd_command(cmd->device, str_t, tag, doorbell, hwq_id, 452 transfer_len, intr, lba, opcode, group_id); 453 } 454 455 static void ufshcd_print_clk_freqs(struct ufs_hba *hba) 456 { 457 struct ufs_clk_info *clki; 458 struct list_head *head = &hba->clk_list_head; 459 460 if (list_empty(head)) 461 return; 462 463 list_for_each_entry(clki, head, list) { 464 if (!IS_ERR_OR_NULL(clki->clk) && clki->min_freq && 465 clki->max_freq) 466 dev_err(hba->dev, "clk: %s, rate: %u\n", 467 clki->name, clki->curr_freq); 468 } 469 } 470 471 static void ufshcd_print_evt(struct ufs_hba *hba, u32 id, 472 const char *err_name) 473 { 474 int i; 475 bool found = false; 476 const struct ufs_event_hist *e; 477 478 if (id >= UFS_EVT_CNT) 479 return; 480 481 e = &hba->ufs_stats.event[id]; 482 483 for (i = 0; i < UFS_EVENT_HIST_LENGTH; i++) { 484 int p = (i + e->pos) % UFS_EVENT_HIST_LENGTH; 485 486 if (e->tstamp[p] == 0) 487 continue; 488 dev_err(hba->dev, "%s[%d] = 0x%x at %lld us\n", err_name, p, 489 e->val[p], div_u64(e->tstamp[p], 1000)); 490 found = true; 491 } 492 493 if (!found) 494 dev_err(hba->dev, "No record of %s\n", err_name); 495 else 496 dev_err(hba->dev, "%s: total cnt=%llu\n", err_name, e->cnt); 497 } 498 499 static void ufshcd_print_evt_hist(struct ufs_hba *hba) 500 { 501 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 502 503 ufshcd_print_evt(hba, UFS_EVT_PA_ERR, "pa_err"); 504 ufshcd_print_evt(hba, UFS_EVT_DL_ERR, "dl_err"); 505 ufshcd_print_evt(hba, UFS_EVT_NL_ERR, "nl_err"); 506 ufshcd_print_evt(hba, UFS_EVT_TL_ERR, "tl_err"); 507 ufshcd_print_evt(hba, UFS_EVT_DME_ERR, "dme_err"); 508 ufshcd_print_evt(hba, UFS_EVT_AUTO_HIBERN8_ERR, 509 "auto_hibern8_err"); 510 ufshcd_print_evt(hba, UFS_EVT_FATAL_ERR, "fatal_err"); 511 ufshcd_print_evt(hba, UFS_EVT_LINK_STARTUP_FAIL, 512 "link_startup_fail"); 513 ufshcd_print_evt(hba, UFS_EVT_RESUME_ERR, "resume_fail"); 514 ufshcd_print_evt(hba, UFS_EVT_SUSPEND_ERR, 515 "suspend_fail"); 516 ufshcd_print_evt(hba, UFS_EVT_WL_RES_ERR, "wlun resume_fail"); 517 ufshcd_print_evt(hba, UFS_EVT_WL_SUSP_ERR, 518 "wlun suspend_fail"); 519 ufshcd_print_evt(hba, UFS_EVT_DEV_RESET, "dev_reset"); 520 ufshcd_print_evt(hba, UFS_EVT_HOST_RESET, "host_reset"); 521 ufshcd_print_evt(hba, UFS_EVT_ABORT, "task_abort"); 522 523 ufshcd_vops_dbg_register_dump(hba); 524 } 525 526 static 527 void ufshcd_print_tr(struct ufs_hba *hba, int tag, bool pr_prdt) 528 { 529 const struct ufshcd_lrb *lrbp; 530 int prdt_length; 531 532 lrbp = &hba->lrb[tag]; 533 534 dev_err(hba->dev, "UPIU[%d] - issue time %lld us\n", 535 tag, div_u64(lrbp->issue_time_stamp_local_clock, 1000)); 536 dev_err(hba->dev, "UPIU[%d] - complete time %lld us\n", 537 tag, div_u64(lrbp->compl_time_stamp_local_clock, 1000)); 538 dev_err(hba->dev, 539 "UPIU[%d] - Transfer Request Descriptor phys@0x%llx\n", 540 tag, (u64)lrbp->utrd_dma_addr); 541 542 ufshcd_hex_dump("UPIU TRD: ", lrbp->utr_descriptor_ptr, 543 sizeof(struct utp_transfer_req_desc)); 544 dev_err(hba->dev, "UPIU[%d] - Request UPIU phys@0x%llx\n", tag, 545 (u64)lrbp->ucd_req_dma_addr); 546 ufshcd_hex_dump("UPIU REQ: ", lrbp->ucd_req_ptr, 547 sizeof(struct utp_upiu_req)); 548 dev_err(hba->dev, "UPIU[%d] - Response UPIU phys@0x%llx\n", tag, 549 (u64)lrbp->ucd_rsp_dma_addr); 550 ufshcd_hex_dump("UPIU RSP: ", lrbp->ucd_rsp_ptr, 551 sizeof(struct utp_upiu_rsp)); 552 553 prdt_length = le16_to_cpu( 554 lrbp->utr_descriptor_ptr->prd_table_length); 555 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 556 prdt_length /= ufshcd_sg_entry_size(hba); 557 558 dev_err(hba->dev, 559 "UPIU[%d] - PRDT - %d entries phys@0x%llx\n", 560 tag, prdt_length, 561 (u64)lrbp->ucd_prdt_dma_addr); 562 563 if (pr_prdt) 564 ufshcd_hex_dump("UPIU PRDT: ", lrbp->ucd_prdt_ptr, 565 ufshcd_sg_entry_size(hba) * prdt_length); 566 } 567 568 static bool ufshcd_print_tr_iter(struct request *req, void *priv) 569 { 570 struct scsi_device *sdev = req->q->queuedata; 571 struct Scsi_Host *shost = sdev->host; 572 struct ufs_hba *hba = shost_priv(shost); 573 574 ufshcd_print_tr(hba, req->tag, *(bool *)priv); 575 576 return true; 577 } 578 579 /** 580 * ufshcd_print_trs_all - print trs for all started requests. 581 * @hba: per-adapter instance. 582 * @pr_prdt: need to print prdt or not. 583 */ 584 static void ufshcd_print_trs_all(struct ufs_hba *hba, bool pr_prdt) 585 { 586 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_print_tr_iter, &pr_prdt); 587 } 588 589 static void ufshcd_print_tmrs(struct ufs_hba *hba, unsigned long bitmap) 590 { 591 int tag; 592 593 for_each_set_bit(tag, &bitmap, hba->nutmrs) { 594 struct utp_task_req_desc *tmrdp = &hba->utmrdl_base_addr[tag]; 595 596 dev_err(hba->dev, "TM[%d] - Task Management Header\n", tag); 597 ufshcd_hex_dump("", tmrdp, sizeof(*tmrdp)); 598 } 599 } 600 601 static void ufshcd_print_host_state(struct ufs_hba *hba) 602 { 603 const struct scsi_device *sdev_ufs = hba->ufs_device_wlun; 604 605 dev_err(hba->dev, "UFS Host state=%d\n", hba->ufshcd_state); 606 dev_err(hba->dev, "outstanding reqs=0x%lx tasks=0x%lx\n", 607 hba->outstanding_reqs, hba->outstanding_tasks); 608 dev_err(hba->dev, "saved_err=0x%x, saved_uic_err=0x%x\n", 609 hba->saved_err, hba->saved_uic_err); 610 dev_err(hba->dev, "Device power mode=%d, UIC link state=%d\n", 611 hba->curr_dev_pwr_mode, hba->uic_link_state); 612 dev_err(hba->dev, "PM in progress=%d, sys. suspended=%d\n", 613 hba->pm_op_in_progress, hba->is_sys_suspended); 614 dev_err(hba->dev, "Auto BKOPS=%d, Host self-block=%d\n", 615 hba->auto_bkops_enabled, hba->host->host_self_blocked); 616 dev_err(hba->dev, "Clk gate=%d\n", hba->clk_gating.state); 617 dev_err(hba->dev, 618 "last_hibern8_exit_tstamp at %lld us, hibern8_exit_cnt=%d\n", 619 div_u64(hba->ufs_stats.last_hibern8_exit_tstamp, 1000), 620 hba->ufs_stats.hibern8_exit_cnt); 621 dev_err(hba->dev, "last intr at %lld us, last intr status=0x%x\n", 622 div_u64(hba->ufs_stats.last_intr_ts, 1000), 623 hba->ufs_stats.last_intr_status); 624 dev_err(hba->dev, "error handling flags=0x%x, req. abort count=%d\n", 625 hba->eh_flags, hba->req_abort_count); 626 dev_err(hba->dev, "hba->ufs_version=0x%x, Host capabilities=0x%x, caps=0x%x\n", 627 hba->ufs_version, hba->capabilities, hba->caps); 628 dev_err(hba->dev, "quirks=0x%x, dev. quirks=0x%x\n", hba->quirks, 629 hba->dev_quirks); 630 if (sdev_ufs) 631 dev_err(hba->dev, "UFS dev info: %.8s %.16s rev %.4s\n", 632 sdev_ufs->vendor, sdev_ufs->model, sdev_ufs->rev); 633 634 ufshcd_print_clk_freqs(hba); 635 } 636 637 /** 638 * ufshcd_print_pwr_info - print power params as saved in hba 639 * power info 640 * @hba: per-adapter instance 641 */ 642 static void ufshcd_print_pwr_info(struct ufs_hba *hba) 643 { 644 static const char * const names[] = { 645 "INVALID MODE", 646 "FAST MODE", 647 "SLOW_MODE", 648 "INVALID MODE", 649 "FASTAUTO_MODE", 650 "SLOWAUTO_MODE", 651 "INVALID MODE", 652 }; 653 654 /* 655 * Using dev_dbg to avoid messages during runtime PM to avoid 656 * never-ending cycles of messages written back to storage by user space 657 * causing runtime resume, causing more messages and so on. 658 */ 659 dev_dbg(hba->dev, "%s:[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n", 660 __func__, 661 hba->pwr_info.gear_rx, hba->pwr_info.gear_tx, 662 hba->pwr_info.lane_rx, hba->pwr_info.lane_tx, 663 names[hba->pwr_info.pwr_rx], 664 names[hba->pwr_info.pwr_tx], 665 hba->pwr_info.hs_rate); 666 } 667 668 static void ufshcd_device_reset(struct ufs_hba *hba) 669 { 670 int err; 671 672 err = ufshcd_vops_device_reset(hba); 673 674 if (!err) { 675 ufshcd_set_ufs_dev_active(hba); 676 if (ufshcd_is_wb_allowed(hba)) { 677 hba->dev_info.wb_enabled = false; 678 hba->dev_info.wb_buf_flush_enabled = false; 679 } 680 } 681 if (err != -EOPNOTSUPP) 682 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, err); 683 } 684 685 void ufshcd_delay_us(unsigned long us, unsigned long tolerance) 686 { 687 if (!us) 688 return; 689 690 if (us < 10) 691 udelay(us); 692 else 693 usleep_range(us, us + tolerance); 694 } 695 EXPORT_SYMBOL_GPL(ufshcd_delay_us); 696 697 /** 698 * ufshcd_wait_for_register - wait for register value to change 699 * @hba: per-adapter interface 700 * @reg: mmio register offset 701 * @mask: mask to apply to the read register value 702 * @val: value to wait for 703 * @interval_us: polling interval in microseconds 704 * @timeout_ms: timeout in milliseconds 705 * 706 * Return: -ETIMEDOUT on error, zero on success. 707 */ 708 static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask, 709 u32 val, unsigned long interval_us, 710 unsigned long timeout_ms) 711 { 712 int err = 0; 713 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); 714 715 /* ignore bits that we don't intend to wait on */ 716 val = val & mask; 717 718 while ((ufshcd_readl(hba, reg) & mask) != val) { 719 usleep_range(interval_us, interval_us + 50); 720 if (time_after(jiffies, timeout)) { 721 if ((ufshcd_readl(hba, reg) & mask) != val) 722 err = -ETIMEDOUT; 723 break; 724 } 725 } 726 727 return err; 728 } 729 730 /** 731 * ufshcd_get_intr_mask - Get the interrupt bit mask 732 * @hba: Pointer to adapter instance 733 * 734 * Return: interrupt bit mask per version 735 */ 736 static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba) 737 { 738 if (hba->ufs_version == ufshci_version(1, 0)) 739 return INTERRUPT_MASK_ALL_VER_10; 740 if (hba->ufs_version <= ufshci_version(2, 0)) 741 return INTERRUPT_MASK_ALL_VER_11; 742 743 return INTERRUPT_MASK_ALL_VER_21; 744 } 745 746 /** 747 * ufshcd_get_ufs_version - Get the UFS version supported by the HBA 748 * @hba: Pointer to adapter instance 749 * 750 * Return: UFSHCI version supported by the controller 751 */ 752 static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba) 753 { 754 u32 ufshci_ver; 755 756 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION) 757 ufshci_ver = ufshcd_vops_get_ufs_hci_version(hba); 758 else 759 ufshci_ver = ufshcd_readl(hba, REG_UFS_VERSION); 760 761 /* 762 * UFSHCI v1.x uses a different version scheme, in order 763 * to allow the use of comparisons with the ufshci_version 764 * function, we convert it to the same scheme as ufs 2.0+. 765 */ 766 if (ufshci_ver & 0x00010000) 767 return ufshci_version(1, ufshci_ver & 0x00000100); 768 769 return ufshci_ver; 770 } 771 772 /** 773 * ufshcd_is_device_present - Check if any device connected to 774 * the host controller 775 * @hba: pointer to adapter instance 776 * 777 * Return: true if device present, false if no device detected 778 */ 779 static inline bool ufshcd_is_device_present(struct ufs_hba *hba) 780 { 781 return ufshcd_readl(hba, REG_CONTROLLER_STATUS) & DEVICE_PRESENT; 782 } 783 784 /** 785 * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status 786 * @lrbp: pointer to local command reference block 787 * @cqe: pointer to the completion queue entry 788 * 789 * This function is used to get the OCS field from UTRD 790 * 791 * Return: the OCS field in the UTRD. 792 */ 793 static enum utp_ocs ufshcd_get_tr_ocs(struct ufshcd_lrb *lrbp, 794 struct cq_entry *cqe) 795 { 796 if (cqe) 797 return le32_to_cpu(cqe->status) & MASK_OCS; 798 799 return lrbp->utr_descriptor_ptr->header.ocs & MASK_OCS; 800 } 801 802 /** 803 * ufshcd_utrl_clear() - Clear requests from the controller request list. 804 * @hba: per adapter instance 805 * @mask: mask with one bit set for each request to be cleared 806 */ 807 static inline void ufshcd_utrl_clear(struct ufs_hba *hba, u32 mask) 808 { 809 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 810 mask = ~mask; 811 /* 812 * From the UFSHCI specification: "UTP Transfer Request List CLear 813 * Register (UTRLCLR): This field is bit significant. Each bit 814 * corresponds to a slot in the UTP Transfer Request List, where bit 0 815 * corresponds to request slot 0. A bit in this field is set to ‘0’ 816 * by host software to indicate to the host controller that a transfer 817 * request slot is cleared. The host controller 818 * shall free up any resources associated to the request slot 819 * immediately, and shall set the associated bit in UTRLDBR to ‘0’. The 820 * host software indicates no change to request slots by setting the 821 * associated bits in this field to ‘1’. Bits in this field shall only 822 * be set ‘1’ or ‘0’ by host software when UTRLRSR is set to ‘1’." 823 */ 824 ufshcd_writel(hba, ~mask, REG_UTP_TRANSFER_REQ_LIST_CLEAR); 825 } 826 827 /** 828 * ufshcd_utmrl_clear - Clear a bit in UTMRLCLR register 829 * @hba: per adapter instance 830 * @pos: position of the bit to be cleared 831 */ 832 static inline void ufshcd_utmrl_clear(struct ufs_hba *hba, u32 pos) 833 { 834 if (hba->quirks & UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR) 835 ufshcd_writel(hba, (1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 836 else 837 ufshcd_writel(hba, ~(1 << pos), REG_UTP_TASK_REQ_LIST_CLEAR); 838 } 839 840 /** 841 * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY 842 * @reg: Register value of host controller status 843 * 844 * Return: 0 on success; a positive value if failed. 845 */ 846 static inline int ufshcd_get_lists_status(u32 reg) 847 { 848 return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY); 849 } 850 851 /** 852 * ufshcd_get_uic_cmd_result - Get the UIC command result 853 * @hba: Pointer to adapter instance 854 * 855 * This function gets the result of UIC command completion 856 * 857 * Return: 0 on success; non-zero value on error. 858 */ 859 static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba) 860 { 861 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) & 862 MASK_UIC_COMMAND_RESULT; 863 } 864 865 /** 866 * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command 867 * @hba: Pointer to adapter instance 868 * 869 * This function gets UIC command argument3 870 * 871 * Return: 0 on success; non-zero value on error. 872 */ 873 static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba) 874 { 875 return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3); 876 } 877 878 /** 879 * ufshcd_get_req_rsp - returns the TR response transaction type 880 * @ucd_rsp_ptr: pointer to response UPIU 881 * 882 * Return: UPIU type. 883 */ 884 static inline enum upiu_response_transaction 885 ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr) 886 { 887 return ucd_rsp_ptr->header.transaction_code; 888 } 889 890 /** 891 * ufshcd_is_exception_event - Check if the device raised an exception event 892 * @ucd_rsp_ptr: pointer to response UPIU 893 * 894 * The function checks if the device raised an exception event indicated in 895 * the Device Information field of response UPIU. 896 * 897 * Return: true if exception is raised, false otherwise. 898 */ 899 static inline bool ufshcd_is_exception_event(struct utp_upiu_rsp *ucd_rsp_ptr) 900 { 901 return ucd_rsp_ptr->header.device_information & 1; 902 } 903 904 /** 905 * ufshcd_reset_intr_aggr - Reset interrupt aggregation values. 906 * @hba: per adapter instance 907 */ 908 static inline void 909 ufshcd_reset_intr_aggr(struct ufs_hba *hba) 910 { 911 ufshcd_writel(hba, INT_AGGR_ENABLE | 912 INT_AGGR_COUNTER_AND_TIMER_RESET, 913 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 914 } 915 916 /** 917 * ufshcd_config_intr_aggr - Configure interrupt aggregation values. 918 * @hba: per adapter instance 919 * @cnt: Interrupt aggregation counter threshold 920 * @tmout: Interrupt aggregation timeout value 921 */ 922 static inline void 923 ufshcd_config_intr_aggr(struct ufs_hba *hba, u8 cnt, u8 tmout) 924 { 925 ufshcd_writel(hba, INT_AGGR_ENABLE | INT_AGGR_PARAM_WRITE | 926 INT_AGGR_COUNTER_THLD_VAL(cnt) | 927 INT_AGGR_TIMEOUT_VAL(tmout), 928 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 929 } 930 931 /** 932 * ufshcd_disable_intr_aggr - Disables interrupt aggregation. 933 * @hba: per adapter instance 934 */ 935 static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba) 936 { 937 ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL); 938 } 939 940 /** 941 * ufshcd_enable_run_stop_reg - Enable run-stop registers, 942 * When run-stop registers are set to 1, it indicates the 943 * host controller that it can process the requests 944 * @hba: per adapter instance 945 */ 946 static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba) 947 { 948 ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT, 949 REG_UTP_TASK_REQ_LIST_RUN_STOP); 950 ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT, 951 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP); 952 } 953 954 /** 955 * ufshcd_hba_start - Start controller initialization sequence 956 * @hba: per adapter instance 957 */ 958 static inline void ufshcd_hba_start(struct ufs_hba *hba) 959 { 960 u32 val = CONTROLLER_ENABLE; 961 962 if (ufshcd_crypto_enable(hba)) 963 val |= CRYPTO_GENERAL_ENABLE; 964 965 ufshcd_writel(hba, val, REG_CONTROLLER_ENABLE); 966 } 967 968 /** 969 * ufshcd_is_hba_active - Get controller state 970 * @hba: per adapter instance 971 * 972 * Return: true if and only if the controller is active. 973 */ 974 bool ufshcd_is_hba_active(struct ufs_hba *hba) 975 { 976 return ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE; 977 } 978 EXPORT_SYMBOL_GPL(ufshcd_is_hba_active); 979 980 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba) 981 { 982 /* HCI version 1.0 and 1.1 supports UniPro 1.41 */ 983 if (hba->ufs_version <= ufshci_version(1, 1)) 984 return UFS_UNIPRO_VER_1_41; 985 else 986 return UFS_UNIPRO_VER_1_6; 987 } 988 EXPORT_SYMBOL(ufshcd_get_local_unipro_ver); 989 990 static bool ufshcd_is_unipro_pa_params_tuning_req(struct ufs_hba *hba) 991 { 992 /* 993 * If both host and device support UniPro ver1.6 or later, PA layer 994 * parameters tuning happens during link startup itself. 995 * 996 * We can manually tune PA layer parameters if either host or device 997 * doesn't support UniPro ver 1.6 or later. But to keep manual tuning 998 * logic simple, we will only do manual tuning if local unipro version 999 * doesn't support ver1.6 or later. 1000 */ 1001 return ufshcd_get_local_unipro_ver(hba) < UFS_UNIPRO_VER_1_6; 1002 } 1003 1004 /** 1005 * ufshcd_set_clk_freq - set UFS controller clock frequencies 1006 * @hba: per adapter instance 1007 * @scale_up: If True, set max possible frequency othewise set low frequency 1008 * 1009 * Return: 0 if successful; < 0 upon failure. 1010 */ 1011 static int ufshcd_set_clk_freq(struct ufs_hba *hba, bool scale_up) 1012 { 1013 int ret = 0; 1014 struct ufs_clk_info *clki; 1015 struct list_head *head = &hba->clk_list_head; 1016 1017 if (list_empty(head)) 1018 goto out; 1019 1020 list_for_each_entry(clki, head, list) { 1021 if (!IS_ERR_OR_NULL(clki->clk)) { 1022 if (scale_up && clki->max_freq) { 1023 if (clki->curr_freq == clki->max_freq) 1024 continue; 1025 1026 ret = clk_set_rate(clki->clk, clki->max_freq); 1027 if (ret) { 1028 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1029 __func__, clki->name, 1030 clki->max_freq, ret); 1031 break; 1032 } 1033 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1034 "scaled up", clki->name, 1035 clki->curr_freq, 1036 clki->max_freq); 1037 1038 clki->curr_freq = clki->max_freq; 1039 1040 } else if (!scale_up && clki->min_freq) { 1041 if (clki->curr_freq == clki->min_freq) 1042 continue; 1043 1044 ret = clk_set_rate(clki->clk, clki->min_freq); 1045 if (ret) { 1046 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 1047 __func__, clki->name, 1048 clki->min_freq, ret); 1049 break; 1050 } 1051 trace_ufshcd_clk_scaling(dev_name(hba->dev), 1052 "scaled down", clki->name, 1053 clki->curr_freq, 1054 clki->min_freq); 1055 clki->curr_freq = clki->min_freq; 1056 } 1057 } 1058 dev_dbg(hba->dev, "%s: clk: %s, rate: %lu\n", __func__, 1059 clki->name, clk_get_rate(clki->clk)); 1060 } 1061 1062 out: 1063 return ret; 1064 } 1065 1066 int ufshcd_opp_config_clks(struct device *dev, struct opp_table *opp_table, 1067 struct dev_pm_opp *opp, void *data, 1068 bool scaling_down) 1069 { 1070 struct ufs_hba *hba = dev_get_drvdata(dev); 1071 struct list_head *head = &hba->clk_list_head; 1072 struct ufs_clk_info *clki; 1073 unsigned long freq; 1074 u8 idx = 0; 1075 int ret; 1076 1077 list_for_each_entry(clki, head, list) { 1078 if (!IS_ERR_OR_NULL(clki->clk)) { 1079 freq = dev_pm_opp_get_freq_indexed(opp, idx++); 1080 1081 /* Do not set rate for clocks having frequency as 0 */ 1082 if (!freq) 1083 continue; 1084 1085 ret = clk_set_rate(clki->clk, freq); 1086 if (ret) { 1087 dev_err(dev, "%s: %s clk set rate(%ldHz) failed, %d\n", 1088 __func__, clki->name, freq, ret); 1089 return ret; 1090 } 1091 1092 trace_ufshcd_clk_scaling(dev_name(dev), 1093 (scaling_down ? "scaled down" : "scaled up"), 1094 clki->name, hba->clk_scaling.target_freq, freq); 1095 } 1096 } 1097 1098 return 0; 1099 } 1100 EXPORT_SYMBOL_GPL(ufshcd_opp_config_clks); 1101 1102 static int ufshcd_opp_set_rate(struct ufs_hba *hba, unsigned long freq) 1103 { 1104 struct dev_pm_opp *opp; 1105 int ret; 1106 1107 opp = dev_pm_opp_find_freq_floor_indexed(hba->dev, 1108 &freq, 0); 1109 if (IS_ERR(opp)) 1110 return PTR_ERR(opp); 1111 1112 ret = dev_pm_opp_set_opp(hba->dev, opp); 1113 dev_pm_opp_put(opp); 1114 1115 return ret; 1116 } 1117 1118 /** 1119 * ufshcd_scale_clks - scale up or scale down UFS controller clocks 1120 * @hba: per adapter instance 1121 * @freq: frequency to scale 1122 * @scale_up: True if scaling up and false if scaling down 1123 * 1124 * Return: 0 if successful; < 0 upon failure. 1125 */ 1126 static int ufshcd_scale_clks(struct ufs_hba *hba, unsigned long freq, 1127 bool scale_up) 1128 { 1129 int ret = 0; 1130 ktime_t start = ktime_get(); 1131 1132 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, PRE_CHANGE); 1133 if (ret) 1134 goto out; 1135 1136 if (hba->use_pm_opp) 1137 ret = ufshcd_opp_set_rate(hba, freq); 1138 else 1139 ret = ufshcd_set_clk_freq(hba, scale_up); 1140 if (ret) 1141 goto out; 1142 1143 ret = ufshcd_vops_clk_scale_notify(hba, scale_up, POST_CHANGE); 1144 if (ret) { 1145 if (hba->use_pm_opp) 1146 ufshcd_opp_set_rate(hba, 1147 hba->devfreq->previous_freq); 1148 else 1149 ufshcd_set_clk_freq(hba, !scale_up); 1150 } 1151 1152 out: 1153 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1154 (scale_up ? "up" : "down"), 1155 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1156 return ret; 1157 } 1158 1159 /** 1160 * ufshcd_is_devfreq_scaling_required - check if scaling is required or not 1161 * @hba: per adapter instance 1162 * @freq: frequency to scale 1163 * @scale_up: True if scaling up and false if scaling down 1164 * 1165 * Return: true if scaling is required, false otherwise. 1166 */ 1167 static bool ufshcd_is_devfreq_scaling_required(struct ufs_hba *hba, 1168 unsigned long freq, bool scale_up) 1169 { 1170 struct ufs_clk_info *clki; 1171 struct list_head *head = &hba->clk_list_head; 1172 1173 if (list_empty(head)) 1174 return false; 1175 1176 if (hba->use_pm_opp) 1177 return freq != hba->clk_scaling.target_freq; 1178 1179 list_for_each_entry(clki, head, list) { 1180 if (!IS_ERR_OR_NULL(clki->clk)) { 1181 if (scale_up && clki->max_freq) { 1182 if (clki->curr_freq == clki->max_freq) 1183 continue; 1184 return true; 1185 } else if (!scale_up && clki->min_freq) { 1186 if (clki->curr_freq == clki->min_freq) 1187 continue; 1188 return true; 1189 } 1190 } 1191 } 1192 1193 return false; 1194 } 1195 1196 /* 1197 * Determine the number of pending commands by counting the bits in the SCSI 1198 * device budget maps. This approach has been selected because a bit is set in 1199 * the budget map before scsi_host_queue_ready() checks the host_self_blocked 1200 * flag. The host_self_blocked flag can be modified by calling 1201 * scsi_block_requests() or scsi_unblock_requests(). 1202 */ 1203 static u32 ufshcd_pending_cmds(struct ufs_hba *hba) 1204 { 1205 const struct scsi_device *sdev; 1206 u32 pending = 0; 1207 1208 lockdep_assert_held(hba->host->host_lock); 1209 __shost_for_each_device(sdev, hba->host) 1210 pending += sbitmap_weight(&sdev->budget_map); 1211 1212 return pending; 1213 } 1214 1215 /* 1216 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1217 * has expired. 1218 * 1219 * Return: 0 upon success; -EBUSY upon timeout. 1220 */ 1221 static int ufshcd_wait_for_doorbell_clr(struct ufs_hba *hba, 1222 u64 wait_timeout_us) 1223 { 1224 unsigned long flags; 1225 int ret = 0; 1226 u32 tm_doorbell; 1227 u32 tr_pending; 1228 bool timeout = false, do_last_check = false; 1229 ktime_t start; 1230 1231 ufshcd_hold(hba); 1232 spin_lock_irqsave(hba->host->host_lock, flags); 1233 /* 1234 * Wait for all the outstanding tasks/transfer requests. 1235 * Verify by checking the doorbell registers are clear. 1236 */ 1237 start = ktime_get(); 1238 do { 1239 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL) { 1240 ret = -EBUSY; 1241 goto out; 1242 } 1243 1244 tm_doorbell = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 1245 tr_pending = ufshcd_pending_cmds(hba); 1246 if (!tm_doorbell && !tr_pending) { 1247 timeout = false; 1248 break; 1249 } else if (do_last_check) { 1250 break; 1251 } 1252 1253 spin_unlock_irqrestore(hba->host->host_lock, flags); 1254 io_schedule_timeout(msecs_to_jiffies(20)); 1255 if (ktime_to_us(ktime_sub(ktime_get(), start)) > 1256 wait_timeout_us) { 1257 timeout = true; 1258 /* 1259 * We might have scheduled out for long time so make 1260 * sure to check if doorbells are cleared by this time 1261 * or not. 1262 */ 1263 do_last_check = true; 1264 } 1265 spin_lock_irqsave(hba->host->host_lock, flags); 1266 } while (tm_doorbell || tr_pending); 1267 1268 if (timeout) { 1269 dev_err(hba->dev, 1270 "%s: timedout waiting for doorbell to clear (tm=0x%x, tr=0x%x)\n", 1271 __func__, tm_doorbell, tr_pending); 1272 ret = -EBUSY; 1273 } 1274 out: 1275 spin_unlock_irqrestore(hba->host->host_lock, flags); 1276 ufshcd_release(hba); 1277 return ret; 1278 } 1279 1280 /** 1281 * ufshcd_scale_gear - scale up/down UFS gear 1282 * @hba: per adapter instance 1283 * @scale_up: True for scaling up gear and false for scaling down 1284 * 1285 * Return: 0 for success; -EBUSY if scaling can't happen at this time; 1286 * non-zero for any other errors. 1287 */ 1288 static int ufshcd_scale_gear(struct ufs_hba *hba, bool scale_up) 1289 { 1290 int ret = 0; 1291 struct ufs_pa_layer_attr new_pwr_info; 1292 1293 if (scale_up) { 1294 memcpy(&new_pwr_info, &hba->clk_scaling.saved_pwr_info, 1295 sizeof(struct ufs_pa_layer_attr)); 1296 } else { 1297 memcpy(&new_pwr_info, &hba->pwr_info, 1298 sizeof(struct ufs_pa_layer_attr)); 1299 1300 if (hba->pwr_info.gear_tx > hba->clk_scaling.min_gear || 1301 hba->pwr_info.gear_rx > hba->clk_scaling.min_gear) { 1302 /* save the current power mode */ 1303 memcpy(&hba->clk_scaling.saved_pwr_info, 1304 &hba->pwr_info, 1305 sizeof(struct ufs_pa_layer_attr)); 1306 1307 /* scale down gear */ 1308 new_pwr_info.gear_tx = hba->clk_scaling.min_gear; 1309 new_pwr_info.gear_rx = hba->clk_scaling.min_gear; 1310 } 1311 } 1312 1313 /* check if the power mode needs to be changed or not? */ 1314 ret = ufshcd_config_pwr_mode(hba, &new_pwr_info); 1315 if (ret) 1316 dev_err(hba->dev, "%s: failed err %d, old gear: (tx %d rx %d), new gear: (tx %d rx %d)", 1317 __func__, ret, 1318 hba->pwr_info.gear_tx, hba->pwr_info.gear_rx, 1319 new_pwr_info.gear_tx, new_pwr_info.gear_rx); 1320 1321 return ret; 1322 } 1323 1324 /* 1325 * Wait until all pending SCSI commands and TMFs have finished or the timeout 1326 * has expired. 1327 * 1328 * Return: 0 upon success; -EBUSY upon timeout. 1329 */ 1330 static int ufshcd_clock_scaling_prepare(struct ufs_hba *hba, u64 timeout_us) 1331 { 1332 int ret = 0; 1333 /* 1334 * make sure that there are no outstanding requests when 1335 * clock scaling is in progress 1336 */ 1337 ufshcd_scsi_block_requests(hba); 1338 mutex_lock(&hba->wb_mutex); 1339 down_write(&hba->clk_scaling_lock); 1340 1341 if (!hba->clk_scaling.is_allowed || 1342 ufshcd_wait_for_doorbell_clr(hba, timeout_us)) { 1343 ret = -EBUSY; 1344 up_write(&hba->clk_scaling_lock); 1345 mutex_unlock(&hba->wb_mutex); 1346 ufshcd_scsi_unblock_requests(hba); 1347 goto out; 1348 } 1349 1350 /* let's not get into low power until clock scaling is completed */ 1351 ufshcd_hold(hba); 1352 1353 out: 1354 return ret; 1355 } 1356 1357 static void ufshcd_clock_scaling_unprepare(struct ufs_hba *hba, int err, bool scale_up) 1358 { 1359 up_write(&hba->clk_scaling_lock); 1360 1361 /* Enable Write Booster if we have scaled up else disable it */ 1362 if (ufshcd_enable_wb_if_scaling_up(hba) && !err) 1363 ufshcd_wb_toggle(hba, scale_up); 1364 1365 mutex_unlock(&hba->wb_mutex); 1366 1367 ufshcd_scsi_unblock_requests(hba); 1368 ufshcd_release(hba); 1369 } 1370 1371 /** 1372 * ufshcd_devfreq_scale - scale up/down UFS clocks and gear 1373 * @hba: per adapter instance 1374 * @freq: frequency to scale 1375 * @scale_up: True for scaling up and false for scalin down 1376 * 1377 * Return: 0 for success; -EBUSY if scaling can't happen at this time; non-zero 1378 * for any other errors. 1379 */ 1380 static int ufshcd_devfreq_scale(struct ufs_hba *hba, unsigned long freq, 1381 bool scale_up) 1382 { 1383 int ret = 0; 1384 1385 ret = ufshcd_clock_scaling_prepare(hba, 1 * USEC_PER_SEC); 1386 if (ret) 1387 return ret; 1388 1389 /* scale down the gear before scaling down clocks */ 1390 if (!scale_up) { 1391 ret = ufshcd_scale_gear(hba, false); 1392 if (ret) 1393 goto out_unprepare; 1394 } 1395 1396 ret = ufshcd_scale_clks(hba, freq, scale_up); 1397 if (ret) { 1398 if (!scale_up) 1399 ufshcd_scale_gear(hba, true); 1400 goto out_unprepare; 1401 } 1402 1403 /* scale up the gear after scaling up clocks */ 1404 if (scale_up) { 1405 ret = ufshcd_scale_gear(hba, true); 1406 if (ret) { 1407 ufshcd_scale_clks(hba, hba->devfreq->previous_freq, 1408 false); 1409 goto out_unprepare; 1410 } 1411 } 1412 1413 out_unprepare: 1414 ufshcd_clock_scaling_unprepare(hba, ret, scale_up); 1415 return ret; 1416 } 1417 1418 static void ufshcd_clk_scaling_suspend_work(struct work_struct *work) 1419 { 1420 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1421 clk_scaling.suspend_work); 1422 unsigned long irq_flags; 1423 1424 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1425 if (hba->clk_scaling.active_reqs || hba->clk_scaling.is_suspended) { 1426 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1427 return; 1428 } 1429 hba->clk_scaling.is_suspended = true; 1430 hba->clk_scaling.window_start_t = 0; 1431 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1432 1433 devfreq_suspend_device(hba->devfreq); 1434 } 1435 1436 static void ufshcd_clk_scaling_resume_work(struct work_struct *work) 1437 { 1438 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1439 clk_scaling.resume_work); 1440 unsigned long irq_flags; 1441 1442 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1443 if (!hba->clk_scaling.is_suspended) { 1444 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1445 return; 1446 } 1447 hba->clk_scaling.is_suspended = false; 1448 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1449 1450 devfreq_resume_device(hba->devfreq); 1451 } 1452 1453 static int ufshcd_devfreq_target(struct device *dev, 1454 unsigned long *freq, u32 flags) 1455 { 1456 int ret = 0; 1457 struct ufs_hba *hba = dev_get_drvdata(dev); 1458 ktime_t start; 1459 bool scale_up, sched_clk_scaling_suspend_work = false; 1460 struct list_head *clk_list = &hba->clk_list_head; 1461 struct ufs_clk_info *clki; 1462 unsigned long irq_flags; 1463 1464 if (!ufshcd_is_clkscaling_supported(hba)) 1465 return -EINVAL; 1466 1467 if (hba->use_pm_opp) { 1468 struct dev_pm_opp *opp; 1469 1470 /* Get the recommended frequency from OPP framework */ 1471 opp = devfreq_recommended_opp(dev, freq, flags); 1472 if (IS_ERR(opp)) 1473 return PTR_ERR(opp); 1474 1475 dev_pm_opp_put(opp); 1476 } else { 1477 /* Override with the closest supported frequency */ 1478 clki = list_first_entry(&hba->clk_list_head, struct ufs_clk_info, 1479 list); 1480 *freq = (unsigned long) clk_round_rate(clki->clk, *freq); 1481 } 1482 1483 spin_lock_irqsave(hba->host->host_lock, irq_flags); 1484 if (ufshcd_eh_in_progress(hba)) { 1485 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1486 return 0; 1487 } 1488 1489 /* Skip scaling clock when clock scaling is suspended */ 1490 if (hba->clk_scaling.is_suspended) { 1491 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1492 dev_warn(hba->dev, "clock scaling is suspended, skip"); 1493 return 0; 1494 } 1495 1496 if (!hba->clk_scaling.active_reqs) 1497 sched_clk_scaling_suspend_work = true; 1498 1499 if (list_empty(clk_list)) { 1500 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1501 goto out; 1502 } 1503 1504 /* Decide based on the target or rounded-off frequency and update */ 1505 if (hba->use_pm_opp) 1506 scale_up = *freq > hba->clk_scaling.target_freq; 1507 else 1508 scale_up = *freq == clki->max_freq; 1509 1510 if (!hba->use_pm_opp && !scale_up) 1511 *freq = clki->min_freq; 1512 1513 /* Update the frequency */ 1514 if (!ufshcd_is_devfreq_scaling_required(hba, *freq, scale_up)) { 1515 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1516 ret = 0; 1517 goto out; /* no state change required */ 1518 } 1519 spin_unlock_irqrestore(hba->host->host_lock, irq_flags); 1520 1521 start = ktime_get(); 1522 ret = ufshcd_devfreq_scale(hba, *freq, scale_up); 1523 if (!ret) 1524 hba->clk_scaling.target_freq = *freq; 1525 1526 trace_ufshcd_profile_clk_scaling(dev_name(hba->dev), 1527 (scale_up ? "up" : "down"), 1528 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 1529 1530 out: 1531 if (sched_clk_scaling_suspend_work && !scale_up) 1532 queue_work(hba->clk_scaling.workq, 1533 &hba->clk_scaling.suspend_work); 1534 1535 return ret; 1536 } 1537 1538 static int ufshcd_devfreq_get_dev_status(struct device *dev, 1539 struct devfreq_dev_status *stat) 1540 { 1541 struct ufs_hba *hba = dev_get_drvdata(dev); 1542 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 1543 unsigned long flags; 1544 ktime_t curr_t; 1545 1546 if (!ufshcd_is_clkscaling_supported(hba)) 1547 return -EINVAL; 1548 1549 memset(stat, 0, sizeof(*stat)); 1550 1551 spin_lock_irqsave(hba->host->host_lock, flags); 1552 curr_t = ktime_get(); 1553 if (!scaling->window_start_t) 1554 goto start_window; 1555 1556 /* 1557 * If current frequency is 0, then the ondemand governor considers 1558 * there's no initial frequency set. And it always requests to set 1559 * to max. frequency. 1560 */ 1561 if (hba->use_pm_opp) { 1562 stat->current_frequency = hba->clk_scaling.target_freq; 1563 } else { 1564 struct list_head *clk_list = &hba->clk_list_head; 1565 struct ufs_clk_info *clki; 1566 1567 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1568 stat->current_frequency = clki->curr_freq; 1569 } 1570 1571 if (scaling->is_busy_started) 1572 scaling->tot_busy_t += ktime_us_delta(curr_t, 1573 scaling->busy_start_t); 1574 stat->total_time = ktime_us_delta(curr_t, scaling->window_start_t); 1575 stat->busy_time = scaling->tot_busy_t; 1576 start_window: 1577 scaling->window_start_t = curr_t; 1578 scaling->tot_busy_t = 0; 1579 1580 if (scaling->active_reqs) { 1581 scaling->busy_start_t = curr_t; 1582 scaling->is_busy_started = true; 1583 } else { 1584 scaling->busy_start_t = 0; 1585 scaling->is_busy_started = false; 1586 } 1587 spin_unlock_irqrestore(hba->host->host_lock, flags); 1588 return 0; 1589 } 1590 1591 static int ufshcd_devfreq_init(struct ufs_hba *hba) 1592 { 1593 struct list_head *clk_list = &hba->clk_list_head; 1594 struct ufs_clk_info *clki; 1595 struct devfreq *devfreq; 1596 int ret; 1597 1598 /* Skip devfreq if we don't have any clocks in the list */ 1599 if (list_empty(clk_list)) 1600 return 0; 1601 1602 if (!hba->use_pm_opp) { 1603 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1604 dev_pm_opp_add(hba->dev, clki->min_freq, 0); 1605 dev_pm_opp_add(hba->dev, clki->max_freq, 0); 1606 } 1607 1608 ufshcd_vops_config_scaling_param(hba, &hba->vps->devfreq_profile, 1609 &hba->vps->ondemand_data); 1610 devfreq = devfreq_add_device(hba->dev, 1611 &hba->vps->devfreq_profile, 1612 DEVFREQ_GOV_SIMPLE_ONDEMAND, 1613 &hba->vps->ondemand_data); 1614 if (IS_ERR(devfreq)) { 1615 ret = PTR_ERR(devfreq); 1616 dev_err(hba->dev, "Unable to register with devfreq %d\n", ret); 1617 1618 if (!hba->use_pm_opp) { 1619 dev_pm_opp_remove(hba->dev, clki->min_freq); 1620 dev_pm_opp_remove(hba->dev, clki->max_freq); 1621 } 1622 return ret; 1623 } 1624 1625 hba->devfreq = devfreq; 1626 1627 return 0; 1628 } 1629 1630 static void ufshcd_devfreq_remove(struct ufs_hba *hba) 1631 { 1632 struct list_head *clk_list = &hba->clk_list_head; 1633 1634 if (!hba->devfreq) 1635 return; 1636 1637 devfreq_remove_device(hba->devfreq); 1638 hba->devfreq = NULL; 1639 1640 if (!hba->use_pm_opp) { 1641 struct ufs_clk_info *clki; 1642 1643 clki = list_first_entry(clk_list, struct ufs_clk_info, list); 1644 dev_pm_opp_remove(hba->dev, clki->min_freq); 1645 dev_pm_opp_remove(hba->dev, clki->max_freq); 1646 } 1647 } 1648 1649 static void ufshcd_suspend_clkscaling(struct ufs_hba *hba) 1650 { 1651 unsigned long flags; 1652 bool suspend = false; 1653 1654 cancel_work_sync(&hba->clk_scaling.suspend_work); 1655 cancel_work_sync(&hba->clk_scaling.resume_work); 1656 1657 spin_lock_irqsave(hba->host->host_lock, flags); 1658 if (!hba->clk_scaling.is_suspended) { 1659 suspend = true; 1660 hba->clk_scaling.is_suspended = true; 1661 hba->clk_scaling.window_start_t = 0; 1662 } 1663 spin_unlock_irqrestore(hba->host->host_lock, flags); 1664 1665 if (suspend) 1666 devfreq_suspend_device(hba->devfreq); 1667 } 1668 1669 static void ufshcd_resume_clkscaling(struct ufs_hba *hba) 1670 { 1671 unsigned long flags; 1672 bool resume = false; 1673 1674 spin_lock_irqsave(hba->host->host_lock, flags); 1675 if (hba->clk_scaling.is_suspended) { 1676 resume = true; 1677 hba->clk_scaling.is_suspended = false; 1678 } 1679 spin_unlock_irqrestore(hba->host->host_lock, flags); 1680 1681 if (resume) 1682 devfreq_resume_device(hba->devfreq); 1683 } 1684 1685 static ssize_t ufshcd_clkscale_enable_show(struct device *dev, 1686 struct device_attribute *attr, char *buf) 1687 { 1688 struct ufs_hba *hba = dev_get_drvdata(dev); 1689 1690 return sysfs_emit(buf, "%d\n", hba->clk_scaling.is_enabled); 1691 } 1692 1693 static ssize_t ufshcd_clkscale_enable_store(struct device *dev, 1694 struct device_attribute *attr, const char *buf, size_t count) 1695 { 1696 struct ufs_hba *hba = dev_get_drvdata(dev); 1697 u32 value; 1698 int err = 0; 1699 1700 if (kstrtou32(buf, 0, &value)) 1701 return -EINVAL; 1702 1703 down(&hba->host_sem); 1704 if (!ufshcd_is_user_access_allowed(hba)) { 1705 err = -EBUSY; 1706 goto out; 1707 } 1708 1709 value = !!value; 1710 if (value == hba->clk_scaling.is_enabled) 1711 goto out; 1712 1713 ufshcd_rpm_get_sync(hba); 1714 ufshcd_hold(hba); 1715 1716 hba->clk_scaling.is_enabled = value; 1717 1718 if (value) { 1719 ufshcd_resume_clkscaling(hba); 1720 } else { 1721 ufshcd_suspend_clkscaling(hba); 1722 err = ufshcd_devfreq_scale(hba, ULONG_MAX, true); 1723 if (err) 1724 dev_err(hba->dev, "%s: failed to scale clocks up %d\n", 1725 __func__, err); 1726 } 1727 1728 ufshcd_release(hba); 1729 ufshcd_rpm_put_sync(hba); 1730 out: 1731 up(&hba->host_sem); 1732 return err ? err : count; 1733 } 1734 1735 static void ufshcd_init_clk_scaling_sysfs(struct ufs_hba *hba) 1736 { 1737 hba->clk_scaling.enable_attr.show = ufshcd_clkscale_enable_show; 1738 hba->clk_scaling.enable_attr.store = ufshcd_clkscale_enable_store; 1739 sysfs_attr_init(&hba->clk_scaling.enable_attr.attr); 1740 hba->clk_scaling.enable_attr.attr.name = "clkscale_enable"; 1741 hba->clk_scaling.enable_attr.attr.mode = 0644; 1742 if (device_create_file(hba->dev, &hba->clk_scaling.enable_attr)) 1743 dev_err(hba->dev, "Failed to create sysfs for clkscale_enable\n"); 1744 } 1745 1746 static void ufshcd_remove_clk_scaling_sysfs(struct ufs_hba *hba) 1747 { 1748 if (hba->clk_scaling.enable_attr.attr.name) 1749 device_remove_file(hba->dev, &hba->clk_scaling.enable_attr); 1750 } 1751 1752 static void ufshcd_init_clk_scaling(struct ufs_hba *hba) 1753 { 1754 char wq_name[sizeof("ufs_clkscaling_00")]; 1755 1756 if (!ufshcd_is_clkscaling_supported(hba)) 1757 return; 1758 1759 if (!hba->clk_scaling.min_gear) 1760 hba->clk_scaling.min_gear = UFS_HS_G1; 1761 1762 INIT_WORK(&hba->clk_scaling.suspend_work, 1763 ufshcd_clk_scaling_suspend_work); 1764 INIT_WORK(&hba->clk_scaling.resume_work, 1765 ufshcd_clk_scaling_resume_work); 1766 1767 snprintf(wq_name, sizeof(wq_name), "ufs_clkscaling_%d", 1768 hba->host->host_no); 1769 hba->clk_scaling.workq = create_singlethread_workqueue(wq_name); 1770 1771 hba->clk_scaling.is_initialized = true; 1772 } 1773 1774 static void ufshcd_exit_clk_scaling(struct ufs_hba *hba) 1775 { 1776 if (!hba->clk_scaling.is_initialized) 1777 return; 1778 1779 ufshcd_remove_clk_scaling_sysfs(hba); 1780 destroy_workqueue(hba->clk_scaling.workq); 1781 ufshcd_devfreq_remove(hba); 1782 hba->clk_scaling.is_initialized = false; 1783 } 1784 1785 static void ufshcd_ungate_work(struct work_struct *work) 1786 { 1787 int ret; 1788 unsigned long flags; 1789 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1790 clk_gating.ungate_work); 1791 1792 cancel_delayed_work_sync(&hba->clk_gating.gate_work); 1793 1794 spin_lock_irqsave(hba->host->host_lock, flags); 1795 if (hba->clk_gating.state == CLKS_ON) { 1796 spin_unlock_irqrestore(hba->host->host_lock, flags); 1797 return; 1798 } 1799 1800 spin_unlock_irqrestore(hba->host->host_lock, flags); 1801 ufshcd_hba_vreg_set_hpm(hba); 1802 ufshcd_setup_clocks(hba, true); 1803 1804 ufshcd_enable_irq(hba); 1805 1806 /* Exit from hibern8 */ 1807 if (ufshcd_can_hibern8_during_gating(hba)) { 1808 /* Prevent gating in this path */ 1809 hba->clk_gating.is_suspended = true; 1810 if (ufshcd_is_link_hibern8(hba)) { 1811 ret = ufshcd_uic_hibern8_exit(hba); 1812 if (ret) 1813 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 1814 __func__, ret); 1815 else 1816 ufshcd_set_link_active(hba); 1817 } 1818 hba->clk_gating.is_suspended = false; 1819 } 1820 } 1821 1822 /** 1823 * ufshcd_hold - Enable clocks that were gated earlier due to ufshcd_release. 1824 * Also, exit from hibern8 mode and set the link as active. 1825 * @hba: per adapter instance 1826 */ 1827 void ufshcd_hold(struct ufs_hba *hba) 1828 { 1829 bool flush_result; 1830 unsigned long flags; 1831 1832 if (!ufshcd_is_clkgating_allowed(hba) || 1833 !hba->clk_gating.is_initialized) 1834 return; 1835 spin_lock_irqsave(hba->host->host_lock, flags); 1836 hba->clk_gating.active_reqs++; 1837 1838 start: 1839 switch (hba->clk_gating.state) { 1840 case CLKS_ON: 1841 /* 1842 * Wait for the ungate work to complete if in progress. 1843 * Though the clocks may be in ON state, the link could 1844 * still be in hibner8 state if hibern8 is allowed 1845 * during clock gating. 1846 * Make sure we exit hibern8 state also in addition to 1847 * clocks being ON. 1848 */ 1849 if (ufshcd_can_hibern8_during_gating(hba) && 1850 ufshcd_is_link_hibern8(hba)) { 1851 spin_unlock_irqrestore(hba->host->host_lock, flags); 1852 flush_result = flush_work(&hba->clk_gating.ungate_work); 1853 if (hba->clk_gating.is_suspended && !flush_result) 1854 return; 1855 spin_lock_irqsave(hba->host->host_lock, flags); 1856 goto start; 1857 } 1858 break; 1859 case REQ_CLKS_OFF: 1860 if (cancel_delayed_work(&hba->clk_gating.gate_work)) { 1861 hba->clk_gating.state = CLKS_ON; 1862 trace_ufshcd_clk_gating(dev_name(hba->dev), 1863 hba->clk_gating.state); 1864 break; 1865 } 1866 /* 1867 * If we are here, it means gating work is either done or 1868 * currently running. Hence, fall through to cancel gating 1869 * work and to enable clocks. 1870 */ 1871 fallthrough; 1872 case CLKS_OFF: 1873 hba->clk_gating.state = REQ_CLKS_ON; 1874 trace_ufshcd_clk_gating(dev_name(hba->dev), 1875 hba->clk_gating.state); 1876 queue_work(hba->clk_gating.clk_gating_workq, 1877 &hba->clk_gating.ungate_work); 1878 /* 1879 * fall through to check if we should wait for this 1880 * work to be done or not. 1881 */ 1882 fallthrough; 1883 case REQ_CLKS_ON: 1884 spin_unlock_irqrestore(hba->host->host_lock, flags); 1885 flush_work(&hba->clk_gating.ungate_work); 1886 /* Make sure state is CLKS_ON before returning */ 1887 spin_lock_irqsave(hba->host->host_lock, flags); 1888 goto start; 1889 default: 1890 dev_err(hba->dev, "%s: clk gating is in invalid state %d\n", 1891 __func__, hba->clk_gating.state); 1892 break; 1893 } 1894 spin_unlock_irqrestore(hba->host->host_lock, flags); 1895 } 1896 EXPORT_SYMBOL_GPL(ufshcd_hold); 1897 1898 static void ufshcd_gate_work(struct work_struct *work) 1899 { 1900 struct ufs_hba *hba = container_of(work, struct ufs_hba, 1901 clk_gating.gate_work.work); 1902 unsigned long flags; 1903 int ret; 1904 1905 spin_lock_irqsave(hba->host->host_lock, flags); 1906 /* 1907 * In case you are here to cancel this work the gating state 1908 * would be marked as REQ_CLKS_ON. In this case save time by 1909 * skipping the gating work and exit after changing the clock 1910 * state to CLKS_ON. 1911 */ 1912 if (hba->clk_gating.is_suspended || 1913 (hba->clk_gating.state != REQ_CLKS_OFF)) { 1914 hba->clk_gating.state = CLKS_ON; 1915 trace_ufshcd_clk_gating(dev_name(hba->dev), 1916 hba->clk_gating.state); 1917 goto rel_lock; 1918 } 1919 1920 if (hba->clk_gating.active_reqs 1921 || hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL 1922 || hba->outstanding_reqs || hba->outstanding_tasks 1923 || hba->active_uic_cmd || hba->uic_async_done) 1924 goto rel_lock; 1925 1926 spin_unlock_irqrestore(hba->host->host_lock, flags); 1927 1928 /* put the link into hibern8 mode before turning off clocks */ 1929 if (ufshcd_can_hibern8_during_gating(hba)) { 1930 ret = ufshcd_uic_hibern8_enter(hba); 1931 if (ret) { 1932 hba->clk_gating.state = CLKS_ON; 1933 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 1934 __func__, ret); 1935 trace_ufshcd_clk_gating(dev_name(hba->dev), 1936 hba->clk_gating.state); 1937 goto out; 1938 } 1939 ufshcd_set_link_hibern8(hba); 1940 } 1941 1942 ufshcd_disable_irq(hba); 1943 1944 ufshcd_setup_clocks(hba, false); 1945 1946 /* Put the host controller in low power mode if possible */ 1947 ufshcd_hba_vreg_set_lpm(hba); 1948 /* 1949 * In case you are here to cancel this work the gating state 1950 * would be marked as REQ_CLKS_ON. In this case keep the state 1951 * as REQ_CLKS_ON which would anyway imply that clocks are off 1952 * and a request to turn them on is pending. By doing this way, 1953 * we keep the state machine in tact and this would ultimately 1954 * prevent from doing cancel work multiple times when there are 1955 * new requests arriving before the current cancel work is done. 1956 */ 1957 spin_lock_irqsave(hba->host->host_lock, flags); 1958 if (hba->clk_gating.state == REQ_CLKS_OFF) { 1959 hba->clk_gating.state = CLKS_OFF; 1960 trace_ufshcd_clk_gating(dev_name(hba->dev), 1961 hba->clk_gating.state); 1962 } 1963 rel_lock: 1964 spin_unlock_irqrestore(hba->host->host_lock, flags); 1965 out: 1966 return; 1967 } 1968 1969 /* host lock must be held before calling this variant */ 1970 static void __ufshcd_release(struct ufs_hba *hba) 1971 { 1972 if (!ufshcd_is_clkgating_allowed(hba)) 1973 return; 1974 1975 hba->clk_gating.active_reqs--; 1976 1977 if (hba->clk_gating.active_reqs || hba->clk_gating.is_suspended || 1978 hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL || 1979 hba->outstanding_tasks || !hba->clk_gating.is_initialized || 1980 hba->active_uic_cmd || hba->uic_async_done || 1981 hba->clk_gating.state == CLKS_OFF) 1982 return; 1983 1984 hba->clk_gating.state = REQ_CLKS_OFF; 1985 trace_ufshcd_clk_gating(dev_name(hba->dev), hba->clk_gating.state); 1986 queue_delayed_work(hba->clk_gating.clk_gating_workq, 1987 &hba->clk_gating.gate_work, 1988 msecs_to_jiffies(hba->clk_gating.delay_ms)); 1989 } 1990 1991 void ufshcd_release(struct ufs_hba *hba) 1992 { 1993 unsigned long flags; 1994 1995 spin_lock_irqsave(hba->host->host_lock, flags); 1996 __ufshcd_release(hba); 1997 spin_unlock_irqrestore(hba->host->host_lock, flags); 1998 } 1999 EXPORT_SYMBOL_GPL(ufshcd_release); 2000 2001 static ssize_t ufshcd_clkgate_delay_show(struct device *dev, 2002 struct device_attribute *attr, char *buf) 2003 { 2004 struct ufs_hba *hba = dev_get_drvdata(dev); 2005 2006 return sysfs_emit(buf, "%lu\n", hba->clk_gating.delay_ms); 2007 } 2008 2009 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value) 2010 { 2011 struct ufs_hba *hba = dev_get_drvdata(dev); 2012 unsigned long flags; 2013 2014 spin_lock_irqsave(hba->host->host_lock, flags); 2015 hba->clk_gating.delay_ms = value; 2016 spin_unlock_irqrestore(hba->host->host_lock, flags); 2017 } 2018 EXPORT_SYMBOL_GPL(ufshcd_clkgate_delay_set); 2019 2020 static ssize_t ufshcd_clkgate_delay_store(struct device *dev, 2021 struct device_attribute *attr, const char *buf, size_t count) 2022 { 2023 unsigned long value; 2024 2025 if (kstrtoul(buf, 0, &value)) 2026 return -EINVAL; 2027 2028 ufshcd_clkgate_delay_set(dev, value); 2029 return count; 2030 } 2031 2032 static ssize_t ufshcd_clkgate_enable_show(struct device *dev, 2033 struct device_attribute *attr, char *buf) 2034 { 2035 struct ufs_hba *hba = dev_get_drvdata(dev); 2036 2037 return sysfs_emit(buf, "%d\n", hba->clk_gating.is_enabled); 2038 } 2039 2040 static ssize_t ufshcd_clkgate_enable_store(struct device *dev, 2041 struct device_attribute *attr, const char *buf, size_t count) 2042 { 2043 struct ufs_hba *hba = dev_get_drvdata(dev); 2044 unsigned long flags; 2045 u32 value; 2046 2047 if (kstrtou32(buf, 0, &value)) 2048 return -EINVAL; 2049 2050 value = !!value; 2051 2052 spin_lock_irqsave(hba->host->host_lock, flags); 2053 if (value == hba->clk_gating.is_enabled) 2054 goto out; 2055 2056 if (value) 2057 __ufshcd_release(hba); 2058 else 2059 hba->clk_gating.active_reqs++; 2060 2061 hba->clk_gating.is_enabled = value; 2062 out: 2063 spin_unlock_irqrestore(hba->host->host_lock, flags); 2064 return count; 2065 } 2066 2067 static void ufshcd_init_clk_gating_sysfs(struct ufs_hba *hba) 2068 { 2069 hba->clk_gating.delay_attr.show = ufshcd_clkgate_delay_show; 2070 hba->clk_gating.delay_attr.store = ufshcd_clkgate_delay_store; 2071 sysfs_attr_init(&hba->clk_gating.delay_attr.attr); 2072 hba->clk_gating.delay_attr.attr.name = "clkgate_delay_ms"; 2073 hba->clk_gating.delay_attr.attr.mode = 0644; 2074 if (device_create_file(hba->dev, &hba->clk_gating.delay_attr)) 2075 dev_err(hba->dev, "Failed to create sysfs for clkgate_delay\n"); 2076 2077 hba->clk_gating.enable_attr.show = ufshcd_clkgate_enable_show; 2078 hba->clk_gating.enable_attr.store = ufshcd_clkgate_enable_store; 2079 sysfs_attr_init(&hba->clk_gating.enable_attr.attr); 2080 hba->clk_gating.enable_attr.attr.name = "clkgate_enable"; 2081 hba->clk_gating.enable_attr.attr.mode = 0644; 2082 if (device_create_file(hba->dev, &hba->clk_gating.enable_attr)) 2083 dev_err(hba->dev, "Failed to create sysfs for clkgate_enable\n"); 2084 } 2085 2086 static void ufshcd_remove_clk_gating_sysfs(struct ufs_hba *hba) 2087 { 2088 if (hba->clk_gating.delay_attr.attr.name) 2089 device_remove_file(hba->dev, &hba->clk_gating.delay_attr); 2090 if (hba->clk_gating.enable_attr.attr.name) 2091 device_remove_file(hba->dev, &hba->clk_gating.enable_attr); 2092 } 2093 2094 static void ufshcd_init_clk_gating(struct ufs_hba *hba) 2095 { 2096 char wq_name[sizeof("ufs_clk_gating_00")]; 2097 2098 if (!ufshcd_is_clkgating_allowed(hba)) 2099 return; 2100 2101 hba->clk_gating.state = CLKS_ON; 2102 2103 hba->clk_gating.delay_ms = 150; 2104 INIT_DELAYED_WORK(&hba->clk_gating.gate_work, ufshcd_gate_work); 2105 INIT_WORK(&hba->clk_gating.ungate_work, ufshcd_ungate_work); 2106 2107 snprintf(wq_name, ARRAY_SIZE(wq_name), "ufs_clk_gating_%d", 2108 hba->host->host_no); 2109 hba->clk_gating.clk_gating_workq = alloc_ordered_workqueue(wq_name, 2110 WQ_MEM_RECLAIM | WQ_HIGHPRI); 2111 2112 ufshcd_init_clk_gating_sysfs(hba); 2113 2114 hba->clk_gating.is_enabled = true; 2115 hba->clk_gating.is_initialized = true; 2116 } 2117 2118 static void ufshcd_exit_clk_gating(struct ufs_hba *hba) 2119 { 2120 if (!hba->clk_gating.is_initialized) 2121 return; 2122 2123 ufshcd_remove_clk_gating_sysfs(hba); 2124 2125 /* Ungate the clock if necessary. */ 2126 ufshcd_hold(hba); 2127 hba->clk_gating.is_initialized = false; 2128 ufshcd_release(hba); 2129 2130 destroy_workqueue(hba->clk_gating.clk_gating_workq); 2131 } 2132 2133 static void ufshcd_clk_scaling_start_busy(struct ufs_hba *hba) 2134 { 2135 bool queue_resume_work = false; 2136 ktime_t curr_t = ktime_get(); 2137 unsigned long flags; 2138 2139 if (!ufshcd_is_clkscaling_supported(hba)) 2140 return; 2141 2142 spin_lock_irqsave(hba->host->host_lock, flags); 2143 if (!hba->clk_scaling.active_reqs++) 2144 queue_resume_work = true; 2145 2146 if (!hba->clk_scaling.is_enabled || hba->pm_op_in_progress) { 2147 spin_unlock_irqrestore(hba->host->host_lock, flags); 2148 return; 2149 } 2150 2151 if (queue_resume_work) 2152 queue_work(hba->clk_scaling.workq, 2153 &hba->clk_scaling.resume_work); 2154 2155 if (!hba->clk_scaling.window_start_t) { 2156 hba->clk_scaling.window_start_t = curr_t; 2157 hba->clk_scaling.tot_busy_t = 0; 2158 hba->clk_scaling.is_busy_started = false; 2159 } 2160 2161 if (!hba->clk_scaling.is_busy_started) { 2162 hba->clk_scaling.busy_start_t = curr_t; 2163 hba->clk_scaling.is_busy_started = true; 2164 } 2165 spin_unlock_irqrestore(hba->host->host_lock, flags); 2166 } 2167 2168 static void ufshcd_clk_scaling_update_busy(struct ufs_hba *hba) 2169 { 2170 struct ufs_clk_scaling *scaling = &hba->clk_scaling; 2171 unsigned long flags; 2172 2173 if (!ufshcd_is_clkscaling_supported(hba)) 2174 return; 2175 2176 spin_lock_irqsave(hba->host->host_lock, flags); 2177 hba->clk_scaling.active_reqs--; 2178 if (!scaling->active_reqs && scaling->is_busy_started) { 2179 scaling->tot_busy_t += ktime_to_us(ktime_sub(ktime_get(), 2180 scaling->busy_start_t)); 2181 scaling->busy_start_t = 0; 2182 scaling->is_busy_started = false; 2183 } 2184 spin_unlock_irqrestore(hba->host->host_lock, flags); 2185 } 2186 2187 static inline int ufshcd_monitor_opcode2dir(u8 opcode) 2188 { 2189 if (opcode == READ_6 || opcode == READ_10 || opcode == READ_16) 2190 return READ; 2191 else if (opcode == WRITE_6 || opcode == WRITE_10 || opcode == WRITE_16) 2192 return WRITE; 2193 else 2194 return -EINVAL; 2195 } 2196 2197 static inline bool ufshcd_should_inform_monitor(struct ufs_hba *hba, 2198 struct ufshcd_lrb *lrbp) 2199 { 2200 const struct ufs_hba_monitor *m = &hba->monitor; 2201 2202 return (m->enabled && lrbp && lrbp->cmd && 2203 (!m->chunk_size || m->chunk_size == lrbp->cmd->sdb.length) && 2204 ktime_before(hba->monitor.enabled_ts, lrbp->issue_time_stamp)); 2205 } 2206 2207 static void ufshcd_start_monitor(struct ufs_hba *hba, 2208 const struct ufshcd_lrb *lrbp) 2209 { 2210 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2211 unsigned long flags; 2212 2213 spin_lock_irqsave(hba->host->host_lock, flags); 2214 if (dir >= 0 && hba->monitor.nr_queued[dir]++ == 0) 2215 hba->monitor.busy_start_ts[dir] = ktime_get(); 2216 spin_unlock_irqrestore(hba->host->host_lock, flags); 2217 } 2218 2219 static void ufshcd_update_monitor(struct ufs_hba *hba, const struct ufshcd_lrb *lrbp) 2220 { 2221 int dir = ufshcd_monitor_opcode2dir(*lrbp->cmd->cmnd); 2222 unsigned long flags; 2223 2224 spin_lock_irqsave(hba->host->host_lock, flags); 2225 if (dir >= 0 && hba->monitor.nr_queued[dir] > 0) { 2226 const struct request *req = scsi_cmd_to_rq(lrbp->cmd); 2227 struct ufs_hba_monitor *m = &hba->monitor; 2228 ktime_t now, inc, lat; 2229 2230 now = lrbp->compl_time_stamp; 2231 inc = ktime_sub(now, m->busy_start_ts[dir]); 2232 m->total_busy[dir] = ktime_add(m->total_busy[dir], inc); 2233 m->nr_sec_rw[dir] += blk_rq_sectors(req); 2234 2235 /* Update latencies */ 2236 m->nr_req[dir]++; 2237 lat = ktime_sub(now, lrbp->issue_time_stamp); 2238 m->lat_sum[dir] += lat; 2239 if (m->lat_max[dir] < lat || !m->lat_max[dir]) 2240 m->lat_max[dir] = lat; 2241 if (m->lat_min[dir] > lat || !m->lat_min[dir]) 2242 m->lat_min[dir] = lat; 2243 2244 m->nr_queued[dir]--; 2245 /* Push forward the busy start of monitor */ 2246 m->busy_start_ts[dir] = now; 2247 } 2248 spin_unlock_irqrestore(hba->host->host_lock, flags); 2249 } 2250 2251 /** 2252 * ufshcd_send_command - Send SCSI or device management commands 2253 * @hba: per adapter instance 2254 * @task_tag: Task tag of the command 2255 * @hwq: pointer to hardware queue instance 2256 */ 2257 static inline 2258 void ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag, 2259 struct ufs_hw_queue *hwq) 2260 { 2261 struct ufshcd_lrb *lrbp = &hba->lrb[task_tag]; 2262 unsigned long flags; 2263 2264 lrbp->issue_time_stamp = ktime_get(); 2265 lrbp->issue_time_stamp_local_clock = local_clock(); 2266 lrbp->compl_time_stamp = ktime_set(0, 0); 2267 lrbp->compl_time_stamp_local_clock = 0; 2268 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_SEND); 2269 if (lrbp->cmd) 2270 ufshcd_clk_scaling_start_busy(hba); 2271 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 2272 ufshcd_start_monitor(hba, lrbp); 2273 2274 if (is_mcq_enabled(hba)) { 2275 int utrd_size = sizeof(struct utp_transfer_req_desc); 2276 struct utp_transfer_req_desc *src = lrbp->utr_descriptor_ptr; 2277 struct utp_transfer_req_desc *dest; 2278 2279 spin_lock(&hwq->sq_lock); 2280 dest = hwq->sqe_base_addr + hwq->sq_tail_slot; 2281 memcpy(dest, src, utrd_size); 2282 ufshcd_inc_sq_tail(hwq); 2283 spin_unlock(&hwq->sq_lock); 2284 } else { 2285 spin_lock_irqsave(&hba->outstanding_lock, flags); 2286 if (hba->vops && hba->vops->setup_xfer_req) 2287 hba->vops->setup_xfer_req(hba, lrbp->task_tag, 2288 !!lrbp->cmd); 2289 __set_bit(lrbp->task_tag, &hba->outstanding_reqs); 2290 ufshcd_writel(hba, 1 << lrbp->task_tag, 2291 REG_UTP_TRANSFER_REQ_DOOR_BELL); 2292 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 2293 } 2294 } 2295 2296 /** 2297 * ufshcd_copy_sense_data - Copy sense data in case of check condition 2298 * @lrbp: pointer to local reference block 2299 */ 2300 static inline void ufshcd_copy_sense_data(struct ufshcd_lrb *lrbp) 2301 { 2302 u8 *const sense_buffer = lrbp->cmd->sense_buffer; 2303 u16 resp_len; 2304 int len; 2305 2306 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header.data_segment_length); 2307 if (sense_buffer && resp_len) { 2308 int len_to_copy; 2309 2310 len = be16_to_cpu(lrbp->ucd_rsp_ptr->sr.sense_data_len); 2311 len_to_copy = min_t(int, UFS_SENSE_SIZE, len); 2312 2313 memcpy(sense_buffer, lrbp->ucd_rsp_ptr->sr.sense_data, 2314 len_to_copy); 2315 } 2316 } 2317 2318 /** 2319 * ufshcd_copy_query_response() - Copy the Query Response and the data 2320 * descriptor 2321 * @hba: per adapter instance 2322 * @lrbp: pointer to local reference block 2323 * 2324 * Return: 0 upon success; < 0 upon failure. 2325 */ 2326 static 2327 int ufshcd_copy_query_response(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2328 { 2329 struct ufs_query_res *query_res = &hba->dev_cmd.query.response; 2330 2331 memcpy(&query_res->upiu_res, &lrbp->ucd_rsp_ptr->qr, QUERY_OSF_SIZE); 2332 2333 /* Get the descriptor */ 2334 if (hba->dev_cmd.query.descriptor && 2335 lrbp->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) { 2336 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + 2337 GENERAL_UPIU_REQUEST_SIZE; 2338 u16 resp_len; 2339 u16 buf_len; 2340 2341 /* data segment length */ 2342 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 2343 .data_segment_length); 2344 buf_len = be16_to_cpu( 2345 hba->dev_cmd.query.request.upiu_req.length); 2346 if (likely(buf_len >= resp_len)) { 2347 memcpy(hba->dev_cmd.query.descriptor, descp, resp_len); 2348 } else { 2349 dev_warn(hba->dev, 2350 "%s: rsp size %d is bigger than buffer size %d", 2351 __func__, resp_len, buf_len); 2352 return -EINVAL; 2353 } 2354 } 2355 2356 return 0; 2357 } 2358 2359 /** 2360 * ufshcd_hba_capabilities - Read controller capabilities 2361 * @hba: per adapter instance 2362 * 2363 * Return: 0 on success, negative on error. 2364 */ 2365 static inline int ufshcd_hba_capabilities(struct ufs_hba *hba) 2366 { 2367 int err; 2368 2369 hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES); 2370 if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS) 2371 hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT; 2372 2373 /* nutrs and nutmrs are 0 based values */ 2374 hba->nutrs = (hba->capabilities & MASK_TRANSFER_REQUESTS_SLOTS) + 1; 2375 hba->nutmrs = 2376 ((hba->capabilities & MASK_TASK_MANAGEMENT_REQUEST_SLOTS) >> 16) + 1; 2377 hba->reserved_slot = hba->nutrs - 1; 2378 2379 /* Read crypto capabilities */ 2380 err = ufshcd_hba_init_crypto_capabilities(hba); 2381 if (err) { 2382 dev_err(hba->dev, "crypto setup failed\n"); 2383 return err; 2384 } 2385 2386 hba->mcq_sup = FIELD_GET(MASK_MCQ_SUPPORT, hba->capabilities); 2387 if (!hba->mcq_sup) 2388 return 0; 2389 2390 hba->mcq_capabilities = ufshcd_readl(hba, REG_MCQCAP); 2391 hba->ext_iid_sup = FIELD_GET(MASK_EXT_IID_SUPPORT, 2392 hba->mcq_capabilities); 2393 2394 return 0; 2395 } 2396 2397 /** 2398 * ufshcd_ready_for_uic_cmd - Check if controller is ready 2399 * to accept UIC commands 2400 * @hba: per adapter instance 2401 * 2402 * Return: true on success, else false. 2403 */ 2404 static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba) 2405 { 2406 u32 val; 2407 int ret = read_poll_timeout(ufshcd_readl, val, val & UIC_COMMAND_READY, 2408 500, UIC_CMD_TIMEOUT * 1000, false, hba, 2409 REG_CONTROLLER_STATUS); 2410 return ret == 0; 2411 } 2412 2413 /** 2414 * ufshcd_get_upmcrs - Get the power mode change request status 2415 * @hba: Pointer to adapter instance 2416 * 2417 * This function gets the UPMCRS field of HCS register 2418 * 2419 * Return: value of UPMCRS field. 2420 */ 2421 static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba) 2422 { 2423 return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7; 2424 } 2425 2426 /** 2427 * ufshcd_dispatch_uic_cmd - Dispatch an UIC command to the Unipro layer 2428 * @hba: per adapter instance 2429 * @uic_cmd: UIC command 2430 */ 2431 static inline void 2432 ufshcd_dispatch_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2433 { 2434 lockdep_assert_held(&hba->uic_cmd_mutex); 2435 2436 WARN_ON(hba->active_uic_cmd); 2437 2438 hba->active_uic_cmd = uic_cmd; 2439 2440 /* Write Args */ 2441 ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1); 2442 ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2); 2443 ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3); 2444 2445 ufshcd_add_uic_command_trace(hba, uic_cmd, UFS_CMD_SEND); 2446 2447 /* Write UIC Cmd */ 2448 ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK, 2449 REG_UIC_COMMAND); 2450 } 2451 2452 /** 2453 * ufshcd_wait_for_uic_cmd - Wait for completion of an UIC command 2454 * @hba: per adapter instance 2455 * @uic_cmd: UIC command 2456 * 2457 * Return: 0 only if success. 2458 */ 2459 static int 2460 ufshcd_wait_for_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2461 { 2462 int ret; 2463 unsigned long flags; 2464 2465 lockdep_assert_held(&hba->uic_cmd_mutex); 2466 2467 if (wait_for_completion_timeout(&uic_cmd->done, 2468 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 2469 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2470 } else { 2471 ret = -ETIMEDOUT; 2472 dev_err(hba->dev, 2473 "uic cmd 0x%x with arg3 0x%x completion timeout\n", 2474 uic_cmd->command, uic_cmd->argument3); 2475 2476 if (!uic_cmd->cmd_active) { 2477 dev_err(hba->dev, "%s: UIC cmd has been completed, return the result\n", 2478 __func__); 2479 ret = uic_cmd->argument2 & MASK_UIC_COMMAND_RESULT; 2480 } 2481 } 2482 2483 spin_lock_irqsave(hba->host->host_lock, flags); 2484 hba->active_uic_cmd = NULL; 2485 spin_unlock_irqrestore(hba->host->host_lock, flags); 2486 2487 return ret; 2488 } 2489 2490 /** 2491 * __ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2492 * @hba: per adapter instance 2493 * @uic_cmd: UIC command 2494 * @completion: initialize the completion only if this is set to true 2495 * 2496 * Return: 0 only if success. 2497 */ 2498 static int 2499 __ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd, 2500 bool completion) 2501 { 2502 lockdep_assert_held(&hba->uic_cmd_mutex); 2503 2504 if (!ufshcd_ready_for_uic_cmd(hba)) { 2505 dev_err(hba->dev, 2506 "Controller not ready to accept UIC commands\n"); 2507 return -EIO; 2508 } 2509 2510 if (completion) 2511 init_completion(&uic_cmd->done); 2512 2513 uic_cmd->cmd_active = 1; 2514 ufshcd_dispatch_uic_cmd(hba, uic_cmd); 2515 2516 return 0; 2517 } 2518 2519 /** 2520 * ufshcd_send_uic_cmd - Send UIC commands and retrieve the result 2521 * @hba: per adapter instance 2522 * @uic_cmd: UIC command 2523 * 2524 * Return: 0 only if success. 2525 */ 2526 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd) 2527 { 2528 int ret; 2529 2530 if (hba->quirks & UFSHCD_QUIRK_BROKEN_UIC_CMD) 2531 return 0; 2532 2533 ufshcd_hold(hba); 2534 mutex_lock(&hba->uic_cmd_mutex); 2535 ufshcd_add_delay_before_dme_cmd(hba); 2536 2537 ret = __ufshcd_send_uic_cmd(hba, uic_cmd, true); 2538 if (!ret) 2539 ret = ufshcd_wait_for_uic_cmd(hba, uic_cmd); 2540 2541 mutex_unlock(&hba->uic_cmd_mutex); 2542 2543 ufshcd_release(hba); 2544 return ret; 2545 } 2546 2547 /** 2548 * ufshcd_sgl_to_prdt - SG list to PRTD (Physical Region Description Table, 4DW format) 2549 * @hba: per-adapter instance 2550 * @lrbp: pointer to local reference block 2551 * @sg_entries: The number of sg lists actually used 2552 * @sg_list: Pointer to SG list 2553 */ 2554 static void ufshcd_sgl_to_prdt(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, int sg_entries, 2555 struct scatterlist *sg_list) 2556 { 2557 struct ufshcd_sg_entry *prd; 2558 struct scatterlist *sg; 2559 int i; 2560 2561 if (sg_entries) { 2562 2563 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) 2564 lrbp->utr_descriptor_ptr->prd_table_length = 2565 cpu_to_le16(sg_entries * ufshcd_sg_entry_size(hba)); 2566 else 2567 lrbp->utr_descriptor_ptr->prd_table_length = cpu_to_le16(sg_entries); 2568 2569 prd = lrbp->ucd_prdt_ptr; 2570 2571 for_each_sg(sg_list, sg, sg_entries, i) { 2572 const unsigned int len = sg_dma_len(sg); 2573 2574 /* 2575 * From the UFSHCI spec: "Data Byte Count (DBC): A '0' 2576 * based value that indicates the length, in bytes, of 2577 * the data block. A maximum of length of 256KB may 2578 * exist for any entry. Bits 1:0 of this field shall be 2579 * 11b to indicate Dword granularity. A value of '3' 2580 * indicates 4 bytes, '7' indicates 8 bytes, etc." 2581 */ 2582 WARN_ONCE(len > SZ_256K, "len = %#x\n", len); 2583 prd->size = cpu_to_le32(len - 1); 2584 prd->addr = cpu_to_le64(sg->dma_address); 2585 prd->reserved = 0; 2586 prd = (void *)prd + ufshcd_sg_entry_size(hba); 2587 } 2588 } else { 2589 lrbp->utr_descriptor_ptr->prd_table_length = 0; 2590 } 2591 } 2592 2593 /** 2594 * ufshcd_map_sg - Map scatter-gather list to prdt 2595 * @hba: per adapter instance 2596 * @lrbp: pointer to local reference block 2597 * 2598 * Return: 0 in case of success, non-zero value in case of failure. 2599 */ 2600 static int ufshcd_map_sg(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2601 { 2602 struct scsi_cmnd *cmd = lrbp->cmd; 2603 int sg_segments = scsi_dma_map(cmd); 2604 2605 if (sg_segments < 0) 2606 return sg_segments; 2607 2608 ufshcd_sgl_to_prdt(hba, lrbp, sg_segments, scsi_sglist(cmd)); 2609 2610 return 0; 2611 } 2612 2613 /** 2614 * ufshcd_enable_intr - enable interrupts 2615 * @hba: per adapter instance 2616 * @intrs: interrupt bits 2617 */ 2618 static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs) 2619 { 2620 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2621 2622 if (hba->ufs_version == ufshci_version(1, 0)) { 2623 u32 rw; 2624 rw = set & INTERRUPT_MASK_RW_VER_10; 2625 set = rw | ((set ^ intrs) & intrs); 2626 } else { 2627 set |= intrs; 2628 } 2629 2630 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2631 } 2632 2633 /** 2634 * ufshcd_disable_intr - disable interrupts 2635 * @hba: per adapter instance 2636 * @intrs: interrupt bits 2637 */ 2638 static void ufshcd_disable_intr(struct ufs_hba *hba, u32 intrs) 2639 { 2640 u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 2641 2642 if (hba->ufs_version == ufshci_version(1, 0)) { 2643 u32 rw; 2644 rw = (set & INTERRUPT_MASK_RW_VER_10) & 2645 ~(intrs & INTERRUPT_MASK_RW_VER_10); 2646 set = rw | ((set & intrs) & ~INTERRUPT_MASK_RW_VER_10); 2647 2648 } else { 2649 set &= ~intrs; 2650 } 2651 2652 ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE); 2653 } 2654 2655 /** 2656 * ufshcd_prepare_req_desc_hdr - Fill UTP Transfer request descriptor header according to request 2657 * descriptor according to request 2658 * @lrbp: pointer to local reference block 2659 * @upiu_flags: flags required in the header 2660 * @cmd_dir: requests data direction 2661 * @ehs_length: Total EHS Length (in 32‐bytes units of all Extra Header Segments) 2662 */ 2663 static void ufshcd_prepare_req_desc_hdr(struct ufshcd_lrb *lrbp, u8 *upiu_flags, 2664 enum dma_data_direction cmd_dir, int ehs_length) 2665 { 2666 struct utp_transfer_req_desc *req_desc = lrbp->utr_descriptor_ptr; 2667 struct request_desc_header *h = &req_desc->header; 2668 enum utp_data_direction data_direction; 2669 2670 *h = (typeof(*h)){ }; 2671 2672 if (cmd_dir == DMA_FROM_DEVICE) { 2673 data_direction = UTP_DEVICE_TO_HOST; 2674 *upiu_flags = UPIU_CMD_FLAGS_READ; 2675 } else if (cmd_dir == DMA_TO_DEVICE) { 2676 data_direction = UTP_HOST_TO_DEVICE; 2677 *upiu_flags = UPIU_CMD_FLAGS_WRITE; 2678 } else { 2679 data_direction = UTP_NO_DATA_TRANSFER; 2680 *upiu_flags = UPIU_CMD_FLAGS_NONE; 2681 } 2682 2683 h->command_type = lrbp->command_type; 2684 h->data_direction = data_direction; 2685 h->ehs_length = ehs_length; 2686 2687 if (lrbp->intr_cmd) 2688 h->interrupt = 1; 2689 2690 /* Prepare crypto related dwords */ 2691 ufshcd_prepare_req_desc_hdr_crypto(lrbp, h); 2692 2693 /* 2694 * assigning invalid value for command status. Controller 2695 * updates OCS on command completion, with the command 2696 * status 2697 */ 2698 h->ocs = OCS_INVALID_COMMAND_STATUS; 2699 2700 req_desc->prd_table_length = 0; 2701 } 2702 2703 /** 2704 * ufshcd_prepare_utp_scsi_cmd_upiu() - fills the utp_transfer_req_desc, 2705 * for scsi commands 2706 * @lrbp: local reference block pointer 2707 * @upiu_flags: flags 2708 */ 2709 static 2710 void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufshcd_lrb *lrbp, u8 upiu_flags) 2711 { 2712 struct scsi_cmnd *cmd = lrbp->cmd; 2713 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2714 unsigned short cdb_len; 2715 2716 ucd_req_ptr->header = (struct utp_upiu_header){ 2717 .transaction_code = UPIU_TRANSACTION_COMMAND, 2718 .flags = upiu_flags, 2719 .lun = lrbp->lun, 2720 .task_tag = lrbp->task_tag, 2721 .command_set_type = UPIU_COMMAND_SET_TYPE_SCSI, 2722 }; 2723 2724 ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(cmd->sdb.length); 2725 2726 cdb_len = min_t(unsigned short, cmd->cmd_len, UFS_CDB_SIZE); 2727 memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE); 2728 memcpy(ucd_req_ptr->sc.cdb, cmd->cmnd, cdb_len); 2729 2730 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2731 } 2732 2733 /** 2734 * ufshcd_prepare_utp_query_req_upiu() - fill the utp_transfer_req_desc for query request 2735 * @hba: UFS hba 2736 * @lrbp: local reference block pointer 2737 * @upiu_flags: flags 2738 */ 2739 static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba, 2740 struct ufshcd_lrb *lrbp, u8 upiu_flags) 2741 { 2742 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2743 struct ufs_query *query = &hba->dev_cmd.query; 2744 u16 len = be16_to_cpu(query->request.upiu_req.length); 2745 2746 /* Query request header */ 2747 ucd_req_ptr->header = (struct utp_upiu_header){ 2748 .transaction_code = UPIU_TRANSACTION_QUERY_REQ, 2749 .flags = upiu_flags, 2750 .lun = lrbp->lun, 2751 .task_tag = lrbp->task_tag, 2752 .query_function = query->request.query_func, 2753 /* Data segment length only need for WRITE_DESC */ 2754 .data_segment_length = 2755 query->request.upiu_req.opcode == 2756 UPIU_QUERY_OPCODE_WRITE_DESC ? 2757 cpu_to_be16(len) : 2758 0, 2759 }; 2760 2761 /* Copy the Query Request buffer as is */ 2762 memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, 2763 QUERY_OSF_SIZE); 2764 2765 /* Copy the Descriptor */ 2766 if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC) 2767 memcpy(ucd_req_ptr + 1, query->descriptor, len); 2768 2769 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2770 } 2771 2772 static inline void ufshcd_prepare_utp_nop_upiu(struct ufshcd_lrb *lrbp) 2773 { 2774 struct utp_upiu_req *ucd_req_ptr = lrbp->ucd_req_ptr; 2775 2776 memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req)); 2777 2778 ucd_req_ptr->header = (struct utp_upiu_header){ 2779 .transaction_code = UPIU_TRANSACTION_NOP_OUT, 2780 .task_tag = lrbp->task_tag, 2781 }; 2782 2783 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 2784 } 2785 2786 /** 2787 * ufshcd_compose_devman_upiu - UFS Protocol Information Unit(UPIU) 2788 * for Device Management Purposes 2789 * @hba: per adapter instance 2790 * @lrbp: pointer to local reference block 2791 * 2792 * Return: 0 upon success; < 0 upon failure. 2793 */ 2794 static int ufshcd_compose_devman_upiu(struct ufs_hba *hba, 2795 struct ufshcd_lrb *lrbp) 2796 { 2797 u8 upiu_flags; 2798 int ret = 0; 2799 2800 if (hba->ufs_version <= ufshci_version(1, 1)) 2801 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 2802 else 2803 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2804 2805 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 2806 if (hba->dev_cmd.type == DEV_CMD_TYPE_QUERY) 2807 ufshcd_prepare_utp_query_req_upiu(hba, lrbp, upiu_flags); 2808 else if (hba->dev_cmd.type == DEV_CMD_TYPE_NOP) 2809 ufshcd_prepare_utp_nop_upiu(lrbp); 2810 else 2811 ret = -EINVAL; 2812 2813 return ret; 2814 } 2815 2816 /** 2817 * ufshcd_comp_scsi_upiu - UFS Protocol Information Unit(UPIU) 2818 * for SCSI Purposes 2819 * @hba: per adapter instance 2820 * @lrbp: pointer to local reference block 2821 */ 2822 static void ufshcd_comp_scsi_upiu(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 2823 { 2824 struct request *rq = scsi_cmd_to_rq(lrbp->cmd); 2825 unsigned int ioprio_class = IOPRIO_PRIO_CLASS(req_get_ioprio(rq)); 2826 u8 upiu_flags; 2827 2828 if (hba->ufs_version <= ufshci_version(1, 1)) 2829 lrbp->command_type = UTP_CMD_TYPE_SCSI; 2830 else 2831 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 2832 2833 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, 2834 lrbp->cmd->sc_data_direction, 0); 2835 if (ioprio_class == IOPRIO_CLASS_RT) 2836 upiu_flags |= UPIU_CMD_FLAGS_CP; 2837 ufshcd_prepare_utp_scsi_cmd_upiu(lrbp, upiu_flags); 2838 } 2839 2840 /** 2841 * ufshcd_upiu_wlun_to_scsi_wlun - maps UPIU W-LUN id to SCSI W-LUN ID 2842 * @upiu_wlun_id: UPIU W-LUN id 2843 * 2844 * Return: SCSI W-LUN id. 2845 */ 2846 static inline u16 ufshcd_upiu_wlun_to_scsi_wlun(u8 upiu_wlun_id) 2847 { 2848 return (upiu_wlun_id & ~UFS_UPIU_WLUN_ID) | SCSI_W_LUN_BASE; 2849 } 2850 2851 static inline bool is_device_wlun(struct scsi_device *sdev) 2852 { 2853 return sdev->lun == 2854 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN); 2855 } 2856 2857 /* 2858 * Associate the UFS controller queue with the default and poll HCTX types. 2859 * Initialize the mq_map[] arrays. 2860 */ 2861 static void ufshcd_map_queues(struct Scsi_Host *shost) 2862 { 2863 struct ufs_hba *hba = shost_priv(shost); 2864 int i, queue_offset = 0; 2865 2866 if (!is_mcq_supported(hba)) { 2867 hba->nr_queues[HCTX_TYPE_DEFAULT] = 1; 2868 hba->nr_queues[HCTX_TYPE_READ] = 0; 2869 hba->nr_queues[HCTX_TYPE_POLL] = 1; 2870 hba->nr_hw_queues = 1; 2871 } 2872 2873 for (i = 0; i < shost->nr_maps; i++) { 2874 struct blk_mq_queue_map *map = &shost->tag_set.map[i]; 2875 2876 map->nr_queues = hba->nr_queues[i]; 2877 if (!map->nr_queues) 2878 continue; 2879 map->queue_offset = queue_offset; 2880 if (i == HCTX_TYPE_POLL && !is_mcq_supported(hba)) 2881 map->queue_offset = 0; 2882 2883 blk_mq_map_queues(map); 2884 queue_offset += map->nr_queues; 2885 } 2886 } 2887 2888 static void ufshcd_init_lrb(struct ufs_hba *hba, struct ufshcd_lrb *lrb, int i) 2889 { 2890 struct utp_transfer_cmd_desc *cmd_descp = (void *)hba->ucdl_base_addr + 2891 i * ufshcd_get_ucd_size(hba); 2892 struct utp_transfer_req_desc *utrdlp = hba->utrdl_base_addr; 2893 dma_addr_t cmd_desc_element_addr = hba->ucdl_dma_addr + 2894 i * ufshcd_get_ucd_size(hba); 2895 u16 response_offset = offsetof(struct utp_transfer_cmd_desc, 2896 response_upiu); 2897 u16 prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table); 2898 2899 lrb->utr_descriptor_ptr = utrdlp + i; 2900 lrb->utrd_dma_addr = hba->utrdl_dma_addr + 2901 i * sizeof(struct utp_transfer_req_desc); 2902 lrb->ucd_req_ptr = (struct utp_upiu_req *)cmd_descp->command_upiu; 2903 lrb->ucd_req_dma_addr = cmd_desc_element_addr; 2904 lrb->ucd_rsp_ptr = (struct utp_upiu_rsp *)cmd_descp->response_upiu; 2905 lrb->ucd_rsp_dma_addr = cmd_desc_element_addr + response_offset; 2906 lrb->ucd_prdt_ptr = (struct ufshcd_sg_entry *)cmd_descp->prd_table; 2907 lrb->ucd_prdt_dma_addr = cmd_desc_element_addr + prdt_offset; 2908 } 2909 2910 /** 2911 * ufshcd_queuecommand - main entry point for SCSI requests 2912 * @host: SCSI host pointer 2913 * @cmd: command from SCSI Midlayer 2914 * 2915 * Return: 0 for success, non-zero in case of failure. 2916 */ 2917 static int ufshcd_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd) 2918 { 2919 struct ufs_hba *hba = shost_priv(host); 2920 int tag = scsi_cmd_to_rq(cmd)->tag; 2921 struct ufshcd_lrb *lrbp; 2922 int err = 0; 2923 struct ufs_hw_queue *hwq = NULL; 2924 2925 switch (hba->ufshcd_state) { 2926 case UFSHCD_STATE_OPERATIONAL: 2927 break; 2928 case UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: 2929 /* 2930 * SCSI error handler can call ->queuecommand() while UFS error 2931 * handler is in progress. Error interrupts could change the 2932 * state from UFSHCD_STATE_RESET to 2933 * UFSHCD_STATE_EH_SCHEDULED_NON_FATAL. Prevent requests 2934 * being issued in that case. 2935 */ 2936 if (ufshcd_eh_in_progress(hba)) { 2937 err = SCSI_MLQUEUE_HOST_BUSY; 2938 goto out; 2939 } 2940 break; 2941 case UFSHCD_STATE_EH_SCHEDULED_FATAL: 2942 /* 2943 * pm_runtime_get_sync() is used at error handling preparation 2944 * stage. If a scsi cmd, e.g. the SSU cmd, is sent from hba's 2945 * PM ops, it can never be finished if we let SCSI layer keep 2946 * retrying it, which gets err handler stuck forever. Neither 2947 * can we let the scsi cmd pass through, because UFS is in bad 2948 * state, the scsi cmd may eventually time out, which will get 2949 * err handler blocked for too long. So, just fail the scsi cmd 2950 * sent from PM ops, err handler can recover PM error anyways. 2951 */ 2952 if (hba->pm_op_in_progress) { 2953 hba->force_reset = true; 2954 set_host_byte(cmd, DID_BAD_TARGET); 2955 scsi_done(cmd); 2956 goto out; 2957 } 2958 fallthrough; 2959 case UFSHCD_STATE_RESET: 2960 err = SCSI_MLQUEUE_HOST_BUSY; 2961 goto out; 2962 case UFSHCD_STATE_ERROR: 2963 set_host_byte(cmd, DID_ERROR); 2964 scsi_done(cmd); 2965 goto out; 2966 } 2967 2968 hba->req_abort_count = 0; 2969 2970 ufshcd_hold(hba); 2971 2972 lrbp = &hba->lrb[tag]; 2973 lrbp->cmd = cmd; 2974 lrbp->task_tag = tag; 2975 lrbp->lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 2976 lrbp->intr_cmd = !ufshcd_is_intr_aggr_allowed(hba); 2977 2978 ufshcd_prepare_lrbp_crypto(scsi_cmd_to_rq(cmd), lrbp); 2979 2980 lrbp->req_abort_skip = false; 2981 2982 ufshcd_comp_scsi_upiu(hba, lrbp); 2983 2984 err = ufshcd_map_sg(hba, lrbp); 2985 if (err) { 2986 ufshcd_release(hba); 2987 goto out; 2988 } 2989 2990 if (is_mcq_enabled(hba)) 2991 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(cmd)); 2992 2993 ufshcd_send_command(hba, tag, hwq); 2994 2995 out: 2996 if (ufs_trigger_eh()) { 2997 unsigned long flags; 2998 2999 spin_lock_irqsave(hba->host->host_lock, flags); 3000 ufshcd_schedule_eh_work(hba); 3001 spin_unlock_irqrestore(hba->host->host_lock, flags); 3002 } 3003 3004 return err; 3005 } 3006 3007 static int ufshcd_compose_dev_cmd(struct ufs_hba *hba, 3008 struct ufshcd_lrb *lrbp, enum dev_cmd_type cmd_type, int tag) 3009 { 3010 lrbp->cmd = NULL; 3011 lrbp->task_tag = tag; 3012 lrbp->lun = 0; /* device management cmd is not specific to any LUN */ 3013 lrbp->intr_cmd = true; /* No interrupt aggregation */ 3014 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 3015 hba->dev_cmd.type = cmd_type; 3016 3017 return ufshcd_compose_devman_upiu(hba, lrbp); 3018 } 3019 3020 /* 3021 * Check with the block layer if the command is inflight 3022 * @cmd: command to check. 3023 * 3024 * Return: true if command is inflight; false if not. 3025 */ 3026 bool ufshcd_cmd_inflight(struct scsi_cmnd *cmd) 3027 { 3028 struct request *rq; 3029 3030 if (!cmd) 3031 return false; 3032 3033 rq = scsi_cmd_to_rq(cmd); 3034 if (!blk_mq_request_started(rq)) 3035 return false; 3036 3037 return true; 3038 } 3039 3040 /* 3041 * Clear the pending command in the controller and wait until 3042 * the controller confirms that the command has been cleared. 3043 * @hba: per adapter instance 3044 * @task_tag: The tag number of the command to be cleared. 3045 */ 3046 static int ufshcd_clear_cmd(struct ufs_hba *hba, u32 task_tag) 3047 { 3048 u32 mask = 1U << task_tag; 3049 unsigned long flags; 3050 int err; 3051 3052 if (is_mcq_enabled(hba)) { 3053 /* 3054 * MCQ mode. Clean up the MCQ resources similar to 3055 * what the ufshcd_utrl_clear() does for SDB mode. 3056 */ 3057 err = ufshcd_mcq_sq_cleanup(hba, task_tag); 3058 if (err) { 3059 dev_err(hba->dev, "%s: failed tag=%d. err=%d\n", 3060 __func__, task_tag, err); 3061 return err; 3062 } 3063 return 0; 3064 } 3065 3066 /* clear outstanding transaction before retry */ 3067 spin_lock_irqsave(hba->host->host_lock, flags); 3068 ufshcd_utrl_clear(hba, mask); 3069 spin_unlock_irqrestore(hba->host->host_lock, flags); 3070 3071 /* 3072 * wait for h/w to clear corresponding bit in door-bell. 3073 * max. wait is 1 sec. 3074 */ 3075 return ufshcd_wait_for_register(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL, 3076 mask, ~mask, 1000, 1000); 3077 } 3078 3079 /** 3080 * ufshcd_dev_cmd_completion() - handles device management command responses 3081 * @hba: per adapter instance 3082 * @lrbp: pointer to local reference block 3083 * 3084 * Return: 0 upon success; < 0 upon failure. 3085 */ 3086 static int 3087 ufshcd_dev_cmd_completion(struct ufs_hba *hba, struct ufshcd_lrb *lrbp) 3088 { 3089 enum upiu_response_transaction resp; 3090 int err = 0; 3091 3092 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 3093 resp = ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr); 3094 3095 switch (resp) { 3096 case UPIU_TRANSACTION_NOP_IN: 3097 if (hba->dev_cmd.type != DEV_CMD_TYPE_NOP) { 3098 err = -EINVAL; 3099 dev_err(hba->dev, "%s: unexpected response %x\n", 3100 __func__, resp); 3101 } 3102 break; 3103 case UPIU_TRANSACTION_QUERY_RSP: { 3104 u8 response = lrbp->ucd_rsp_ptr->header.response; 3105 3106 if (response == 0) 3107 err = ufshcd_copy_query_response(hba, lrbp); 3108 break; 3109 } 3110 case UPIU_TRANSACTION_REJECT_UPIU: 3111 /* TODO: handle Reject UPIU Response */ 3112 err = -EPERM; 3113 dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n", 3114 __func__); 3115 break; 3116 case UPIU_TRANSACTION_RESPONSE: 3117 if (hba->dev_cmd.type != DEV_CMD_TYPE_RPMB) { 3118 err = -EINVAL; 3119 dev_err(hba->dev, "%s: unexpected response %x\n", __func__, resp); 3120 } 3121 break; 3122 default: 3123 err = -EINVAL; 3124 dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n", 3125 __func__, resp); 3126 break; 3127 } 3128 3129 return err; 3130 } 3131 3132 static int ufshcd_wait_for_dev_cmd(struct ufs_hba *hba, 3133 struct ufshcd_lrb *lrbp, int max_timeout) 3134 { 3135 unsigned long time_left = msecs_to_jiffies(max_timeout); 3136 unsigned long flags; 3137 bool pending; 3138 int err; 3139 3140 retry: 3141 time_left = wait_for_completion_timeout(hba->dev_cmd.complete, 3142 time_left); 3143 3144 if (likely(time_left)) { 3145 /* 3146 * The completion handler called complete() and the caller of 3147 * this function still owns the @lrbp tag so the code below does 3148 * not trigger any race conditions. 3149 */ 3150 hba->dev_cmd.complete = NULL; 3151 err = ufshcd_get_tr_ocs(lrbp, NULL); 3152 if (!err) 3153 err = ufshcd_dev_cmd_completion(hba, lrbp); 3154 } else { 3155 err = -ETIMEDOUT; 3156 dev_dbg(hba->dev, "%s: dev_cmd request timedout, tag %d\n", 3157 __func__, lrbp->task_tag); 3158 3159 /* MCQ mode */ 3160 if (is_mcq_enabled(hba)) { 3161 err = ufshcd_clear_cmd(hba, lrbp->task_tag); 3162 hba->dev_cmd.complete = NULL; 3163 return err; 3164 } 3165 3166 /* SDB mode */ 3167 if (ufshcd_clear_cmd(hba, lrbp->task_tag) == 0) { 3168 /* successfully cleared the command, retry if needed */ 3169 err = -EAGAIN; 3170 /* 3171 * Since clearing the command succeeded we also need to 3172 * clear the task tag bit from the outstanding_reqs 3173 * variable. 3174 */ 3175 spin_lock_irqsave(&hba->outstanding_lock, flags); 3176 pending = test_bit(lrbp->task_tag, 3177 &hba->outstanding_reqs); 3178 if (pending) { 3179 hba->dev_cmd.complete = NULL; 3180 __clear_bit(lrbp->task_tag, 3181 &hba->outstanding_reqs); 3182 } 3183 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3184 3185 if (!pending) { 3186 /* 3187 * The completion handler ran while we tried to 3188 * clear the command. 3189 */ 3190 time_left = 1; 3191 goto retry; 3192 } 3193 } else { 3194 dev_err(hba->dev, "%s: failed to clear tag %d\n", 3195 __func__, lrbp->task_tag); 3196 3197 spin_lock_irqsave(&hba->outstanding_lock, flags); 3198 pending = test_bit(lrbp->task_tag, 3199 &hba->outstanding_reqs); 3200 if (pending) 3201 hba->dev_cmd.complete = NULL; 3202 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 3203 3204 if (!pending) { 3205 /* 3206 * The completion handler ran while we tried to 3207 * clear the command. 3208 */ 3209 time_left = 1; 3210 goto retry; 3211 } 3212 } 3213 } 3214 3215 return err; 3216 } 3217 3218 /** 3219 * ufshcd_exec_dev_cmd - API for sending device management requests 3220 * @hba: UFS hba 3221 * @cmd_type: specifies the type (NOP, Query...) 3222 * @timeout: timeout in milliseconds 3223 * 3224 * Return: 0 upon success; < 0 upon failure. 3225 * 3226 * NOTE: Since there is only one available tag for device management commands, 3227 * it is expected you hold the hba->dev_cmd.lock mutex. 3228 */ 3229 static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, 3230 enum dev_cmd_type cmd_type, int timeout) 3231 { 3232 DECLARE_COMPLETION_ONSTACK(wait); 3233 const u32 tag = hba->reserved_slot; 3234 struct ufshcd_lrb *lrbp; 3235 int err; 3236 3237 /* Protects use of hba->reserved_slot. */ 3238 lockdep_assert_held(&hba->dev_cmd.lock); 3239 3240 down_read(&hba->clk_scaling_lock); 3241 3242 lrbp = &hba->lrb[tag]; 3243 lrbp->cmd = NULL; 3244 err = ufshcd_compose_dev_cmd(hba, lrbp, cmd_type, tag); 3245 if (unlikely(err)) 3246 goto out; 3247 3248 hba->dev_cmd.complete = &wait; 3249 3250 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 3251 3252 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 3253 err = ufshcd_wait_for_dev_cmd(hba, lrbp, timeout); 3254 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 3255 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 3256 3257 out: 3258 up_read(&hba->clk_scaling_lock); 3259 return err; 3260 } 3261 3262 /** 3263 * ufshcd_init_query() - init the query response and request parameters 3264 * @hba: per-adapter instance 3265 * @request: address of the request pointer to be initialized 3266 * @response: address of the response pointer to be initialized 3267 * @opcode: operation to perform 3268 * @idn: flag idn to access 3269 * @index: LU number to access 3270 * @selector: query/flag/descriptor further identification 3271 */ 3272 static inline void ufshcd_init_query(struct ufs_hba *hba, 3273 struct ufs_query_req **request, struct ufs_query_res **response, 3274 enum query_opcode opcode, u8 idn, u8 index, u8 selector) 3275 { 3276 *request = &hba->dev_cmd.query.request; 3277 *response = &hba->dev_cmd.query.response; 3278 memset(*request, 0, sizeof(struct ufs_query_req)); 3279 memset(*response, 0, sizeof(struct ufs_query_res)); 3280 (*request)->upiu_req.opcode = opcode; 3281 (*request)->upiu_req.idn = idn; 3282 (*request)->upiu_req.index = index; 3283 (*request)->upiu_req.selector = selector; 3284 } 3285 3286 static int ufshcd_query_flag_retry(struct ufs_hba *hba, 3287 enum query_opcode opcode, enum flag_idn idn, u8 index, bool *flag_res) 3288 { 3289 int ret; 3290 int retries; 3291 3292 for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) { 3293 ret = ufshcd_query_flag(hba, opcode, idn, index, flag_res); 3294 if (ret) 3295 dev_dbg(hba->dev, 3296 "%s: failed with error %d, retries %d\n", 3297 __func__, ret, retries); 3298 else 3299 break; 3300 } 3301 3302 if (ret) 3303 dev_err(hba->dev, 3304 "%s: query flag, opcode %d, idn %d, failed with error %d after %d retries\n", 3305 __func__, opcode, idn, ret, retries); 3306 return ret; 3307 } 3308 3309 /** 3310 * ufshcd_query_flag() - API function for sending flag query requests 3311 * @hba: per-adapter instance 3312 * @opcode: flag query to perform 3313 * @idn: flag idn to access 3314 * @index: flag index to access 3315 * @flag_res: the flag value after the query request completes 3316 * 3317 * Return: 0 for success, non-zero in case of failure. 3318 */ 3319 int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode, 3320 enum flag_idn idn, u8 index, bool *flag_res) 3321 { 3322 struct ufs_query_req *request = NULL; 3323 struct ufs_query_res *response = NULL; 3324 int err, selector = 0; 3325 int timeout = QUERY_REQ_TIMEOUT; 3326 3327 BUG_ON(!hba); 3328 3329 ufshcd_hold(hba); 3330 mutex_lock(&hba->dev_cmd.lock); 3331 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3332 selector); 3333 3334 switch (opcode) { 3335 case UPIU_QUERY_OPCODE_SET_FLAG: 3336 case UPIU_QUERY_OPCODE_CLEAR_FLAG: 3337 case UPIU_QUERY_OPCODE_TOGGLE_FLAG: 3338 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3339 break; 3340 case UPIU_QUERY_OPCODE_READ_FLAG: 3341 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3342 if (!flag_res) { 3343 /* No dummy reads */ 3344 dev_err(hba->dev, "%s: Invalid argument for read request\n", 3345 __func__); 3346 err = -EINVAL; 3347 goto out_unlock; 3348 } 3349 break; 3350 default: 3351 dev_err(hba->dev, 3352 "%s: Expected query flag opcode but got = %d\n", 3353 __func__, opcode); 3354 err = -EINVAL; 3355 goto out_unlock; 3356 } 3357 3358 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout); 3359 3360 if (err) { 3361 dev_err(hba->dev, 3362 "%s: Sending flag query for idn %d failed, err = %d\n", 3363 __func__, idn, err); 3364 goto out_unlock; 3365 } 3366 3367 if (flag_res) 3368 *flag_res = (be32_to_cpu(response->upiu_res.value) & 3369 MASK_QUERY_UPIU_FLAG_LOC) & 0x1; 3370 3371 out_unlock: 3372 mutex_unlock(&hba->dev_cmd.lock); 3373 ufshcd_release(hba); 3374 return err; 3375 } 3376 3377 /** 3378 * ufshcd_query_attr - API function for sending attribute requests 3379 * @hba: per-adapter instance 3380 * @opcode: attribute opcode 3381 * @idn: attribute idn to access 3382 * @index: index field 3383 * @selector: selector field 3384 * @attr_val: the attribute value after the query request completes 3385 * 3386 * Return: 0 for success, non-zero in case of failure. 3387 */ 3388 int ufshcd_query_attr(struct ufs_hba *hba, enum query_opcode opcode, 3389 enum attr_idn idn, u8 index, u8 selector, u32 *attr_val) 3390 { 3391 struct ufs_query_req *request = NULL; 3392 struct ufs_query_res *response = NULL; 3393 int err; 3394 3395 BUG_ON(!hba); 3396 3397 if (!attr_val) { 3398 dev_err(hba->dev, "%s: attribute value required for opcode 0x%x\n", 3399 __func__, opcode); 3400 return -EINVAL; 3401 } 3402 3403 ufshcd_hold(hba); 3404 3405 mutex_lock(&hba->dev_cmd.lock); 3406 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3407 selector); 3408 3409 switch (opcode) { 3410 case UPIU_QUERY_OPCODE_WRITE_ATTR: 3411 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3412 request->upiu_req.value = cpu_to_be32(*attr_val); 3413 break; 3414 case UPIU_QUERY_OPCODE_READ_ATTR: 3415 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3416 break; 3417 default: 3418 dev_err(hba->dev, "%s: Expected query attr opcode but got = 0x%.2x\n", 3419 __func__, opcode); 3420 err = -EINVAL; 3421 goto out_unlock; 3422 } 3423 3424 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3425 3426 if (err) { 3427 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3428 __func__, opcode, idn, index, err); 3429 goto out_unlock; 3430 } 3431 3432 *attr_val = be32_to_cpu(response->upiu_res.value); 3433 3434 out_unlock: 3435 mutex_unlock(&hba->dev_cmd.lock); 3436 ufshcd_release(hba); 3437 return err; 3438 } 3439 3440 /** 3441 * ufshcd_query_attr_retry() - API function for sending query 3442 * attribute with retries 3443 * @hba: per-adapter instance 3444 * @opcode: attribute opcode 3445 * @idn: attribute idn to access 3446 * @index: index field 3447 * @selector: selector field 3448 * @attr_val: the attribute value after the query request 3449 * completes 3450 * 3451 * Return: 0 for success, non-zero in case of failure. 3452 */ 3453 int ufshcd_query_attr_retry(struct ufs_hba *hba, 3454 enum query_opcode opcode, enum attr_idn idn, u8 index, u8 selector, 3455 u32 *attr_val) 3456 { 3457 int ret = 0; 3458 u32 retries; 3459 3460 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3461 ret = ufshcd_query_attr(hba, opcode, idn, index, 3462 selector, attr_val); 3463 if (ret) 3464 dev_dbg(hba->dev, "%s: failed with error %d, retries %d\n", 3465 __func__, ret, retries); 3466 else 3467 break; 3468 } 3469 3470 if (ret) 3471 dev_err(hba->dev, 3472 "%s: query attribute, idn %d, failed with error %d after %d retries\n", 3473 __func__, idn, ret, QUERY_REQ_RETRIES); 3474 return ret; 3475 } 3476 3477 static int __ufshcd_query_descriptor(struct ufs_hba *hba, 3478 enum query_opcode opcode, enum desc_idn idn, u8 index, 3479 u8 selector, u8 *desc_buf, int *buf_len) 3480 { 3481 struct ufs_query_req *request = NULL; 3482 struct ufs_query_res *response = NULL; 3483 int err; 3484 3485 BUG_ON(!hba); 3486 3487 if (!desc_buf) { 3488 dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n", 3489 __func__, opcode); 3490 return -EINVAL; 3491 } 3492 3493 if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) { 3494 dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n", 3495 __func__, *buf_len); 3496 return -EINVAL; 3497 } 3498 3499 ufshcd_hold(hba); 3500 3501 mutex_lock(&hba->dev_cmd.lock); 3502 ufshcd_init_query(hba, &request, &response, opcode, idn, index, 3503 selector); 3504 hba->dev_cmd.query.descriptor = desc_buf; 3505 request->upiu_req.length = cpu_to_be16(*buf_len); 3506 3507 switch (opcode) { 3508 case UPIU_QUERY_OPCODE_WRITE_DESC: 3509 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 3510 break; 3511 case UPIU_QUERY_OPCODE_READ_DESC: 3512 request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST; 3513 break; 3514 default: 3515 dev_err(hba->dev, 3516 "%s: Expected query descriptor opcode but got = 0x%.2x\n", 3517 __func__, opcode); 3518 err = -EINVAL; 3519 goto out_unlock; 3520 } 3521 3522 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 3523 3524 if (err) { 3525 dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n", 3526 __func__, opcode, idn, index, err); 3527 goto out_unlock; 3528 } 3529 3530 *buf_len = be16_to_cpu(response->upiu_res.length); 3531 3532 out_unlock: 3533 hba->dev_cmd.query.descriptor = NULL; 3534 mutex_unlock(&hba->dev_cmd.lock); 3535 ufshcd_release(hba); 3536 return err; 3537 } 3538 3539 /** 3540 * ufshcd_query_descriptor_retry - API function for sending descriptor requests 3541 * @hba: per-adapter instance 3542 * @opcode: attribute opcode 3543 * @idn: attribute idn to access 3544 * @index: index field 3545 * @selector: selector field 3546 * @desc_buf: the buffer that contains the descriptor 3547 * @buf_len: length parameter passed to the device 3548 * 3549 * The buf_len parameter will contain, on return, the length parameter 3550 * received on the response. 3551 * 3552 * Return: 0 for success, non-zero in case of failure. 3553 */ 3554 int ufshcd_query_descriptor_retry(struct ufs_hba *hba, 3555 enum query_opcode opcode, 3556 enum desc_idn idn, u8 index, 3557 u8 selector, 3558 u8 *desc_buf, int *buf_len) 3559 { 3560 int err; 3561 int retries; 3562 3563 for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) { 3564 err = __ufshcd_query_descriptor(hba, opcode, idn, index, 3565 selector, desc_buf, buf_len); 3566 if (!err || err == -EINVAL) 3567 break; 3568 } 3569 3570 return err; 3571 } 3572 3573 /** 3574 * ufshcd_read_desc_param - read the specified descriptor parameter 3575 * @hba: Pointer to adapter instance 3576 * @desc_id: descriptor idn value 3577 * @desc_index: descriptor index 3578 * @param_offset: offset of the parameter to read 3579 * @param_read_buf: pointer to buffer where parameter would be read 3580 * @param_size: sizeof(param_read_buf) 3581 * 3582 * Return: 0 in case of success, non-zero otherwise. 3583 */ 3584 int ufshcd_read_desc_param(struct ufs_hba *hba, 3585 enum desc_idn desc_id, 3586 int desc_index, 3587 u8 param_offset, 3588 u8 *param_read_buf, 3589 u8 param_size) 3590 { 3591 int ret; 3592 u8 *desc_buf; 3593 int buff_len = QUERY_DESC_MAX_SIZE; 3594 bool is_kmalloc = true; 3595 3596 /* Safety check */ 3597 if (desc_id >= QUERY_DESC_IDN_MAX || !param_size) 3598 return -EINVAL; 3599 3600 /* Check whether we need temp memory */ 3601 if (param_offset != 0 || param_size < buff_len) { 3602 desc_buf = kzalloc(buff_len, GFP_KERNEL); 3603 if (!desc_buf) 3604 return -ENOMEM; 3605 } else { 3606 desc_buf = param_read_buf; 3607 is_kmalloc = false; 3608 } 3609 3610 /* Request for full descriptor */ 3611 ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC, 3612 desc_id, desc_index, 0, 3613 desc_buf, &buff_len); 3614 if (ret) { 3615 dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d\n", 3616 __func__, desc_id, desc_index, param_offset, ret); 3617 goto out; 3618 } 3619 3620 /* Update descriptor length */ 3621 buff_len = desc_buf[QUERY_DESC_LENGTH_OFFSET]; 3622 3623 if (param_offset >= buff_len) { 3624 dev_err(hba->dev, "%s: Invalid offset 0x%x in descriptor IDN 0x%x, length 0x%x\n", 3625 __func__, param_offset, desc_id, buff_len); 3626 ret = -EINVAL; 3627 goto out; 3628 } 3629 3630 /* Sanity check */ 3631 if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) { 3632 dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header\n", 3633 __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]); 3634 ret = -EINVAL; 3635 goto out; 3636 } 3637 3638 if (is_kmalloc) { 3639 /* Make sure we don't copy more data than available */ 3640 if (param_offset >= buff_len) 3641 ret = -EINVAL; 3642 else 3643 memcpy(param_read_buf, &desc_buf[param_offset], 3644 min_t(u32, param_size, buff_len - param_offset)); 3645 } 3646 out: 3647 if (is_kmalloc) 3648 kfree(desc_buf); 3649 return ret; 3650 } 3651 3652 /** 3653 * struct uc_string_id - unicode string 3654 * 3655 * @len: size of this descriptor inclusive 3656 * @type: descriptor type 3657 * @uc: unicode string character 3658 */ 3659 struct uc_string_id { 3660 u8 len; 3661 u8 type; 3662 wchar_t uc[]; 3663 } __packed; 3664 3665 /* replace non-printable or non-ASCII characters with spaces */ 3666 static inline char ufshcd_remove_non_printable(u8 ch) 3667 { 3668 return (ch >= 0x20 && ch <= 0x7e) ? ch : ' '; 3669 } 3670 3671 /** 3672 * ufshcd_read_string_desc - read string descriptor 3673 * @hba: pointer to adapter instance 3674 * @desc_index: descriptor index 3675 * @buf: pointer to buffer where descriptor would be read, 3676 * the caller should free the memory. 3677 * @ascii: if true convert from unicode to ascii characters 3678 * null terminated string. 3679 * 3680 * Return: 3681 * * string size on success. 3682 * * -ENOMEM: on allocation failure 3683 * * -EINVAL: on a wrong parameter 3684 */ 3685 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index, 3686 u8 **buf, bool ascii) 3687 { 3688 struct uc_string_id *uc_str; 3689 u8 *str; 3690 int ret; 3691 3692 if (!buf) 3693 return -EINVAL; 3694 3695 uc_str = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 3696 if (!uc_str) 3697 return -ENOMEM; 3698 3699 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_STRING, desc_index, 0, 3700 (u8 *)uc_str, QUERY_DESC_MAX_SIZE); 3701 if (ret < 0) { 3702 dev_err(hba->dev, "Reading String Desc failed after %d retries. err = %d\n", 3703 QUERY_REQ_RETRIES, ret); 3704 str = NULL; 3705 goto out; 3706 } 3707 3708 if (uc_str->len <= QUERY_DESC_HDR_SIZE) { 3709 dev_dbg(hba->dev, "String Desc is of zero length\n"); 3710 str = NULL; 3711 ret = 0; 3712 goto out; 3713 } 3714 3715 if (ascii) { 3716 ssize_t ascii_len; 3717 int i; 3718 /* remove header and divide by 2 to move from UTF16 to UTF8 */ 3719 ascii_len = (uc_str->len - QUERY_DESC_HDR_SIZE) / 2 + 1; 3720 str = kzalloc(ascii_len, GFP_KERNEL); 3721 if (!str) { 3722 ret = -ENOMEM; 3723 goto out; 3724 } 3725 3726 /* 3727 * the descriptor contains string in UTF16 format 3728 * we need to convert to utf-8 so it can be displayed 3729 */ 3730 ret = utf16s_to_utf8s(uc_str->uc, 3731 uc_str->len - QUERY_DESC_HDR_SIZE, 3732 UTF16_BIG_ENDIAN, str, ascii_len - 1); 3733 3734 /* replace non-printable or non-ASCII characters with spaces */ 3735 for (i = 0; i < ret; i++) 3736 str[i] = ufshcd_remove_non_printable(str[i]); 3737 3738 str[ret++] = '\0'; 3739 3740 } else { 3741 str = kmemdup(uc_str, uc_str->len, GFP_KERNEL); 3742 if (!str) { 3743 ret = -ENOMEM; 3744 goto out; 3745 } 3746 ret = uc_str->len; 3747 } 3748 out: 3749 *buf = str; 3750 kfree(uc_str); 3751 return ret; 3752 } 3753 3754 /** 3755 * ufshcd_read_unit_desc_param - read the specified unit descriptor parameter 3756 * @hba: Pointer to adapter instance 3757 * @lun: lun id 3758 * @param_offset: offset of the parameter to read 3759 * @param_read_buf: pointer to buffer where parameter would be read 3760 * @param_size: sizeof(param_read_buf) 3761 * 3762 * Return: 0 in case of success, non-zero otherwise. 3763 */ 3764 static inline int ufshcd_read_unit_desc_param(struct ufs_hba *hba, 3765 int lun, 3766 enum unit_desc_param param_offset, 3767 u8 *param_read_buf, 3768 u32 param_size) 3769 { 3770 /* 3771 * Unit descriptors are only available for general purpose LUs (LUN id 3772 * from 0 to 7) and RPMB Well known LU. 3773 */ 3774 if (!ufs_is_valid_unit_desc_lun(&hba->dev_info, lun)) 3775 return -EOPNOTSUPP; 3776 3777 return ufshcd_read_desc_param(hba, QUERY_DESC_IDN_UNIT, lun, 3778 param_offset, param_read_buf, param_size); 3779 } 3780 3781 static int ufshcd_get_ref_clk_gating_wait(struct ufs_hba *hba) 3782 { 3783 int err = 0; 3784 u32 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3785 3786 if (hba->dev_info.wspecversion >= 0x300) { 3787 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 3788 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME, 0, 0, 3789 &gating_wait); 3790 if (err) 3791 dev_err(hba->dev, "Failed reading bRefClkGatingWait. err = %d, use default %uus\n", 3792 err, gating_wait); 3793 3794 if (gating_wait == 0) { 3795 gating_wait = UFSHCD_REF_CLK_GATING_WAIT_US; 3796 dev_err(hba->dev, "Undefined ref clk gating wait time, use default %uus\n", 3797 gating_wait); 3798 } 3799 3800 hba->dev_info.clk_gating_wait_us = gating_wait; 3801 } 3802 3803 return err; 3804 } 3805 3806 /** 3807 * ufshcd_memory_alloc - allocate memory for host memory space data structures 3808 * @hba: per adapter instance 3809 * 3810 * 1. Allocate DMA memory for Command Descriptor array 3811 * Each command descriptor consist of Command UPIU, Response UPIU and PRDT 3812 * 2. Allocate DMA memory for UTP Transfer Request Descriptor List (UTRDL). 3813 * 3. Allocate DMA memory for UTP Task Management Request Descriptor List 3814 * (UTMRDL) 3815 * 4. Allocate memory for local reference block(lrb). 3816 * 3817 * Return: 0 for success, non-zero in case of failure. 3818 */ 3819 static int ufshcd_memory_alloc(struct ufs_hba *hba) 3820 { 3821 size_t utmrdl_size, utrdl_size, ucdl_size; 3822 3823 /* Allocate memory for UTP command descriptors */ 3824 ucdl_size = ufshcd_get_ucd_size(hba) * hba->nutrs; 3825 hba->ucdl_base_addr = dmam_alloc_coherent(hba->dev, 3826 ucdl_size, 3827 &hba->ucdl_dma_addr, 3828 GFP_KERNEL); 3829 3830 /* 3831 * UFSHCI requires UTP command descriptor to be 128 byte aligned. 3832 */ 3833 if (!hba->ucdl_base_addr || 3834 WARN_ON(hba->ucdl_dma_addr & (128 - 1))) { 3835 dev_err(hba->dev, 3836 "Command Descriptor Memory allocation failed\n"); 3837 goto out; 3838 } 3839 3840 /* 3841 * Allocate memory for UTP Transfer descriptors 3842 * UFSHCI requires 1KB alignment of UTRD 3843 */ 3844 utrdl_size = (sizeof(struct utp_transfer_req_desc) * hba->nutrs); 3845 hba->utrdl_base_addr = dmam_alloc_coherent(hba->dev, 3846 utrdl_size, 3847 &hba->utrdl_dma_addr, 3848 GFP_KERNEL); 3849 if (!hba->utrdl_base_addr || 3850 WARN_ON(hba->utrdl_dma_addr & (SZ_1K - 1))) { 3851 dev_err(hba->dev, 3852 "Transfer Descriptor Memory allocation failed\n"); 3853 goto out; 3854 } 3855 3856 /* 3857 * Skip utmrdl allocation; it may have been 3858 * allocated during first pass and not released during 3859 * MCQ memory allocation. 3860 * See ufshcd_release_sdb_queue() and ufshcd_config_mcq() 3861 */ 3862 if (hba->utmrdl_base_addr) 3863 goto skip_utmrdl; 3864 /* 3865 * Allocate memory for UTP Task Management descriptors 3866 * UFSHCI requires 1KB alignment of UTMRD 3867 */ 3868 utmrdl_size = sizeof(struct utp_task_req_desc) * hba->nutmrs; 3869 hba->utmrdl_base_addr = dmam_alloc_coherent(hba->dev, 3870 utmrdl_size, 3871 &hba->utmrdl_dma_addr, 3872 GFP_KERNEL); 3873 if (!hba->utmrdl_base_addr || 3874 WARN_ON(hba->utmrdl_dma_addr & (SZ_1K - 1))) { 3875 dev_err(hba->dev, 3876 "Task Management Descriptor Memory allocation failed\n"); 3877 goto out; 3878 } 3879 3880 skip_utmrdl: 3881 /* Allocate memory for local reference block */ 3882 hba->lrb = devm_kcalloc(hba->dev, 3883 hba->nutrs, sizeof(struct ufshcd_lrb), 3884 GFP_KERNEL); 3885 if (!hba->lrb) { 3886 dev_err(hba->dev, "LRB Memory allocation failed\n"); 3887 goto out; 3888 } 3889 return 0; 3890 out: 3891 return -ENOMEM; 3892 } 3893 3894 /** 3895 * ufshcd_host_memory_configure - configure local reference block with 3896 * memory offsets 3897 * @hba: per adapter instance 3898 * 3899 * Configure Host memory space 3900 * 1. Update Corresponding UTRD.UCDBA and UTRD.UCDBAU with UCD DMA 3901 * address. 3902 * 2. Update each UTRD with Response UPIU offset, Response UPIU length 3903 * and PRDT offset. 3904 * 3. Save the corresponding addresses of UTRD, UCD.CMD, UCD.RSP and UCD.PRDT 3905 * into local reference block. 3906 */ 3907 static void ufshcd_host_memory_configure(struct ufs_hba *hba) 3908 { 3909 struct utp_transfer_req_desc *utrdlp; 3910 dma_addr_t cmd_desc_dma_addr; 3911 dma_addr_t cmd_desc_element_addr; 3912 u16 response_offset; 3913 u16 prdt_offset; 3914 int cmd_desc_size; 3915 int i; 3916 3917 utrdlp = hba->utrdl_base_addr; 3918 3919 response_offset = 3920 offsetof(struct utp_transfer_cmd_desc, response_upiu); 3921 prdt_offset = 3922 offsetof(struct utp_transfer_cmd_desc, prd_table); 3923 3924 cmd_desc_size = ufshcd_get_ucd_size(hba); 3925 cmd_desc_dma_addr = hba->ucdl_dma_addr; 3926 3927 for (i = 0; i < hba->nutrs; i++) { 3928 /* Configure UTRD with command descriptor base address */ 3929 cmd_desc_element_addr = 3930 (cmd_desc_dma_addr + (cmd_desc_size * i)); 3931 utrdlp[i].command_desc_base_addr = 3932 cpu_to_le64(cmd_desc_element_addr); 3933 3934 /* Response upiu and prdt offset should be in double words */ 3935 if (hba->quirks & UFSHCD_QUIRK_PRDT_BYTE_GRAN) { 3936 utrdlp[i].response_upiu_offset = 3937 cpu_to_le16(response_offset); 3938 utrdlp[i].prd_table_offset = 3939 cpu_to_le16(prdt_offset); 3940 utrdlp[i].response_upiu_length = 3941 cpu_to_le16(ALIGNED_UPIU_SIZE); 3942 } else { 3943 utrdlp[i].response_upiu_offset = 3944 cpu_to_le16(response_offset >> 2); 3945 utrdlp[i].prd_table_offset = 3946 cpu_to_le16(prdt_offset >> 2); 3947 utrdlp[i].response_upiu_length = 3948 cpu_to_le16(ALIGNED_UPIU_SIZE >> 2); 3949 } 3950 3951 ufshcd_init_lrb(hba, &hba->lrb[i], i); 3952 } 3953 } 3954 3955 /** 3956 * ufshcd_dme_link_startup - Notify Unipro to perform link startup 3957 * @hba: per adapter instance 3958 * 3959 * UIC_CMD_DME_LINK_STARTUP command must be issued to Unipro layer, 3960 * in order to initialize the Unipro link startup procedure. 3961 * Once the Unipro links are up, the device connected to the controller 3962 * is detected. 3963 * 3964 * Return: 0 on success, non-zero value on failure. 3965 */ 3966 static int ufshcd_dme_link_startup(struct ufs_hba *hba) 3967 { 3968 struct uic_command uic_cmd = {0}; 3969 int ret; 3970 3971 uic_cmd.command = UIC_CMD_DME_LINK_STARTUP; 3972 3973 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3974 if (ret) 3975 dev_dbg(hba->dev, 3976 "dme-link-startup: error code %d\n", ret); 3977 return ret; 3978 } 3979 /** 3980 * ufshcd_dme_reset - UIC command for DME_RESET 3981 * @hba: per adapter instance 3982 * 3983 * DME_RESET command is issued in order to reset UniPro stack. 3984 * This function now deals with cold reset. 3985 * 3986 * Return: 0 on success, non-zero value on failure. 3987 */ 3988 static int ufshcd_dme_reset(struct ufs_hba *hba) 3989 { 3990 struct uic_command uic_cmd = {0}; 3991 int ret; 3992 3993 uic_cmd.command = UIC_CMD_DME_RESET; 3994 3995 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 3996 if (ret) 3997 dev_err(hba->dev, 3998 "dme-reset: error code %d\n", ret); 3999 4000 return ret; 4001 } 4002 4003 int ufshcd_dme_configure_adapt(struct ufs_hba *hba, 4004 int agreed_gear, 4005 int adapt_val) 4006 { 4007 int ret; 4008 4009 if (agreed_gear < UFS_HS_G4) 4010 adapt_val = PA_NO_ADAPT; 4011 4012 ret = ufshcd_dme_set(hba, 4013 UIC_ARG_MIB(PA_TXHSADAPTTYPE), 4014 adapt_val); 4015 return ret; 4016 } 4017 EXPORT_SYMBOL_GPL(ufshcd_dme_configure_adapt); 4018 4019 /** 4020 * ufshcd_dme_enable - UIC command for DME_ENABLE 4021 * @hba: per adapter instance 4022 * 4023 * DME_ENABLE command is issued in order to enable UniPro stack. 4024 * 4025 * Return: 0 on success, non-zero value on failure. 4026 */ 4027 static int ufshcd_dme_enable(struct ufs_hba *hba) 4028 { 4029 struct uic_command uic_cmd = {0}; 4030 int ret; 4031 4032 uic_cmd.command = UIC_CMD_DME_ENABLE; 4033 4034 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4035 if (ret) 4036 dev_err(hba->dev, 4037 "dme-enable: error code %d\n", ret); 4038 4039 return ret; 4040 } 4041 4042 static inline void ufshcd_add_delay_before_dme_cmd(struct ufs_hba *hba) 4043 { 4044 #define MIN_DELAY_BEFORE_DME_CMDS_US 1000 4045 unsigned long min_sleep_time_us; 4046 4047 if (!(hba->quirks & UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS)) 4048 return; 4049 4050 /* 4051 * last_dme_cmd_tstamp will be 0 only for 1st call to 4052 * this function 4053 */ 4054 if (unlikely(!ktime_to_us(hba->last_dme_cmd_tstamp))) { 4055 min_sleep_time_us = MIN_DELAY_BEFORE_DME_CMDS_US; 4056 } else { 4057 unsigned long delta = 4058 (unsigned long) ktime_to_us( 4059 ktime_sub(ktime_get(), 4060 hba->last_dme_cmd_tstamp)); 4061 4062 if (delta < MIN_DELAY_BEFORE_DME_CMDS_US) 4063 min_sleep_time_us = 4064 MIN_DELAY_BEFORE_DME_CMDS_US - delta; 4065 else 4066 return; /* no more delay required */ 4067 } 4068 4069 /* allow sleep for extra 50us if needed */ 4070 usleep_range(min_sleep_time_us, min_sleep_time_us + 50); 4071 } 4072 4073 /** 4074 * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET 4075 * @hba: per adapter instance 4076 * @attr_sel: uic command argument1 4077 * @attr_set: attribute set type as uic command argument2 4078 * @mib_val: setting value as uic command argument3 4079 * @peer: indicate whether peer or local 4080 * 4081 * Return: 0 on success, non-zero value on failure. 4082 */ 4083 int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, 4084 u8 attr_set, u32 mib_val, u8 peer) 4085 { 4086 struct uic_command uic_cmd = {0}; 4087 static const char *const action[] = { 4088 "dme-set", 4089 "dme-peer-set" 4090 }; 4091 const char *set = action[!!peer]; 4092 int ret; 4093 int retries = UFS_UIC_COMMAND_RETRIES; 4094 4095 uic_cmd.command = peer ? 4096 UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET; 4097 uic_cmd.argument1 = attr_sel; 4098 uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set); 4099 uic_cmd.argument3 = mib_val; 4100 4101 do { 4102 /* for peer attributes we retry upon failure */ 4103 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4104 if (ret) 4105 dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n", 4106 set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret); 4107 } while (ret && peer && --retries); 4108 4109 if (ret) 4110 dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n", 4111 set, UIC_GET_ATTR_ID(attr_sel), mib_val, 4112 UFS_UIC_COMMAND_RETRIES - retries); 4113 4114 return ret; 4115 } 4116 EXPORT_SYMBOL_GPL(ufshcd_dme_set_attr); 4117 4118 /** 4119 * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET 4120 * @hba: per adapter instance 4121 * @attr_sel: uic command argument1 4122 * @mib_val: the value of the attribute as returned by the UIC command 4123 * @peer: indicate whether peer or local 4124 * 4125 * Return: 0 on success, non-zero value on failure. 4126 */ 4127 int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel, 4128 u32 *mib_val, u8 peer) 4129 { 4130 struct uic_command uic_cmd = {0}; 4131 static const char *const action[] = { 4132 "dme-get", 4133 "dme-peer-get" 4134 }; 4135 const char *get = action[!!peer]; 4136 int ret; 4137 int retries = UFS_UIC_COMMAND_RETRIES; 4138 struct ufs_pa_layer_attr orig_pwr_info; 4139 struct ufs_pa_layer_attr temp_pwr_info; 4140 bool pwr_mode_change = false; 4141 4142 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE)) { 4143 orig_pwr_info = hba->pwr_info; 4144 temp_pwr_info = orig_pwr_info; 4145 4146 if (orig_pwr_info.pwr_tx == FAST_MODE || 4147 orig_pwr_info.pwr_rx == FAST_MODE) { 4148 temp_pwr_info.pwr_tx = FASTAUTO_MODE; 4149 temp_pwr_info.pwr_rx = FASTAUTO_MODE; 4150 pwr_mode_change = true; 4151 } else if (orig_pwr_info.pwr_tx == SLOW_MODE || 4152 orig_pwr_info.pwr_rx == SLOW_MODE) { 4153 temp_pwr_info.pwr_tx = SLOWAUTO_MODE; 4154 temp_pwr_info.pwr_rx = SLOWAUTO_MODE; 4155 pwr_mode_change = true; 4156 } 4157 if (pwr_mode_change) { 4158 ret = ufshcd_change_power_mode(hba, &temp_pwr_info); 4159 if (ret) 4160 goto out; 4161 } 4162 } 4163 4164 uic_cmd.command = peer ? 4165 UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET; 4166 uic_cmd.argument1 = attr_sel; 4167 4168 do { 4169 /* for peer attributes we retry upon failure */ 4170 ret = ufshcd_send_uic_cmd(hba, &uic_cmd); 4171 if (ret) 4172 dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n", 4173 get, UIC_GET_ATTR_ID(attr_sel), ret); 4174 } while (ret && peer && --retries); 4175 4176 if (ret) 4177 dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n", 4178 get, UIC_GET_ATTR_ID(attr_sel), 4179 UFS_UIC_COMMAND_RETRIES - retries); 4180 4181 if (mib_val && !ret) 4182 *mib_val = uic_cmd.argument3; 4183 4184 if (peer && (hba->quirks & UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE) 4185 && pwr_mode_change) 4186 ufshcd_change_power_mode(hba, &orig_pwr_info); 4187 out: 4188 return ret; 4189 } 4190 EXPORT_SYMBOL_GPL(ufshcd_dme_get_attr); 4191 4192 /** 4193 * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power 4194 * state) and waits for it to take effect. 4195 * 4196 * @hba: per adapter instance 4197 * @cmd: UIC command to execute 4198 * 4199 * DME operations like DME_SET(PA_PWRMODE), DME_HIBERNATE_ENTER & 4200 * DME_HIBERNATE_EXIT commands take some time to take its effect on both host 4201 * and device UniPro link and hence it's final completion would be indicated by 4202 * dedicated status bits in Interrupt Status register (UPMS, UHES, UHXS) in 4203 * addition to normal UIC command completion Status (UCCS). This function only 4204 * returns after the relevant status bits indicate the completion. 4205 * 4206 * Return: 0 on success, non-zero value on failure. 4207 */ 4208 static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd) 4209 { 4210 DECLARE_COMPLETION_ONSTACK(uic_async_done); 4211 unsigned long flags; 4212 u8 status; 4213 int ret; 4214 bool reenable_intr = false; 4215 4216 mutex_lock(&hba->uic_cmd_mutex); 4217 ufshcd_add_delay_before_dme_cmd(hba); 4218 4219 spin_lock_irqsave(hba->host->host_lock, flags); 4220 if (ufshcd_is_link_broken(hba)) { 4221 ret = -ENOLINK; 4222 goto out_unlock; 4223 } 4224 hba->uic_async_done = &uic_async_done; 4225 if (ufshcd_readl(hba, REG_INTERRUPT_ENABLE) & UIC_COMMAND_COMPL) { 4226 ufshcd_disable_intr(hba, UIC_COMMAND_COMPL); 4227 /* 4228 * Make sure UIC command completion interrupt is disabled before 4229 * issuing UIC command. 4230 */ 4231 wmb(); 4232 reenable_intr = true; 4233 } 4234 spin_unlock_irqrestore(hba->host->host_lock, flags); 4235 ret = __ufshcd_send_uic_cmd(hba, cmd, false); 4236 if (ret) { 4237 dev_err(hba->dev, 4238 "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n", 4239 cmd->command, cmd->argument3, ret); 4240 goto out; 4241 } 4242 4243 if (!wait_for_completion_timeout(hba->uic_async_done, 4244 msecs_to_jiffies(UIC_CMD_TIMEOUT))) { 4245 dev_err(hba->dev, 4246 "pwr ctrl cmd 0x%x with mode 0x%x completion timeout\n", 4247 cmd->command, cmd->argument3); 4248 4249 if (!cmd->cmd_active) { 4250 dev_err(hba->dev, "%s: Power Mode Change operation has been completed, go check UPMCRS\n", 4251 __func__); 4252 goto check_upmcrs; 4253 } 4254 4255 ret = -ETIMEDOUT; 4256 goto out; 4257 } 4258 4259 check_upmcrs: 4260 status = ufshcd_get_upmcrs(hba); 4261 if (status != PWR_LOCAL) { 4262 dev_err(hba->dev, 4263 "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n", 4264 cmd->command, status); 4265 ret = (status != PWR_OK) ? status : -1; 4266 } 4267 out: 4268 if (ret) { 4269 ufshcd_print_host_state(hba); 4270 ufshcd_print_pwr_info(hba); 4271 ufshcd_print_evt_hist(hba); 4272 } 4273 4274 spin_lock_irqsave(hba->host->host_lock, flags); 4275 hba->active_uic_cmd = NULL; 4276 hba->uic_async_done = NULL; 4277 if (reenable_intr) 4278 ufshcd_enable_intr(hba, UIC_COMMAND_COMPL); 4279 if (ret) { 4280 ufshcd_set_link_broken(hba); 4281 ufshcd_schedule_eh_work(hba); 4282 } 4283 out_unlock: 4284 spin_unlock_irqrestore(hba->host->host_lock, flags); 4285 mutex_unlock(&hba->uic_cmd_mutex); 4286 4287 return ret; 4288 } 4289 4290 /** 4291 * ufshcd_uic_change_pwr_mode - Perform the UIC power mode chage 4292 * using DME_SET primitives. 4293 * @hba: per adapter instance 4294 * @mode: powr mode value 4295 * 4296 * Return: 0 on success, non-zero value on failure. 4297 */ 4298 int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode) 4299 { 4300 struct uic_command uic_cmd = {0}; 4301 int ret; 4302 4303 if (hba->quirks & UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP) { 4304 ret = ufshcd_dme_set(hba, 4305 UIC_ARG_MIB_SEL(PA_RXHSUNTERMCAP, 0), 1); 4306 if (ret) { 4307 dev_err(hba->dev, "%s: failed to enable PA_RXHSUNTERMCAP ret %d\n", 4308 __func__, ret); 4309 goto out; 4310 } 4311 } 4312 4313 uic_cmd.command = UIC_CMD_DME_SET; 4314 uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE); 4315 uic_cmd.argument3 = mode; 4316 ufshcd_hold(hba); 4317 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4318 ufshcd_release(hba); 4319 4320 out: 4321 return ret; 4322 } 4323 EXPORT_SYMBOL_GPL(ufshcd_uic_change_pwr_mode); 4324 4325 int ufshcd_link_recovery(struct ufs_hba *hba) 4326 { 4327 int ret; 4328 unsigned long flags; 4329 4330 spin_lock_irqsave(hba->host->host_lock, flags); 4331 hba->ufshcd_state = UFSHCD_STATE_RESET; 4332 ufshcd_set_eh_in_progress(hba); 4333 spin_unlock_irqrestore(hba->host->host_lock, flags); 4334 4335 /* Reset the attached device */ 4336 ufshcd_device_reset(hba); 4337 4338 ret = ufshcd_host_reset_and_restore(hba); 4339 4340 spin_lock_irqsave(hba->host->host_lock, flags); 4341 if (ret) 4342 hba->ufshcd_state = UFSHCD_STATE_ERROR; 4343 ufshcd_clear_eh_in_progress(hba); 4344 spin_unlock_irqrestore(hba->host->host_lock, flags); 4345 4346 if (ret) 4347 dev_err(hba->dev, "%s: link recovery failed, err %d", 4348 __func__, ret); 4349 4350 return ret; 4351 } 4352 EXPORT_SYMBOL_GPL(ufshcd_link_recovery); 4353 4354 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba) 4355 { 4356 int ret; 4357 struct uic_command uic_cmd = {0}; 4358 ktime_t start = ktime_get(); 4359 4360 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, PRE_CHANGE); 4361 4362 uic_cmd.command = UIC_CMD_DME_HIBER_ENTER; 4363 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4364 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "enter", 4365 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4366 4367 if (ret) 4368 dev_err(hba->dev, "%s: hibern8 enter failed. ret = %d\n", 4369 __func__, ret); 4370 else 4371 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_ENTER, 4372 POST_CHANGE); 4373 4374 return ret; 4375 } 4376 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_enter); 4377 4378 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba) 4379 { 4380 struct uic_command uic_cmd = {0}; 4381 int ret; 4382 ktime_t start = ktime_get(); 4383 4384 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, PRE_CHANGE); 4385 4386 uic_cmd.command = UIC_CMD_DME_HIBER_EXIT; 4387 ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd); 4388 trace_ufshcd_profile_hibern8(dev_name(hba->dev), "exit", 4389 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 4390 4391 if (ret) { 4392 dev_err(hba->dev, "%s: hibern8 exit failed. ret = %d\n", 4393 __func__, ret); 4394 } else { 4395 ufshcd_vops_hibern8_notify(hba, UIC_CMD_DME_HIBER_EXIT, 4396 POST_CHANGE); 4397 hba->ufs_stats.last_hibern8_exit_tstamp = local_clock(); 4398 hba->ufs_stats.hibern8_exit_cnt++; 4399 } 4400 4401 return ret; 4402 } 4403 EXPORT_SYMBOL_GPL(ufshcd_uic_hibern8_exit); 4404 4405 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit) 4406 { 4407 unsigned long flags; 4408 bool update = false; 4409 4410 if (!ufshcd_is_auto_hibern8_supported(hba)) 4411 return; 4412 4413 spin_lock_irqsave(hba->host->host_lock, flags); 4414 if (hba->ahit != ahit) { 4415 hba->ahit = ahit; 4416 update = true; 4417 } 4418 spin_unlock_irqrestore(hba->host->host_lock, flags); 4419 4420 if (update && 4421 !pm_runtime_suspended(&hba->ufs_device_wlun->sdev_gendev)) { 4422 ufshcd_rpm_get_sync(hba); 4423 ufshcd_hold(hba); 4424 ufshcd_auto_hibern8_enable(hba); 4425 ufshcd_release(hba); 4426 ufshcd_rpm_put_sync(hba); 4427 } 4428 } 4429 EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update); 4430 4431 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba) 4432 { 4433 if (!ufshcd_is_auto_hibern8_supported(hba)) 4434 return; 4435 4436 ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER); 4437 } 4438 4439 /** 4440 * ufshcd_init_pwr_info - setting the POR (power on reset) 4441 * values in hba power info 4442 * @hba: per-adapter instance 4443 */ 4444 static void ufshcd_init_pwr_info(struct ufs_hba *hba) 4445 { 4446 hba->pwr_info.gear_rx = UFS_PWM_G1; 4447 hba->pwr_info.gear_tx = UFS_PWM_G1; 4448 hba->pwr_info.lane_rx = UFS_LANE_1; 4449 hba->pwr_info.lane_tx = UFS_LANE_1; 4450 hba->pwr_info.pwr_rx = SLOWAUTO_MODE; 4451 hba->pwr_info.pwr_tx = SLOWAUTO_MODE; 4452 hba->pwr_info.hs_rate = 0; 4453 } 4454 4455 /** 4456 * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device 4457 * @hba: per-adapter instance 4458 * 4459 * Return: 0 upon success; < 0 upon failure. 4460 */ 4461 static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba) 4462 { 4463 struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info; 4464 4465 if (hba->max_pwr_info.is_valid) 4466 return 0; 4467 4468 if (hba->quirks & UFSHCD_QUIRK_HIBERN_FASTAUTO) { 4469 pwr_info->pwr_tx = FASTAUTO_MODE; 4470 pwr_info->pwr_rx = FASTAUTO_MODE; 4471 } else { 4472 pwr_info->pwr_tx = FAST_MODE; 4473 pwr_info->pwr_rx = FAST_MODE; 4474 } 4475 pwr_info->hs_rate = PA_HS_MODE_B; 4476 4477 /* Get the connected lane count */ 4478 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES), 4479 &pwr_info->lane_rx); 4480 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4481 &pwr_info->lane_tx); 4482 4483 if (!pwr_info->lane_rx || !pwr_info->lane_tx) { 4484 dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n", 4485 __func__, 4486 pwr_info->lane_rx, 4487 pwr_info->lane_tx); 4488 return -EINVAL; 4489 } 4490 4491 /* 4492 * First, get the maximum gears of HS speed. 4493 * If a zero value, it means there is no HSGEAR capability. 4494 * Then, get the maximum gears of PWM speed. 4495 */ 4496 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx); 4497 if (!pwr_info->gear_rx) { 4498 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4499 &pwr_info->gear_rx); 4500 if (!pwr_info->gear_rx) { 4501 dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n", 4502 __func__, pwr_info->gear_rx); 4503 return -EINVAL; 4504 } 4505 pwr_info->pwr_rx = SLOW_MODE; 4506 } 4507 4508 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), 4509 &pwr_info->gear_tx); 4510 if (!pwr_info->gear_tx) { 4511 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR), 4512 &pwr_info->gear_tx); 4513 if (!pwr_info->gear_tx) { 4514 dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n", 4515 __func__, pwr_info->gear_tx); 4516 return -EINVAL; 4517 } 4518 pwr_info->pwr_tx = SLOW_MODE; 4519 } 4520 4521 hba->max_pwr_info.is_valid = true; 4522 return 0; 4523 } 4524 4525 static int ufshcd_change_power_mode(struct ufs_hba *hba, 4526 struct ufs_pa_layer_attr *pwr_mode) 4527 { 4528 int ret; 4529 4530 /* if already configured to the requested pwr_mode */ 4531 if (!hba->force_pmc && 4532 pwr_mode->gear_rx == hba->pwr_info.gear_rx && 4533 pwr_mode->gear_tx == hba->pwr_info.gear_tx && 4534 pwr_mode->lane_rx == hba->pwr_info.lane_rx && 4535 pwr_mode->lane_tx == hba->pwr_info.lane_tx && 4536 pwr_mode->pwr_rx == hba->pwr_info.pwr_rx && 4537 pwr_mode->pwr_tx == hba->pwr_info.pwr_tx && 4538 pwr_mode->hs_rate == hba->pwr_info.hs_rate) { 4539 dev_dbg(hba->dev, "%s: power already configured\n", __func__); 4540 return 0; 4541 } 4542 4543 /* 4544 * Configure attributes for power mode change with below. 4545 * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION, 4546 * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION, 4547 * - PA_HSSERIES 4548 */ 4549 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx); 4550 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES), 4551 pwr_mode->lane_rx); 4552 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4553 pwr_mode->pwr_rx == FAST_MODE) 4554 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), true); 4555 else 4556 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), false); 4557 4558 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx); 4559 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES), 4560 pwr_mode->lane_tx); 4561 if (pwr_mode->pwr_tx == FASTAUTO_MODE || 4562 pwr_mode->pwr_tx == FAST_MODE) 4563 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), true); 4564 else 4565 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), false); 4566 4567 if (pwr_mode->pwr_rx == FASTAUTO_MODE || 4568 pwr_mode->pwr_tx == FASTAUTO_MODE || 4569 pwr_mode->pwr_rx == FAST_MODE || 4570 pwr_mode->pwr_tx == FAST_MODE) 4571 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES), 4572 pwr_mode->hs_rate); 4573 4574 if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) { 4575 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 4576 DL_FC0ProtectionTimeOutVal_Default); 4577 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 4578 DL_TC0ReplayTimeOutVal_Default); 4579 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 4580 DL_AFC0ReqTimeOutVal_Default); 4581 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3), 4582 DL_FC1ProtectionTimeOutVal_Default); 4583 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4), 4584 DL_TC1ReplayTimeOutVal_Default); 4585 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5), 4586 DL_AFC1ReqTimeOutVal_Default); 4587 4588 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal), 4589 DL_FC0ProtectionTimeOutVal_Default); 4590 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal), 4591 DL_TC0ReplayTimeOutVal_Default); 4592 ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal), 4593 DL_AFC0ReqTimeOutVal_Default); 4594 } 4595 4596 ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 4597 | pwr_mode->pwr_tx); 4598 4599 if (ret) { 4600 dev_err(hba->dev, 4601 "%s: power mode change failed %d\n", __func__, ret); 4602 } else { 4603 ufshcd_vops_pwr_change_notify(hba, POST_CHANGE, NULL, 4604 pwr_mode); 4605 4606 memcpy(&hba->pwr_info, pwr_mode, 4607 sizeof(struct ufs_pa_layer_attr)); 4608 } 4609 4610 return ret; 4611 } 4612 4613 /** 4614 * ufshcd_config_pwr_mode - configure a new power mode 4615 * @hba: per-adapter instance 4616 * @desired_pwr_mode: desired power configuration 4617 * 4618 * Return: 0 upon success; < 0 upon failure. 4619 */ 4620 int ufshcd_config_pwr_mode(struct ufs_hba *hba, 4621 struct ufs_pa_layer_attr *desired_pwr_mode) 4622 { 4623 struct ufs_pa_layer_attr final_params = { 0 }; 4624 int ret; 4625 4626 ret = ufshcd_vops_pwr_change_notify(hba, PRE_CHANGE, 4627 desired_pwr_mode, &final_params); 4628 4629 if (ret) 4630 memcpy(&final_params, desired_pwr_mode, sizeof(final_params)); 4631 4632 ret = ufshcd_change_power_mode(hba, &final_params); 4633 4634 return ret; 4635 } 4636 EXPORT_SYMBOL_GPL(ufshcd_config_pwr_mode); 4637 4638 /** 4639 * ufshcd_complete_dev_init() - checks device readiness 4640 * @hba: per-adapter instance 4641 * 4642 * Set fDeviceInit flag and poll until device toggles it. 4643 * 4644 * Return: 0 upon success; < 0 upon failure. 4645 */ 4646 static int ufshcd_complete_dev_init(struct ufs_hba *hba) 4647 { 4648 int err; 4649 bool flag_res = true; 4650 ktime_t timeout; 4651 4652 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 4653 QUERY_FLAG_IDN_FDEVICEINIT, 0, NULL); 4654 if (err) { 4655 dev_err(hba->dev, 4656 "%s: setting fDeviceInit flag failed with error %d\n", 4657 __func__, err); 4658 goto out; 4659 } 4660 4661 /* Poll fDeviceInit flag to be cleared */ 4662 timeout = ktime_add_ms(ktime_get(), FDEVICEINIT_COMPL_TIMEOUT); 4663 do { 4664 err = ufshcd_query_flag(hba, UPIU_QUERY_OPCODE_READ_FLAG, 4665 QUERY_FLAG_IDN_FDEVICEINIT, 0, &flag_res); 4666 if (!flag_res) 4667 break; 4668 usleep_range(500, 1000); 4669 } while (ktime_before(ktime_get(), timeout)); 4670 4671 if (err) { 4672 dev_err(hba->dev, 4673 "%s: reading fDeviceInit flag failed with error %d\n", 4674 __func__, err); 4675 } else if (flag_res) { 4676 dev_err(hba->dev, 4677 "%s: fDeviceInit was not cleared by the device\n", 4678 __func__); 4679 err = -EBUSY; 4680 } 4681 out: 4682 return err; 4683 } 4684 4685 /** 4686 * ufshcd_make_hba_operational - Make UFS controller operational 4687 * @hba: per adapter instance 4688 * 4689 * To bring UFS host controller to operational state, 4690 * 1. Enable required interrupts 4691 * 2. Configure interrupt aggregation 4692 * 3. Program UTRL and UTMRL base address 4693 * 4. Configure run-stop-registers 4694 * 4695 * Return: 0 on success, non-zero value on failure. 4696 */ 4697 int ufshcd_make_hba_operational(struct ufs_hba *hba) 4698 { 4699 int err = 0; 4700 u32 reg; 4701 4702 /* Enable required interrupts */ 4703 ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS); 4704 4705 /* Configure interrupt aggregation */ 4706 if (ufshcd_is_intr_aggr_allowed(hba)) 4707 ufshcd_config_intr_aggr(hba, hba->nutrs - 1, INT_AGGR_DEF_TO); 4708 else 4709 ufshcd_disable_intr_aggr(hba); 4710 4711 /* Configure UTRL and UTMRL base address registers */ 4712 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 4713 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 4714 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 4715 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 4716 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 4717 REG_UTP_TASK_REQ_LIST_BASE_L); 4718 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 4719 REG_UTP_TASK_REQ_LIST_BASE_H); 4720 4721 /* 4722 * Make sure base address and interrupt setup are updated before 4723 * enabling the run/stop registers below. 4724 */ 4725 wmb(); 4726 4727 /* 4728 * UCRDY, UTMRLDY and UTRLRDY bits must be 1 4729 */ 4730 reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS); 4731 if (!(ufshcd_get_lists_status(reg))) { 4732 ufshcd_enable_run_stop_reg(hba); 4733 } else { 4734 dev_err(hba->dev, 4735 "Host controller not ready to process requests"); 4736 err = -EIO; 4737 } 4738 4739 return err; 4740 } 4741 EXPORT_SYMBOL_GPL(ufshcd_make_hba_operational); 4742 4743 /** 4744 * ufshcd_hba_stop - Send controller to reset state 4745 * @hba: per adapter instance 4746 */ 4747 void ufshcd_hba_stop(struct ufs_hba *hba) 4748 { 4749 unsigned long flags; 4750 int err; 4751 4752 /* 4753 * Obtain the host lock to prevent that the controller is disabled 4754 * while the UFS interrupt handler is active on another CPU. 4755 */ 4756 spin_lock_irqsave(hba->host->host_lock, flags); 4757 ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE); 4758 spin_unlock_irqrestore(hba->host->host_lock, flags); 4759 4760 err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE, 4761 CONTROLLER_ENABLE, CONTROLLER_DISABLE, 4762 10, 1); 4763 if (err) 4764 dev_err(hba->dev, "%s: Controller disable failed\n", __func__); 4765 } 4766 EXPORT_SYMBOL_GPL(ufshcd_hba_stop); 4767 4768 /** 4769 * ufshcd_hba_execute_hce - initialize the controller 4770 * @hba: per adapter instance 4771 * 4772 * The controller resets itself and controller firmware initialization 4773 * sequence kicks off. When controller is ready it will set 4774 * the Host Controller Enable bit to 1. 4775 * 4776 * Return: 0 on success, non-zero value on failure. 4777 */ 4778 static int ufshcd_hba_execute_hce(struct ufs_hba *hba) 4779 { 4780 int retry_outer = 3; 4781 int retry_inner; 4782 4783 start: 4784 if (ufshcd_is_hba_active(hba)) 4785 /* change controller state to "reset state" */ 4786 ufshcd_hba_stop(hba); 4787 4788 /* UniPro link is disabled at this point */ 4789 ufshcd_set_link_off(hba); 4790 4791 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4792 4793 /* start controller initialization sequence */ 4794 ufshcd_hba_start(hba); 4795 4796 /* 4797 * To initialize a UFS host controller HCE bit must be set to 1. 4798 * During initialization the HCE bit value changes from 1->0->1. 4799 * When the host controller completes initialization sequence 4800 * it sets the value of HCE bit to 1. The same HCE bit is read back 4801 * to check if the controller has completed initialization sequence. 4802 * So without this delay the value HCE = 1, set in the previous 4803 * instruction might be read back. 4804 * This delay can be changed based on the controller. 4805 */ 4806 ufshcd_delay_us(hba->vps->hba_enable_delay_us, 100); 4807 4808 /* wait for the host controller to complete initialization */ 4809 retry_inner = 50; 4810 while (!ufshcd_is_hba_active(hba)) { 4811 if (retry_inner) { 4812 retry_inner--; 4813 } else { 4814 dev_err(hba->dev, 4815 "Controller enable failed\n"); 4816 if (retry_outer) { 4817 retry_outer--; 4818 goto start; 4819 } 4820 return -EIO; 4821 } 4822 usleep_range(1000, 1100); 4823 } 4824 4825 /* enable UIC related interrupts */ 4826 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4827 4828 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4829 4830 return 0; 4831 } 4832 4833 int ufshcd_hba_enable(struct ufs_hba *hba) 4834 { 4835 int ret; 4836 4837 if (hba->quirks & UFSHCI_QUIRK_BROKEN_HCE) { 4838 ufshcd_set_link_off(hba); 4839 ufshcd_vops_hce_enable_notify(hba, PRE_CHANGE); 4840 4841 /* enable UIC related interrupts */ 4842 ufshcd_enable_intr(hba, UFSHCD_UIC_MASK); 4843 ret = ufshcd_dme_reset(hba); 4844 if (ret) { 4845 dev_err(hba->dev, "DME_RESET failed\n"); 4846 return ret; 4847 } 4848 4849 ret = ufshcd_dme_enable(hba); 4850 if (ret) { 4851 dev_err(hba->dev, "Enabling DME failed\n"); 4852 return ret; 4853 } 4854 4855 ufshcd_vops_hce_enable_notify(hba, POST_CHANGE); 4856 } else { 4857 ret = ufshcd_hba_execute_hce(hba); 4858 } 4859 4860 return ret; 4861 } 4862 EXPORT_SYMBOL_GPL(ufshcd_hba_enable); 4863 4864 static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer) 4865 { 4866 int tx_lanes = 0, i, err = 0; 4867 4868 if (!peer) 4869 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4870 &tx_lanes); 4871 else 4872 ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 4873 &tx_lanes); 4874 for (i = 0; i < tx_lanes; i++) { 4875 if (!peer) 4876 err = ufshcd_dme_set(hba, 4877 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4878 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4879 0); 4880 else 4881 err = ufshcd_dme_peer_set(hba, 4882 UIC_ARG_MIB_SEL(TX_LCC_ENABLE, 4883 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)), 4884 0); 4885 if (err) { 4886 dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d", 4887 __func__, peer, i, err); 4888 break; 4889 } 4890 } 4891 4892 return err; 4893 } 4894 4895 static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba) 4896 { 4897 return ufshcd_disable_tx_lcc(hba, true); 4898 } 4899 4900 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val) 4901 { 4902 struct ufs_event_hist *e; 4903 4904 if (id >= UFS_EVT_CNT) 4905 return; 4906 4907 e = &hba->ufs_stats.event[id]; 4908 e->val[e->pos] = val; 4909 e->tstamp[e->pos] = local_clock(); 4910 e->cnt += 1; 4911 e->pos = (e->pos + 1) % UFS_EVENT_HIST_LENGTH; 4912 4913 ufshcd_vops_event_notify(hba, id, &val); 4914 } 4915 EXPORT_SYMBOL_GPL(ufshcd_update_evt_hist); 4916 4917 /** 4918 * ufshcd_link_startup - Initialize unipro link startup 4919 * @hba: per adapter instance 4920 * 4921 * Return: 0 for success, non-zero in case of failure. 4922 */ 4923 static int ufshcd_link_startup(struct ufs_hba *hba) 4924 { 4925 int ret; 4926 int retries = DME_LINKSTARTUP_RETRIES; 4927 bool link_startup_again = false; 4928 4929 /* 4930 * If UFS device isn't active then we will have to issue link startup 4931 * 2 times to make sure the device state move to active. 4932 */ 4933 if (!ufshcd_is_ufs_dev_active(hba)) 4934 link_startup_again = true; 4935 4936 link_startup: 4937 do { 4938 ufshcd_vops_link_startup_notify(hba, PRE_CHANGE); 4939 4940 ret = ufshcd_dme_link_startup(hba); 4941 4942 /* check if device is detected by inter-connect layer */ 4943 if (!ret && !ufshcd_is_device_present(hba)) { 4944 ufshcd_update_evt_hist(hba, 4945 UFS_EVT_LINK_STARTUP_FAIL, 4946 0); 4947 dev_err(hba->dev, "%s: Device not present\n", __func__); 4948 ret = -ENXIO; 4949 goto out; 4950 } 4951 4952 /* 4953 * DME link lost indication is only received when link is up, 4954 * but we can't be sure if the link is up until link startup 4955 * succeeds. So reset the local Uni-Pro and try again. 4956 */ 4957 if (ret && retries && ufshcd_hba_enable(hba)) { 4958 ufshcd_update_evt_hist(hba, 4959 UFS_EVT_LINK_STARTUP_FAIL, 4960 (u32)ret); 4961 goto out; 4962 } 4963 } while (ret && retries--); 4964 4965 if (ret) { 4966 /* failed to get the link up... retire */ 4967 ufshcd_update_evt_hist(hba, 4968 UFS_EVT_LINK_STARTUP_FAIL, 4969 (u32)ret); 4970 goto out; 4971 } 4972 4973 if (link_startup_again) { 4974 link_startup_again = false; 4975 retries = DME_LINKSTARTUP_RETRIES; 4976 goto link_startup; 4977 } 4978 4979 /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */ 4980 ufshcd_init_pwr_info(hba); 4981 ufshcd_print_pwr_info(hba); 4982 4983 if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) { 4984 ret = ufshcd_disable_device_tx_lcc(hba); 4985 if (ret) 4986 goto out; 4987 } 4988 4989 /* Include any host controller configuration via UIC commands */ 4990 ret = ufshcd_vops_link_startup_notify(hba, POST_CHANGE); 4991 if (ret) 4992 goto out; 4993 4994 /* Clear UECPA once due to LINERESET has happened during LINK_STARTUP */ 4995 ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 4996 ret = ufshcd_make_hba_operational(hba); 4997 out: 4998 if (ret) { 4999 dev_err(hba->dev, "link startup failed %d\n", ret); 5000 ufshcd_print_host_state(hba); 5001 ufshcd_print_pwr_info(hba); 5002 ufshcd_print_evt_hist(hba); 5003 } 5004 return ret; 5005 } 5006 5007 /** 5008 * ufshcd_verify_dev_init() - Verify device initialization 5009 * @hba: per-adapter instance 5010 * 5011 * Send NOP OUT UPIU and wait for NOP IN response to check whether the 5012 * device Transport Protocol (UTP) layer is ready after a reset. 5013 * If the UTP layer at the device side is not initialized, it may 5014 * not respond with NOP IN UPIU within timeout of %NOP_OUT_TIMEOUT 5015 * and we retry sending NOP OUT for %NOP_OUT_RETRIES iterations. 5016 * 5017 * Return: 0 upon success; < 0 upon failure. 5018 */ 5019 static int ufshcd_verify_dev_init(struct ufs_hba *hba) 5020 { 5021 int err = 0; 5022 int retries; 5023 5024 ufshcd_hold(hba); 5025 mutex_lock(&hba->dev_cmd.lock); 5026 for (retries = NOP_OUT_RETRIES; retries > 0; retries--) { 5027 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP, 5028 hba->nop_out_timeout); 5029 5030 if (!err || err == -ETIMEDOUT) 5031 break; 5032 5033 dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err); 5034 } 5035 mutex_unlock(&hba->dev_cmd.lock); 5036 ufshcd_release(hba); 5037 5038 if (err) 5039 dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err); 5040 return err; 5041 } 5042 5043 /** 5044 * ufshcd_setup_links - associate link b/w device wlun and other luns 5045 * @sdev: pointer to SCSI device 5046 * @hba: pointer to ufs hba 5047 */ 5048 static void ufshcd_setup_links(struct ufs_hba *hba, struct scsi_device *sdev) 5049 { 5050 struct device_link *link; 5051 5052 /* 5053 * Device wlun is the supplier & rest of the luns are consumers. 5054 * This ensures that device wlun suspends after all other luns. 5055 */ 5056 if (hba->ufs_device_wlun) { 5057 link = device_link_add(&sdev->sdev_gendev, 5058 &hba->ufs_device_wlun->sdev_gendev, 5059 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 5060 if (!link) { 5061 dev_err(&sdev->sdev_gendev, "Failed establishing link - %s\n", 5062 dev_name(&hba->ufs_device_wlun->sdev_gendev)); 5063 return; 5064 } 5065 hba->luns_avail--; 5066 /* Ignore REPORT_LUN wlun probing */ 5067 if (hba->luns_avail == 1) { 5068 ufshcd_rpm_put(hba); 5069 return; 5070 } 5071 } else { 5072 /* 5073 * Device wlun is probed. The assumption is that WLUNs are 5074 * scanned before other LUNs. 5075 */ 5076 hba->luns_avail--; 5077 } 5078 } 5079 5080 /** 5081 * ufshcd_lu_init - Initialize the relevant parameters of the LU 5082 * @hba: per-adapter instance 5083 * @sdev: pointer to SCSI device 5084 */ 5085 static void ufshcd_lu_init(struct ufs_hba *hba, struct scsi_device *sdev) 5086 { 5087 int len = QUERY_DESC_MAX_SIZE; 5088 u8 lun = ufshcd_scsi_to_upiu_lun(sdev->lun); 5089 u8 lun_qdepth = hba->nutrs; 5090 u8 *desc_buf; 5091 int ret; 5092 5093 desc_buf = kzalloc(len, GFP_KERNEL); 5094 if (!desc_buf) 5095 goto set_qdepth; 5096 5097 ret = ufshcd_read_unit_desc_param(hba, lun, 0, desc_buf, len); 5098 if (ret < 0) { 5099 if (ret == -EOPNOTSUPP) 5100 /* If LU doesn't support unit descriptor, its queue depth is set to 1 */ 5101 lun_qdepth = 1; 5102 kfree(desc_buf); 5103 goto set_qdepth; 5104 } 5105 5106 if (desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH]) { 5107 /* 5108 * In per-LU queueing architecture, bLUQueueDepth will not be 0, then we will 5109 * use the smaller between UFSHCI CAP.NUTRS and UFS LU bLUQueueDepth 5110 */ 5111 lun_qdepth = min_t(int, desc_buf[UNIT_DESC_PARAM_LU_Q_DEPTH], hba->nutrs); 5112 } 5113 /* 5114 * According to UFS device specification, the write protection mode is only supported by 5115 * normal LU, not supported by WLUN. 5116 */ 5117 if (hba->dev_info.f_power_on_wp_en && lun < hba->dev_info.max_lu_supported && 5118 !hba->dev_info.is_lu_power_on_wp && 5119 desc_buf[UNIT_DESC_PARAM_LU_WR_PROTECT] == UFS_LU_POWER_ON_WP) 5120 hba->dev_info.is_lu_power_on_wp = true; 5121 5122 /* In case of RPMB LU, check if advanced RPMB mode is enabled */ 5123 if (desc_buf[UNIT_DESC_PARAM_UNIT_INDEX] == UFS_UPIU_RPMB_WLUN && 5124 desc_buf[RPMB_UNIT_DESC_PARAM_REGION_EN] & BIT(4)) 5125 hba->dev_info.b_advanced_rpmb_en = true; 5126 5127 5128 kfree(desc_buf); 5129 set_qdepth: 5130 /* 5131 * For WLUNs that don't support unit descriptor, queue depth is set to 1. For LUs whose 5132 * bLUQueueDepth == 0, the queue depth is set to a maximum value that host can queue. 5133 */ 5134 dev_dbg(hba->dev, "Set LU %x queue depth %d\n", lun, lun_qdepth); 5135 scsi_change_queue_depth(sdev, lun_qdepth); 5136 } 5137 5138 /** 5139 * ufshcd_slave_alloc - handle initial SCSI device configurations 5140 * @sdev: pointer to SCSI device 5141 * 5142 * Return: success. 5143 */ 5144 static int ufshcd_slave_alloc(struct scsi_device *sdev) 5145 { 5146 struct ufs_hba *hba; 5147 5148 hba = shost_priv(sdev->host); 5149 5150 /* Mode sense(6) is not supported by UFS, so use Mode sense(10) */ 5151 sdev->use_10_for_ms = 1; 5152 5153 /* DBD field should be set to 1 in mode sense(10) */ 5154 sdev->set_dbd_for_ms = 1; 5155 5156 /* allow SCSI layer to restart the device in case of errors */ 5157 sdev->allow_restart = 1; 5158 5159 /* REPORT SUPPORTED OPERATION CODES is not supported */ 5160 sdev->no_report_opcodes = 1; 5161 5162 /* WRITE_SAME command is not supported */ 5163 sdev->no_write_same = 1; 5164 5165 ufshcd_lu_init(hba, sdev); 5166 5167 ufshcd_setup_links(hba, sdev); 5168 5169 return 0; 5170 } 5171 5172 /** 5173 * ufshcd_change_queue_depth - change queue depth 5174 * @sdev: pointer to SCSI device 5175 * @depth: required depth to set 5176 * 5177 * Change queue depth and make sure the max. limits are not crossed. 5178 * 5179 * Return: new queue depth. 5180 */ 5181 static int ufshcd_change_queue_depth(struct scsi_device *sdev, int depth) 5182 { 5183 return scsi_change_queue_depth(sdev, min(depth, sdev->host->can_queue)); 5184 } 5185 5186 /** 5187 * ufshcd_slave_configure - adjust SCSI device configurations 5188 * @sdev: pointer to SCSI device 5189 * 5190 * Return: 0 (success). 5191 */ 5192 static int ufshcd_slave_configure(struct scsi_device *sdev) 5193 { 5194 struct ufs_hba *hba = shost_priv(sdev->host); 5195 struct request_queue *q = sdev->request_queue; 5196 5197 blk_queue_update_dma_pad(q, PRDT_DATA_BYTE_COUNT_PAD - 1); 5198 5199 /* 5200 * Block runtime-pm until all consumers are added. 5201 * Refer ufshcd_setup_links(). 5202 */ 5203 if (is_device_wlun(sdev)) 5204 pm_runtime_get_noresume(&sdev->sdev_gendev); 5205 else if (ufshcd_is_rpm_autosuspend_allowed(hba)) 5206 sdev->rpm_autosuspend = 1; 5207 /* 5208 * Do not print messages during runtime PM to avoid never-ending cycles 5209 * of messages written back to storage by user space causing runtime 5210 * resume, causing more messages and so on. 5211 */ 5212 sdev->silence_suspend = 1; 5213 5214 if (hba->vops && hba->vops->config_scsi_dev) 5215 hba->vops->config_scsi_dev(sdev); 5216 5217 ufshcd_crypto_register(hba, q); 5218 5219 return 0; 5220 } 5221 5222 /** 5223 * ufshcd_slave_destroy - remove SCSI device configurations 5224 * @sdev: pointer to SCSI device 5225 */ 5226 static void ufshcd_slave_destroy(struct scsi_device *sdev) 5227 { 5228 struct ufs_hba *hba; 5229 unsigned long flags; 5230 5231 hba = shost_priv(sdev->host); 5232 5233 /* Drop the reference as it won't be needed anymore */ 5234 if (ufshcd_scsi_to_upiu_lun(sdev->lun) == UFS_UPIU_UFS_DEVICE_WLUN) { 5235 spin_lock_irqsave(hba->host->host_lock, flags); 5236 hba->ufs_device_wlun = NULL; 5237 spin_unlock_irqrestore(hba->host->host_lock, flags); 5238 } else if (hba->ufs_device_wlun) { 5239 struct device *supplier = NULL; 5240 5241 /* Ensure UFS Device WLUN exists and does not disappear */ 5242 spin_lock_irqsave(hba->host->host_lock, flags); 5243 if (hba->ufs_device_wlun) { 5244 supplier = &hba->ufs_device_wlun->sdev_gendev; 5245 get_device(supplier); 5246 } 5247 spin_unlock_irqrestore(hba->host->host_lock, flags); 5248 5249 if (supplier) { 5250 /* 5251 * If a LUN fails to probe (e.g. absent BOOT WLUN), the 5252 * device will not have been registered but can still 5253 * have a device link holding a reference to the device. 5254 */ 5255 device_link_remove(&sdev->sdev_gendev, supplier); 5256 put_device(supplier); 5257 } 5258 } 5259 } 5260 5261 /** 5262 * ufshcd_scsi_cmd_status - Update SCSI command result based on SCSI status 5263 * @lrbp: pointer to local reference block of completed command 5264 * @scsi_status: SCSI command status 5265 * 5266 * Return: value base on SCSI command status. 5267 */ 5268 static inline int 5269 ufshcd_scsi_cmd_status(struct ufshcd_lrb *lrbp, int scsi_status) 5270 { 5271 int result = 0; 5272 5273 switch (scsi_status) { 5274 case SAM_STAT_CHECK_CONDITION: 5275 ufshcd_copy_sense_data(lrbp); 5276 fallthrough; 5277 case SAM_STAT_GOOD: 5278 result |= DID_OK << 16 | scsi_status; 5279 break; 5280 case SAM_STAT_TASK_SET_FULL: 5281 case SAM_STAT_BUSY: 5282 case SAM_STAT_TASK_ABORTED: 5283 ufshcd_copy_sense_data(lrbp); 5284 result |= scsi_status; 5285 break; 5286 default: 5287 result |= DID_ERROR << 16; 5288 break; 5289 } /* end of switch */ 5290 5291 return result; 5292 } 5293 5294 /** 5295 * ufshcd_transfer_rsp_status - Get overall status of the response 5296 * @hba: per adapter instance 5297 * @lrbp: pointer to local reference block of completed command 5298 * @cqe: pointer to the completion queue entry 5299 * 5300 * Return: result of the command to notify SCSI midlayer. 5301 */ 5302 static inline int 5303 ufshcd_transfer_rsp_status(struct ufs_hba *hba, struct ufshcd_lrb *lrbp, 5304 struct cq_entry *cqe) 5305 { 5306 int result = 0; 5307 int scsi_status; 5308 enum utp_ocs ocs; 5309 u8 upiu_flags; 5310 u32 resid; 5311 5312 upiu_flags = lrbp->ucd_rsp_ptr->header.flags; 5313 resid = be32_to_cpu(lrbp->ucd_rsp_ptr->sr.residual_transfer_count); 5314 /* 5315 * Test !overflow instead of underflow to support UFS devices that do 5316 * not set either flag. 5317 */ 5318 if (resid && !(upiu_flags & UPIU_RSP_FLAG_OVERFLOW)) 5319 scsi_set_resid(lrbp->cmd, resid); 5320 5321 /* overall command status of utrd */ 5322 ocs = ufshcd_get_tr_ocs(lrbp, cqe); 5323 5324 if (hba->quirks & UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR) { 5325 if (lrbp->ucd_rsp_ptr->header.response || 5326 lrbp->ucd_rsp_ptr->header.status) 5327 ocs = OCS_SUCCESS; 5328 } 5329 5330 switch (ocs) { 5331 case OCS_SUCCESS: 5332 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 5333 switch (ufshcd_get_req_rsp(lrbp->ucd_rsp_ptr)) { 5334 case UPIU_TRANSACTION_RESPONSE: 5335 /* 5336 * get the result based on SCSI status response 5337 * to notify the SCSI midlayer of the command status 5338 */ 5339 scsi_status = lrbp->ucd_rsp_ptr->header.status; 5340 result = ufshcd_scsi_cmd_status(lrbp, scsi_status); 5341 5342 /* 5343 * Currently we are only supporting BKOPs exception 5344 * events hence we can ignore BKOPs exception event 5345 * during power management callbacks. BKOPs exception 5346 * event is not expected to be raised in runtime suspend 5347 * callback as it allows the urgent bkops. 5348 * During system suspend, we are anyway forcefully 5349 * disabling the bkops and if urgent bkops is needed 5350 * it will be enabled on system resume. Long term 5351 * solution could be to abort the system suspend if 5352 * UFS device needs urgent BKOPs. 5353 */ 5354 if (!hba->pm_op_in_progress && 5355 !ufshcd_eh_in_progress(hba) && 5356 ufshcd_is_exception_event(lrbp->ucd_rsp_ptr)) 5357 /* Flushed in suspend */ 5358 schedule_work(&hba->eeh_work); 5359 break; 5360 case UPIU_TRANSACTION_REJECT_UPIU: 5361 /* TODO: handle Reject UPIU Response */ 5362 result = DID_ERROR << 16; 5363 dev_err(hba->dev, 5364 "Reject UPIU not fully implemented\n"); 5365 break; 5366 default: 5367 dev_err(hba->dev, 5368 "Unexpected request response code = %x\n", 5369 result); 5370 result = DID_ERROR << 16; 5371 break; 5372 } 5373 break; 5374 case OCS_ABORTED: 5375 result |= DID_ABORT << 16; 5376 break; 5377 case OCS_INVALID_COMMAND_STATUS: 5378 result |= DID_REQUEUE << 16; 5379 break; 5380 case OCS_INVALID_CMD_TABLE_ATTR: 5381 case OCS_INVALID_PRDT_ATTR: 5382 case OCS_MISMATCH_DATA_BUF_SIZE: 5383 case OCS_MISMATCH_RESP_UPIU_SIZE: 5384 case OCS_PEER_COMM_FAILURE: 5385 case OCS_FATAL_ERROR: 5386 case OCS_DEVICE_FATAL_ERROR: 5387 case OCS_INVALID_CRYPTO_CONFIG: 5388 case OCS_GENERAL_CRYPTO_ERROR: 5389 default: 5390 result |= DID_ERROR << 16; 5391 dev_err(hba->dev, 5392 "OCS error from controller = %x for tag %d\n", 5393 ocs, lrbp->task_tag); 5394 ufshcd_print_evt_hist(hba); 5395 ufshcd_print_host_state(hba); 5396 break; 5397 } /* end of switch */ 5398 5399 if ((host_byte(result) != DID_OK) && 5400 (host_byte(result) != DID_REQUEUE) && !hba->silence_err_logs) 5401 ufshcd_print_tr(hba, lrbp->task_tag, true); 5402 return result; 5403 } 5404 5405 static bool ufshcd_is_auto_hibern8_error(struct ufs_hba *hba, 5406 u32 intr_mask) 5407 { 5408 if (!ufshcd_is_auto_hibern8_supported(hba) || 5409 !ufshcd_is_auto_hibern8_enabled(hba)) 5410 return false; 5411 5412 if (!(intr_mask & UFSHCD_UIC_HIBERN8_MASK)) 5413 return false; 5414 5415 if (hba->active_uic_cmd && 5416 (hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_ENTER || 5417 hba->active_uic_cmd->command == UIC_CMD_DME_HIBER_EXIT)) 5418 return false; 5419 5420 return true; 5421 } 5422 5423 /** 5424 * ufshcd_uic_cmd_compl - handle completion of uic command 5425 * @hba: per adapter instance 5426 * @intr_status: interrupt status generated by the controller 5427 * 5428 * Return: 5429 * IRQ_HANDLED - If interrupt is valid 5430 * IRQ_NONE - If invalid interrupt 5431 */ 5432 static irqreturn_t ufshcd_uic_cmd_compl(struct ufs_hba *hba, u32 intr_status) 5433 { 5434 irqreturn_t retval = IRQ_NONE; 5435 5436 spin_lock(hba->host->host_lock); 5437 if (ufshcd_is_auto_hibern8_error(hba, intr_status)) 5438 hba->errors |= (UFSHCD_UIC_HIBERN8_MASK & intr_status); 5439 5440 if ((intr_status & UIC_COMMAND_COMPL) && hba->active_uic_cmd) { 5441 hba->active_uic_cmd->argument2 |= 5442 ufshcd_get_uic_cmd_result(hba); 5443 hba->active_uic_cmd->argument3 = 5444 ufshcd_get_dme_attr_val(hba); 5445 if (!hba->uic_async_done) 5446 hba->active_uic_cmd->cmd_active = 0; 5447 complete(&hba->active_uic_cmd->done); 5448 retval = IRQ_HANDLED; 5449 } 5450 5451 if ((intr_status & UFSHCD_UIC_PWR_MASK) && hba->uic_async_done) { 5452 hba->active_uic_cmd->cmd_active = 0; 5453 complete(hba->uic_async_done); 5454 retval = IRQ_HANDLED; 5455 } 5456 5457 if (retval == IRQ_HANDLED) 5458 ufshcd_add_uic_command_trace(hba, hba->active_uic_cmd, 5459 UFS_CMD_COMP); 5460 spin_unlock(hba->host->host_lock); 5461 return retval; 5462 } 5463 5464 /* Release the resources allocated for processing a SCSI command. */ 5465 void ufshcd_release_scsi_cmd(struct ufs_hba *hba, 5466 struct ufshcd_lrb *lrbp) 5467 { 5468 struct scsi_cmnd *cmd = lrbp->cmd; 5469 5470 scsi_dma_unmap(cmd); 5471 ufshcd_release(hba); 5472 ufshcd_clk_scaling_update_busy(hba); 5473 } 5474 5475 /** 5476 * ufshcd_compl_one_cqe - handle a completion queue entry 5477 * @hba: per adapter instance 5478 * @task_tag: the task tag of the request to be completed 5479 * @cqe: pointer to the completion queue entry 5480 */ 5481 void ufshcd_compl_one_cqe(struct ufs_hba *hba, int task_tag, 5482 struct cq_entry *cqe) 5483 { 5484 struct ufshcd_lrb *lrbp; 5485 struct scsi_cmnd *cmd; 5486 enum utp_ocs ocs; 5487 5488 lrbp = &hba->lrb[task_tag]; 5489 lrbp->compl_time_stamp = ktime_get(); 5490 cmd = lrbp->cmd; 5491 if (cmd) { 5492 if (unlikely(ufshcd_should_inform_monitor(hba, lrbp))) 5493 ufshcd_update_monitor(hba, lrbp); 5494 ufshcd_add_command_trace(hba, task_tag, UFS_CMD_COMP); 5495 cmd->result = ufshcd_transfer_rsp_status(hba, lrbp, cqe); 5496 ufshcd_release_scsi_cmd(hba, lrbp); 5497 /* Do not touch lrbp after scsi done */ 5498 scsi_done(cmd); 5499 } else if (lrbp->command_type == UTP_CMD_TYPE_DEV_MANAGE || 5500 lrbp->command_type == UTP_CMD_TYPE_UFS_STORAGE) { 5501 if (hba->dev_cmd.complete) { 5502 if (cqe) { 5503 ocs = le32_to_cpu(cqe->status) & MASK_OCS; 5504 lrbp->utr_descriptor_ptr->header.ocs = ocs; 5505 } 5506 complete(hba->dev_cmd.complete); 5507 } 5508 } 5509 } 5510 5511 /** 5512 * __ufshcd_transfer_req_compl - handle SCSI and query command completion 5513 * @hba: per adapter instance 5514 * @completed_reqs: bitmask that indicates which requests to complete 5515 */ 5516 static void __ufshcd_transfer_req_compl(struct ufs_hba *hba, 5517 unsigned long completed_reqs) 5518 { 5519 int tag; 5520 5521 for_each_set_bit(tag, &completed_reqs, hba->nutrs) 5522 ufshcd_compl_one_cqe(hba, tag, NULL); 5523 } 5524 5525 /* Any value that is not an existing queue number is fine for this constant. */ 5526 enum { 5527 UFSHCD_POLL_FROM_INTERRUPT_CONTEXT = -1 5528 }; 5529 5530 static void ufshcd_clear_polled(struct ufs_hba *hba, 5531 unsigned long *completed_reqs) 5532 { 5533 int tag; 5534 5535 for_each_set_bit(tag, completed_reqs, hba->nutrs) { 5536 struct scsi_cmnd *cmd = hba->lrb[tag].cmd; 5537 5538 if (!cmd) 5539 continue; 5540 if (scsi_cmd_to_rq(cmd)->cmd_flags & REQ_POLLED) 5541 __clear_bit(tag, completed_reqs); 5542 } 5543 } 5544 5545 /* 5546 * Return: > 0 if one or more commands have been completed or 0 if no 5547 * requests have been completed. 5548 */ 5549 static int ufshcd_poll(struct Scsi_Host *shost, unsigned int queue_num) 5550 { 5551 struct ufs_hba *hba = shost_priv(shost); 5552 unsigned long completed_reqs, flags; 5553 u32 tr_doorbell; 5554 struct ufs_hw_queue *hwq; 5555 5556 if (is_mcq_enabled(hba)) { 5557 hwq = &hba->uhq[queue_num]; 5558 5559 return ufshcd_mcq_poll_cqe_lock(hba, hwq); 5560 } 5561 5562 spin_lock_irqsave(&hba->outstanding_lock, flags); 5563 tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 5564 completed_reqs = ~tr_doorbell & hba->outstanding_reqs; 5565 WARN_ONCE(completed_reqs & ~hba->outstanding_reqs, 5566 "completed: %#lx; outstanding: %#lx\n", completed_reqs, 5567 hba->outstanding_reqs); 5568 if (queue_num == UFSHCD_POLL_FROM_INTERRUPT_CONTEXT) { 5569 /* Do not complete polled requests from interrupt context. */ 5570 ufshcd_clear_polled(hba, &completed_reqs); 5571 } 5572 hba->outstanding_reqs &= ~completed_reqs; 5573 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 5574 5575 if (completed_reqs) 5576 __ufshcd_transfer_req_compl(hba, completed_reqs); 5577 5578 return completed_reqs != 0; 5579 } 5580 5581 /** 5582 * ufshcd_mcq_compl_pending_transfer - MCQ mode function. It is 5583 * invoked from the error handler context or ufshcd_host_reset_and_restore() 5584 * to complete the pending transfers and free the resources associated with 5585 * the scsi command. 5586 * 5587 * @hba: per adapter instance 5588 * @force_compl: This flag is set to true when invoked 5589 * from ufshcd_host_reset_and_restore() in which case it requires special 5590 * handling because the host controller has been reset by ufshcd_hba_stop(). 5591 */ 5592 static void ufshcd_mcq_compl_pending_transfer(struct ufs_hba *hba, 5593 bool force_compl) 5594 { 5595 struct ufs_hw_queue *hwq; 5596 struct ufshcd_lrb *lrbp; 5597 struct scsi_cmnd *cmd; 5598 unsigned long flags; 5599 u32 hwq_num, utag; 5600 int tag; 5601 5602 for (tag = 0; tag < hba->nutrs; tag++) { 5603 lrbp = &hba->lrb[tag]; 5604 cmd = lrbp->cmd; 5605 if (!ufshcd_cmd_inflight(cmd) || 5606 test_bit(SCMD_STATE_COMPLETE, &cmd->state)) 5607 continue; 5608 5609 utag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 5610 hwq_num = blk_mq_unique_tag_to_hwq(utag); 5611 hwq = &hba->uhq[hwq_num]; 5612 5613 if (force_compl) { 5614 ufshcd_mcq_compl_all_cqes_lock(hba, hwq); 5615 /* 5616 * For those cmds of which the cqes are not present 5617 * in the cq, complete them explicitly. 5618 */ 5619 spin_lock_irqsave(&hwq->cq_lock, flags); 5620 if (cmd && !test_bit(SCMD_STATE_COMPLETE, &cmd->state)) { 5621 set_host_byte(cmd, DID_REQUEUE); 5622 ufshcd_release_scsi_cmd(hba, lrbp); 5623 scsi_done(cmd); 5624 } 5625 spin_unlock_irqrestore(&hwq->cq_lock, flags); 5626 } else { 5627 ufshcd_mcq_poll_cqe_lock(hba, hwq); 5628 } 5629 } 5630 } 5631 5632 /** 5633 * ufshcd_transfer_req_compl - handle SCSI and query command completion 5634 * @hba: per adapter instance 5635 * 5636 * Return: 5637 * IRQ_HANDLED - If interrupt is valid 5638 * IRQ_NONE - If invalid interrupt 5639 */ 5640 static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba) 5641 { 5642 /* Resetting interrupt aggregation counters first and reading the 5643 * DOOR_BELL afterward allows us to handle all the completed requests. 5644 * In order to prevent other interrupts starvation the DB is read once 5645 * after reset. The down side of this solution is the possibility of 5646 * false interrupt if device completes another request after resetting 5647 * aggregation and before reading the DB. 5648 */ 5649 if (ufshcd_is_intr_aggr_allowed(hba) && 5650 !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR)) 5651 ufshcd_reset_intr_aggr(hba); 5652 5653 if (ufs_fail_completion()) 5654 return IRQ_HANDLED; 5655 5656 /* 5657 * Ignore the ufshcd_poll() return value and return IRQ_HANDLED since we 5658 * do not want polling to trigger spurious interrupt complaints. 5659 */ 5660 ufshcd_poll(hba->host, UFSHCD_POLL_FROM_INTERRUPT_CONTEXT); 5661 5662 return IRQ_HANDLED; 5663 } 5664 5665 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask) 5666 { 5667 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 5668 QUERY_ATTR_IDN_EE_CONTROL, 0, 0, 5669 &ee_ctrl_mask); 5670 } 5671 5672 int ufshcd_write_ee_control(struct ufs_hba *hba) 5673 { 5674 int err; 5675 5676 mutex_lock(&hba->ee_ctrl_mutex); 5677 err = __ufshcd_write_ee_control(hba, hba->ee_ctrl_mask); 5678 mutex_unlock(&hba->ee_ctrl_mutex); 5679 if (err) 5680 dev_err(hba->dev, "%s: failed to write ee control %d\n", 5681 __func__, err); 5682 return err; 5683 } 5684 5685 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask, 5686 const u16 *other_mask, u16 set, u16 clr) 5687 { 5688 u16 new_mask, ee_ctrl_mask; 5689 int err = 0; 5690 5691 mutex_lock(&hba->ee_ctrl_mutex); 5692 new_mask = (*mask & ~clr) | set; 5693 ee_ctrl_mask = new_mask | *other_mask; 5694 if (ee_ctrl_mask != hba->ee_ctrl_mask) 5695 err = __ufshcd_write_ee_control(hba, ee_ctrl_mask); 5696 /* Still need to update 'mask' even if 'ee_ctrl_mask' was unchanged */ 5697 if (!err) { 5698 hba->ee_ctrl_mask = ee_ctrl_mask; 5699 *mask = new_mask; 5700 } 5701 mutex_unlock(&hba->ee_ctrl_mutex); 5702 return err; 5703 } 5704 5705 /** 5706 * ufshcd_disable_ee - disable exception event 5707 * @hba: per-adapter instance 5708 * @mask: exception event to disable 5709 * 5710 * Disables exception event in the device so that the EVENT_ALERT 5711 * bit is not set. 5712 * 5713 * Return: zero on success, non-zero error value on failure. 5714 */ 5715 static inline int ufshcd_disable_ee(struct ufs_hba *hba, u16 mask) 5716 { 5717 return ufshcd_update_ee_drv_mask(hba, 0, mask); 5718 } 5719 5720 /** 5721 * ufshcd_enable_ee - enable exception event 5722 * @hba: per-adapter instance 5723 * @mask: exception event to enable 5724 * 5725 * Enable corresponding exception event in the device to allow 5726 * device to alert host in critical scenarios. 5727 * 5728 * Return: zero on success, non-zero error value on failure. 5729 */ 5730 static inline int ufshcd_enable_ee(struct ufs_hba *hba, u16 mask) 5731 { 5732 return ufshcd_update_ee_drv_mask(hba, mask, 0); 5733 } 5734 5735 /** 5736 * ufshcd_enable_auto_bkops - Allow device managed BKOPS 5737 * @hba: per-adapter instance 5738 * 5739 * Allow device to manage background operations on its own. Enabling 5740 * this might lead to inconsistent latencies during normal data transfers 5741 * as the device is allowed to manage its own way of handling background 5742 * operations. 5743 * 5744 * Return: zero on success, non-zero on failure. 5745 */ 5746 static int ufshcd_enable_auto_bkops(struct ufs_hba *hba) 5747 { 5748 int err = 0; 5749 5750 if (hba->auto_bkops_enabled) 5751 goto out; 5752 5753 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG, 5754 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5755 if (err) { 5756 dev_err(hba->dev, "%s: failed to enable bkops %d\n", 5757 __func__, err); 5758 goto out; 5759 } 5760 5761 hba->auto_bkops_enabled = true; 5762 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Enabled"); 5763 5764 /* No need of URGENT_BKOPS exception from the device */ 5765 err = ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5766 if (err) 5767 dev_err(hba->dev, "%s: failed to disable exception event %d\n", 5768 __func__, err); 5769 out: 5770 return err; 5771 } 5772 5773 /** 5774 * ufshcd_disable_auto_bkops - block device in doing background operations 5775 * @hba: per-adapter instance 5776 * 5777 * Disabling background operations improves command response latency but 5778 * has drawback of device moving into critical state where the device is 5779 * not-operable. Make sure to call ufshcd_enable_auto_bkops() whenever the 5780 * host is idle so that BKOPS are managed effectively without any negative 5781 * impacts. 5782 * 5783 * Return: zero on success, non-zero on failure. 5784 */ 5785 static int ufshcd_disable_auto_bkops(struct ufs_hba *hba) 5786 { 5787 int err = 0; 5788 5789 if (!hba->auto_bkops_enabled) 5790 goto out; 5791 5792 /* 5793 * If host assisted BKOPs is to be enabled, make sure 5794 * urgent bkops exception is allowed. 5795 */ 5796 err = ufshcd_enable_ee(hba, MASK_EE_URGENT_BKOPS); 5797 if (err) { 5798 dev_err(hba->dev, "%s: failed to enable exception event %d\n", 5799 __func__, err); 5800 goto out; 5801 } 5802 5803 err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_CLEAR_FLAG, 5804 QUERY_FLAG_IDN_BKOPS_EN, 0, NULL); 5805 if (err) { 5806 dev_err(hba->dev, "%s: failed to disable bkops %d\n", 5807 __func__, err); 5808 ufshcd_disable_ee(hba, MASK_EE_URGENT_BKOPS); 5809 goto out; 5810 } 5811 5812 hba->auto_bkops_enabled = false; 5813 trace_ufshcd_auto_bkops_state(dev_name(hba->dev), "Disabled"); 5814 hba->is_urgent_bkops_lvl_checked = false; 5815 out: 5816 return err; 5817 } 5818 5819 /** 5820 * ufshcd_force_reset_auto_bkops - force reset auto bkops state 5821 * @hba: per adapter instance 5822 * 5823 * After a device reset the device may toggle the BKOPS_EN flag 5824 * to default value. The s/w tracking variables should be updated 5825 * as well. This function would change the auto-bkops state based on 5826 * UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND. 5827 */ 5828 static void ufshcd_force_reset_auto_bkops(struct ufs_hba *hba) 5829 { 5830 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) { 5831 hba->auto_bkops_enabled = false; 5832 hba->ee_ctrl_mask |= MASK_EE_URGENT_BKOPS; 5833 ufshcd_enable_auto_bkops(hba); 5834 } else { 5835 hba->auto_bkops_enabled = true; 5836 hba->ee_ctrl_mask &= ~MASK_EE_URGENT_BKOPS; 5837 ufshcd_disable_auto_bkops(hba); 5838 } 5839 hba->urgent_bkops_lvl = BKOPS_STATUS_PERF_IMPACT; 5840 hba->is_urgent_bkops_lvl_checked = false; 5841 } 5842 5843 static inline int ufshcd_get_bkops_status(struct ufs_hba *hba, u32 *status) 5844 { 5845 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5846 QUERY_ATTR_IDN_BKOPS_STATUS, 0, 0, status); 5847 } 5848 5849 /** 5850 * ufshcd_bkops_ctrl - control the auto bkops based on current bkops status 5851 * @hba: per-adapter instance 5852 * @status: bkops_status value 5853 * 5854 * Read the bkops_status from the UFS device and Enable fBackgroundOpsEn 5855 * flag in the device to permit background operations if the device 5856 * bkops_status is greater than or equal to "status" argument passed to 5857 * this function, disable otherwise. 5858 * 5859 * Return: 0 for success, non-zero in case of failure. 5860 * 5861 * NOTE: Caller of this function can check the "hba->auto_bkops_enabled" flag 5862 * to know whether auto bkops is enabled or disabled after this function 5863 * returns control to it. 5864 */ 5865 static int ufshcd_bkops_ctrl(struct ufs_hba *hba, 5866 enum bkops_status status) 5867 { 5868 int err; 5869 u32 curr_status = 0; 5870 5871 err = ufshcd_get_bkops_status(hba, &curr_status); 5872 if (err) { 5873 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5874 __func__, err); 5875 goto out; 5876 } else if (curr_status > BKOPS_STATUS_MAX) { 5877 dev_err(hba->dev, "%s: invalid BKOPS status %d\n", 5878 __func__, curr_status); 5879 err = -EINVAL; 5880 goto out; 5881 } 5882 5883 if (curr_status >= status) 5884 err = ufshcd_enable_auto_bkops(hba); 5885 else 5886 err = ufshcd_disable_auto_bkops(hba); 5887 out: 5888 return err; 5889 } 5890 5891 /** 5892 * ufshcd_urgent_bkops - handle urgent bkops exception event 5893 * @hba: per-adapter instance 5894 * 5895 * Enable fBackgroundOpsEn flag in the device to permit background 5896 * operations. 5897 * 5898 * If BKOPs is enabled, this function returns 0, 1 if the bkops in not enabled 5899 * and negative error value for any other failure. 5900 * 5901 * Return: 0 upon success; < 0 upon failure. 5902 */ 5903 static int ufshcd_urgent_bkops(struct ufs_hba *hba) 5904 { 5905 return ufshcd_bkops_ctrl(hba, hba->urgent_bkops_lvl); 5906 } 5907 5908 static inline int ufshcd_get_ee_status(struct ufs_hba *hba, u32 *status) 5909 { 5910 return ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5911 QUERY_ATTR_IDN_EE_STATUS, 0, 0, status); 5912 } 5913 5914 static void ufshcd_bkops_exception_event_handler(struct ufs_hba *hba) 5915 { 5916 int err; 5917 u32 curr_status = 0; 5918 5919 if (hba->is_urgent_bkops_lvl_checked) 5920 goto enable_auto_bkops; 5921 5922 err = ufshcd_get_bkops_status(hba, &curr_status); 5923 if (err) { 5924 dev_err(hba->dev, "%s: failed to get BKOPS status %d\n", 5925 __func__, err); 5926 goto out; 5927 } 5928 5929 /* 5930 * We are seeing that some devices are raising the urgent bkops 5931 * exception events even when BKOPS status doesn't indicate performace 5932 * impacted or critical. Handle these device by determining their urgent 5933 * bkops status at runtime. 5934 */ 5935 if (curr_status < BKOPS_STATUS_PERF_IMPACT) { 5936 dev_err(hba->dev, "%s: device raised urgent BKOPS exception for bkops status %d\n", 5937 __func__, curr_status); 5938 /* update the current status as the urgent bkops level */ 5939 hba->urgent_bkops_lvl = curr_status; 5940 hba->is_urgent_bkops_lvl_checked = true; 5941 } 5942 5943 enable_auto_bkops: 5944 err = ufshcd_enable_auto_bkops(hba); 5945 out: 5946 if (err < 0) 5947 dev_err(hba->dev, "%s: failed to handle urgent bkops %d\n", 5948 __func__, err); 5949 } 5950 5951 static void ufshcd_temp_exception_event_handler(struct ufs_hba *hba, u16 status) 5952 { 5953 u32 value; 5954 5955 if (ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 5956 QUERY_ATTR_IDN_CASE_ROUGH_TEMP, 0, 0, &value)) 5957 return; 5958 5959 dev_info(hba->dev, "exception Tcase %d\n", value - 80); 5960 5961 ufs_hwmon_notify_event(hba, status & MASK_EE_URGENT_TEMP); 5962 5963 /* 5964 * A placeholder for the platform vendors to add whatever additional 5965 * steps required 5966 */ 5967 } 5968 5969 static int __ufshcd_wb_toggle(struct ufs_hba *hba, bool set, enum flag_idn idn) 5970 { 5971 u8 index; 5972 enum query_opcode opcode = set ? UPIU_QUERY_OPCODE_SET_FLAG : 5973 UPIU_QUERY_OPCODE_CLEAR_FLAG; 5974 5975 index = ufshcd_wb_get_query_index(hba); 5976 return ufshcd_query_flag_retry(hba, opcode, idn, index, NULL); 5977 } 5978 5979 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable) 5980 { 5981 int ret; 5982 5983 if (!ufshcd_is_wb_allowed(hba) || 5984 hba->dev_info.wb_enabled == enable) 5985 return 0; 5986 5987 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_EN); 5988 if (ret) { 5989 dev_err(hba->dev, "%s: Write Booster %s failed %d\n", 5990 __func__, enable ? "enabling" : "disabling", ret); 5991 return ret; 5992 } 5993 5994 hba->dev_info.wb_enabled = enable; 5995 dev_dbg(hba->dev, "%s: Write Booster %s\n", 5996 __func__, enable ? "enabled" : "disabled"); 5997 5998 return ret; 5999 } 6000 6001 static void ufshcd_wb_toggle_buf_flush_during_h8(struct ufs_hba *hba, 6002 bool enable) 6003 { 6004 int ret; 6005 6006 ret = __ufshcd_wb_toggle(hba, enable, 6007 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8); 6008 if (ret) { 6009 dev_err(hba->dev, "%s: WB-Buf Flush during H8 %s failed %d\n", 6010 __func__, enable ? "enabling" : "disabling", ret); 6011 return; 6012 } 6013 dev_dbg(hba->dev, "%s: WB-Buf Flush during H8 %s\n", 6014 __func__, enable ? "enabled" : "disabled"); 6015 } 6016 6017 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable) 6018 { 6019 int ret; 6020 6021 if (!ufshcd_is_wb_allowed(hba) || 6022 hba->dev_info.wb_buf_flush_enabled == enable) 6023 return 0; 6024 6025 ret = __ufshcd_wb_toggle(hba, enable, QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN); 6026 if (ret) { 6027 dev_err(hba->dev, "%s: WB-Buf Flush %s failed %d\n", 6028 __func__, enable ? "enabling" : "disabling", ret); 6029 return ret; 6030 } 6031 6032 hba->dev_info.wb_buf_flush_enabled = enable; 6033 dev_dbg(hba->dev, "%s: WB-Buf Flush %s\n", 6034 __func__, enable ? "enabled" : "disabled"); 6035 6036 return ret; 6037 } 6038 6039 static bool ufshcd_wb_presrv_usrspc_keep_vcc_on(struct ufs_hba *hba, 6040 u32 avail_buf) 6041 { 6042 u32 cur_buf; 6043 int ret; 6044 u8 index; 6045 6046 index = ufshcd_wb_get_query_index(hba); 6047 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6048 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE, 6049 index, 0, &cur_buf); 6050 if (ret) { 6051 dev_err(hba->dev, "%s: dCurWriteBoosterBufferSize read failed %d\n", 6052 __func__, ret); 6053 return false; 6054 } 6055 6056 if (!cur_buf) { 6057 dev_info(hba->dev, "dCurWBBuf: %d WB disabled until free-space is available\n", 6058 cur_buf); 6059 return false; 6060 } 6061 /* Let it continue to flush when available buffer exceeds threshold */ 6062 return avail_buf < hba->vps->wb_flush_threshold; 6063 } 6064 6065 static void ufshcd_wb_force_disable(struct ufs_hba *hba) 6066 { 6067 if (ufshcd_is_wb_buf_flush_allowed(hba)) 6068 ufshcd_wb_toggle_buf_flush(hba, false); 6069 6070 ufshcd_wb_toggle_buf_flush_during_h8(hba, false); 6071 ufshcd_wb_toggle(hba, false); 6072 hba->caps &= ~UFSHCD_CAP_WB_EN; 6073 6074 dev_info(hba->dev, "%s: WB force disabled\n", __func__); 6075 } 6076 6077 static bool ufshcd_is_wb_buf_lifetime_available(struct ufs_hba *hba) 6078 { 6079 u32 lifetime; 6080 int ret; 6081 u8 index; 6082 6083 index = ufshcd_wb_get_query_index(hba); 6084 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6085 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST, 6086 index, 0, &lifetime); 6087 if (ret) { 6088 dev_err(hba->dev, 6089 "%s: bWriteBoosterBufferLifeTimeEst read failed %d\n", 6090 __func__, ret); 6091 return false; 6092 } 6093 6094 if (lifetime == UFS_WB_EXCEED_LIFETIME) { 6095 dev_err(hba->dev, "%s: WB buf lifetime is exhausted 0x%02X\n", 6096 __func__, lifetime); 6097 return false; 6098 } 6099 6100 dev_dbg(hba->dev, "%s: WB buf lifetime is 0x%02X\n", 6101 __func__, lifetime); 6102 6103 return true; 6104 } 6105 6106 static bool ufshcd_wb_need_flush(struct ufs_hba *hba) 6107 { 6108 int ret; 6109 u32 avail_buf; 6110 u8 index; 6111 6112 if (!ufshcd_is_wb_allowed(hba)) 6113 return false; 6114 6115 if (!ufshcd_is_wb_buf_lifetime_available(hba)) { 6116 ufshcd_wb_force_disable(hba); 6117 return false; 6118 } 6119 6120 /* 6121 * The ufs device needs the vcc to be ON to flush. 6122 * With user-space reduction enabled, it's enough to enable flush 6123 * by checking only the available buffer. The threshold 6124 * defined here is > 90% full. 6125 * With user-space preserved enabled, the current-buffer 6126 * should be checked too because the wb buffer size can reduce 6127 * when disk tends to be full. This info is provided by current 6128 * buffer (dCurrentWriteBoosterBufferSize). There's no point in 6129 * keeping vcc on when current buffer is empty. 6130 */ 6131 index = ufshcd_wb_get_query_index(hba); 6132 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 6133 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE, 6134 index, 0, &avail_buf); 6135 if (ret) { 6136 dev_warn(hba->dev, "%s: dAvailableWriteBoosterBufferSize read failed %d\n", 6137 __func__, ret); 6138 return false; 6139 } 6140 6141 if (!hba->dev_info.b_presrv_uspc_en) 6142 return avail_buf <= UFS_WB_BUF_REMAIN_PERCENT(10); 6143 6144 return ufshcd_wb_presrv_usrspc_keep_vcc_on(hba, avail_buf); 6145 } 6146 6147 static void ufshcd_rpm_dev_flush_recheck_work(struct work_struct *work) 6148 { 6149 struct ufs_hba *hba = container_of(to_delayed_work(work), 6150 struct ufs_hba, 6151 rpm_dev_flush_recheck_work); 6152 /* 6153 * To prevent unnecessary VCC power drain after device finishes 6154 * WriteBooster buffer flush or Auto BKOPs, force runtime resume 6155 * after a certain delay to recheck the threshold by next runtime 6156 * suspend. 6157 */ 6158 ufshcd_rpm_get_sync(hba); 6159 ufshcd_rpm_put_sync(hba); 6160 } 6161 6162 /** 6163 * ufshcd_exception_event_handler - handle exceptions raised by device 6164 * @work: pointer to work data 6165 * 6166 * Read bExceptionEventStatus attribute from the device and handle the 6167 * exception event accordingly. 6168 */ 6169 static void ufshcd_exception_event_handler(struct work_struct *work) 6170 { 6171 struct ufs_hba *hba; 6172 int err; 6173 u32 status = 0; 6174 hba = container_of(work, struct ufs_hba, eeh_work); 6175 6176 ufshcd_scsi_block_requests(hba); 6177 err = ufshcd_get_ee_status(hba, &status); 6178 if (err) { 6179 dev_err(hba->dev, "%s: failed to get exception status %d\n", 6180 __func__, err); 6181 goto out; 6182 } 6183 6184 trace_ufshcd_exception_event(dev_name(hba->dev), status); 6185 6186 if (status & hba->ee_drv_mask & MASK_EE_URGENT_BKOPS) 6187 ufshcd_bkops_exception_event_handler(hba); 6188 6189 if (status & hba->ee_drv_mask & MASK_EE_URGENT_TEMP) 6190 ufshcd_temp_exception_event_handler(hba, status); 6191 6192 ufs_debugfs_exception_event(hba, status); 6193 out: 6194 ufshcd_scsi_unblock_requests(hba); 6195 } 6196 6197 /* Complete requests that have door-bell cleared */ 6198 static void ufshcd_complete_requests(struct ufs_hba *hba, bool force_compl) 6199 { 6200 if (is_mcq_enabled(hba)) 6201 ufshcd_mcq_compl_pending_transfer(hba, force_compl); 6202 else 6203 ufshcd_transfer_req_compl(hba); 6204 6205 ufshcd_tmc_handler(hba); 6206 } 6207 6208 /** 6209 * ufshcd_quirk_dl_nac_errors - This function checks if error handling is 6210 * to recover from the DL NAC errors or not. 6211 * @hba: per-adapter instance 6212 * 6213 * Return: true if error handling is required, false otherwise. 6214 */ 6215 static bool ufshcd_quirk_dl_nac_errors(struct ufs_hba *hba) 6216 { 6217 unsigned long flags; 6218 bool err_handling = true; 6219 6220 spin_lock_irqsave(hba->host->host_lock, flags); 6221 /* 6222 * UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS only workaround the 6223 * device fatal error and/or DL NAC & REPLAY timeout errors. 6224 */ 6225 if (hba->saved_err & (CONTROLLER_FATAL_ERROR | SYSTEM_BUS_FATAL_ERROR)) 6226 goto out; 6227 6228 if ((hba->saved_err & DEVICE_FATAL_ERROR) || 6229 ((hba->saved_err & UIC_ERROR) && 6230 (hba->saved_uic_err & UFSHCD_UIC_DL_TCx_REPLAY_ERROR))) 6231 goto out; 6232 6233 if ((hba->saved_err & UIC_ERROR) && 6234 (hba->saved_uic_err & UFSHCD_UIC_DL_NAC_RECEIVED_ERROR)) { 6235 int err; 6236 /* 6237 * wait for 50ms to see if we can get any other errors or not. 6238 */ 6239 spin_unlock_irqrestore(hba->host->host_lock, flags); 6240 msleep(50); 6241 spin_lock_irqsave(hba->host->host_lock, flags); 6242 6243 /* 6244 * now check if we have got any other severe errors other than 6245 * DL NAC error? 6246 */ 6247 if ((hba->saved_err & INT_FATAL_ERRORS) || 6248 ((hba->saved_err & UIC_ERROR) && 6249 (hba->saved_uic_err & ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR))) 6250 goto out; 6251 6252 /* 6253 * As DL NAC is the only error received so far, send out NOP 6254 * command to confirm if link is still active or not. 6255 * - If we don't get any response then do error recovery. 6256 * - If we get response then clear the DL NAC error bit. 6257 */ 6258 6259 spin_unlock_irqrestore(hba->host->host_lock, flags); 6260 err = ufshcd_verify_dev_init(hba); 6261 spin_lock_irqsave(hba->host->host_lock, flags); 6262 6263 if (err) 6264 goto out; 6265 6266 /* Link seems to be alive hence ignore the DL NAC errors */ 6267 if (hba->saved_uic_err == UFSHCD_UIC_DL_NAC_RECEIVED_ERROR) 6268 hba->saved_err &= ~UIC_ERROR; 6269 /* clear NAC error */ 6270 hba->saved_uic_err &= ~UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6271 if (!hba->saved_uic_err) 6272 err_handling = false; 6273 } 6274 out: 6275 spin_unlock_irqrestore(hba->host->host_lock, flags); 6276 return err_handling; 6277 } 6278 6279 /* host lock must be held before calling this func */ 6280 static inline bool ufshcd_is_saved_err_fatal(struct ufs_hba *hba) 6281 { 6282 return (hba->saved_uic_err & UFSHCD_UIC_DL_PA_INIT_ERROR) || 6283 (hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)); 6284 } 6285 6286 void ufshcd_schedule_eh_work(struct ufs_hba *hba) 6287 { 6288 lockdep_assert_held(hba->host->host_lock); 6289 6290 /* handle fatal errors only when link is not in error state */ 6291 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6292 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6293 ufshcd_is_saved_err_fatal(hba)) 6294 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_FATAL; 6295 else 6296 hba->ufshcd_state = UFSHCD_STATE_EH_SCHEDULED_NON_FATAL; 6297 queue_work(hba->eh_wq, &hba->eh_work); 6298 } 6299 } 6300 6301 static void ufshcd_force_error_recovery(struct ufs_hba *hba) 6302 { 6303 spin_lock_irq(hba->host->host_lock); 6304 hba->force_reset = true; 6305 ufshcd_schedule_eh_work(hba); 6306 spin_unlock_irq(hba->host->host_lock); 6307 } 6308 6309 static void ufshcd_clk_scaling_allow(struct ufs_hba *hba, bool allow) 6310 { 6311 mutex_lock(&hba->wb_mutex); 6312 down_write(&hba->clk_scaling_lock); 6313 hba->clk_scaling.is_allowed = allow; 6314 up_write(&hba->clk_scaling_lock); 6315 mutex_unlock(&hba->wb_mutex); 6316 } 6317 6318 static void ufshcd_clk_scaling_suspend(struct ufs_hba *hba, bool suspend) 6319 { 6320 if (suspend) { 6321 if (hba->clk_scaling.is_enabled) 6322 ufshcd_suspend_clkscaling(hba); 6323 ufshcd_clk_scaling_allow(hba, false); 6324 } else { 6325 ufshcd_clk_scaling_allow(hba, true); 6326 if (hba->clk_scaling.is_enabled) 6327 ufshcd_resume_clkscaling(hba); 6328 } 6329 } 6330 6331 static void ufshcd_err_handling_prepare(struct ufs_hba *hba) 6332 { 6333 ufshcd_rpm_get_sync(hba); 6334 if (pm_runtime_status_suspended(&hba->ufs_device_wlun->sdev_gendev) || 6335 hba->is_sys_suspended) { 6336 enum ufs_pm_op pm_op; 6337 6338 /* 6339 * Don't assume anything of resume, if 6340 * resume fails, irq and clocks can be OFF, and powers 6341 * can be OFF or in LPM. 6342 */ 6343 ufshcd_setup_hba_vreg(hba, true); 6344 ufshcd_enable_irq(hba); 6345 ufshcd_setup_vreg(hba, true); 6346 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 6347 ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 6348 ufshcd_hold(hba); 6349 if (!ufshcd_is_clkgating_allowed(hba)) 6350 ufshcd_setup_clocks(hba, true); 6351 ufshcd_release(hba); 6352 pm_op = hba->is_sys_suspended ? UFS_SYSTEM_PM : UFS_RUNTIME_PM; 6353 ufshcd_vops_resume(hba, pm_op); 6354 } else { 6355 ufshcd_hold(hba); 6356 if (ufshcd_is_clkscaling_supported(hba) && 6357 hba->clk_scaling.is_enabled) 6358 ufshcd_suspend_clkscaling(hba); 6359 ufshcd_clk_scaling_allow(hba, false); 6360 } 6361 ufshcd_scsi_block_requests(hba); 6362 /* Wait for ongoing ufshcd_queuecommand() calls to finish. */ 6363 blk_mq_wait_quiesce_done(&hba->host->tag_set); 6364 cancel_work_sync(&hba->eeh_work); 6365 } 6366 6367 static void ufshcd_err_handling_unprepare(struct ufs_hba *hba) 6368 { 6369 ufshcd_scsi_unblock_requests(hba); 6370 ufshcd_release(hba); 6371 if (ufshcd_is_clkscaling_supported(hba)) 6372 ufshcd_clk_scaling_suspend(hba, false); 6373 ufshcd_rpm_put(hba); 6374 } 6375 6376 static inline bool ufshcd_err_handling_should_stop(struct ufs_hba *hba) 6377 { 6378 return (!hba->is_powered || hba->shutting_down || 6379 !hba->ufs_device_wlun || 6380 hba->ufshcd_state == UFSHCD_STATE_ERROR || 6381 (!(hba->saved_err || hba->saved_uic_err || hba->force_reset || 6382 ufshcd_is_link_broken(hba)))); 6383 } 6384 6385 #ifdef CONFIG_PM 6386 static void ufshcd_recover_pm_error(struct ufs_hba *hba) 6387 { 6388 struct Scsi_Host *shost = hba->host; 6389 struct scsi_device *sdev; 6390 struct request_queue *q; 6391 int ret; 6392 6393 hba->is_sys_suspended = false; 6394 /* 6395 * Set RPM status of wlun device to RPM_ACTIVE, 6396 * this also clears its runtime error. 6397 */ 6398 ret = pm_runtime_set_active(&hba->ufs_device_wlun->sdev_gendev); 6399 6400 /* hba device might have a runtime error otherwise */ 6401 if (ret) 6402 ret = pm_runtime_set_active(hba->dev); 6403 /* 6404 * If wlun device had runtime error, we also need to resume those 6405 * consumer scsi devices in case any of them has failed to be 6406 * resumed due to supplier runtime resume failure. This is to unblock 6407 * blk_queue_enter in case there are bios waiting inside it. 6408 */ 6409 if (!ret) { 6410 shost_for_each_device(sdev, shost) { 6411 q = sdev->request_queue; 6412 if (q->dev && (q->rpm_status == RPM_SUSPENDED || 6413 q->rpm_status == RPM_SUSPENDING)) 6414 pm_request_resume(q->dev); 6415 } 6416 } 6417 } 6418 #else 6419 static inline void ufshcd_recover_pm_error(struct ufs_hba *hba) 6420 { 6421 } 6422 #endif 6423 6424 static bool ufshcd_is_pwr_mode_restore_needed(struct ufs_hba *hba) 6425 { 6426 struct ufs_pa_layer_attr *pwr_info = &hba->pwr_info; 6427 u32 mode; 6428 6429 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode); 6430 6431 if (pwr_info->pwr_rx != ((mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK)) 6432 return true; 6433 6434 if (pwr_info->pwr_tx != (mode & PWRMODE_MASK)) 6435 return true; 6436 6437 return false; 6438 } 6439 6440 static bool ufshcd_abort_one(struct request *rq, void *priv) 6441 { 6442 int *ret = priv; 6443 u32 tag = rq->tag; 6444 struct scsi_cmnd *cmd = blk_mq_rq_to_pdu(rq); 6445 struct scsi_device *sdev = cmd->device; 6446 struct Scsi_Host *shost = sdev->host; 6447 struct ufs_hba *hba = shost_priv(shost); 6448 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 6449 struct ufs_hw_queue *hwq; 6450 unsigned long flags; 6451 6452 *ret = ufshcd_try_to_abort_task(hba, tag); 6453 dev_err(hba->dev, "Aborting tag %d / CDB %#02x %s\n", tag, 6454 hba->lrb[tag].cmd ? hba->lrb[tag].cmd->cmnd[0] : -1, 6455 *ret ? "failed" : "succeeded"); 6456 6457 /* Release cmd in MCQ mode if abort succeeds */ 6458 if (is_mcq_enabled(hba) && (*ret == 0)) { 6459 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 6460 spin_lock_irqsave(&hwq->cq_lock, flags); 6461 if (ufshcd_cmd_inflight(lrbp->cmd)) 6462 ufshcd_release_scsi_cmd(hba, lrbp); 6463 spin_unlock_irqrestore(&hwq->cq_lock, flags); 6464 } 6465 6466 return *ret == 0; 6467 } 6468 6469 /** 6470 * ufshcd_abort_all - Abort all pending commands. 6471 * @hba: Host bus adapter pointer. 6472 * 6473 * Return: true if and only if the host controller needs to be reset. 6474 */ 6475 static bool ufshcd_abort_all(struct ufs_hba *hba) 6476 { 6477 int tag, ret = 0; 6478 6479 blk_mq_tagset_busy_iter(&hba->host->tag_set, ufshcd_abort_one, &ret); 6480 if (ret) 6481 goto out; 6482 6483 /* Clear pending task management requests */ 6484 for_each_set_bit(tag, &hba->outstanding_tasks, hba->nutmrs) { 6485 ret = ufshcd_clear_tm_cmd(hba, tag); 6486 if (ret) 6487 goto out; 6488 } 6489 6490 out: 6491 /* Complete the requests that are cleared by s/w */ 6492 ufshcd_complete_requests(hba, false); 6493 6494 return ret != 0; 6495 } 6496 6497 /** 6498 * ufshcd_err_handler - handle UFS errors that require s/w attention 6499 * @work: pointer to work structure 6500 */ 6501 static void ufshcd_err_handler(struct work_struct *work) 6502 { 6503 int retries = MAX_ERR_HANDLER_RETRIES; 6504 struct ufs_hba *hba; 6505 unsigned long flags; 6506 bool needs_restore; 6507 bool needs_reset; 6508 int pmc_err; 6509 6510 hba = container_of(work, struct ufs_hba, eh_work); 6511 6512 dev_info(hba->dev, 6513 "%s started; HBA state %s; powered %d; shutting down %d; saved_err = %d; saved_uic_err = %d; force_reset = %d%s\n", 6514 __func__, ufshcd_state_name[hba->ufshcd_state], 6515 hba->is_powered, hba->shutting_down, hba->saved_err, 6516 hba->saved_uic_err, hba->force_reset, 6517 ufshcd_is_link_broken(hba) ? "; link is broken" : ""); 6518 6519 down(&hba->host_sem); 6520 spin_lock_irqsave(hba->host->host_lock, flags); 6521 if (ufshcd_err_handling_should_stop(hba)) { 6522 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6523 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6524 spin_unlock_irqrestore(hba->host->host_lock, flags); 6525 up(&hba->host_sem); 6526 return; 6527 } 6528 ufshcd_set_eh_in_progress(hba); 6529 spin_unlock_irqrestore(hba->host->host_lock, flags); 6530 ufshcd_err_handling_prepare(hba); 6531 /* Complete requests that have door-bell cleared by h/w */ 6532 ufshcd_complete_requests(hba, false); 6533 spin_lock_irqsave(hba->host->host_lock, flags); 6534 again: 6535 needs_restore = false; 6536 needs_reset = false; 6537 6538 if (hba->ufshcd_state != UFSHCD_STATE_ERROR) 6539 hba->ufshcd_state = UFSHCD_STATE_RESET; 6540 /* 6541 * A full reset and restore might have happened after preparation 6542 * is finished, double check whether we should stop. 6543 */ 6544 if (ufshcd_err_handling_should_stop(hba)) 6545 goto skip_err_handling; 6546 6547 if (hba->dev_quirks & UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6548 bool ret; 6549 6550 spin_unlock_irqrestore(hba->host->host_lock, flags); 6551 /* release the lock as ufshcd_quirk_dl_nac_errors() may sleep */ 6552 ret = ufshcd_quirk_dl_nac_errors(hba); 6553 spin_lock_irqsave(hba->host->host_lock, flags); 6554 if (!ret && ufshcd_err_handling_should_stop(hba)) 6555 goto skip_err_handling; 6556 } 6557 6558 if ((hba->saved_err & (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6559 (hba->saved_uic_err && 6560 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6561 bool pr_prdt = !!(hba->saved_err & SYSTEM_BUS_FATAL_ERROR); 6562 6563 spin_unlock_irqrestore(hba->host->host_lock, flags); 6564 ufshcd_print_host_state(hba); 6565 ufshcd_print_pwr_info(hba); 6566 ufshcd_print_evt_hist(hba); 6567 ufshcd_print_tmrs(hba, hba->outstanding_tasks); 6568 ufshcd_print_trs_all(hba, pr_prdt); 6569 spin_lock_irqsave(hba->host->host_lock, flags); 6570 } 6571 6572 /* 6573 * if host reset is required then skip clearing the pending 6574 * transfers forcefully because they will get cleared during 6575 * host reset and restore 6576 */ 6577 if (hba->force_reset || ufshcd_is_link_broken(hba) || 6578 ufshcd_is_saved_err_fatal(hba) || 6579 ((hba->saved_err & UIC_ERROR) && 6580 (hba->saved_uic_err & (UFSHCD_UIC_DL_NAC_RECEIVED_ERROR | 6581 UFSHCD_UIC_DL_TCx_REPLAY_ERROR)))) { 6582 needs_reset = true; 6583 goto do_reset; 6584 } 6585 6586 /* 6587 * If LINERESET was caught, UFS might have been put to PWM mode, 6588 * check if power mode restore is needed. 6589 */ 6590 if (hba->saved_uic_err & UFSHCD_UIC_PA_GENERIC_ERROR) { 6591 hba->saved_uic_err &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6592 if (!hba->saved_uic_err) 6593 hba->saved_err &= ~UIC_ERROR; 6594 spin_unlock_irqrestore(hba->host->host_lock, flags); 6595 if (ufshcd_is_pwr_mode_restore_needed(hba)) 6596 needs_restore = true; 6597 spin_lock_irqsave(hba->host->host_lock, flags); 6598 if (!hba->saved_err && !needs_restore) 6599 goto skip_err_handling; 6600 } 6601 6602 hba->silence_err_logs = true; 6603 /* release lock as clear command might sleep */ 6604 spin_unlock_irqrestore(hba->host->host_lock, flags); 6605 6606 needs_reset = ufshcd_abort_all(hba); 6607 6608 spin_lock_irqsave(hba->host->host_lock, flags); 6609 hba->silence_err_logs = false; 6610 if (needs_reset) 6611 goto do_reset; 6612 6613 /* 6614 * After all reqs and tasks are cleared from doorbell, 6615 * now it is safe to retore power mode. 6616 */ 6617 if (needs_restore) { 6618 spin_unlock_irqrestore(hba->host->host_lock, flags); 6619 /* 6620 * Hold the scaling lock just in case dev cmds 6621 * are sent via bsg and/or sysfs. 6622 */ 6623 down_write(&hba->clk_scaling_lock); 6624 hba->force_pmc = true; 6625 pmc_err = ufshcd_config_pwr_mode(hba, &(hba->pwr_info)); 6626 if (pmc_err) { 6627 needs_reset = true; 6628 dev_err(hba->dev, "%s: Failed to restore power mode, err = %d\n", 6629 __func__, pmc_err); 6630 } 6631 hba->force_pmc = false; 6632 ufshcd_print_pwr_info(hba); 6633 up_write(&hba->clk_scaling_lock); 6634 spin_lock_irqsave(hba->host->host_lock, flags); 6635 } 6636 6637 do_reset: 6638 /* Fatal errors need reset */ 6639 if (needs_reset) { 6640 int err; 6641 6642 hba->force_reset = false; 6643 spin_unlock_irqrestore(hba->host->host_lock, flags); 6644 err = ufshcd_reset_and_restore(hba); 6645 if (err) 6646 dev_err(hba->dev, "%s: reset and restore failed with err %d\n", 6647 __func__, err); 6648 else 6649 ufshcd_recover_pm_error(hba); 6650 spin_lock_irqsave(hba->host->host_lock, flags); 6651 } 6652 6653 skip_err_handling: 6654 if (!needs_reset) { 6655 if (hba->ufshcd_state == UFSHCD_STATE_RESET) 6656 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 6657 if (hba->saved_err || hba->saved_uic_err) 6658 dev_err_ratelimited(hba->dev, "%s: exit: saved_err 0x%x saved_uic_err 0x%x", 6659 __func__, hba->saved_err, hba->saved_uic_err); 6660 } 6661 /* Exit in an operational state or dead */ 6662 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 6663 hba->ufshcd_state != UFSHCD_STATE_ERROR) { 6664 if (--retries) 6665 goto again; 6666 hba->ufshcd_state = UFSHCD_STATE_ERROR; 6667 } 6668 ufshcd_clear_eh_in_progress(hba); 6669 spin_unlock_irqrestore(hba->host->host_lock, flags); 6670 ufshcd_err_handling_unprepare(hba); 6671 up(&hba->host_sem); 6672 6673 dev_info(hba->dev, "%s finished; HBA state %s\n", __func__, 6674 ufshcd_state_name[hba->ufshcd_state]); 6675 } 6676 6677 /** 6678 * ufshcd_update_uic_error - check and set fatal UIC error flags. 6679 * @hba: per-adapter instance 6680 * 6681 * Return: 6682 * IRQ_HANDLED - If interrupt is valid 6683 * IRQ_NONE - If invalid interrupt 6684 */ 6685 static irqreturn_t ufshcd_update_uic_error(struct ufs_hba *hba) 6686 { 6687 u32 reg; 6688 irqreturn_t retval = IRQ_NONE; 6689 6690 /* PHY layer error */ 6691 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER); 6692 if ((reg & UIC_PHY_ADAPTER_LAYER_ERROR) && 6693 (reg & UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK)) { 6694 ufshcd_update_evt_hist(hba, UFS_EVT_PA_ERR, reg); 6695 /* 6696 * To know whether this error is fatal or not, DB timeout 6697 * must be checked but this error is handled separately. 6698 */ 6699 if (reg & UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK) 6700 dev_dbg(hba->dev, "%s: UIC Lane error reported\n", 6701 __func__); 6702 6703 /* Got a LINERESET indication. */ 6704 if (reg & UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR) { 6705 struct uic_command *cmd = NULL; 6706 6707 hba->uic_error |= UFSHCD_UIC_PA_GENERIC_ERROR; 6708 if (hba->uic_async_done && hba->active_uic_cmd) 6709 cmd = hba->active_uic_cmd; 6710 /* 6711 * Ignore the LINERESET during power mode change 6712 * operation via DME_SET command. 6713 */ 6714 if (cmd && (cmd->command == UIC_CMD_DME_SET)) 6715 hba->uic_error &= ~UFSHCD_UIC_PA_GENERIC_ERROR; 6716 } 6717 retval |= IRQ_HANDLED; 6718 } 6719 6720 /* PA_INIT_ERROR is fatal and needs UIC reset */ 6721 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DATA_LINK_LAYER); 6722 if ((reg & UIC_DATA_LINK_LAYER_ERROR) && 6723 (reg & UIC_DATA_LINK_LAYER_ERROR_CODE_MASK)) { 6724 ufshcd_update_evt_hist(hba, UFS_EVT_DL_ERR, reg); 6725 6726 if (reg & UIC_DATA_LINK_LAYER_ERROR_PA_INIT) 6727 hba->uic_error |= UFSHCD_UIC_DL_PA_INIT_ERROR; 6728 else if (hba->dev_quirks & 6729 UFS_DEVICE_QUIRK_RECOVERY_FROM_DL_NAC_ERRORS) { 6730 if (reg & UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED) 6731 hba->uic_error |= 6732 UFSHCD_UIC_DL_NAC_RECEIVED_ERROR; 6733 else if (reg & UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT) 6734 hba->uic_error |= UFSHCD_UIC_DL_TCx_REPLAY_ERROR; 6735 } 6736 retval |= IRQ_HANDLED; 6737 } 6738 6739 /* UIC NL/TL/DME errors needs software retry */ 6740 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_NETWORK_LAYER); 6741 if ((reg & UIC_NETWORK_LAYER_ERROR) && 6742 (reg & UIC_NETWORK_LAYER_ERROR_CODE_MASK)) { 6743 ufshcd_update_evt_hist(hba, UFS_EVT_NL_ERR, reg); 6744 hba->uic_error |= UFSHCD_UIC_NL_ERROR; 6745 retval |= IRQ_HANDLED; 6746 } 6747 6748 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_TRANSPORT_LAYER); 6749 if ((reg & UIC_TRANSPORT_LAYER_ERROR) && 6750 (reg & UIC_TRANSPORT_LAYER_ERROR_CODE_MASK)) { 6751 ufshcd_update_evt_hist(hba, UFS_EVT_TL_ERR, reg); 6752 hba->uic_error |= UFSHCD_UIC_TL_ERROR; 6753 retval |= IRQ_HANDLED; 6754 } 6755 6756 reg = ufshcd_readl(hba, REG_UIC_ERROR_CODE_DME); 6757 if ((reg & UIC_DME_ERROR) && 6758 (reg & UIC_DME_ERROR_CODE_MASK)) { 6759 ufshcd_update_evt_hist(hba, UFS_EVT_DME_ERR, reg); 6760 hba->uic_error |= UFSHCD_UIC_DME_ERROR; 6761 retval |= IRQ_HANDLED; 6762 } 6763 6764 dev_dbg(hba->dev, "%s: UIC error flags = 0x%08x\n", 6765 __func__, hba->uic_error); 6766 return retval; 6767 } 6768 6769 /** 6770 * ufshcd_check_errors - Check for errors that need s/w attention 6771 * @hba: per-adapter instance 6772 * @intr_status: interrupt status generated by the controller 6773 * 6774 * Return: 6775 * IRQ_HANDLED - If interrupt is valid 6776 * IRQ_NONE - If invalid interrupt 6777 */ 6778 static irqreturn_t ufshcd_check_errors(struct ufs_hba *hba, u32 intr_status) 6779 { 6780 bool queue_eh_work = false; 6781 irqreturn_t retval = IRQ_NONE; 6782 6783 spin_lock(hba->host->host_lock); 6784 hba->errors |= UFSHCD_ERROR_MASK & intr_status; 6785 6786 if (hba->errors & INT_FATAL_ERRORS) { 6787 ufshcd_update_evt_hist(hba, UFS_EVT_FATAL_ERR, 6788 hba->errors); 6789 queue_eh_work = true; 6790 } 6791 6792 if (hba->errors & UIC_ERROR) { 6793 hba->uic_error = 0; 6794 retval = ufshcd_update_uic_error(hba); 6795 if (hba->uic_error) 6796 queue_eh_work = true; 6797 } 6798 6799 if (hba->errors & UFSHCD_UIC_HIBERN8_MASK) { 6800 dev_err(hba->dev, 6801 "%s: Auto Hibern8 %s failed - status: 0x%08x, upmcrs: 0x%08x\n", 6802 __func__, (hba->errors & UIC_HIBERNATE_ENTER) ? 6803 "Enter" : "Exit", 6804 hba->errors, ufshcd_get_upmcrs(hba)); 6805 ufshcd_update_evt_hist(hba, UFS_EVT_AUTO_HIBERN8_ERR, 6806 hba->errors); 6807 ufshcd_set_link_broken(hba); 6808 queue_eh_work = true; 6809 } 6810 6811 if (queue_eh_work) { 6812 /* 6813 * update the transfer error masks to sticky bits, let's do this 6814 * irrespective of current ufshcd_state. 6815 */ 6816 hba->saved_err |= hba->errors; 6817 hba->saved_uic_err |= hba->uic_error; 6818 6819 /* dump controller state before resetting */ 6820 if ((hba->saved_err & 6821 (INT_FATAL_ERRORS | UFSHCD_UIC_HIBERN8_MASK)) || 6822 (hba->saved_uic_err && 6823 (hba->saved_uic_err != UFSHCD_UIC_PA_GENERIC_ERROR))) { 6824 dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x\n", 6825 __func__, hba->saved_err, 6826 hba->saved_uic_err); 6827 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, 6828 "host_regs: "); 6829 ufshcd_print_pwr_info(hba); 6830 } 6831 ufshcd_schedule_eh_work(hba); 6832 retval |= IRQ_HANDLED; 6833 } 6834 /* 6835 * if (!queue_eh_work) - 6836 * Other errors are either non-fatal where host recovers 6837 * itself without s/w intervention or errors that will be 6838 * handled by the SCSI core layer. 6839 */ 6840 hba->errors = 0; 6841 hba->uic_error = 0; 6842 spin_unlock(hba->host->host_lock); 6843 return retval; 6844 } 6845 6846 /** 6847 * ufshcd_tmc_handler - handle task management function completion 6848 * @hba: per adapter instance 6849 * 6850 * Return: 6851 * IRQ_HANDLED - If interrupt is valid 6852 * IRQ_NONE - If invalid interrupt 6853 */ 6854 static irqreturn_t ufshcd_tmc_handler(struct ufs_hba *hba) 6855 { 6856 unsigned long flags, pending, issued; 6857 irqreturn_t ret = IRQ_NONE; 6858 int tag; 6859 6860 spin_lock_irqsave(hba->host->host_lock, flags); 6861 pending = ufshcd_readl(hba, REG_UTP_TASK_REQ_DOOR_BELL); 6862 issued = hba->outstanding_tasks & ~pending; 6863 for_each_set_bit(tag, &issued, hba->nutmrs) { 6864 struct request *req = hba->tmf_rqs[tag]; 6865 struct completion *c = req->end_io_data; 6866 6867 complete(c); 6868 ret = IRQ_HANDLED; 6869 } 6870 spin_unlock_irqrestore(hba->host->host_lock, flags); 6871 6872 return ret; 6873 } 6874 6875 /** 6876 * ufshcd_handle_mcq_cq_events - handle MCQ completion queue events 6877 * @hba: per adapter instance 6878 * 6879 * Return: IRQ_HANDLED if interrupt is handled. 6880 */ 6881 static irqreturn_t ufshcd_handle_mcq_cq_events(struct ufs_hba *hba) 6882 { 6883 struct ufs_hw_queue *hwq; 6884 unsigned long outstanding_cqs; 6885 unsigned int nr_queues; 6886 int i, ret; 6887 u32 events; 6888 6889 ret = ufshcd_vops_get_outstanding_cqs(hba, &outstanding_cqs); 6890 if (ret) 6891 outstanding_cqs = (1U << hba->nr_hw_queues) - 1; 6892 6893 /* Exclude the poll queues */ 6894 nr_queues = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; 6895 for_each_set_bit(i, &outstanding_cqs, nr_queues) { 6896 hwq = &hba->uhq[i]; 6897 6898 events = ufshcd_mcq_read_cqis(hba, i); 6899 if (events) 6900 ufshcd_mcq_write_cqis(hba, events, i); 6901 6902 if (events & UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS) 6903 ufshcd_mcq_poll_cqe_lock(hba, hwq); 6904 } 6905 6906 return IRQ_HANDLED; 6907 } 6908 6909 /** 6910 * ufshcd_sl_intr - Interrupt service routine 6911 * @hba: per adapter instance 6912 * @intr_status: contains interrupts generated by the controller 6913 * 6914 * Return: 6915 * IRQ_HANDLED - If interrupt is valid 6916 * IRQ_NONE - If invalid interrupt 6917 */ 6918 static irqreturn_t ufshcd_sl_intr(struct ufs_hba *hba, u32 intr_status) 6919 { 6920 irqreturn_t retval = IRQ_NONE; 6921 6922 if (intr_status & UFSHCD_UIC_MASK) 6923 retval |= ufshcd_uic_cmd_compl(hba, intr_status); 6924 6925 if (intr_status & UFSHCD_ERROR_MASK || hba->errors) 6926 retval |= ufshcd_check_errors(hba, intr_status); 6927 6928 if (intr_status & UTP_TASK_REQ_COMPL) 6929 retval |= ufshcd_tmc_handler(hba); 6930 6931 if (intr_status & UTP_TRANSFER_REQ_COMPL) 6932 retval |= ufshcd_transfer_req_compl(hba); 6933 6934 if (intr_status & MCQ_CQ_EVENT_STATUS) 6935 retval |= ufshcd_handle_mcq_cq_events(hba); 6936 6937 return retval; 6938 } 6939 6940 /** 6941 * ufshcd_intr - Main interrupt service routine 6942 * @irq: irq number 6943 * @__hba: pointer to adapter instance 6944 * 6945 * Return: 6946 * IRQ_HANDLED - If interrupt is valid 6947 * IRQ_NONE - If invalid interrupt 6948 */ 6949 static irqreturn_t ufshcd_intr(int irq, void *__hba) 6950 { 6951 u32 intr_status, enabled_intr_status = 0; 6952 irqreturn_t retval = IRQ_NONE; 6953 struct ufs_hba *hba = __hba; 6954 int retries = hba->nutrs; 6955 6956 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6957 hba->ufs_stats.last_intr_status = intr_status; 6958 hba->ufs_stats.last_intr_ts = local_clock(); 6959 6960 /* 6961 * There could be max of hba->nutrs reqs in flight and in worst case 6962 * if the reqs get finished 1 by 1 after the interrupt status is 6963 * read, make sure we handle them by checking the interrupt status 6964 * again in a loop until we process all of the reqs before returning. 6965 */ 6966 while (intr_status && retries--) { 6967 enabled_intr_status = 6968 intr_status & ufshcd_readl(hba, REG_INTERRUPT_ENABLE); 6969 ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS); 6970 if (enabled_intr_status) 6971 retval |= ufshcd_sl_intr(hba, enabled_intr_status); 6972 6973 intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS); 6974 } 6975 6976 if (enabled_intr_status && retval == IRQ_NONE && 6977 (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL) || 6978 hba->outstanding_reqs) && !ufshcd_eh_in_progress(hba)) { 6979 dev_err(hba->dev, "%s: Unhandled interrupt 0x%08x (0x%08x, 0x%08x)\n", 6980 __func__, 6981 intr_status, 6982 hba->ufs_stats.last_intr_status, 6983 enabled_intr_status); 6984 ufshcd_dump_regs(hba, 0, UFSHCI_REG_SPACE_SIZE, "host_regs: "); 6985 } 6986 6987 return retval; 6988 } 6989 6990 static int ufshcd_clear_tm_cmd(struct ufs_hba *hba, int tag) 6991 { 6992 int err = 0; 6993 u32 mask = 1 << tag; 6994 unsigned long flags; 6995 6996 if (!test_bit(tag, &hba->outstanding_tasks)) 6997 goto out; 6998 6999 spin_lock_irqsave(hba->host->host_lock, flags); 7000 ufshcd_utmrl_clear(hba, tag); 7001 spin_unlock_irqrestore(hba->host->host_lock, flags); 7002 7003 /* poll for max. 1 sec to clear door bell register by h/w */ 7004 err = ufshcd_wait_for_register(hba, 7005 REG_UTP_TASK_REQ_DOOR_BELL, 7006 mask, 0, 1000, 1000); 7007 7008 dev_err(hba->dev, "Clearing task management function with tag %d %s\n", 7009 tag, err < 0 ? "failed" : "succeeded"); 7010 7011 out: 7012 return err; 7013 } 7014 7015 static int __ufshcd_issue_tm_cmd(struct ufs_hba *hba, 7016 struct utp_task_req_desc *treq, u8 tm_function) 7017 { 7018 struct request_queue *q = hba->tmf_queue; 7019 struct Scsi_Host *host = hba->host; 7020 DECLARE_COMPLETION_ONSTACK(wait); 7021 struct request *req; 7022 unsigned long flags; 7023 int task_tag, err; 7024 7025 /* 7026 * blk_mq_alloc_request() is used here only to get a free tag. 7027 */ 7028 req = blk_mq_alloc_request(q, REQ_OP_DRV_OUT, 0); 7029 if (IS_ERR(req)) 7030 return PTR_ERR(req); 7031 7032 req->end_io_data = &wait; 7033 ufshcd_hold(hba); 7034 7035 spin_lock_irqsave(host->host_lock, flags); 7036 7037 task_tag = req->tag; 7038 hba->tmf_rqs[req->tag] = req; 7039 treq->upiu_req.req_header.task_tag = task_tag; 7040 7041 memcpy(hba->utmrdl_base_addr + task_tag, treq, sizeof(*treq)); 7042 ufshcd_vops_setup_task_mgmt(hba, task_tag, tm_function); 7043 7044 /* send command to the controller */ 7045 __set_bit(task_tag, &hba->outstanding_tasks); 7046 7047 ufshcd_writel(hba, 1 << task_tag, REG_UTP_TASK_REQ_DOOR_BELL); 7048 /* Make sure that doorbell is committed immediately */ 7049 wmb(); 7050 7051 spin_unlock_irqrestore(host->host_lock, flags); 7052 7053 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_SEND); 7054 7055 /* wait until the task management command is completed */ 7056 err = wait_for_completion_io_timeout(&wait, 7057 msecs_to_jiffies(TM_CMD_TIMEOUT)); 7058 if (!err) { 7059 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_ERR); 7060 dev_err(hba->dev, "%s: task management cmd 0x%.2x timed-out\n", 7061 __func__, tm_function); 7062 if (ufshcd_clear_tm_cmd(hba, task_tag)) 7063 dev_WARN(hba->dev, "%s: unable to clear tm cmd (slot %d) after timeout\n", 7064 __func__, task_tag); 7065 err = -ETIMEDOUT; 7066 } else { 7067 err = 0; 7068 memcpy(treq, hba->utmrdl_base_addr + task_tag, sizeof(*treq)); 7069 7070 ufshcd_add_tm_upiu_trace(hba, task_tag, UFS_TM_COMP); 7071 } 7072 7073 spin_lock_irqsave(hba->host->host_lock, flags); 7074 hba->tmf_rqs[req->tag] = NULL; 7075 __clear_bit(task_tag, &hba->outstanding_tasks); 7076 spin_unlock_irqrestore(hba->host->host_lock, flags); 7077 7078 ufshcd_release(hba); 7079 blk_mq_free_request(req); 7080 7081 return err; 7082 } 7083 7084 /** 7085 * ufshcd_issue_tm_cmd - issues task management commands to controller 7086 * @hba: per adapter instance 7087 * @lun_id: LUN ID to which TM command is sent 7088 * @task_id: task ID to which the TM command is applicable 7089 * @tm_function: task management function opcode 7090 * @tm_response: task management service response return value 7091 * 7092 * Return: non-zero value on error, zero on success. 7093 */ 7094 static int ufshcd_issue_tm_cmd(struct ufs_hba *hba, int lun_id, int task_id, 7095 u8 tm_function, u8 *tm_response) 7096 { 7097 struct utp_task_req_desc treq = { }; 7098 enum utp_ocs ocs_value; 7099 int err; 7100 7101 /* Configure task request descriptor */ 7102 treq.header.interrupt = 1; 7103 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7104 7105 /* Configure task request UPIU */ 7106 treq.upiu_req.req_header.transaction_code = UPIU_TRANSACTION_TASK_REQ; 7107 treq.upiu_req.req_header.lun = lun_id; 7108 treq.upiu_req.req_header.tm_function = tm_function; 7109 7110 /* 7111 * The host shall provide the same value for LUN field in the basic 7112 * header and for Input Parameter. 7113 */ 7114 treq.upiu_req.input_param1 = cpu_to_be32(lun_id); 7115 treq.upiu_req.input_param2 = cpu_to_be32(task_id); 7116 7117 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_function); 7118 if (err == -ETIMEDOUT) 7119 return err; 7120 7121 ocs_value = treq.header.ocs & MASK_OCS; 7122 if (ocs_value != OCS_SUCCESS) 7123 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", 7124 __func__, ocs_value); 7125 else if (tm_response) 7126 *tm_response = be32_to_cpu(treq.upiu_rsp.output_param1) & 7127 MASK_TM_SERVICE_RESP; 7128 return err; 7129 } 7130 7131 /** 7132 * ufshcd_issue_devman_upiu_cmd - API for sending "utrd" type requests 7133 * @hba: per-adapter instance 7134 * @req_upiu: upiu request 7135 * @rsp_upiu: upiu reply 7136 * @desc_buff: pointer to descriptor buffer, NULL if NA 7137 * @buff_len: descriptor size, 0 if NA 7138 * @cmd_type: specifies the type (NOP, Query...) 7139 * @desc_op: descriptor operation 7140 * 7141 * Those type of requests uses UTP Transfer Request Descriptor - utrd. 7142 * Therefore, it "rides" the device management infrastructure: uses its tag and 7143 * tasks work queues. 7144 * 7145 * Since there is only one available tag for device management commands, 7146 * the caller is expected to hold the hba->dev_cmd.lock mutex. 7147 * 7148 * Return: 0 upon success; < 0 upon failure. 7149 */ 7150 static int ufshcd_issue_devman_upiu_cmd(struct ufs_hba *hba, 7151 struct utp_upiu_req *req_upiu, 7152 struct utp_upiu_req *rsp_upiu, 7153 u8 *desc_buff, int *buff_len, 7154 enum dev_cmd_type cmd_type, 7155 enum query_opcode desc_op) 7156 { 7157 DECLARE_COMPLETION_ONSTACK(wait); 7158 const u32 tag = hba->reserved_slot; 7159 struct ufshcd_lrb *lrbp; 7160 int err = 0; 7161 u8 upiu_flags; 7162 7163 /* Protects use of hba->reserved_slot. */ 7164 lockdep_assert_held(&hba->dev_cmd.lock); 7165 7166 down_read(&hba->clk_scaling_lock); 7167 7168 lrbp = &hba->lrb[tag]; 7169 lrbp->cmd = NULL; 7170 lrbp->task_tag = tag; 7171 lrbp->lun = 0; 7172 lrbp->intr_cmd = true; 7173 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7174 hba->dev_cmd.type = cmd_type; 7175 7176 if (hba->ufs_version <= ufshci_version(1, 1)) 7177 lrbp->command_type = UTP_CMD_TYPE_DEV_MANAGE; 7178 else 7179 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7180 7181 /* update the task tag in the request upiu */ 7182 req_upiu->header.task_tag = tag; 7183 7184 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, DMA_NONE, 0); 7185 7186 /* just copy the upiu request as it is */ 7187 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7188 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_WRITE_DESC) { 7189 /* The Data Segment Area is optional depending upon the query 7190 * function value. for WRITE DESCRIPTOR, the data segment 7191 * follows right after the tsf. 7192 */ 7193 memcpy(lrbp->ucd_req_ptr + 1, desc_buff, *buff_len); 7194 *buff_len = 0; 7195 } 7196 7197 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7198 7199 hba->dev_cmd.complete = &wait; 7200 7201 ufshcd_add_query_upiu_trace(hba, UFS_QUERY_SEND, lrbp->ucd_req_ptr); 7202 7203 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7204 /* 7205 * ignore the returning value here - ufshcd_check_query_response is 7206 * bound to fail since dev_cmd.query and dev_cmd.type were left empty. 7207 * read the response directly ignoring all errors. 7208 */ 7209 ufshcd_wait_for_dev_cmd(hba, lrbp, QUERY_REQ_TIMEOUT); 7210 7211 /* just copy the upiu response as it is */ 7212 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7213 if (desc_buff && desc_op == UPIU_QUERY_OPCODE_READ_DESC) { 7214 u8 *descp = (u8 *)lrbp->ucd_rsp_ptr + sizeof(*rsp_upiu); 7215 u16 resp_len = be16_to_cpu(lrbp->ucd_rsp_ptr->header 7216 .data_segment_length); 7217 7218 if (*buff_len >= resp_len) { 7219 memcpy(desc_buff, descp, resp_len); 7220 *buff_len = resp_len; 7221 } else { 7222 dev_warn(hba->dev, 7223 "%s: rsp size %d is bigger than buffer size %d", 7224 __func__, resp_len, *buff_len); 7225 *buff_len = 0; 7226 err = -EINVAL; 7227 } 7228 } 7229 ufshcd_add_query_upiu_trace(hba, err ? UFS_QUERY_ERR : UFS_QUERY_COMP, 7230 (struct utp_upiu_req *)lrbp->ucd_rsp_ptr); 7231 7232 up_read(&hba->clk_scaling_lock); 7233 return err; 7234 } 7235 7236 /** 7237 * ufshcd_exec_raw_upiu_cmd - API function for sending raw upiu commands 7238 * @hba: per-adapter instance 7239 * @req_upiu: upiu request 7240 * @rsp_upiu: upiu reply - only 8 DW as we do not support scsi commands 7241 * @msgcode: message code, one of UPIU Transaction Codes Initiator to Target 7242 * @desc_buff: pointer to descriptor buffer, NULL if NA 7243 * @buff_len: descriptor size, 0 if NA 7244 * @desc_op: descriptor operation 7245 * 7246 * Supports UTP Transfer requests (nop and query), and UTP Task 7247 * Management requests. 7248 * It is up to the caller to fill the upiu conent properly, as it will 7249 * be copied without any further input validations. 7250 * 7251 * Return: 0 upon success; < 0 upon failure. 7252 */ 7253 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba, 7254 struct utp_upiu_req *req_upiu, 7255 struct utp_upiu_req *rsp_upiu, 7256 enum upiu_request_transaction msgcode, 7257 u8 *desc_buff, int *buff_len, 7258 enum query_opcode desc_op) 7259 { 7260 int err; 7261 enum dev_cmd_type cmd_type = DEV_CMD_TYPE_QUERY; 7262 struct utp_task_req_desc treq = { }; 7263 enum utp_ocs ocs_value; 7264 u8 tm_f = req_upiu->header.tm_function; 7265 7266 switch (msgcode) { 7267 case UPIU_TRANSACTION_NOP_OUT: 7268 cmd_type = DEV_CMD_TYPE_NOP; 7269 fallthrough; 7270 case UPIU_TRANSACTION_QUERY_REQ: 7271 ufshcd_hold(hba); 7272 mutex_lock(&hba->dev_cmd.lock); 7273 err = ufshcd_issue_devman_upiu_cmd(hba, req_upiu, rsp_upiu, 7274 desc_buff, buff_len, 7275 cmd_type, desc_op); 7276 mutex_unlock(&hba->dev_cmd.lock); 7277 ufshcd_release(hba); 7278 7279 break; 7280 case UPIU_TRANSACTION_TASK_REQ: 7281 treq.header.interrupt = 1; 7282 treq.header.ocs = OCS_INVALID_COMMAND_STATUS; 7283 7284 memcpy(&treq.upiu_req, req_upiu, sizeof(*req_upiu)); 7285 7286 err = __ufshcd_issue_tm_cmd(hba, &treq, tm_f); 7287 if (err == -ETIMEDOUT) 7288 break; 7289 7290 ocs_value = treq.header.ocs & MASK_OCS; 7291 if (ocs_value != OCS_SUCCESS) { 7292 dev_err(hba->dev, "%s: failed, ocs = 0x%x\n", __func__, 7293 ocs_value); 7294 break; 7295 } 7296 7297 memcpy(rsp_upiu, &treq.upiu_rsp, sizeof(*rsp_upiu)); 7298 7299 break; 7300 default: 7301 err = -EINVAL; 7302 7303 break; 7304 } 7305 7306 return err; 7307 } 7308 7309 /** 7310 * ufshcd_advanced_rpmb_req_handler - handle advanced RPMB request 7311 * @hba: per adapter instance 7312 * @req_upiu: upiu request 7313 * @rsp_upiu: upiu reply 7314 * @req_ehs: EHS field which contains Advanced RPMB Request Message 7315 * @rsp_ehs: EHS field which returns Advanced RPMB Response Message 7316 * @sg_cnt: The number of sg lists actually used 7317 * @sg_list: Pointer to SG list when DATA IN/OUT UPIU is required in ARPMB operation 7318 * @dir: DMA direction 7319 * 7320 * Return: zero on success, non-zero on failure. 7321 */ 7322 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu, 7323 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *req_ehs, 7324 struct ufs_ehs *rsp_ehs, int sg_cnt, struct scatterlist *sg_list, 7325 enum dma_data_direction dir) 7326 { 7327 DECLARE_COMPLETION_ONSTACK(wait); 7328 const u32 tag = hba->reserved_slot; 7329 struct ufshcd_lrb *lrbp; 7330 int err = 0; 7331 int result; 7332 u8 upiu_flags; 7333 u8 *ehs_data; 7334 u16 ehs_len; 7335 7336 /* Protects use of hba->reserved_slot. */ 7337 ufshcd_hold(hba); 7338 mutex_lock(&hba->dev_cmd.lock); 7339 down_read(&hba->clk_scaling_lock); 7340 7341 lrbp = &hba->lrb[tag]; 7342 lrbp->cmd = NULL; 7343 lrbp->task_tag = tag; 7344 lrbp->lun = UFS_UPIU_RPMB_WLUN; 7345 7346 lrbp->intr_cmd = true; 7347 ufshcd_prepare_lrbp_crypto(NULL, lrbp); 7348 hba->dev_cmd.type = DEV_CMD_TYPE_RPMB; 7349 7350 /* Advanced RPMB starts from UFS 4.0, so its command type is UTP_CMD_TYPE_UFS_STORAGE */ 7351 lrbp->command_type = UTP_CMD_TYPE_UFS_STORAGE; 7352 7353 /* 7354 * According to UFSHCI 4.0 specification page 24, if EHSLUTRDS is 0, host controller takes 7355 * EHS length from CMD UPIU, and SW driver use EHS Length field in CMD UPIU. if it is 1, 7356 * HW controller takes EHS length from UTRD. 7357 */ 7358 if (hba->capabilities & MASK_EHSLUTRD_SUPPORTED) 7359 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 2); 7360 else 7361 ufshcd_prepare_req_desc_hdr(lrbp, &upiu_flags, dir, 0); 7362 7363 /* update the task tag */ 7364 req_upiu->header.task_tag = tag; 7365 7366 /* copy the UPIU(contains CDB) request as it is */ 7367 memcpy(lrbp->ucd_req_ptr, req_upiu, sizeof(*lrbp->ucd_req_ptr)); 7368 /* Copy EHS, starting with byte32, immediately after the CDB package */ 7369 memcpy(lrbp->ucd_req_ptr + 1, req_ehs, sizeof(*req_ehs)); 7370 7371 if (dir != DMA_NONE && sg_list) 7372 ufshcd_sgl_to_prdt(hba, lrbp, sg_cnt, sg_list); 7373 7374 memset(lrbp->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp)); 7375 7376 hba->dev_cmd.complete = &wait; 7377 7378 ufshcd_send_command(hba, tag, hba->dev_cmd_queue); 7379 7380 err = ufshcd_wait_for_dev_cmd(hba, lrbp, ADVANCED_RPMB_REQ_TIMEOUT); 7381 7382 if (!err) { 7383 /* Just copy the upiu response as it is */ 7384 memcpy(rsp_upiu, lrbp->ucd_rsp_ptr, sizeof(*rsp_upiu)); 7385 /* Get the response UPIU result */ 7386 result = (lrbp->ucd_rsp_ptr->header.response << 8) | 7387 lrbp->ucd_rsp_ptr->header.status; 7388 7389 ehs_len = lrbp->ucd_rsp_ptr->header.ehs_length; 7390 /* 7391 * Since the bLength in EHS indicates the total size of the EHS Header and EHS Data 7392 * in 32 Byte units, the value of the bLength Request/Response for Advanced RPMB 7393 * Message is 02h 7394 */ 7395 if (ehs_len == 2 && rsp_ehs) { 7396 /* 7397 * ucd_rsp_ptr points to a buffer with a length of 512 bytes 7398 * (ALIGNED_UPIU_SIZE = 512), and the EHS data just starts from byte32 7399 */ 7400 ehs_data = (u8 *)lrbp->ucd_rsp_ptr + EHS_OFFSET_IN_RESPONSE; 7401 memcpy(rsp_ehs, ehs_data, ehs_len * 32); 7402 } 7403 } 7404 7405 up_read(&hba->clk_scaling_lock); 7406 mutex_unlock(&hba->dev_cmd.lock); 7407 ufshcd_release(hba); 7408 return err ? : result; 7409 } 7410 7411 /** 7412 * ufshcd_eh_device_reset_handler() - Reset a single logical unit. 7413 * @cmd: SCSI command pointer 7414 * 7415 * Return: SUCCESS or FAILED. 7416 */ 7417 static int ufshcd_eh_device_reset_handler(struct scsi_cmnd *cmd) 7418 { 7419 unsigned long flags, pending_reqs = 0, not_cleared = 0; 7420 struct Scsi_Host *host; 7421 struct ufs_hba *hba; 7422 struct ufs_hw_queue *hwq; 7423 struct ufshcd_lrb *lrbp; 7424 u32 pos, not_cleared_mask = 0; 7425 int err; 7426 u8 resp = 0xF, lun; 7427 7428 host = cmd->device->host; 7429 hba = shost_priv(host); 7430 7431 lun = ufshcd_scsi_to_upiu_lun(cmd->device->lun); 7432 err = ufshcd_issue_tm_cmd(hba, lun, 0, UFS_LOGICAL_RESET, &resp); 7433 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7434 if (!err) 7435 err = resp; 7436 goto out; 7437 } 7438 7439 if (is_mcq_enabled(hba)) { 7440 for (pos = 0; pos < hba->nutrs; pos++) { 7441 lrbp = &hba->lrb[pos]; 7442 if (ufshcd_cmd_inflight(lrbp->cmd) && 7443 lrbp->lun == lun) { 7444 ufshcd_clear_cmd(hba, pos); 7445 hwq = ufshcd_mcq_req_to_hwq(hba, scsi_cmd_to_rq(lrbp->cmd)); 7446 ufshcd_mcq_poll_cqe_lock(hba, hwq); 7447 } 7448 } 7449 err = 0; 7450 goto out; 7451 } 7452 7453 /* clear the commands that were pending for corresponding LUN */ 7454 spin_lock_irqsave(&hba->outstanding_lock, flags); 7455 for_each_set_bit(pos, &hba->outstanding_reqs, hba->nutrs) 7456 if (hba->lrb[pos].lun == lun) 7457 __set_bit(pos, &pending_reqs); 7458 hba->outstanding_reqs &= ~pending_reqs; 7459 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7460 7461 for_each_set_bit(pos, &pending_reqs, hba->nutrs) { 7462 if (ufshcd_clear_cmd(hba, pos) < 0) { 7463 spin_lock_irqsave(&hba->outstanding_lock, flags); 7464 not_cleared = 1U << pos & 7465 ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7466 hba->outstanding_reqs |= not_cleared; 7467 not_cleared_mask |= not_cleared; 7468 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7469 7470 dev_err(hba->dev, "%s: failed to clear request %d\n", 7471 __func__, pos); 7472 } 7473 } 7474 __ufshcd_transfer_req_compl(hba, pending_reqs & ~not_cleared_mask); 7475 7476 out: 7477 hba->req_abort_count = 0; 7478 ufshcd_update_evt_hist(hba, UFS_EVT_DEV_RESET, (u32)err); 7479 if (!err) { 7480 err = SUCCESS; 7481 } else { 7482 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7483 err = FAILED; 7484 } 7485 return err; 7486 } 7487 7488 static void ufshcd_set_req_abort_skip(struct ufs_hba *hba, unsigned long bitmap) 7489 { 7490 struct ufshcd_lrb *lrbp; 7491 int tag; 7492 7493 for_each_set_bit(tag, &bitmap, hba->nutrs) { 7494 lrbp = &hba->lrb[tag]; 7495 lrbp->req_abort_skip = true; 7496 } 7497 } 7498 7499 /** 7500 * ufshcd_try_to_abort_task - abort a specific task 7501 * @hba: Pointer to adapter instance 7502 * @tag: Task tag/index to be aborted 7503 * 7504 * Abort the pending command in device by sending UFS_ABORT_TASK task management 7505 * command, and in host controller by clearing the door-bell register. There can 7506 * be race between controller sending the command to the device while abort is 7507 * issued. To avoid that, first issue UFS_QUERY_TASK to check if the command is 7508 * really issued and then try to abort it. 7509 * 7510 * Return: zero on success, non-zero on failure. 7511 */ 7512 int ufshcd_try_to_abort_task(struct ufs_hba *hba, int tag) 7513 { 7514 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7515 int err = 0; 7516 int poll_cnt; 7517 u8 resp = 0xF; 7518 u32 reg; 7519 7520 for (poll_cnt = 100; poll_cnt; poll_cnt--) { 7521 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7522 UFS_QUERY_TASK, &resp); 7523 if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED) { 7524 /* cmd pending in the device */ 7525 dev_err(hba->dev, "%s: cmd pending in the device. tag = %d\n", 7526 __func__, tag); 7527 break; 7528 } else if (!err && resp == UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7529 /* 7530 * cmd not pending in the device, check if it is 7531 * in transition. 7532 */ 7533 dev_err(hba->dev, "%s: cmd at tag %d not pending in the device.\n", 7534 __func__, tag); 7535 if (is_mcq_enabled(hba)) { 7536 /* MCQ mode */ 7537 if (ufshcd_cmd_inflight(lrbp->cmd)) { 7538 /* sleep for max. 200us same delay as in SDB mode */ 7539 usleep_range(100, 200); 7540 continue; 7541 } 7542 /* command completed already */ 7543 dev_err(hba->dev, "%s: cmd at tag=%d is cleared.\n", 7544 __func__, tag); 7545 goto out; 7546 } 7547 7548 /* Single Doorbell Mode */ 7549 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7550 if (reg & (1 << tag)) { 7551 /* sleep for max. 200us to stabilize */ 7552 usleep_range(100, 200); 7553 continue; 7554 } 7555 /* command completed already */ 7556 dev_err(hba->dev, "%s: cmd at tag %d successfully cleared from DB.\n", 7557 __func__, tag); 7558 goto out; 7559 } else { 7560 dev_err(hba->dev, 7561 "%s: no response from device. tag = %d, err %d\n", 7562 __func__, tag, err); 7563 if (!err) 7564 err = resp; /* service response error */ 7565 goto out; 7566 } 7567 } 7568 7569 if (!poll_cnt) { 7570 err = -EBUSY; 7571 goto out; 7572 } 7573 7574 err = ufshcd_issue_tm_cmd(hba, lrbp->lun, lrbp->task_tag, 7575 UFS_ABORT_TASK, &resp); 7576 if (err || resp != UPIU_TASK_MANAGEMENT_FUNC_COMPL) { 7577 if (!err) { 7578 err = resp; /* service response error */ 7579 dev_err(hba->dev, "%s: issued. tag = %d, err %d\n", 7580 __func__, tag, err); 7581 } 7582 goto out; 7583 } 7584 7585 err = ufshcd_clear_cmd(hba, tag); 7586 if (err) 7587 dev_err(hba->dev, "%s: Failed clearing cmd at tag %d, err %d\n", 7588 __func__, tag, err); 7589 7590 out: 7591 return err; 7592 } 7593 7594 /** 7595 * ufshcd_abort - scsi host template eh_abort_handler callback 7596 * @cmd: SCSI command pointer 7597 * 7598 * Return: SUCCESS or FAILED. 7599 */ 7600 static int ufshcd_abort(struct scsi_cmnd *cmd) 7601 { 7602 struct Scsi_Host *host = cmd->device->host; 7603 struct ufs_hba *hba = shost_priv(host); 7604 int tag = scsi_cmd_to_rq(cmd)->tag; 7605 struct ufshcd_lrb *lrbp = &hba->lrb[tag]; 7606 unsigned long flags; 7607 int err = FAILED; 7608 bool outstanding; 7609 u32 reg; 7610 7611 ufshcd_hold(hba); 7612 7613 if (!is_mcq_enabled(hba)) { 7614 reg = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL); 7615 if (!test_bit(tag, &hba->outstanding_reqs)) { 7616 /* If command is already aborted/completed, return FAILED. */ 7617 dev_err(hba->dev, 7618 "%s: cmd at tag %d already completed, outstanding=0x%lx, doorbell=0x%x\n", 7619 __func__, tag, hba->outstanding_reqs, reg); 7620 goto release; 7621 } 7622 } 7623 7624 /* Print Transfer Request of aborted task */ 7625 dev_info(hba->dev, "%s: Device abort task at tag %d\n", __func__, tag); 7626 7627 /* 7628 * Print detailed info about aborted request. 7629 * As more than one request might get aborted at the same time, 7630 * print full information only for the first aborted request in order 7631 * to reduce repeated printouts. For other aborted requests only print 7632 * basic details. 7633 */ 7634 scsi_print_command(cmd); 7635 if (!hba->req_abort_count) { 7636 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, tag); 7637 ufshcd_print_evt_hist(hba); 7638 ufshcd_print_host_state(hba); 7639 ufshcd_print_pwr_info(hba); 7640 ufshcd_print_tr(hba, tag, true); 7641 } else { 7642 ufshcd_print_tr(hba, tag, false); 7643 } 7644 hba->req_abort_count++; 7645 7646 if (!is_mcq_enabled(hba) && !(reg & (1 << tag))) { 7647 /* only execute this code in single doorbell mode */ 7648 dev_err(hba->dev, 7649 "%s: cmd was completed, but without a notifying intr, tag = %d", 7650 __func__, tag); 7651 __ufshcd_transfer_req_compl(hba, 1UL << tag); 7652 goto release; 7653 } 7654 7655 /* 7656 * Task abort to the device W-LUN is illegal. When this command 7657 * will fail, due to spec violation, scsi err handling next step 7658 * will be to send LU reset which, again, is a spec violation. 7659 * To avoid these unnecessary/illegal steps, first we clean up 7660 * the lrb taken by this cmd and re-set it in outstanding_reqs, 7661 * then queue the eh_work and bail. 7662 */ 7663 if (lrbp->lun == UFS_UPIU_UFS_DEVICE_WLUN) { 7664 ufshcd_update_evt_hist(hba, UFS_EVT_ABORT, lrbp->lun); 7665 7666 spin_lock_irqsave(host->host_lock, flags); 7667 hba->force_reset = true; 7668 ufshcd_schedule_eh_work(hba); 7669 spin_unlock_irqrestore(host->host_lock, flags); 7670 goto release; 7671 } 7672 7673 if (is_mcq_enabled(hba)) { 7674 /* MCQ mode. Branch off to handle abort for mcq mode */ 7675 err = ufshcd_mcq_abort(cmd); 7676 goto release; 7677 } 7678 7679 /* Skip task abort in case previous aborts failed and report failure */ 7680 if (lrbp->req_abort_skip) { 7681 dev_err(hba->dev, "%s: skipping abort\n", __func__); 7682 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7683 goto release; 7684 } 7685 7686 err = ufshcd_try_to_abort_task(hba, tag); 7687 if (err) { 7688 dev_err(hba->dev, "%s: failed with err %d\n", __func__, err); 7689 ufshcd_set_req_abort_skip(hba, hba->outstanding_reqs); 7690 err = FAILED; 7691 goto release; 7692 } 7693 7694 /* 7695 * Clear the corresponding bit from outstanding_reqs since the command 7696 * has been aborted successfully. 7697 */ 7698 spin_lock_irqsave(&hba->outstanding_lock, flags); 7699 outstanding = __test_and_clear_bit(tag, &hba->outstanding_reqs); 7700 spin_unlock_irqrestore(&hba->outstanding_lock, flags); 7701 7702 if (outstanding) 7703 ufshcd_release_scsi_cmd(hba, lrbp); 7704 7705 err = SUCCESS; 7706 7707 release: 7708 /* Matches the ufshcd_hold() call at the start of this function. */ 7709 ufshcd_release(hba); 7710 return err; 7711 } 7712 7713 /** 7714 * ufshcd_host_reset_and_restore - reset and restore host controller 7715 * @hba: per-adapter instance 7716 * 7717 * Note that host controller reset may issue DME_RESET to 7718 * local and remote (device) Uni-Pro stack and the attributes 7719 * are reset to default state. 7720 * 7721 * Return: zero on success, non-zero on failure. 7722 */ 7723 static int ufshcd_host_reset_and_restore(struct ufs_hba *hba) 7724 { 7725 int err; 7726 7727 /* 7728 * Stop the host controller and complete the requests 7729 * cleared by h/w 7730 */ 7731 ufshcd_hba_stop(hba); 7732 hba->silence_err_logs = true; 7733 ufshcd_complete_requests(hba, true); 7734 hba->silence_err_logs = false; 7735 7736 /* scale up clocks to max frequency before full reinitialization */ 7737 ufshcd_scale_clks(hba, ULONG_MAX, true); 7738 7739 err = ufshcd_hba_enable(hba); 7740 7741 /* Establish the link again and restore the device */ 7742 if (!err) 7743 err = ufshcd_probe_hba(hba, false); 7744 7745 if (err) 7746 dev_err(hba->dev, "%s: Host init failed %d\n", __func__, err); 7747 ufshcd_update_evt_hist(hba, UFS_EVT_HOST_RESET, (u32)err); 7748 return err; 7749 } 7750 7751 /** 7752 * ufshcd_reset_and_restore - reset and re-initialize host/device 7753 * @hba: per-adapter instance 7754 * 7755 * Reset and recover device, host and re-establish link. This 7756 * is helpful to recover the communication in fatal error conditions. 7757 * 7758 * Return: zero on success, non-zero on failure. 7759 */ 7760 static int ufshcd_reset_and_restore(struct ufs_hba *hba) 7761 { 7762 u32 saved_err = 0; 7763 u32 saved_uic_err = 0; 7764 int err = 0; 7765 unsigned long flags; 7766 int retries = MAX_HOST_RESET_RETRIES; 7767 7768 spin_lock_irqsave(hba->host->host_lock, flags); 7769 do { 7770 /* 7771 * This is a fresh start, cache and clear saved error first, 7772 * in case new error generated during reset and restore. 7773 */ 7774 saved_err |= hba->saved_err; 7775 saved_uic_err |= hba->saved_uic_err; 7776 hba->saved_err = 0; 7777 hba->saved_uic_err = 0; 7778 hba->force_reset = false; 7779 hba->ufshcd_state = UFSHCD_STATE_RESET; 7780 spin_unlock_irqrestore(hba->host->host_lock, flags); 7781 7782 /* Reset the attached device */ 7783 ufshcd_device_reset(hba); 7784 7785 err = ufshcd_host_reset_and_restore(hba); 7786 7787 spin_lock_irqsave(hba->host->host_lock, flags); 7788 if (err) 7789 continue; 7790 /* Do not exit unless operational or dead */ 7791 if (hba->ufshcd_state != UFSHCD_STATE_OPERATIONAL && 7792 hba->ufshcd_state != UFSHCD_STATE_ERROR && 7793 hba->ufshcd_state != UFSHCD_STATE_EH_SCHEDULED_NON_FATAL) 7794 err = -EAGAIN; 7795 } while (err && --retries); 7796 7797 /* 7798 * Inform scsi mid-layer that we did reset and allow to handle 7799 * Unit Attention properly. 7800 */ 7801 scsi_report_bus_reset(hba->host, 0); 7802 if (err) { 7803 hba->ufshcd_state = UFSHCD_STATE_ERROR; 7804 hba->saved_err |= saved_err; 7805 hba->saved_uic_err |= saved_uic_err; 7806 } 7807 spin_unlock_irqrestore(hba->host->host_lock, flags); 7808 7809 return err; 7810 } 7811 7812 /** 7813 * ufshcd_eh_host_reset_handler - host reset handler registered to scsi layer 7814 * @cmd: SCSI command pointer 7815 * 7816 * Return: SUCCESS or FAILED. 7817 */ 7818 static int ufshcd_eh_host_reset_handler(struct scsi_cmnd *cmd) 7819 { 7820 int err = SUCCESS; 7821 unsigned long flags; 7822 struct ufs_hba *hba; 7823 7824 hba = shost_priv(cmd->device->host); 7825 7826 /* 7827 * If runtime PM sent SSU and got a timeout, scsi_error_handler is 7828 * stuck in this function waiting for flush_work(&hba->eh_work). And 7829 * ufshcd_err_handler(eh_work) is stuck waiting for runtime PM. Do 7830 * ufshcd_link_recovery instead of eh_work to prevent deadlock. 7831 */ 7832 if (hba->pm_op_in_progress) { 7833 if (ufshcd_link_recovery(hba)) 7834 err = FAILED; 7835 7836 return err; 7837 } 7838 7839 spin_lock_irqsave(hba->host->host_lock, flags); 7840 hba->force_reset = true; 7841 ufshcd_schedule_eh_work(hba); 7842 dev_err(hba->dev, "%s: reset in progress - 1\n", __func__); 7843 spin_unlock_irqrestore(hba->host->host_lock, flags); 7844 7845 flush_work(&hba->eh_work); 7846 7847 spin_lock_irqsave(hba->host->host_lock, flags); 7848 if (hba->ufshcd_state == UFSHCD_STATE_ERROR) 7849 err = FAILED; 7850 spin_unlock_irqrestore(hba->host->host_lock, flags); 7851 7852 return err; 7853 } 7854 7855 /** 7856 * ufshcd_get_max_icc_level - calculate the ICC level 7857 * @sup_curr_uA: max. current supported by the regulator 7858 * @start_scan: row at the desc table to start scan from 7859 * @buff: power descriptor buffer 7860 * 7861 * Return: calculated max ICC level for specific regulator. 7862 */ 7863 static u32 ufshcd_get_max_icc_level(int sup_curr_uA, u32 start_scan, 7864 const char *buff) 7865 { 7866 int i; 7867 int curr_uA; 7868 u16 data; 7869 u16 unit; 7870 7871 for (i = start_scan; i >= 0; i--) { 7872 data = get_unaligned_be16(&buff[2 * i]); 7873 unit = (data & ATTR_ICC_LVL_UNIT_MASK) >> 7874 ATTR_ICC_LVL_UNIT_OFFSET; 7875 curr_uA = data & ATTR_ICC_LVL_VALUE_MASK; 7876 switch (unit) { 7877 case UFSHCD_NANO_AMP: 7878 curr_uA = curr_uA / 1000; 7879 break; 7880 case UFSHCD_MILI_AMP: 7881 curr_uA = curr_uA * 1000; 7882 break; 7883 case UFSHCD_AMP: 7884 curr_uA = curr_uA * 1000 * 1000; 7885 break; 7886 case UFSHCD_MICRO_AMP: 7887 default: 7888 break; 7889 } 7890 if (sup_curr_uA >= curr_uA) 7891 break; 7892 } 7893 if (i < 0) { 7894 i = 0; 7895 pr_err("%s: Couldn't find valid icc_level = %d", __func__, i); 7896 } 7897 7898 return (u32)i; 7899 } 7900 7901 /** 7902 * ufshcd_find_max_sup_active_icc_level - calculate the max ICC level 7903 * In case regulators are not initialized we'll return 0 7904 * @hba: per-adapter instance 7905 * @desc_buf: power descriptor buffer to extract ICC levels from. 7906 * 7907 * Return: calculated ICC level. 7908 */ 7909 static u32 ufshcd_find_max_sup_active_icc_level(struct ufs_hba *hba, 7910 const u8 *desc_buf) 7911 { 7912 u32 icc_level = 0; 7913 7914 if (!hba->vreg_info.vcc || !hba->vreg_info.vccq || 7915 !hba->vreg_info.vccq2) { 7916 /* 7917 * Using dev_dbg to avoid messages during runtime PM to avoid 7918 * never-ending cycles of messages written back to storage by 7919 * user space causing runtime resume, causing more messages and 7920 * so on. 7921 */ 7922 dev_dbg(hba->dev, 7923 "%s: Regulator capability was not set, actvIccLevel=%d", 7924 __func__, icc_level); 7925 goto out; 7926 } 7927 7928 if (hba->vreg_info.vcc->max_uA) 7929 icc_level = ufshcd_get_max_icc_level( 7930 hba->vreg_info.vcc->max_uA, 7931 POWER_DESC_MAX_ACTV_ICC_LVLS - 1, 7932 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCC_0]); 7933 7934 if (hba->vreg_info.vccq->max_uA) 7935 icc_level = ufshcd_get_max_icc_level( 7936 hba->vreg_info.vccq->max_uA, 7937 icc_level, 7938 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ_0]); 7939 7940 if (hba->vreg_info.vccq2->max_uA) 7941 icc_level = ufshcd_get_max_icc_level( 7942 hba->vreg_info.vccq2->max_uA, 7943 icc_level, 7944 &desc_buf[PWR_DESC_ACTIVE_LVLS_VCCQ2_0]); 7945 out: 7946 return icc_level; 7947 } 7948 7949 static void ufshcd_set_active_icc_lvl(struct ufs_hba *hba) 7950 { 7951 int ret; 7952 u8 *desc_buf; 7953 u32 icc_level; 7954 7955 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 7956 if (!desc_buf) 7957 return; 7958 7959 ret = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_POWER, 0, 0, 7960 desc_buf, QUERY_DESC_MAX_SIZE); 7961 if (ret) { 7962 dev_err(hba->dev, 7963 "%s: Failed reading power descriptor ret = %d", 7964 __func__, ret); 7965 goto out; 7966 } 7967 7968 icc_level = ufshcd_find_max_sup_active_icc_level(hba, desc_buf); 7969 dev_dbg(hba->dev, "%s: setting icc_level 0x%x", __func__, icc_level); 7970 7971 ret = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 7972 QUERY_ATTR_IDN_ACTIVE_ICC_LVL, 0, 0, &icc_level); 7973 7974 if (ret) 7975 dev_err(hba->dev, 7976 "%s: Failed configuring bActiveICCLevel = %d ret = %d", 7977 __func__, icc_level, ret); 7978 7979 out: 7980 kfree(desc_buf); 7981 } 7982 7983 static inline void ufshcd_blk_pm_runtime_init(struct scsi_device *sdev) 7984 { 7985 scsi_autopm_get_device(sdev); 7986 blk_pm_runtime_init(sdev->request_queue, &sdev->sdev_gendev); 7987 if (sdev->rpm_autosuspend) 7988 pm_runtime_set_autosuspend_delay(&sdev->sdev_gendev, 7989 RPM_AUTOSUSPEND_DELAY_MS); 7990 scsi_autopm_put_device(sdev); 7991 } 7992 7993 /** 7994 * ufshcd_scsi_add_wlus - Adds required W-LUs 7995 * @hba: per-adapter instance 7996 * 7997 * UFS device specification requires the UFS devices to support 4 well known 7998 * logical units: 7999 * "REPORT_LUNS" (address: 01h) 8000 * "UFS Device" (address: 50h) 8001 * "RPMB" (address: 44h) 8002 * "BOOT" (address: 30h) 8003 * UFS device's power management needs to be controlled by "POWER CONDITION" 8004 * field of SSU (START STOP UNIT) command. But this "power condition" field 8005 * will take effect only when its sent to "UFS device" well known logical unit 8006 * hence we require the scsi_device instance to represent this logical unit in 8007 * order for the UFS host driver to send the SSU command for power management. 8008 * 8009 * We also require the scsi_device instance for "RPMB" (Replay Protected Memory 8010 * Block) LU so user space process can control this LU. User space may also 8011 * want to have access to BOOT LU. 8012 * 8013 * This function adds scsi device instances for each of all well known LUs 8014 * (except "REPORT LUNS" LU). 8015 * 8016 * Return: zero on success (all required W-LUs are added successfully), 8017 * non-zero error value on failure (if failed to add any of the required W-LU). 8018 */ 8019 static int ufshcd_scsi_add_wlus(struct ufs_hba *hba) 8020 { 8021 int ret = 0; 8022 struct scsi_device *sdev_boot, *sdev_rpmb; 8023 8024 hba->ufs_device_wlun = __scsi_add_device(hba->host, 0, 0, 8025 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_UFS_DEVICE_WLUN), NULL); 8026 if (IS_ERR(hba->ufs_device_wlun)) { 8027 ret = PTR_ERR(hba->ufs_device_wlun); 8028 hba->ufs_device_wlun = NULL; 8029 goto out; 8030 } 8031 scsi_device_put(hba->ufs_device_wlun); 8032 8033 sdev_rpmb = __scsi_add_device(hba->host, 0, 0, 8034 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_RPMB_WLUN), NULL); 8035 if (IS_ERR(sdev_rpmb)) { 8036 ret = PTR_ERR(sdev_rpmb); 8037 goto remove_ufs_device_wlun; 8038 } 8039 ufshcd_blk_pm_runtime_init(sdev_rpmb); 8040 scsi_device_put(sdev_rpmb); 8041 8042 sdev_boot = __scsi_add_device(hba->host, 0, 0, 8043 ufshcd_upiu_wlun_to_scsi_wlun(UFS_UPIU_BOOT_WLUN), NULL); 8044 if (IS_ERR(sdev_boot)) { 8045 dev_err(hba->dev, "%s: BOOT WLUN not found\n", __func__); 8046 } else { 8047 ufshcd_blk_pm_runtime_init(sdev_boot); 8048 scsi_device_put(sdev_boot); 8049 } 8050 goto out; 8051 8052 remove_ufs_device_wlun: 8053 scsi_remove_device(hba->ufs_device_wlun); 8054 out: 8055 return ret; 8056 } 8057 8058 static void ufshcd_wb_probe(struct ufs_hba *hba, const u8 *desc_buf) 8059 { 8060 struct ufs_dev_info *dev_info = &hba->dev_info; 8061 u8 lun; 8062 u32 d_lu_wb_buf_alloc; 8063 u32 ext_ufs_feature; 8064 8065 if (!ufshcd_is_wb_allowed(hba)) 8066 return; 8067 8068 /* 8069 * Probe WB only for UFS-2.2 and UFS-3.1 (and later) devices or 8070 * UFS devices with quirk UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES 8071 * enabled 8072 */ 8073 if (!(dev_info->wspecversion >= 0x310 || 8074 dev_info->wspecversion == 0x220 || 8075 (hba->dev_quirks & UFS_DEVICE_QUIRK_SUPPORT_EXTENDED_FEATURES))) 8076 goto wb_disabled; 8077 8078 ext_ufs_feature = get_unaligned_be32(desc_buf + 8079 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8080 8081 if (!(ext_ufs_feature & UFS_DEV_WRITE_BOOSTER_SUP)) 8082 goto wb_disabled; 8083 8084 /* 8085 * WB may be supported but not configured while provisioning. The spec 8086 * says, in dedicated wb buffer mode, a max of 1 lun would have wb 8087 * buffer configured. 8088 */ 8089 dev_info->wb_buffer_type = desc_buf[DEVICE_DESC_PARAM_WB_TYPE]; 8090 8091 dev_info->b_presrv_uspc_en = 8092 desc_buf[DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN]; 8093 8094 if (dev_info->wb_buffer_type == WB_BUF_MODE_SHARED) { 8095 if (!get_unaligned_be32(desc_buf + 8096 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS)) 8097 goto wb_disabled; 8098 } else { 8099 for (lun = 0; lun < UFS_UPIU_MAX_WB_LUN_ID; lun++) { 8100 d_lu_wb_buf_alloc = 0; 8101 ufshcd_read_unit_desc_param(hba, 8102 lun, 8103 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS, 8104 (u8 *)&d_lu_wb_buf_alloc, 8105 sizeof(d_lu_wb_buf_alloc)); 8106 if (d_lu_wb_buf_alloc) { 8107 dev_info->wb_dedicated_lu = lun; 8108 break; 8109 } 8110 } 8111 8112 if (!d_lu_wb_buf_alloc) 8113 goto wb_disabled; 8114 } 8115 8116 if (!ufshcd_is_wb_buf_lifetime_available(hba)) 8117 goto wb_disabled; 8118 8119 return; 8120 8121 wb_disabled: 8122 hba->caps &= ~UFSHCD_CAP_WB_EN; 8123 } 8124 8125 static void ufshcd_temp_notif_probe(struct ufs_hba *hba, const u8 *desc_buf) 8126 { 8127 struct ufs_dev_info *dev_info = &hba->dev_info; 8128 u32 ext_ufs_feature; 8129 u8 mask = 0; 8130 8131 if (!(hba->caps & UFSHCD_CAP_TEMP_NOTIF) || dev_info->wspecversion < 0x300) 8132 return; 8133 8134 ext_ufs_feature = get_unaligned_be32(desc_buf + DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8135 8136 if (ext_ufs_feature & UFS_DEV_LOW_TEMP_NOTIF) 8137 mask |= MASK_EE_TOO_LOW_TEMP; 8138 8139 if (ext_ufs_feature & UFS_DEV_HIGH_TEMP_NOTIF) 8140 mask |= MASK_EE_TOO_HIGH_TEMP; 8141 8142 if (mask) { 8143 ufshcd_enable_ee(hba, mask); 8144 ufs_hwmon_probe(hba, mask); 8145 } 8146 } 8147 8148 static void ufshcd_ext_iid_probe(struct ufs_hba *hba, u8 *desc_buf) 8149 { 8150 struct ufs_dev_info *dev_info = &hba->dev_info; 8151 u32 ext_ufs_feature; 8152 u32 ext_iid_en = 0; 8153 int err; 8154 8155 /* Only UFS-4.0 and above may support EXT_IID */ 8156 if (dev_info->wspecversion < 0x400) 8157 goto out; 8158 8159 ext_ufs_feature = get_unaligned_be32(desc_buf + 8160 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP); 8161 if (!(ext_ufs_feature & UFS_DEV_EXT_IID_SUP)) 8162 goto out; 8163 8164 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8165 QUERY_ATTR_IDN_EXT_IID_EN, 0, 0, &ext_iid_en); 8166 if (err) 8167 dev_err(hba->dev, "failed reading bEXTIIDEn. err = %d\n", err); 8168 8169 out: 8170 dev_info->b_ext_iid_en = ext_iid_en; 8171 } 8172 8173 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba, 8174 const struct ufs_dev_quirk *fixups) 8175 { 8176 const struct ufs_dev_quirk *f; 8177 struct ufs_dev_info *dev_info = &hba->dev_info; 8178 8179 if (!fixups) 8180 return; 8181 8182 for (f = fixups; f->quirk; f++) { 8183 if ((f->wmanufacturerid == dev_info->wmanufacturerid || 8184 f->wmanufacturerid == UFS_ANY_VENDOR) && 8185 ((dev_info->model && 8186 STR_PRFX_EQUAL(f->model, dev_info->model)) || 8187 !strcmp(f->model, UFS_ANY_MODEL))) 8188 hba->dev_quirks |= f->quirk; 8189 } 8190 } 8191 EXPORT_SYMBOL_GPL(ufshcd_fixup_dev_quirks); 8192 8193 static void ufs_fixup_device_setup(struct ufs_hba *hba) 8194 { 8195 /* fix by general quirk table */ 8196 ufshcd_fixup_dev_quirks(hba, ufs_fixups); 8197 8198 /* allow vendors to fix quirks */ 8199 ufshcd_vops_fixup_dev_quirks(hba); 8200 } 8201 8202 static int ufs_get_device_desc(struct ufs_hba *hba) 8203 { 8204 int err; 8205 u8 model_index; 8206 u8 *desc_buf; 8207 struct ufs_dev_info *dev_info = &hba->dev_info; 8208 8209 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8210 if (!desc_buf) { 8211 err = -ENOMEM; 8212 goto out; 8213 } 8214 8215 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_DEVICE, 0, 0, desc_buf, 8216 QUERY_DESC_MAX_SIZE); 8217 if (err) { 8218 dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n", 8219 __func__, err); 8220 goto out; 8221 } 8222 8223 /* 8224 * getting vendor (manufacturerID) and Bank Index in big endian 8225 * format 8226 */ 8227 dev_info->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 | 8228 desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1]; 8229 8230 /* getting Specification Version in big endian format */ 8231 dev_info->wspecversion = desc_buf[DEVICE_DESC_PARAM_SPEC_VER] << 8 | 8232 desc_buf[DEVICE_DESC_PARAM_SPEC_VER + 1]; 8233 dev_info->bqueuedepth = desc_buf[DEVICE_DESC_PARAM_Q_DPTH]; 8234 8235 model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME]; 8236 8237 err = ufshcd_read_string_desc(hba, model_index, 8238 &dev_info->model, SD_ASCII_STD); 8239 if (err < 0) { 8240 dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n", 8241 __func__, err); 8242 goto out; 8243 } 8244 8245 hba->luns_avail = desc_buf[DEVICE_DESC_PARAM_NUM_LU] + 8246 desc_buf[DEVICE_DESC_PARAM_NUM_WLU]; 8247 8248 ufs_fixup_device_setup(hba); 8249 8250 ufshcd_wb_probe(hba, desc_buf); 8251 8252 ufshcd_temp_notif_probe(hba, desc_buf); 8253 8254 if (hba->ext_iid_sup) 8255 ufshcd_ext_iid_probe(hba, desc_buf); 8256 8257 /* 8258 * ufshcd_read_string_desc returns size of the string 8259 * reset the error value 8260 */ 8261 err = 0; 8262 8263 out: 8264 kfree(desc_buf); 8265 return err; 8266 } 8267 8268 static void ufs_put_device_desc(struct ufs_hba *hba) 8269 { 8270 struct ufs_dev_info *dev_info = &hba->dev_info; 8271 8272 kfree(dev_info->model); 8273 dev_info->model = NULL; 8274 } 8275 8276 /** 8277 * ufshcd_tune_pa_tactivate - Tunes PA_TActivate of local UniPro 8278 * @hba: per-adapter instance 8279 * 8280 * PA_TActivate parameter can be tuned manually if UniPro version is less than 8281 * 1.61. PA_TActivate needs to be greater than or equal to peerM-PHY's 8282 * RX_MIN_ACTIVATETIME_CAPABILITY attribute. This optimal value can help reduce 8283 * the hibern8 exit latency. 8284 * 8285 * Return: zero on success, non-zero error value on failure. 8286 */ 8287 static int ufshcd_tune_pa_tactivate(struct ufs_hba *hba) 8288 { 8289 int ret = 0; 8290 u32 peer_rx_min_activatetime = 0, tuned_pa_tactivate; 8291 8292 ret = ufshcd_dme_peer_get(hba, 8293 UIC_ARG_MIB_SEL( 8294 RX_MIN_ACTIVATETIME_CAPABILITY, 8295 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8296 &peer_rx_min_activatetime); 8297 if (ret) 8298 goto out; 8299 8300 /* make sure proper unit conversion is applied */ 8301 tuned_pa_tactivate = 8302 ((peer_rx_min_activatetime * RX_MIN_ACTIVATETIME_UNIT_US) 8303 / PA_TACTIVATE_TIME_UNIT_US); 8304 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8305 tuned_pa_tactivate); 8306 8307 out: 8308 return ret; 8309 } 8310 8311 /** 8312 * ufshcd_tune_pa_hibern8time - Tunes PA_Hibern8Time of local UniPro 8313 * @hba: per-adapter instance 8314 * 8315 * PA_Hibern8Time parameter can be tuned manually if UniPro version is less than 8316 * 1.61. PA_Hibern8Time needs to be maximum of local M-PHY's 8317 * TX_HIBERN8TIME_CAPABILITY & peer M-PHY's RX_HIBERN8TIME_CAPABILITY. 8318 * This optimal value can help reduce the hibern8 exit latency. 8319 * 8320 * Return: zero on success, non-zero error value on failure. 8321 */ 8322 static int ufshcd_tune_pa_hibern8time(struct ufs_hba *hba) 8323 { 8324 int ret = 0; 8325 u32 local_tx_hibern8_time_cap = 0, peer_rx_hibern8_time_cap = 0; 8326 u32 max_hibern8_time, tuned_pa_hibern8time; 8327 8328 ret = ufshcd_dme_get(hba, 8329 UIC_ARG_MIB_SEL(TX_HIBERN8TIME_CAPABILITY, 8330 UIC_ARG_MPHY_TX_GEN_SEL_INDEX(0)), 8331 &local_tx_hibern8_time_cap); 8332 if (ret) 8333 goto out; 8334 8335 ret = ufshcd_dme_peer_get(hba, 8336 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAPABILITY, 8337 UIC_ARG_MPHY_RX_GEN_SEL_INDEX(0)), 8338 &peer_rx_hibern8_time_cap); 8339 if (ret) 8340 goto out; 8341 8342 max_hibern8_time = max(local_tx_hibern8_time_cap, 8343 peer_rx_hibern8_time_cap); 8344 /* make sure proper unit conversion is applied */ 8345 tuned_pa_hibern8time = ((max_hibern8_time * HIBERN8TIME_UNIT_US) 8346 / PA_HIBERN8_TIME_UNIT_US); 8347 ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 8348 tuned_pa_hibern8time); 8349 out: 8350 return ret; 8351 } 8352 8353 /** 8354 * ufshcd_quirk_tune_host_pa_tactivate - Ensures that host PA_TACTIVATE is 8355 * less than device PA_TACTIVATE time. 8356 * @hba: per-adapter instance 8357 * 8358 * Some UFS devices require host PA_TACTIVATE to be lower than device 8359 * PA_TACTIVATE, we need to enable UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE quirk 8360 * for such devices. 8361 * 8362 * Return: zero on success, non-zero error value on failure. 8363 */ 8364 static int ufshcd_quirk_tune_host_pa_tactivate(struct ufs_hba *hba) 8365 { 8366 int ret = 0; 8367 u32 granularity, peer_granularity; 8368 u32 pa_tactivate, peer_pa_tactivate; 8369 u32 pa_tactivate_us, peer_pa_tactivate_us; 8370 static const u8 gran_to_us_table[] = {1, 4, 8, 16, 32, 100}; 8371 8372 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8373 &granularity); 8374 if (ret) 8375 goto out; 8376 8377 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 8378 &peer_granularity); 8379 if (ret) 8380 goto out; 8381 8382 if ((granularity < PA_GRANULARITY_MIN_VAL) || 8383 (granularity > PA_GRANULARITY_MAX_VAL)) { 8384 dev_err(hba->dev, "%s: invalid host PA_GRANULARITY %d", 8385 __func__, granularity); 8386 return -EINVAL; 8387 } 8388 8389 if ((peer_granularity < PA_GRANULARITY_MIN_VAL) || 8390 (peer_granularity > PA_GRANULARITY_MAX_VAL)) { 8391 dev_err(hba->dev, "%s: invalid device PA_GRANULARITY %d", 8392 __func__, peer_granularity); 8393 return -EINVAL; 8394 } 8395 8396 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 8397 if (ret) 8398 goto out; 8399 8400 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), 8401 &peer_pa_tactivate); 8402 if (ret) 8403 goto out; 8404 8405 pa_tactivate_us = pa_tactivate * gran_to_us_table[granularity - 1]; 8406 peer_pa_tactivate_us = peer_pa_tactivate * 8407 gran_to_us_table[peer_granularity - 1]; 8408 8409 if (pa_tactivate_us >= peer_pa_tactivate_us) { 8410 u32 new_peer_pa_tactivate; 8411 8412 new_peer_pa_tactivate = pa_tactivate_us / 8413 gran_to_us_table[peer_granularity - 1]; 8414 new_peer_pa_tactivate++; 8415 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 8416 new_peer_pa_tactivate); 8417 } 8418 8419 out: 8420 return ret; 8421 } 8422 8423 static void ufshcd_tune_unipro_params(struct ufs_hba *hba) 8424 { 8425 if (ufshcd_is_unipro_pa_params_tuning_req(hba)) { 8426 ufshcd_tune_pa_tactivate(hba); 8427 ufshcd_tune_pa_hibern8time(hba); 8428 } 8429 8430 ufshcd_vops_apply_dev_quirks(hba); 8431 8432 if (hba->dev_quirks & UFS_DEVICE_QUIRK_PA_TACTIVATE) 8433 /* set 1ms timeout for PA_TACTIVATE */ 8434 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE), 10); 8435 8436 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE) 8437 ufshcd_quirk_tune_host_pa_tactivate(hba); 8438 } 8439 8440 static void ufshcd_clear_dbg_ufs_stats(struct ufs_hba *hba) 8441 { 8442 hba->ufs_stats.hibern8_exit_cnt = 0; 8443 hba->ufs_stats.last_hibern8_exit_tstamp = ktime_set(0, 0); 8444 hba->req_abort_count = 0; 8445 } 8446 8447 static int ufshcd_device_geo_params_init(struct ufs_hba *hba) 8448 { 8449 int err; 8450 u8 *desc_buf; 8451 8452 desc_buf = kzalloc(QUERY_DESC_MAX_SIZE, GFP_KERNEL); 8453 if (!desc_buf) { 8454 err = -ENOMEM; 8455 goto out; 8456 } 8457 8458 err = ufshcd_read_desc_param(hba, QUERY_DESC_IDN_GEOMETRY, 0, 0, 8459 desc_buf, QUERY_DESC_MAX_SIZE); 8460 if (err) { 8461 dev_err(hba->dev, "%s: Failed reading Geometry Desc. err = %d\n", 8462 __func__, err); 8463 goto out; 8464 } 8465 8466 if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 1) 8467 hba->dev_info.max_lu_supported = 32; 8468 else if (desc_buf[GEOMETRY_DESC_PARAM_MAX_NUM_LUN] == 0) 8469 hba->dev_info.max_lu_supported = 8; 8470 8471 out: 8472 kfree(desc_buf); 8473 return err; 8474 } 8475 8476 struct ufs_ref_clk { 8477 unsigned long freq_hz; 8478 enum ufs_ref_clk_freq val; 8479 }; 8480 8481 static const struct ufs_ref_clk ufs_ref_clk_freqs[] = { 8482 {19200000, REF_CLK_FREQ_19_2_MHZ}, 8483 {26000000, REF_CLK_FREQ_26_MHZ}, 8484 {38400000, REF_CLK_FREQ_38_4_MHZ}, 8485 {52000000, REF_CLK_FREQ_52_MHZ}, 8486 {0, REF_CLK_FREQ_INVAL}, 8487 }; 8488 8489 static enum ufs_ref_clk_freq 8490 ufs_get_bref_clk_from_hz(unsigned long freq) 8491 { 8492 int i; 8493 8494 for (i = 0; ufs_ref_clk_freqs[i].freq_hz; i++) 8495 if (ufs_ref_clk_freqs[i].freq_hz == freq) 8496 return ufs_ref_clk_freqs[i].val; 8497 8498 return REF_CLK_FREQ_INVAL; 8499 } 8500 8501 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk) 8502 { 8503 unsigned long freq; 8504 8505 freq = clk_get_rate(refclk); 8506 8507 hba->dev_ref_clk_freq = 8508 ufs_get_bref_clk_from_hz(freq); 8509 8510 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 8511 dev_err(hba->dev, 8512 "invalid ref_clk setting = %ld\n", freq); 8513 } 8514 8515 static int ufshcd_set_dev_ref_clk(struct ufs_hba *hba) 8516 { 8517 int err; 8518 u32 ref_clk; 8519 u32 freq = hba->dev_ref_clk_freq; 8520 8521 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_READ_ATTR, 8522 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &ref_clk); 8523 8524 if (err) { 8525 dev_err(hba->dev, "failed reading bRefClkFreq. err = %d\n", 8526 err); 8527 goto out; 8528 } 8529 8530 if (ref_clk == freq) 8531 goto out; /* nothing to update */ 8532 8533 err = ufshcd_query_attr_retry(hba, UPIU_QUERY_OPCODE_WRITE_ATTR, 8534 QUERY_ATTR_IDN_REF_CLK_FREQ, 0, 0, &freq); 8535 8536 if (err) { 8537 dev_err(hba->dev, "bRefClkFreq setting to %lu Hz failed\n", 8538 ufs_ref_clk_freqs[freq].freq_hz); 8539 goto out; 8540 } 8541 8542 dev_dbg(hba->dev, "bRefClkFreq setting to %lu Hz succeeded\n", 8543 ufs_ref_clk_freqs[freq].freq_hz); 8544 8545 out: 8546 return err; 8547 } 8548 8549 static int ufshcd_device_params_init(struct ufs_hba *hba) 8550 { 8551 bool flag; 8552 int ret; 8553 8554 /* Init UFS geometry descriptor related parameters */ 8555 ret = ufshcd_device_geo_params_init(hba); 8556 if (ret) 8557 goto out; 8558 8559 /* Check and apply UFS device quirks */ 8560 ret = ufs_get_device_desc(hba); 8561 if (ret) { 8562 dev_err(hba->dev, "%s: Failed getting device info. err = %d\n", 8563 __func__, ret); 8564 goto out; 8565 } 8566 8567 ufshcd_get_ref_clk_gating_wait(hba); 8568 8569 if (!ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG, 8570 QUERY_FLAG_IDN_PWR_ON_WPE, 0, &flag)) 8571 hba->dev_info.f_power_on_wp_en = flag; 8572 8573 /* Probe maximum power mode co-supported by both UFS host and device */ 8574 if (ufshcd_get_max_pwr_mode(hba)) 8575 dev_err(hba->dev, 8576 "%s: Failed getting max supported power mode\n", 8577 __func__); 8578 out: 8579 return ret; 8580 } 8581 8582 static void ufshcd_set_timestamp_attr(struct ufs_hba *hba) 8583 { 8584 int err; 8585 struct ufs_query_req *request = NULL; 8586 struct ufs_query_res *response = NULL; 8587 struct ufs_dev_info *dev_info = &hba->dev_info; 8588 struct utp_upiu_query_v4_0 *upiu_data; 8589 8590 if (dev_info->wspecversion < 0x400) 8591 return; 8592 8593 ufshcd_hold(hba); 8594 8595 mutex_lock(&hba->dev_cmd.lock); 8596 8597 ufshcd_init_query(hba, &request, &response, 8598 UPIU_QUERY_OPCODE_WRITE_ATTR, 8599 QUERY_ATTR_IDN_TIMESTAMP, 0, 0); 8600 8601 request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST; 8602 8603 upiu_data = (struct utp_upiu_query_v4_0 *)&request->upiu_req; 8604 8605 put_unaligned_be64(ktime_get_real_ns(), &upiu_data->osf3); 8606 8607 err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT); 8608 8609 if (err) 8610 dev_err(hba->dev, "%s: failed to set timestamp %d\n", 8611 __func__, err); 8612 8613 mutex_unlock(&hba->dev_cmd.lock); 8614 ufshcd_release(hba); 8615 } 8616 8617 /** 8618 * ufshcd_add_lus - probe and add UFS logical units 8619 * @hba: per-adapter instance 8620 * 8621 * Return: 0 upon success; < 0 upon failure. 8622 */ 8623 static int ufshcd_add_lus(struct ufs_hba *hba) 8624 { 8625 int ret; 8626 8627 /* Add required well known logical units to scsi mid layer */ 8628 ret = ufshcd_scsi_add_wlus(hba); 8629 if (ret) 8630 goto out; 8631 8632 /* Initialize devfreq after UFS device is detected */ 8633 if (ufshcd_is_clkscaling_supported(hba)) { 8634 memcpy(&hba->clk_scaling.saved_pwr_info, 8635 &hba->pwr_info, 8636 sizeof(struct ufs_pa_layer_attr)); 8637 hba->clk_scaling.is_allowed = true; 8638 8639 ret = ufshcd_devfreq_init(hba); 8640 if (ret) 8641 goto out; 8642 8643 hba->clk_scaling.is_enabled = true; 8644 ufshcd_init_clk_scaling_sysfs(hba); 8645 } 8646 8647 ufs_bsg_probe(hba); 8648 scsi_scan_host(hba->host); 8649 pm_runtime_put_sync(hba->dev); 8650 8651 out: 8652 return ret; 8653 } 8654 8655 /* SDB - Single Doorbell */ 8656 static void ufshcd_release_sdb_queue(struct ufs_hba *hba, int nutrs) 8657 { 8658 size_t ucdl_size, utrdl_size; 8659 8660 ucdl_size = ufshcd_get_ucd_size(hba) * nutrs; 8661 dmam_free_coherent(hba->dev, ucdl_size, hba->ucdl_base_addr, 8662 hba->ucdl_dma_addr); 8663 8664 utrdl_size = sizeof(struct utp_transfer_req_desc) * nutrs; 8665 dmam_free_coherent(hba->dev, utrdl_size, hba->utrdl_base_addr, 8666 hba->utrdl_dma_addr); 8667 8668 devm_kfree(hba->dev, hba->lrb); 8669 } 8670 8671 static int ufshcd_alloc_mcq(struct ufs_hba *hba) 8672 { 8673 int ret; 8674 int old_nutrs = hba->nutrs; 8675 8676 ret = ufshcd_mcq_decide_queue_depth(hba); 8677 if (ret < 0) 8678 return ret; 8679 8680 hba->nutrs = ret; 8681 ret = ufshcd_mcq_init(hba); 8682 if (ret) 8683 goto err; 8684 8685 /* 8686 * Previously allocated memory for nutrs may not be enough in MCQ mode. 8687 * Number of supported tags in MCQ mode may be larger than SDB mode. 8688 */ 8689 if (hba->nutrs != old_nutrs) { 8690 ufshcd_release_sdb_queue(hba, old_nutrs); 8691 ret = ufshcd_memory_alloc(hba); 8692 if (ret) 8693 goto err; 8694 ufshcd_host_memory_configure(hba); 8695 } 8696 8697 ret = ufshcd_mcq_memory_alloc(hba); 8698 if (ret) 8699 goto err; 8700 8701 return 0; 8702 err: 8703 hba->nutrs = old_nutrs; 8704 return ret; 8705 } 8706 8707 static void ufshcd_config_mcq(struct ufs_hba *hba) 8708 { 8709 int ret; 8710 u32 intrs; 8711 8712 ret = ufshcd_mcq_vops_config_esi(hba); 8713 dev_info(hba->dev, "ESI %sconfigured\n", ret ? "is not " : ""); 8714 8715 intrs = UFSHCD_ENABLE_MCQ_INTRS; 8716 if (hba->quirks & UFSHCD_QUIRK_MCQ_BROKEN_INTR) 8717 intrs &= ~MCQ_CQ_EVENT_STATUS; 8718 ufshcd_enable_intr(hba, intrs); 8719 ufshcd_mcq_make_queues_operational(hba); 8720 ufshcd_mcq_config_mac(hba, hba->nutrs); 8721 8722 hba->host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 8723 hba->reserved_slot = hba->nutrs - UFSHCD_NUM_RESERVED; 8724 8725 /* Select MCQ mode */ 8726 ufshcd_writel(hba, ufshcd_readl(hba, REG_UFS_MEM_CFG) | 0x1, 8727 REG_UFS_MEM_CFG); 8728 hba->mcq_enabled = true; 8729 8730 dev_info(hba->dev, "MCQ configured, nr_queues=%d, io_queues=%d, read_queue=%d, poll_queues=%d, queue_depth=%d\n", 8731 hba->nr_hw_queues, hba->nr_queues[HCTX_TYPE_DEFAULT], 8732 hba->nr_queues[HCTX_TYPE_READ], hba->nr_queues[HCTX_TYPE_POLL], 8733 hba->nutrs); 8734 } 8735 8736 static int ufshcd_device_init(struct ufs_hba *hba, bool init_dev_params) 8737 { 8738 int ret; 8739 struct Scsi_Host *host = hba->host; 8740 8741 hba->ufshcd_state = UFSHCD_STATE_RESET; 8742 8743 ret = ufshcd_link_startup(hba); 8744 if (ret) 8745 return ret; 8746 8747 if (hba->quirks & UFSHCD_QUIRK_SKIP_PH_CONFIGURATION) 8748 return ret; 8749 8750 /* Debug counters initialization */ 8751 ufshcd_clear_dbg_ufs_stats(hba); 8752 8753 /* UniPro link is active now */ 8754 ufshcd_set_link_active(hba); 8755 8756 /* Reconfigure MCQ upon reset */ 8757 if (is_mcq_enabled(hba) && !init_dev_params) 8758 ufshcd_config_mcq(hba); 8759 8760 /* Verify device initialization by sending NOP OUT UPIU */ 8761 ret = ufshcd_verify_dev_init(hba); 8762 if (ret) 8763 return ret; 8764 8765 /* Initiate UFS initialization, and waiting until completion */ 8766 ret = ufshcd_complete_dev_init(hba); 8767 if (ret) 8768 return ret; 8769 8770 /* 8771 * Initialize UFS device parameters used by driver, these 8772 * parameters are associated with UFS descriptors. 8773 */ 8774 if (init_dev_params) { 8775 ret = ufshcd_device_params_init(hba); 8776 if (ret) 8777 return ret; 8778 if (is_mcq_supported(hba) && !hba->scsi_host_added) { 8779 ret = ufshcd_alloc_mcq(hba); 8780 if (!ret) { 8781 ufshcd_config_mcq(hba); 8782 } else { 8783 /* Continue with SDB mode */ 8784 use_mcq_mode = false; 8785 dev_err(hba->dev, "MCQ mode is disabled, err=%d\n", 8786 ret); 8787 } 8788 ret = scsi_add_host(host, hba->dev); 8789 if (ret) { 8790 dev_err(hba->dev, "scsi_add_host failed\n"); 8791 return ret; 8792 } 8793 hba->scsi_host_added = true; 8794 } else if (is_mcq_supported(hba)) { 8795 /* UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH is set */ 8796 ufshcd_config_mcq(hba); 8797 } 8798 } 8799 8800 ufshcd_tune_unipro_params(hba); 8801 8802 /* UFS device is also active now */ 8803 ufshcd_set_ufs_dev_active(hba); 8804 ufshcd_force_reset_auto_bkops(hba); 8805 8806 ufshcd_set_timestamp_attr(hba); 8807 8808 /* Gear up to HS gear if supported */ 8809 if (hba->max_pwr_info.is_valid) { 8810 /* 8811 * Set the right value to bRefClkFreq before attempting to 8812 * switch to HS gears. 8813 */ 8814 if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL) 8815 ufshcd_set_dev_ref_clk(hba); 8816 ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info); 8817 if (ret) { 8818 dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n", 8819 __func__, ret); 8820 return ret; 8821 } 8822 } 8823 8824 return 0; 8825 } 8826 8827 /** 8828 * ufshcd_probe_hba - probe hba to detect device and initialize it 8829 * @hba: per-adapter instance 8830 * @init_dev_params: whether or not to call ufshcd_device_params_init(). 8831 * 8832 * Execute link-startup and verify device initialization 8833 * 8834 * Return: 0 upon success; < 0 upon failure. 8835 */ 8836 static int ufshcd_probe_hba(struct ufs_hba *hba, bool init_dev_params) 8837 { 8838 ktime_t start = ktime_get(); 8839 unsigned long flags; 8840 int ret; 8841 8842 ret = ufshcd_device_init(hba, init_dev_params); 8843 if (ret) 8844 goto out; 8845 8846 if (!hba->pm_op_in_progress && 8847 (hba->quirks & UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH)) { 8848 /* Reset the device and controller before doing reinit */ 8849 ufshcd_device_reset(hba); 8850 ufshcd_hba_stop(hba); 8851 ufshcd_vops_reinit_notify(hba); 8852 ret = ufshcd_hba_enable(hba); 8853 if (ret) { 8854 dev_err(hba->dev, "Host controller enable failed\n"); 8855 ufshcd_print_evt_hist(hba); 8856 ufshcd_print_host_state(hba); 8857 goto out; 8858 } 8859 8860 /* Reinit the device */ 8861 ret = ufshcd_device_init(hba, init_dev_params); 8862 if (ret) 8863 goto out; 8864 } 8865 8866 ufshcd_print_pwr_info(hba); 8867 8868 /* 8869 * bActiveICCLevel is volatile for UFS device (as per latest v2.1 spec) 8870 * and for removable UFS card as well, hence always set the parameter. 8871 * Note: Error handler may issue the device reset hence resetting 8872 * bActiveICCLevel as well so it is always safe to set this here. 8873 */ 8874 ufshcd_set_active_icc_lvl(hba); 8875 8876 /* Enable UFS Write Booster if supported */ 8877 ufshcd_configure_wb(hba); 8878 8879 if (hba->ee_usr_mask) 8880 ufshcd_write_ee_control(hba); 8881 /* Enable Auto-Hibernate if configured */ 8882 ufshcd_auto_hibern8_enable(hba); 8883 8884 out: 8885 spin_lock_irqsave(hba->host->host_lock, flags); 8886 if (ret) 8887 hba->ufshcd_state = UFSHCD_STATE_ERROR; 8888 else if (hba->ufshcd_state == UFSHCD_STATE_RESET) 8889 hba->ufshcd_state = UFSHCD_STATE_OPERATIONAL; 8890 spin_unlock_irqrestore(hba->host->host_lock, flags); 8891 8892 trace_ufshcd_init(dev_name(hba->dev), ret, 8893 ktime_to_us(ktime_sub(ktime_get(), start)), 8894 hba->curr_dev_pwr_mode, hba->uic_link_state); 8895 return ret; 8896 } 8897 8898 /** 8899 * ufshcd_async_scan - asynchronous execution for probing hba 8900 * @data: data pointer to pass to this function 8901 * @cookie: cookie data 8902 */ 8903 static void ufshcd_async_scan(void *data, async_cookie_t cookie) 8904 { 8905 struct ufs_hba *hba = (struct ufs_hba *)data; 8906 int ret; 8907 8908 down(&hba->host_sem); 8909 /* Initialize hba, detect and initialize UFS device */ 8910 ret = ufshcd_probe_hba(hba, true); 8911 up(&hba->host_sem); 8912 if (ret) 8913 goto out; 8914 8915 /* Probe and add UFS logical units */ 8916 ret = ufshcd_add_lus(hba); 8917 out: 8918 /* 8919 * If we failed to initialize the device or the device is not 8920 * present, turn off the power/clocks etc. 8921 */ 8922 if (ret) { 8923 pm_runtime_put_sync(hba->dev); 8924 ufshcd_hba_exit(hba); 8925 } 8926 } 8927 8928 static enum scsi_timeout_action ufshcd_eh_timed_out(struct scsi_cmnd *scmd) 8929 { 8930 struct ufs_hba *hba = shost_priv(scmd->device->host); 8931 8932 if (!hba->system_suspending) { 8933 /* Activate the error handler in the SCSI core. */ 8934 return SCSI_EH_NOT_HANDLED; 8935 } 8936 8937 /* 8938 * If we get here we know that no TMFs are outstanding and also that 8939 * the only pending command is a START STOP UNIT command. Handle the 8940 * timeout of that command directly to prevent a deadlock between 8941 * ufshcd_set_dev_pwr_mode() and ufshcd_err_handler(). 8942 */ 8943 ufshcd_link_recovery(hba); 8944 dev_info(hba->dev, "%s() finished; outstanding_tasks = %#lx.\n", 8945 __func__, hba->outstanding_tasks); 8946 8947 return hba->outstanding_reqs ? SCSI_EH_RESET_TIMER : SCSI_EH_DONE; 8948 } 8949 8950 static const struct attribute_group *ufshcd_driver_groups[] = { 8951 &ufs_sysfs_unit_descriptor_group, 8952 &ufs_sysfs_lun_attributes_group, 8953 NULL, 8954 }; 8955 8956 static struct ufs_hba_variant_params ufs_hba_vps = { 8957 .hba_enable_delay_us = 1000, 8958 .wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(40), 8959 .devfreq_profile.polling_ms = 100, 8960 .devfreq_profile.target = ufshcd_devfreq_target, 8961 .devfreq_profile.get_dev_status = ufshcd_devfreq_get_dev_status, 8962 .ondemand_data.upthreshold = 70, 8963 .ondemand_data.downdifferential = 5, 8964 }; 8965 8966 static const struct scsi_host_template ufshcd_driver_template = { 8967 .module = THIS_MODULE, 8968 .name = UFSHCD, 8969 .proc_name = UFSHCD, 8970 .map_queues = ufshcd_map_queues, 8971 .queuecommand = ufshcd_queuecommand, 8972 .mq_poll = ufshcd_poll, 8973 .slave_alloc = ufshcd_slave_alloc, 8974 .slave_configure = ufshcd_slave_configure, 8975 .slave_destroy = ufshcd_slave_destroy, 8976 .change_queue_depth = ufshcd_change_queue_depth, 8977 .eh_abort_handler = ufshcd_abort, 8978 .eh_device_reset_handler = ufshcd_eh_device_reset_handler, 8979 .eh_host_reset_handler = ufshcd_eh_host_reset_handler, 8980 .eh_timed_out = ufshcd_eh_timed_out, 8981 .this_id = -1, 8982 .sg_tablesize = SG_ALL, 8983 .cmd_per_lun = UFSHCD_CMD_PER_LUN, 8984 .can_queue = UFSHCD_CAN_QUEUE, 8985 .max_segment_size = PRDT_DATA_BYTE_COUNT_MAX, 8986 .max_sectors = SZ_1M / SECTOR_SIZE, 8987 .max_host_blocked = 1, 8988 .track_queue_depth = 1, 8989 .skip_settle_delay = 1, 8990 .sdev_groups = ufshcd_driver_groups, 8991 .rpm_autosuspend_delay = RPM_AUTOSUSPEND_DELAY_MS, 8992 }; 8993 8994 static int ufshcd_config_vreg_load(struct device *dev, struct ufs_vreg *vreg, 8995 int ua) 8996 { 8997 int ret; 8998 8999 if (!vreg) 9000 return 0; 9001 9002 /* 9003 * "set_load" operation shall be required on those regulators 9004 * which specifically configured current limitation. Otherwise 9005 * zero max_uA may cause unexpected behavior when regulator is 9006 * enabled or set as high power mode. 9007 */ 9008 if (!vreg->max_uA) 9009 return 0; 9010 9011 ret = regulator_set_load(vreg->reg, ua); 9012 if (ret < 0) { 9013 dev_err(dev, "%s: %s set load (ua=%d) failed, err=%d\n", 9014 __func__, vreg->name, ua, ret); 9015 } 9016 9017 return ret; 9018 } 9019 9020 static inline int ufshcd_config_vreg_lpm(struct ufs_hba *hba, 9021 struct ufs_vreg *vreg) 9022 { 9023 return ufshcd_config_vreg_load(hba->dev, vreg, UFS_VREG_LPM_LOAD_UA); 9024 } 9025 9026 static inline int ufshcd_config_vreg_hpm(struct ufs_hba *hba, 9027 struct ufs_vreg *vreg) 9028 { 9029 if (!vreg) 9030 return 0; 9031 9032 return ufshcd_config_vreg_load(hba->dev, vreg, vreg->max_uA); 9033 } 9034 9035 static int ufshcd_config_vreg(struct device *dev, 9036 struct ufs_vreg *vreg, bool on) 9037 { 9038 if (regulator_count_voltages(vreg->reg) <= 0) 9039 return 0; 9040 9041 return ufshcd_config_vreg_load(dev, vreg, on ? vreg->max_uA : 0); 9042 } 9043 9044 static int ufshcd_enable_vreg(struct device *dev, struct ufs_vreg *vreg) 9045 { 9046 int ret = 0; 9047 9048 if (!vreg || vreg->enabled) 9049 goto out; 9050 9051 ret = ufshcd_config_vreg(dev, vreg, true); 9052 if (!ret) 9053 ret = regulator_enable(vreg->reg); 9054 9055 if (!ret) 9056 vreg->enabled = true; 9057 else 9058 dev_err(dev, "%s: %s enable failed, err=%d\n", 9059 __func__, vreg->name, ret); 9060 out: 9061 return ret; 9062 } 9063 9064 static int ufshcd_disable_vreg(struct device *dev, struct ufs_vreg *vreg) 9065 { 9066 int ret = 0; 9067 9068 if (!vreg || !vreg->enabled || vreg->always_on) 9069 goto out; 9070 9071 ret = regulator_disable(vreg->reg); 9072 9073 if (!ret) { 9074 /* ignore errors on applying disable config */ 9075 ufshcd_config_vreg(dev, vreg, false); 9076 vreg->enabled = false; 9077 } else { 9078 dev_err(dev, "%s: %s disable failed, err=%d\n", 9079 __func__, vreg->name, ret); 9080 } 9081 out: 9082 return ret; 9083 } 9084 9085 static int ufshcd_setup_vreg(struct ufs_hba *hba, bool on) 9086 { 9087 int ret = 0; 9088 struct device *dev = hba->dev; 9089 struct ufs_vreg_info *info = &hba->vreg_info; 9090 9091 ret = ufshcd_toggle_vreg(dev, info->vcc, on); 9092 if (ret) 9093 goto out; 9094 9095 ret = ufshcd_toggle_vreg(dev, info->vccq, on); 9096 if (ret) 9097 goto out; 9098 9099 ret = ufshcd_toggle_vreg(dev, info->vccq2, on); 9100 9101 out: 9102 if (ret) { 9103 ufshcd_toggle_vreg(dev, info->vccq2, false); 9104 ufshcd_toggle_vreg(dev, info->vccq, false); 9105 ufshcd_toggle_vreg(dev, info->vcc, false); 9106 } 9107 return ret; 9108 } 9109 9110 static int ufshcd_setup_hba_vreg(struct ufs_hba *hba, bool on) 9111 { 9112 struct ufs_vreg_info *info = &hba->vreg_info; 9113 9114 return ufshcd_toggle_vreg(hba->dev, info->vdd_hba, on); 9115 } 9116 9117 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg) 9118 { 9119 int ret = 0; 9120 9121 if (!vreg) 9122 goto out; 9123 9124 vreg->reg = devm_regulator_get(dev, vreg->name); 9125 if (IS_ERR(vreg->reg)) { 9126 ret = PTR_ERR(vreg->reg); 9127 dev_err(dev, "%s: %s get failed, err=%d\n", 9128 __func__, vreg->name, ret); 9129 } 9130 out: 9131 return ret; 9132 } 9133 EXPORT_SYMBOL_GPL(ufshcd_get_vreg); 9134 9135 static int ufshcd_init_vreg(struct ufs_hba *hba) 9136 { 9137 int ret = 0; 9138 struct device *dev = hba->dev; 9139 struct ufs_vreg_info *info = &hba->vreg_info; 9140 9141 ret = ufshcd_get_vreg(dev, info->vcc); 9142 if (ret) 9143 goto out; 9144 9145 ret = ufshcd_get_vreg(dev, info->vccq); 9146 if (!ret) 9147 ret = ufshcd_get_vreg(dev, info->vccq2); 9148 out: 9149 return ret; 9150 } 9151 9152 static int ufshcd_init_hba_vreg(struct ufs_hba *hba) 9153 { 9154 struct ufs_vreg_info *info = &hba->vreg_info; 9155 9156 return ufshcd_get_vreg(hba->dev, info->vdd_hba); 9157 } 9158 9159 static int ufshcd_setup_clocks(struct ufs_hba *hba, bool on) 9160 { 9161 int ret = 0; 9162 struct ufs_clk_info *clki; 9163 struct list_head *head = &hba->clk_list_head; 9164 unsigned long flags; 9165 ktime_t start = ktime_get(); 9166 bool clk_state_changed = false; 9167 9168 if (list_empty(head)) 9169 goto out; 9170 9171 ret = ufshcd_vops_setup_clocks(hba, on, PRE_CHANGE); 9172 if (ret) 9173 return ret; 9174 9175 list_for_each_entry(clki, head, list) { 9176 if (!IS_ERR_OR_NULL(clki->clk)) { 9177 /* 9178 * Don't disable clocks which are needed 9179 * to keep the link active. 9180 */ 9181 if (ufshcd_is_link_active(hba) && 9182 clki->keep_link_active) 9183 continue; 9184 9185 clk_state_changed = on ^ clki->enabled; 9186 if (on && !clki->enabled) { 9187 ret = clk_prepare_enable(clki->clk); 9188 if (ret) { 9189 dev_err(hba->dev, "%s: %s prepare enable failed, %d\n", 9190 __func__, clki->name, ret); 9191 goto out; 9192 } 9193 } else if (!on && clki->enabled) { 9194 clk_disable_unprepare(clki->clk); 9195 } 9196 clki->enabled = on; 9197 dev_dbg(hba->dev, "%s: clk: %s %sabled\n", __func__, 9198 clki->name, on ? "en" : "dis"); 9199 } 9200 } 9201 9202 ret = ufshcd_vops_setup_clocks(hba, on, POST_CHANGE); 9203 if (ret) 9204 return ret; 9205 9206 out: 9207 if (ret) { 9208 list_for_each_entry(clki, head, list) { 9209 if (!IS_ERR_OR_NULL(clki->clk) && clki->enabled) 9210 clk_disable_unprepare(clki->clk); 9211 } 9212 } else if (!ret && on) { 9213 spin_lock_irqsave(hba->host->host_lock, flags); 9214 hba->clk_gating.state = CLKS_ON; 9215 trace_ufshcd_clk_gating(dev_name(hba->dev), 9216 hba->clk_gating.state); 9217 spin_unlock_irqrestore(hba->host->host_lock, flags); 9218 } 9219 9220 if (clk_state_changed) 9221 trace_ufshcd_profile_clk_gating(dev_name(hba->dev), 9222 (on ? "on" : "off"), 9223 ktime_to_us(ktime_sub(ktime_get(), start)), ret); 9224 return ret; 9225 } 9226 9227 static enum ufs_ref_clk_freq ufshcd_parse_ref_clk_property(struct ufs_hba *hba) 9228 { 9229 u32 freq; 9230 int ret = device_property_read_u32(hba->dev, "ref-clk-freq", &freq); 9231 9232 if (ret) { 9233 dev_dbg(hba->dev, "Cannot query 'ref-clk-freq' property = %d", ret); 9234 return REF_CLK_FREQ_INVAL; 9235 } 9236 9237 return ufs_get_bref_clk_from_hz(freq); 9238 } 9239 9240 static int ufshcd_init_clocks(struct ufs_hba *hba) 9241 { 9242 int ret = 0; 9243 struct ufs_clk_info *clki; 9244 struct device *dev = hba->dev; 9245 struct list_head *head = &hba->clk_list_head; 9246 9247 if (list_empty(head)) 9248 goto out; 9249 9250 list_for_each_entry(clki, head, list) { 9251 if (!clki->name) 9252 continue; 9253 9254 clki->clk = devm_clk_get(dev, clki->name); 9255 if (IS_ERR(clki->clk)) { 9256 ret = PTR_ERR(clki->clk); 9257 dev_err(dev, "%s: %s clk get failed, %d\n", 9258 __func__, clki->name, ret); 9259 goto out; 9260 } 9261 9262 /* 9263 * Parse device ref clk freq as per device tree "ref_clk". 9264 * Default dev_ref_clk_freq is set to REF_CLK_FREQ_INVAL 9265 * in ufshcd_alloc_host(). 9266 */ 9267 if (!strcmp(clki->name, "ref_clk")) 9268 ufshcd_parse_dev_ref_clk_freq(hba, clki->clk); 9269 9270 if (clki->max_freq) { 9271 ret = clk_set_rate(clki->clk, clki->max_freq); 9272 if (ret) { 9273 dev_err(hba->dev, "%s: %s clk set rate(%dHz) failed, %d\n", 9274 __func__, clki->name, 9275 clki->max_freq, ret); 9276 goto out; 9277 } 9278 clki->curr_freq = clki->max_freq; 9279 } 9280 dev_dbg(dev, "%s: clk: %s, rate: %lu\n", __func__, 9281 clki->name, clk_get_rate(clki->clk)); 9282 } 9283 9284 /* Set Max. frequency for all clocks */ 9285 if (hba->use_pm_opp) { 9286 ret = ufshcd_opp_set_rate(hba, ULONG_MAX); 9287 if (ret) { 9288 dev_err(hba->dev, "%s: failed to set OPP: %d", __func__, 9289 ret); 9290 goto out; 9291 } 9292 } 9293 9294 out: 9295 return ret; 9296 } 9297 9298 static int ufshcd_variant_hba_init(struct ufs_hba *hba) 9299 { 9300 int err = 0; 9301 9302 if (!hba->vops) 9303 goto out; 9304 9305 err = ufshcd_vops_init(hba); 9306 if (err) 9307 dev_err_probe(hba->dev, err, 9308 "%s: variant %s init failed with err %d\n", 9309 __func__, ufshcd_get_var_name(hba), err); 9310 out: 9311 return err; 9312 } 9313 9314 static void ufshcd_variant_hba_exit(struct ufs_hba *hba) 9315 { 9316 if (!hba->vops) 9317 return; 9318 9319 ufshcd_vops_exit(hba); 9320 } 9321 9322 static int ufshcd_hba_init(struct ufs_hba *hba) 9323 { 9324 int err; 9325 9326 /* 9327 * Handle host controller power separately from the UFS device power 9328 * rails as it will help controlling the UFS host controller power 9329 * collapse easily which is different than UFS device power collapse. 9330 * Also, enable the host controller power before we go ahead with rest 9331 * of the initialization here. 9332 */ 9333 err = ufshcd_init_hba_vreg(hba); 9334 if (err) 9335 goto out; 9336 9337 err = ufshcd_setup_hba_vreg(hba, true); 9338 if (err) 9339 goto out; 9340 9341 err = ufshcd_init_clocks(hba); 9342 if (err) 9343 goto out_disable_hba_vreg; 9344 9345 if (hba->dev_ref_clk_freq == REF_CLK_FREQ_INVAL) 9346 hba->dev_ref_clk_freq = ufshcd_parse_ref_clk_property(hba); 9347 9348 err = ufshcd_setup_clocks(hba, true); 9349 if (err) 9350 goto out_disable_hba_vreg; 9351 9352 err = ufshcd_init_vreg(hba); 9353 if (err) 9354 goto out_disable_clks; 9355 9356 err = ufshcd_setup_vreg(hba, true); 9357 if (err) 9358 goto out_disable_clks; 9359 9360 err = ufshcd_variant_hba_init(hba); 9361 if (err) 9362 goto out_disable_vreg; 9363 9364 ufs_debugfs_hba_init(hba); 9365 9366 hba->is_powered = true; 9367 goto out; 9368 9369 out_disable_vreg: 9370 ufshcd_setup_vreg(hba, false); 9371 out_disable_clks: 9372 ufshcd_setup_clocks(hba, false); 9373 out_disable_hba_vreg: 9374 ufshcd_setup_hba_vreg(hba, false); 9375 out: 9376 return err; 9377 } 9378 9379 static void ufshcd_hba_exit(struct ufs_hba *hba) 9380 { 9381 if (hba->is_powered) { 9382 ufshcd_exit_clk_scaling(hba); 9383 ufshcd_exit_clk_gating(hba); 9384 if (hba->eh_wq) 9385 destroy_workqueue(hba->eh_wq); 9386 ufs_debugfs_hba_exit(hba); 9387 ufshcd_variant_hba_exit(hba); 9388 ufshcd_setup_vreg(hba, false); 9389 ufshcd_setup_clocks(hba, false); 9390 ufshcd_setup_hba_vreg(hba, false); 9391 hba->is_powered = false; 9392 ufs_put_device_desc(hba); 9393 } 9394 } 9395 9396 static int ufshcd_execute_start_stop(struct scsi_device *sdev, 9397 enum ufs_dev_pwr_mode pwr_mode, 9398 struct scsi_sense_hdr *sshdr) 9399 { 9400 const unsigned char cdb[6] = { START_STOP, 0, 0, 0, pwr_mode << 4, 0 }; 9401 const struct scsi_exec_args args = { 9402 .sshdr = sshdr, 9403 .req_flags = BLK_MQ_REQ_PM, 9404 .scmd_flags = SCMD_FAIL_IF_RECOVERING, 9405 }; 9406 9407 return scsi_execute_cmd(sdev, cdb, REQ_OP_DRV_IN, /*buffer=*/NULL, 9408 /*bufflen=*/0, /*timeout=*/10 * HZ, /*retries=*/0, 9409 &args); 9410 } 9411 9412 /** 9413 * ufshcd_set_dev_pwr_mode - sends START STOP UNIT command to set device 9414 * power mode 9415 * @hba: per adapter instance 9416 * @pwr_mode: device power mode to set 9417 * 9418 * Return: 0 if requested power mode is set successfully; 9419 * < 0 if failed to set the requested power mode. 9420 */ 9421 static int ufshcd_set_dev_pwr_mode(struct ufs_hba *hba, 9422 enum ufs_dev_pwr_mode pwr_mode) 9423 { 9424 struct scsi_sense_hdr sshdr; 9425 struct scsi_device *sdp; 9426 unsigned long flags; 9427 int ret, retries; 9428 9429 spin_lock_irqsave(hba->host->host_lock, flags); 9430 sdp = hba->ufs_device_wlun; 9431 if (sdp && scsi_device_online(sdp)) 9432 ret = scsi_device_get(sdp); 9433 else 9434 ret = -ENODEV; 9435 spin_unlock_irqrestore(hba->host->host_lock, flags); 9436 9437 if (ret) 9438 return ret; 9439 9440 /* 9441 * If scsi commands fail, the scsi mid-layer schedules scsi error- 9442 * handling, which would wait for host to be resumed. Since we know 9443 * we are functional while we are here, skip host resume in error 9444 * handling context. 9445 */ 9446 hba->host->eh_noresume = 1; 9447 9448 /* 9449 * Current function would be generally called from the power management 9450 * callbacks hence set the RQF_PM flag so that it doesn't resume the 9451 * already suspended childs. 9452 */ 9453 for (retries = 3; retries > 0; --retries) { 9454 ret = ufshcd_execute_start_stop(sdp, pwr_mode, &sshdr); 9455 /* 9456 * scsi_execute() only returns a negative value if the request 9457 * queue is dying. 9458 */ 9459 if (ret <= 0) 9460 break; 9461 } 9462 if (ret) { 9463 sdev_printk(KERN_WARNING, sdp, 9464 "START_STOP failed for power mode: %d, result %x\n", 9465 pwr_mode, ret); 9466 if (ret > 0) { 9467 if (scsi_sense_valid(&sshdr)) 9468 scsi_print_sense_hdr(sdp, NULL, &sshdr); 9469 ret = -EIO; 9470 } 9471 } else { 9472 hba->curr_dev_pwr_mode = pwr_mode; 9473 } 9474 9475 scsi_device_put(sdp); 9476 hba->host->eh_noresume = 0; 9477 return ret; 9478 } 9479 9480 static int ufshcd_link_state_transition(struct ufs_hba *hba, 9481 enum uic_link_state req_link_state, 9482 bool check_for_bkops) 9483 { 9484 int ret = 0; 9485 9486 if (req_link_state == hba->uic_link_state) 9487 return 0; 9488 9489 if (req_link_state == UIC_LINK_HIBERN8_STATE) { 9490 ret = ufshcd_uic_hibern8_enter(hba); 9491 if (!ret) { 9492 ufshcd_set_link_hibern8(hba); 9493 } else { 9494 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9495 __func__, ret); 9496 goto out; 9497 } 9498 } 9499 /* 9500 * If autobkops is enabled, link can't be turned off because 9501 * turning off the link would also turn off the device, except in the 9502 * case of DeepSleep where the device is expected to remain powered. 9503 */ 9504 else if ((req_link_state == UIC_LINK_OFF_STATE) && 9505 (!check_for_bkops || !hba->auto_bkops_enabled)) { 9506 /* 9507 * Let's make sure that link is in low power mode, we are doing 9508 * this currently by putting the link in Hibern8. Otherway to 9509 * put the link in low power mode is to send the DME end point 9510 * to device and then send the DME reset command to local 9511 * unipro. But putting the link in hibern8 is much faster. 9512 * 9513 * Note also that putting the link in Hibern8 is a requirement 9514 * for entering DeepSleep. 9515 */ 9516 ret = ufshcd_uic_hibern8_enter(hba); 9517 if (ret) { 9518 dev_err(hba->dev, "%s: hibern8 enter failed %d\n", 9519 __func__, ret); 9520 goto out; 9521 } 9522 /* 9523 * Change controller state to "reset state" which 9524 * should also put the link in off/reset state 9525 */ 9526 ufshcd_hba_stop(hba); 9527 /* 9528 * TODO: Check if we need any delay to make sure that 9529 * controller is reset 9530 */ 9531 ufshcd_set_link_off(hba); 9532 } 9533 9534 out: 9535 return ret; 9536 } 9537 9538 static void ufshcd_vreg_set_lpm(struct ufs_hba *hba) 9539 { 9540 bool vcc_off = false; 9541 9542 /* 9543 * It seems some UFS devices may keep drawing more than sleep current 9544 * (atleast for 500us) from UFS rails (especially from VCCQ rail). 9545 * To avoid this situation, add 2ms delay before putting these UFS 9546 * rails in LPM mode. 9547 */ 9548 if (!ufshcd_is_link_active(hba) && 9549 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM) 9550 usleep_range(2000, 2100); 9551 9552 /* 9553 * If UFS device is either in UFS_Sleep turn off VCC rail to save some 9554 * power. 9555 * 9556 * If UFS device and link is in OFF state, all power supplies (VCC, 9557 * VCCQ, VCCQ2) can be turned off if power on write protect is not 9558 * required. If UFS link is inactive (Hibern8 or OFF state) and device 9559 * is in sleep state, put VCCQ & VCCQ2 rails in LPM mode. 9560 * 9561 * Ignore the error returned by ufshcd_toggle_vreg() as device is anyway 9562 * in low power state which would save some power. 9563 * 9564 * If Write Booster is enabled and the device needs to flush the WB 9565 * buffer OR if bkops status is urgent for WB, keep Vcc on. 9566 */ 9567 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9568 !hba->dev_info.is_lu_power_on_wp) { 9569 ufshcd_setup_vreg(hba, false); 9570 vcc_off = true; 9571 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9572 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9573 vcc_off = true; 9574 if (ufshcd_is_link_hibern8(hba) || ufshcd_is_link_off(hba)) { 9575 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9576 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq2); 9577 } 9578 } 9579 9580 /* 9581 * Some UFS devices require delay after VCC power rail is turned-off. 9582 */ 9583 if (vcc_off && hba->vreg_info.vcc && 9584 hba->dev_quirks & UFS_DEVICE_QUIRK_DELAY_AFTER_LPM) 9585 usleep_range(5000, 5100); 9586 } 9587 9588 #ifdef CONFIG_PM 9589 static int ufshcd_vreg_set_hpm(struct ufs_hba *hba) 9590 { 9591 int ret = 0; 9592 9593 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba) && 9594 !hba->dev_info.is_lu_power_on_wp) { 9595 ret = ufshcd_setup_vreg(hba, true); 9596 } else if (!ufshcd_is_ufs_dev_active(hba)) { 9597 if (!ufshcd_is_link_active(hba)) { 9598 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq); 9599 if (ret) 9600 goto vcc_disable; 9601 ret = ufshcd_config_vreg_hpm(hba, hba->vreg_info.vccq2); 9602 if (ret) 9603 goto vccq_lpm; 9604 } 9605 ret = ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, true); 9606 } 9607 goto out; 9608 9609 vccq_lpm: 9610 ufshcd_config_vreg_lpm(hba, hba->vreg_info.vccq); 9611 vcc_disable: 9612 ufshcd_toggle_vreg(hba->dev, hba->vreg_info.vcc, false); 9613 out: 9614 return ret; 9615 } 9616 #endif /* CONFIG_PM */ 9617 9618 static void ufshcd_hba_vreg_set_lpm(struct ufs_hba *hba) 9619 { 9620 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9621 ufshcd_setup_hba_vreg(hba, false); 9622 } 9623 9624 static void ufshcd_hba_vreg_set_hpm(struct ufs_hba *hba) 9625 { 9626 if (ufshcd_is_link_off(hba) || ufshcd_can_aggressive_pc(hba)) 9627 ufshcd_setup_hba_vreg(hba, true); 9628 } 9629 9630 static int __ufshcd_wl_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9631 { 9632 int ret = 0; 9633 bool check_for_bkops; 9634 enum ufs_pm_level pm_lvl; 9635 enum ufs_dev_pwr_mode req_dev_pwr_mode; 9636 enum uic_link_state req_link_state; 9637 9638 hba->pm_op_in_progress = true; 9639 if (pm_op != UFS_SHUTDOWN_PM) { 9640 pm_lvl = pm_op == UFS_RUNTIME_PM ? 9641 hba->rpm_lvl : hba->spm_lvl; 9642 req_dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(pm_lvl); 9643 req_link_state = ufs_get_pm_lvl_to_link_pwr_state(pm_lvl); 9644 } else { 9645 req_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE; 9646 req_link_state = UIC_LINK_OFF_STATE; 9647 } 9648 9649 /* 9650 * If we can't transition into any of the low power modes 9651 * just gate the clocks. 9652 */ 9653 ufshcd_hold(hba); 9654 hba->clk_gating.is_suspended = true; 9655 9656 if (ufshcd_is_clkscaling_supported(hba)) 9657 ufshcd_clk_scaling_suspend(hba, true); 9658 9659 if (req_dev_pwr_mode == UFS_ACTIVE_PWR_MODE && 9660 req_link_state == UIC_LINK_ACTIVE_STATE) { 9661 goto vops_suspend; 9662 } 9663 9664 if ((req_dev_pwr_mode == hba->curr_dev_pwr_mode) && 9665 (req_link_state == hba->uic_link_state)) 9666 goto enable_scaling; 9667 9668 /* UFS device & link must be active before we enter in this function */ 9669 if (!ufshcd_is_ufs_dev_active(hba) || !ufshcd_is_link_active(hba)) { 9670 ret = -EINVAL; 9671 goto enable_scaling; 9672 } 9673 9674 if (pm_op == UFS_RUNTIME_PM) { 9675 if (ufshcd_can_autobkops_during_suspend(hba)) { 9676 /* 9677 * The device is idle with no requests in the queue, 9678 * allow background operations if bkops status shows 9679 * that performance might be impacted. 9680 */ 9681 ret = ufshcd_urgent_bkops(hba); 9682 if (ret) { 9683 /* 9684 * If return err in suspend flow, IO will hang. 9685 * Trigger error handler and break suspend for 9686 * error recovery. 9687 */ 9688 ufshcd_force_error_recovery(hba); 9689 ret = -EBUSY; 9690 goto enable_scaling; 9691 } 9692 } else { 9693 /* make sure that auto bkops is disabled */ 9694 ufshcd_disable_auto_bkops(hba); 9695 } 9696 /* 9697 * If device needs to do BKOP or WB buffer flush during 9698 * Hibern8, keep device power mode as "active power mode" 9699 * and VCC supply. 9700 */ 9701 hba->dev_info.b_rpm_dev_flush_capable = 9702 hba->auto_bkops_enabled || 9703 (((req_link_state == UIC_LINK_HIBERN8_STATE) || 9704 ((req_link_state == UIC_LINK_ACTIVE_STATE) && 9705 ufshcd_is_auto_hibern8_enabled(hba))) && 9706 ufshcd_wb_need_flush(hba)); 9707 } 9708 9709 flush_work(&hba->eeh_work); 9710 9711 ret = ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9712 if (ret) 9713 goto enable_scaling; 9714 9715 if (req_dev_pwr_mode != hba->curr_dev_pwr_mode) { 9716 if (pm_op != UFS_RUNTIME_PM) 9717 /* ensure that bkops is disabled */ 9718 ufshcd_disable_auto_bkops(hba); 9719 9720 if (!hba->dev_info.b_rpm_dev_flush_capable) { 9721 ret = ufshcd_set_dev_pwr_mode(hba, req_dev_pwr_mode); 9722 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9723 /* 9724 * If return err in suspend flow, IO will hang. 9725 * Trigger error handler and break suspend for 9726 * error recovery. 9727 */ 9728 ufshcd_force_error_recovery(hba); 9729 ret = -EBUSY; 9730 } 9731 if (ret) 9732 goto enable_scaling; 9733 } 9734 } 9735 9736 /* 9737 * In the case of DeepSleep, the device is expected to remain powered 9738 * with the link off, so do not check for bkops. 9739 */ 9740 check_for_bkops = !ufshcd_is_ufs_dev_deepsleep(hba); 9741 ret = ufshcd_link_state_transition(hba, req_link_state, check_for_bkops); 9742 if (ret && pm_op != UFS_SHUTDOWN_PM) { 9743 /* 9744 * If return err in suspend flow, IO will hang. 9745 * Trigger error handler and break suspend for 9746 * error recovery. 9747 */ 9748 ufshcd_force_error_recovery(hba); 9749 ret = -EBUSY; 9750 } 9751 if (ret) 9752 goto set_dev_active; 9753 9754 vops_suspend: 9755 /* 9756 * Call vendor specific suspend callback. As these callbacks may access 9757 * vendor specific host controller register space call them before the 9758 * host clocks are ON. 9759 */ 9760 ret = ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9761 if (ret) 9762 goto set_link_active; 9763 goto out; 9764 9765 set_link_active: 9766 /* 9767 * Device hardware reset is required to exit DeepSleep. Also, for 9768 * DeepSleep, the link is off so host reset and restore will be done 9769 * further below. 9770 */ 9771 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9772 ufshcd_device_reset(hba); 9773 WARN_ON(!ufshcd_is_link_off(hba)); 9774 } 9775 if (ufshcd_is_link_hibern8(hba) && !ufshcd_uic_hibern8_exit(hba)) 9776 ufshcd_set_link_active(hba); 9777 else if (ufshcd_is_link_off(hba)) 9778 ufshcd_host_reset_and_restore(hba); 9779 set_dev_active: 9780 /* Can also get here needing to exit DeepSleep */ 9781 if (ufshcd_is_ufs_dev_deepsleep(hba)) { 9782 ufshcd_device_reset(hba); 9783 ufshcd_host_reset_and_restore(hba); 9784 } 9785 if (!ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE)) 9786 ufshcd_disable_auto_bkops(hba); 9787 enable_scaling: 9788 if (ufshcd_is_clkscaling_supported(hba)) 9789 ufshcd_clk_scaling_suspend(hba, false); 9790 9791 hba->dev_info.b_rpm_dev_flush_capable = false; 9792 out: 9793 if (hba->dev_info.b_rpm_dev_flush_capable) { 9794 schedule_delayed_work(&hba->rpm_dev_flush_recheck_work, 9795 msecs_to_jiffies(RPM_DEV_FLUSH_RECHECK_WORK_DELAY_MS)); 9796 } 9797 9798 if (ret) { 9799 ufshcd_update_evt_hist(hba, UFS_EVT_WL_SUSP_ERR, (u32)ret); 9800 hba->clk_gating.is_suspended = false; 9801 ufshcd_release(hba); 9802 } 9803 hba->pm_op_in_progress = false; 9804 return ret; 9805 } 9806 9807 #ifdef CONFIG_PM 9808 static int __ufshcd_wl_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op) 9809 { 9810 int ret; 9811 enum uic_link_state old_link_state = hba->uic_link_state; 9812 9813 hba->pm_op_in_progress = true; 9814 9815 /* 9816 * Call vendor specific resume callback. As these callbacks may access 9817 * vendor specific host controller register space call them when the 9818 * host clocks are ON. 9819 */ 9820 ret = ufshcd_vops_resume(hba, pm_op); 9821 if (ret) 9822 goto out; 9823 9824 /* For DeepSleep, the only supported option is to have the link off */ 9825 WARN_ON(ufshcd_is_ufs_dev_deepsleep(hba) && !ufshcd_is_link_off(hba)); 9826 9827 if (ufshcd_is_link_hibern8(hba)) { 9828 ret = ufshcd_uic_hibern8_exit(hba); 9829 if (!ret) { 9830 ufshcd_set_link_active(hba); 9831 } else { 9832 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 9833 __func__, ret); 9834 goto vendor_suspend; 9835 } 9836 } else if (ufshcd_is_link_off(hba)) { 9837 /* 9838 * A full initialization of the host and the device is 9839 * required since the link was put to off during suspend. 9840 * Note, in the case of DeepSleep, the device will exit 9841 * DeepSleep due to device reset. 9842 */ 9843 ret = ufshcd_reset_and_restore(hba); 9844 /* 9845 * ufshcd_reset_and_restore() should have already 9846 * set the link state as active 9847 */ 9848 if (ret || !ufshcd_is_link_active(hba)) 9849 goto vendor_suspend; 9850 } 9851 9852 if (!ufshcd_is_ufs_dev_active(hba)) { 9853 ret = ufshcd_set_dev_pwr_mode(hba, UFS_ACTIVE_PWR_MODE); 9854 if (ret) 9855 goto set_old_link_state; 9856 ufshcd_set_timestamp_attr(hba); 9857 } 9858 9859 if (ufshcd_keep_autobkops_enabled_except_suspend(hba)) 9860 ufshcd_enable_auto_bkops(hba); 9861 else 9862 /* 9863 * If BKOPs operations are urgently needed at this moment then 9864 * keep auto-bkops enabled or else disable it. 9865 */ 9866 ufshcd_urgent_bkops(hba); 9867 9868 if (hba->ee_usr_mask) 9869 ufshcd_write_ee_control(hba); 9870 9871 if (ufshcd_is_clkscaling_supported(hba)) 9872 ufshcd_clk_scaling_suspend(hba, false); 9873 9874 if (hba->dev_info.b_rpm_dev_flush_capable) { 9875 hba->dev_info.b_rpm_dev_flush_capable = false; 9876 cancel_delayed_work(&hba->rpm_dev_flush_recheck_work); 9877 } 9878 9879 /* Enable Auto-Hibernate if configured */ 9880 ufshcd_auto_hibern8_enable(hba); 9881 9882 goto out; 9883 9884 set_old_link_state: 9885 ufshcd_link_state_transition(hba, old_link_state, 0); 9886 vendor_suspend: 9887 ufshcd_vops_suspend(hba, pm_op, PRE_CHANGE); 9888 ufshcd_vops_suspend(hba, pm_op, POST_CHANGE); 9889 out: 9890 if (ret) 9891 ufshcd_update_evt_hist(hba, UFS_EVT_WL_RES_ERR, (u32)ret); 9892 hba->clk_gating.is_suspended = false; 9893 ufshcd_release(hba); 9894 hba->pm_op_in_progress = false; 9895 return ret; 9896 } 9897 9898 static int ufshcd_wl_runtime_suspend(struct device *dev) 9899 { 9900 struct scsi_device *sdev = to_scsi_device(dev); 9901 struct ufs_hba *hba; 9902 int ret; 9903 ktime_t start = ktime_get(); 9904 9905 hba = shost_priv(sdev->host); 9906 9907 ret = __ufshcd_wl_suspend(hba, UFS_RUNTIME_PM); 9908 if (ret) 9909 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9910 9911 trace_ufshcd_wl_runtime_suspend(dev_name(dev), ret, 9912 ktime_to_us(ktime_sub(ktime_get(), start)), 9913 hba->curr_dev_pwr_mode, hba->uic_link_state); 9914 9915 return ret; 9916 } 9917 9918 static int ufshcd_wl_runtime_resume(struct device *dev) 9919 { 9920 struct scsi_device *sdev = to_scsi_device(dev); 9921 struct ufs_hba *hba; 9922 int ret = 0; 9923 ktime_t start = ktime_get(); 9924 9925 hba = shost_priv(sdev->host); 9926 9927 ret = __ufshcd_wl_resume(hba, UFS_RUNTIME_PM); 9928 if (ret) 9929 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9930 9931 trace_ufshcd_wl_runtime_resume(dev_name(dev), ret, 9932 ktime_to_us(ktime_sub(ktime_get(), start)), 9933 hba->curr_dev_pwr_mode, hba->uic_link_state); 9934 9935 return ret; 9936 } 9937 #endif 9938 9939 #ifdef CONFIG_PM_SLEEP 9940 static int ufshcd_wl_suspend(struct device *dev) 9941 { 9942 struct scsi_device *sdev = to_scsi_device(dev); 9943 struct ufs_hba *hba; 9944 int ret = 0; 9945 ktime_t start = ktime_get(); 9946 9947 hba = shost_priv(sdev->host); 9948 down(&hba->host_sem); 9949 hba->system_suspending = true; 9950 9951 if (pm_runtime_suspended(dev)) 9952 goto out; 9953 9954 ret = __ufshcd_wl_suspend(hba, UFS_SYSTEM_PM); 9955 if (ret) { 9956 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9957 up(&hba->host_sem); 9958 } 9959 9960 out: 9961 if (!ret) 9962 hba->is_sys_suspended = true; 9963 trace_ufshcd_wl_suspend(dev_name(dev), ret, 9964 ktime_to_us(ktime_sub(ktime_get(), start)), 9965 hba->curr_dev_pwr_mode, hba->uic_link_state); 9966 9967 return ret; 9968 } 9969 9970 static int ufshcd_wl_resume(struct device *dev) 9971 { 9972 struct scsi_device *sdev = to_scsi_device(dev); 9973 struct ufs_hba *hba; 9974 int ret = 0; 9975 ktime_t start = ktime_get(); 9976 9977 hba = shost_priv(sdev->host); 9978 9979 if (pm_runtime_suspended(dev)) 9980 goto out; 9981 9982 ret = __ufshcd_wl_resume(hba, UFS_SYSTEM_PM); 9983 if (ret) 9984 dev_err(&sdev->sdev_gendev, "%s failed: %d\n", __func__, ret); 9985 out: 9986 trace_ufshcd_wl_resume(dev_name(dev), ret, 9987 ktime_to_us(ktime_sub(ktime_get(), start)), 9988 hba->curr_dev_pwr_mode, hba->uic_link_state); 9989 if (!ret) 9990 hba->is_sys_suspended = false; 9991 hba->system_suspending = false; 9992 up(&hba->host_sem); 9993 return ret; 9994 } 9995 #endif 9996 9997 /** 9998 * ufshcd_suspend - helper function for suspend operations 9999 * @hba: per adapter instance 10000 * 10001 * This function will put disable irqs, turn off clocks 10002 * and set vreg and hba-vreg in lpm mode. 10003 * 10004 * Return: 0 upon success; < 0 upon failure. 10005 */ 10006 static int ufshcd_suspend(struct ufs_hba *hba) 10007 { 10008 int ret; 10009 10010 if (!hba->is_powered) 10011 return 0; 10012 /* 10013 * Disable the host irq as host controller as there won't be any 10014 * host controller transaction expected till resume. 10015 */ 10016 ufshcd_disable_irq(hba); 10017 ret = ufshcd_setup_clocks(hba, false); 10018 if (ret) { 10019 ufshcd_enable_irq(hba); 10020 return ret; 10021 } 10022 if (ufshcd_is_clkgating_allowed(hba)) { 10023 hba->clk_gating.state = CLKS_OFF; 10024 trace_ufshcd_clk_gating(dev_name(hba->dev), 10025 hba->clk_gating.state); 10026 } 10027 10028 ufshcd_vreg_set_lpm(hba); 10029 /* Put the host controller in low power mode if possible */ 10030 ufshcd_hba_vreg_set_lpm(hba); 10031 return ret; 10032 } 10033 10034 #ifdef CONFIG_PM 10035 /** 10036 * ufshcd_resume - helper function for resume operations 10037 * @hba: per adapter instance 10038 * 10039 * This function basically turns on the regulators, clocks and 10040 * irqs of the hba. 10041 * 10042 * Return: 0 for success and non-zero for failure. 10043 */ 10044 static int ufshcd_resume(struct ufs_hba *hba) 10045 { 10046 int ret; 10047 10048 if (!hba->is_powered) 10049 return 0; 10050 10051 ufshcd_hba_vreg_set_hpm(hba); 10052 ret = ufshcd_vreg_set_hpm(hba); 10053 if (ret) 10054 goto out; 10055 10056 /* Make sure clocks are enabled before accessing controller */ 10057 ret = ufshcd_setup_clocks(hba, true); 10058 if (ret) 10059 goto disable_vreg; 10060 10061 /* enable the host irq as host controller would be active soon */ 10062 ufshcd_enable_irq(hba); 10063 10064 goto out; 10065 10066 disable_vreg: 10067 ufshcd_vreg_set_lpm(hba); 10068 out: 10069 if (ret) 10070 ufshcd_update_evt_hist(hba, UFS_EVT_RESUME_ERR, (u32)ret); 10071 return ret; 10072 } 10073 #endif /* CONFIG_PM */ 10074 10075 #ifdef CONFIG_PM_SLEEP 10076 /** 10077 * ufshcd_system_suspend - system suspend callback 10078 * @dev: Device associated with the UFS controller. 10079 * 10080 * Executed before putting the system into a sleep state in which the contents 10081 * of main memory are preserved. 10082 * 10083 * Return: 0 for success and non-zero for failure. 10084 */ 10085 int ufshcd_system_suspend(struct device *dev) 10086 { 10087 struct ufs_hba *hba = dev_get_drvdata(dev); 10088 int ret = 0; 10089 ktime_t start = ktime_get(); 10090 10091 if (pm_runtime_suspended(hba->dev)) 10092 goto out; 10093 10094 ret = ufshcd_suspend(hba); 10095 out: 10096 trace_ufshcd_system_suspend(dev_name(hba->dev), ret, 10097 ktime_to_us(ktime_sub(ktime_get(), start)), 10098 hba->curr_dev_pwr_mode, hba->uic_link_state); 10099 return ret; 10100 } 10101 EXPORT_SYMBOL(ufshcd_system_suspend); 10102 10103 /** 10104 * ufshcd_system_resume - system resume callback 10105 * @dev: Device associated with the UFS controller. 10106 * 10107 * Executed after waking the system up from a sleep state in which the contents 10108 * of main memory were preserved. 10109 * 10110 * Return: 0 for success and non-zero for failure. 10111 */ 10112 int ufshcd_system_resume(struct device *dev) 10113 { 10114 struct ufs_hba *hba = dev_get_drvdata(dev); 10115 ktime_t start = ktime_get(); 10116 int ret = 0; 10117 10118 if (pm_runtime_suspended(hba->dev)) 10119 goto out; 10120 10121 ret = ufshcd_resume(hba); 10122 10123 out: 10124 trace_ufshcd_system_resume(dev_name(hba->dev), ret, 10125 ktime_to_us(ktime_sub(ktime_get(), start)), 10126 hba->curr_dev_pwr_mode, hba->uic_link_state); 10127 10128 return ret; 10129 } 10130 EXPORT_SYMBOL(ufshcd_system_resume); 10131 #endif /* CONFIG_PM_SLEEP */ 10132 10133 #ifdef CONFIG_PM 10134 /** 10135 * ufshcd_runtime_suspend - runtime suspend callback 10136 * @dev: Device associated with the UFS controller. 10137 * 10138 * Check the description of ufshcd_suspend() function for more details. 10139 * 10140 * Return: 0 for success and non-zero for failure. 10141 */ 10142 int ufshcd_runtime_suspend(struct device *dev) 10143 { 10144 struct ufs_hba *hba = dev_get_drvdata(dev); 10145 int ret; 10146 ktime_t start = ktime_get(); 10147 10148 ret = ufshcd_suspend(hba); 10149 10150 trace_ufshcd_runtime_suspend(dev_name(hba->dev), ret, 10151 ktime_to_us(ktime_sub(ktime_get(), start)), 10152 hba->curr_dev_pwr_mode, hba->uic_link_state); 10153 return ret; 10154 } 10155 EXPORT_SYMBOL(ufshcd_runtime_suspend); 10156 10157 /** 10158 * ufshcd_runtime_resume - runtime resume routine 10159 * @dev: Device associated with the UFS controller. 10160 * 10161 * This function basically brings controller 10162 * to active state. Following operations are done in this function: 10163 * 10164 * 1. Turn on all the controller related clocks 10165 * 2. Turn ON VCC rail 10166 * 10167 * Return: 0 upon success; < 0 upon failure. 10168 */ 10169 int ufshcd_runtime_resume(struct device *dev) 10170 { 10171 struct ufs_hba *hba = dev_get_drvdata(dev); 10172 int ret; 10173 ktime_t start = ktime_get(); 10174 10175 ret = ufshcd_resume(hba); 10176 10177 trace_ufshcd_runtime_resume(dev_name(hba->dev), ret, 10178 ktime_to_us(ktime_sub(ktime_get(), start)), 10179 hba->curr_dev_pwr_mode, hba->uic_link_state); 10180 return ret; 10181 } 10182 EXPORT_SYMBOL(ufshcd_runtime_resume); 10183 #endif /* CONFIG_PM */ 10184 10185 static void ufshcd_wl_shutdown(struct device *dev) 10186 { 10187 struct scsi_device *sdev = to_scsi_device(dev); 10188 struct ufs_hba *hba = shost_priv(sdev->host); 10189 10190 down(&hba->host_sem); 10191 hba->shutting_down = true; 10192 up(&hba->host_sem); 10193 10194 /* Turn on everything while shutting down */ 10195 ufshcd_rpm_get_sync(hba); 10196 scsi_device_quiesce(sdev); 10197 shost_for_each_device(sdev, hba->host) { 10198 if (sdev == hba->ufs_device_wlun) 10199 continue; 10200 scsi_device_quiesce(sdev); 10201 } 10202 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10203 10204 /* 10205 * Next, turn off the UFS controller and the UFS regulators. Disable 10206 * clocks. 10207 */ 10208 if (ufshcd_is_ufs_dev_poweroff(hba) && ufshcd_is_link_off(hba)) 10209 ufshcd_suspend(hba); 10210 10211 hba->is_powered = false; 10212 } 10213 10214 /** 10215 * ufshcd_remove - de-allocate SCSI host and host memory space 10216 * data structure memory 10217 * @hba: per adapter instance 10218 */ 10219 void ufshcd_remove(struct ufs_hba *hba) 10220 { 10221 if (hba->ufs_device_wlun) 10222 ufshcd_rpm_get_sync(hba); 10223 ufs_hwmon_remove(hba); 10224 ufs_bsg_remove(hba); 10225 ufs_sysfs_remove_nodes(hba->dev); 10226 blk_mq_destroy_queue(hba->tmf_queue); 10227 blk_put_queue(hba->tmf_queue); 10228 blk_mq_free_tag_set(&hba->tmf_tag_set); 10229 scsi_remove_host(hba->host); 10230 /* disable interrupts */ 10231 ufshcd_disable_intr(hba, hba->intr_mask); 10232 ufshcd_hba_stop(hba); 10233 ufshcd_hba_exit(hba); 10234 } 10235 EXPORT_SYMBOL_GPL(ufshcd_remove); 10236 10237 #ifdef CONFIG_PM_SLEEP 10238 int ufshcd_system_freeze(struct device *dev) 10239 { 10240 10241 return ufshcd_system_suspend(dev); 10242 10243 } 10244 EXPORT_SYMBOL_GPL(ufshcd_system_freeze); 10245 10246 int ufshcd_system_restore(struct device *dev) 10247 { 10248 10249 struct ufs_hba *hba = dev_get_drvdata(dev); 10250 int ret; 10251 10252 ret = ufshcd_system_resume(dev); 10253 if (ret) 10254 return ret; 10255 10256 /* Configure UTRL and UTMRL base address registers */ 10257 ufshcd_writel(hba, lower_32_bits(hba->utrdl_dma_addr), 10258 REG_UTP_TRANSFER_REQ_LIST_BASE_L); 10259 ufshcd_writel(hba, upper_32_bits(hba->utrdl_dma_addr), 10260 REG_UTP_TRANSFER_REQ_LIST_BASE_H); 10261 ufshcd_writel(hba, lower_32_bits(hba->utmrdl_dma_addr), 10262 REG_UTP_TASK_REQ_LIST_BASE_L); 10263 ufshcd_writel(hba, upper_32_bits(hba->utmrdl_dma_addr), 10264 REG_UTP_TASK_REQ_LIST_BASE_H); 10265 /* 10266 * Make sure that UTRL and UTMRL base address registers 10267 * are updated with the latest queue addresses. Only after 10268 * updating these addresses, we can queue the new commands. 10269 */ 10270 mb(); 10271 10272 /* Resuming from hibernate, assume that link was OFF */ 10273 ufshcd_set_link_off(hba); 10274 10275 return 0; 10276 10277 } 10278 EXPORT_SYMBOL_GPL(ufshcd_system_restore); 10279 10280 int ufshcd_system_thaw(struct device *dev) 10281 { 10282 return ufshcd_system_resume(dev); 10283 } 10284 EXPORT_SYMBOL_GPL(ufshcd_system_thaw); 10285 #endif /* CONFIG_PM_SLEEP */ 10286 10287 /** 10288 * ufshcd_dealloc_host - deallocate Host Bus Adapter (HBA) 10289 * @hba: pointer to Host Bus Adapter (HBA) 10290 */ 10291 void ufshcd_dealloc_host(struct ufs_hba *hba) 10292 { 10293 scsi_host_put(hba->host); 10294 } 10295 EXPORT_SYMBOL_GPL(ufshcd_dealloc_host); 10296 10297 /** 10298 * ufshcd_set_dma_mask - Set dma mask based on the controller 10299 * addressing capability 10300 * @hba: per adapter instance 10301 * 10302 * Return: 0 for success, non-zero for failure. 10303 */ 10304 static int ufshcd_set_dma_mask(struct ufs_hba *hba) 10305 { 10306 if (hba->capabilities & MASK_64_ADDRESSING_SUPPORT) { 10307 if (!dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(64))) 10308 return 0; 10309 } 10310 return dma_set_mask_and_coherent(hba->dev, DMA_BIT_MASK(32)); 10311 } 10312 10313 /** 10314 * ufshcd_alloc_host - allocate Host Bus Adapter (HBA) 10315 * @dev: pointer to device handle 10316 * @hba_handle: driver private handle 10317 * 10318 * Return: 0 on success, non-zero value on failure. 10319 */ 10320 int ufshcd_alloc_host(struct device *dev, struct ufs_hba **hba_handle) 10321 { 10322 struct Scsi_Host *host; 10323 struct ufs_hba *hba; 10324 int err = 0; 10325 10326 if (!dev) { 10327 dev_err(dev, 10328 "Invalid memory reference for dev is NULL\n"); 10329 err = -ENODEV; 10330 goto out_error; 10331 } 10332 10333 host = scsi_host_alloc(&ufshcd_driver_template, 10334 sizeof(struct ufs_hba)); 10335 if (!host) { 10336 dev_err(dev, "scsi_host_alloc failed\n"); 10337 err = -ENOMEM; 10338 goto out_error; 10339 } 10340 host->nr_maps = HCTX_TYPE_POLL + 1; 10341 hba = shost_priv(host); 10342 hba->host = host; 10343 hba->dev = dev; 10344 hba->dev_ref_clk_freq = REF_CLK_FREQ_INVAL; 10345 hba->nop_out_timeout = NOP_OUT_TIMEOUT; 10346 ufshcd_set_sg_entry_size(hba, sizeof(struct ufshcd_sg_entry)); 10347 INIT_LIST_HEAD(&hba->clk_list_head); 10348 spin_lock_init(&hba->outstanding_lock); 10349 10350 *hba_handle = hba; 10351 10352 out_error: 10353 return err; 10354 } 10355 EXPORT_SYMBOL(ufshcd_alloc_host); 10356 10357 /* This function exists because blk_mq_alloc_tag_set() requires this. */ 10358 static blk_status_t ufshcd_queue_tmf(struct blk_mq_hw_ctx *hctx, 10359 const struct blk_mq_queue_data *qd) 10360 { 10361 WARN_ON_ONCE(true); 10362 return BLK_STS_NOTSUPP; 10363 } 10364 10365 static const struct blk_mq_ops ufshcd_tmf_ops = { 10366 .queue_rq = ufshcd_queue_tmf, 10367 }; 10368 10369 /** 10370 * ufshcd_init - Driver initialization routine 10371 * @hba: per-adapter instance 10372 * @mmio_base: base register address 10373 * @irq: Interrupt line of device 10374 * 10375 * Return: 0 on success, non-zero value on failure. 10376 */ 10377 int ufshcd_init(struct ufs_hba *hba, void __iomem *mmio_base, unsigned int irq) 10378 { 10379 int err; 10380 struct Scsi_Host *host = hba->host; 10381 struct device *dev = hba->dev; 10382 char eh_wq_name[sizeof("ufs_eh_wq_00")]; 10383 10384 /* 10385 * dev_set_drvdata() must be called before any callbacks are registered 10386 * that use dev_get_drvdata() (frequency scaling, clock scaling, hwmon, 10387 * sysfs). 10388 */ 10389 dev_set_drvdata(dev, hba); 10390 10391 if (!mmio_base) { 10392 dev_err(hba->dev, 10393 "Invalid memory reference for mmio_base is NULL\n"); 10394 err = -ENODEV; 10395 goto out_error; 10396 } 10397 10398 hba->mmio_base = mmio_base; 10399 hba->irq = irq; 10400 hba->vps = &ufs_hba_vps; 10401 10402 err = ufshcd_hba_init(hba); 10403 if (err) 10404 goto out_error; 10405 10406 /* Read capabilities registers */ 10407 err = ufshcd_hba_capabilities(hba); 10408 if (err) 10409 goto out_disable; 10410 10411 /* Get UFS version supported by the controller */ 10412 hba->ufs_version = ufshcd_get_ufs_version(hba); 10413 10414 /* Get Interrupt bit mask per version */ 10415 hba->intr_mask = ufshcd_get_intr_mask(hba); 10416 10417 err = ufshcd_set_dma_mask(hba); 10418 if (err) { 10419 dev_err(hba->dev, "set dma mask failed\n"); 10420 goto out_disable; 10421 } 10422 10423 /* Allocate memory for host memory space */ 10424 err = ufshcd_memory_alloc(hba); 10425 if (err) { 10426 dev_err(hba->dev, "Memory allocation failed\n"); 10427 goto out_disable; 10428 } 10429 10430 /* Configure LRB */ 10431 ufshcd_host_memory_configure(hba); 10432 10433 host->can_queue = hba->nutrs - UFSHCD_NUM_RESERVED; 10434 host->cmd_per_lun = hba->nutrs - UFSHCD_NUM_RESERVED; 10435 host->max_id = UFSHCD_MAX_ID; 10436 host->max_lun = UFS_MAX_LUNS; 10437 host->max_channel = UFSHCD_MAX_CHANNEL; 10438 host->unique_id = host->host_no; 10439 host->max_cmd_len = UFS_CDB_SIZE; 10440 host->queuecommand_may_block = !!(hba->caps & UFSHCD_CAP_CLK_GATING); 10441 10442 hba->max_pwr_info.is_valid = false; 10443 10444 /* Initialize work queues */ 10445 snprintf(eh_wq_name, sizeof(eh_wq_name), "ufs_eh_wq_%d", 10446 hba->host->host_no); 10447 hba->eh_wq = create_singlethread_workqueue(eh_wq_name); 10448 if (!hba->eh_wq) { 10449 dev_err(hba->dev, "%s: failed to create eh workqueue\n", 10450 __func__); 10451 err = -ENOMEM; 10452 goto out_disable; 10453 } 10454 INIT_WORK(&hba->eh_work, ufshcd_err_handler); 10455 INIT_WORK(&hba->eeh_work, ufshcd_exception_event_handler); 10456 10457 sema_init(&hba->host_sem, 1); 10458 10459 /* Initialize UIC command mutex */ 10460 mutex_init(&hba->uic_cmd_mutex); 10461 10462 /* Initialize mutex for device management commands */ 10463 mutex_init(&hba->dev_cmd.lock); 10464 10465 /* Initialize mutex for exception event control */ 10466 mutex_init(&hba->ee_ctrl_mutex); 10467 10468 mutex_init(&hba->wb_mutex); 10469 init_rwsem(&hba->clk_scaling_lock); 10470 10471 ufshcd_init_clk_gating(hba); 10472 10473 ufshcd_init_clk_scaling(hba); 10474 10475 /* 10476 * In order to avoid any spurious interrupt immediately after 10477 * registering UFS controller interrupt handler, clear any pending UFS 10478 * interrupt status and disable all the UFS interrupts. 10479 */ 10480 ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS), 10481 REG_INTERRUPT_STATUS); 10482 ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE); 10483 /* 10484 * Make sure that UFS interrupts are disabled and any pending interrupt 10485 * status is cleared before registering UFS interrupt handler. 10486 */ 10487 mb(); 10488 10489 /* IRQ registration */ 10490 err = devm_request_irq(dev, irq, ufshcd_intr, IRQF_SHARED, UFSHCD, hba); 10491 if (err) { 10492 dev_err(hba->dev, "request irq failed\n"); 10493 goto out_disable; 10494 } else { 10495 hba->is_irq_enabled = true; 10496 } 10497 10498 if (!is_mcq_supported(hba)) { 10499 err = scsi_add_host(host, hba->dev); 10500 if (err) { 10501 dev_err(hba->dev, "scsi_add_host failed\n"); 10502 goto out_disable; 10503 } 10504 } 10505 10506 hba->tmf_tag_set = (struct blk_mq_tag_set) { 10507 .nr_hw_queues = 1, 10508 .queue_depth = hba->nutmrs, 10509 .ops = &ufshcd_tmf_ops, 10510 .flags = BLK_MQ_F_NO_SCHED, 10511 }; 10512 err = blk_mq_alloc_tag_set(&hba->tmf_tag_set); 10513 if (err < 0) 10514 goto out_remove_scsi_host; 10515 hba->tmf_queue = blk_mq_init_queue(&hba->tmf_tag_set); 10516 if (IS_ERR(hba->tmf_queue)) { 10517 err = PTR_ERR(hba->tmf_queue); 10518 goto free_tmf_tag_set; 10519 } 10520 hba->tmf_rqs = devm_kcalloc(hba->dev, hba->nutmrs, 10521 sizeof(*hba->tmf_rqs), GFP_KERNEL); 10522 if (!hba->tmf_rqs) { 10523 err = -ENOMEM; 10524 goto free_tmf_queue; 10525 } 10526 10527 /* Reset the attached device */ 10528 ufshcd_device_reset(hba); 10529 10530 ufshcd_init_crypto(hba); 10531 10532 /* Host controller enable */ 10533 err = ufshcd_hba_enable(hba); 10534 if (err) { 10535 dev_err(hba->dev, "Host controller enable failed\n"); 10536 ufshcd_print_evt_hist(hba); 10537 ufshcd_print_host_state(hba); 10538 goto free_tmf_queue; 10539 } 10540 10541 /* 10542 * Set the default power management level for runtime and system PM. 10543 * Default power saving mode is to keep UFS link in Hibern8 state 10544 * and UFS device in sleep state. 10545 */ 10546 hba->rpm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10547 UFS_SLEEP_PWR_MODE, 10548 UIC_LINK_HIBERN8_STATE); 10549 hba->spm_lvl = ufs_get_desired_pm_lvl_for_dev_link_state( 10550 UFS_SLEEP_PWR_MODE, 10551 UIC_LINK_HIBERN8_STATE); 10552 10553 INIT_DELAYED_WORK(&hba->rpm_dev_flush_recheck_work, 10554 ufshcd_rpm_dev_flush_recheck_work); 10555 10556 /* Set the default auto-hiberate idle timer value to 150 ms */ 10557 if (ufshcd_is_auto_hibern8_supported(hba) && !hba->ahit) { 10558 hba->ahit = FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 150) | 10559 FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3); 10560 } 10561 10562 /* Hold auto suspend until async scan completes */ 10563 pm_runtime_get_sync(dev); 10564 atomic_set(&hba->scsi_block_reqs_cnt, 0); 10565 /* 10566 * We are assuming that device wasn't put in sleep/power-down 10567 * state exclusively during the boot stage before kernel. 10568 * This assumption helps avoid doing link startup twice during 10569 * ufshcd_probe_hba(). 10570 */ 10571 ufshcd_set_ufs_dev_active(hba); 10572 10573 async_schedule(ufshcd_async_scan, hba); 10574 ufs_sysfs_add_nodes(hba->dev); 10575 10576 device_enable_async_suspend(dev); 10577 return 0; 10578 10579 free_tmf_queue: 10580 blk_mq_destroy_queue(hba->tmf_queue); 10581 blk_put_queue(hba->tmf_queue); 10582 free_tmf_tag_set: 10583 blk_mq_free_tag_set(&hba->tmf_tag_set); 10584 out_remove_scsi_host: 10585 scsi_remove_host(hba->host); 10586 out_disable: 10587 hba->is_irq_enabled = false; 10588 ufshcd_hba_exit(hba); 10589 out_error: 10590 return err; 10591 } 10592 EXPORT_SYMBOL_GPL(ufshcd_init); 10593 10594 void ufshcd_resume_complete(struct device *dev) 10595 { 10596 struct ufs_hba *hba = dev_get_drvdata(dev); 10597 10598 if (hba->complete_put) { 10599 ufshcd_rpm_put(hba); 10600 hba->complete_put = false; 10601 } 10602 } 10603 EXPORT_SYMBOL_GPL(ufshcd_resume_complete); 10604 10605 static bool ufshcd_rpm_ok_for_spm(struct ufs_hba *hba) 10606 { 10607 struct device *dev = &hba->ufs_device_wlun->sdev_gendev; 10608 enum ufs_dev_pwr_mode dev_pwr_mode; 10609 enum uic_link_state link_state; 10610 unsigned long flags; 10611 bool res; 10612 10613 spin_lock_irqsave(&dev->power.lock, flags); 10614 dev_pwr_mode = ufs_get_pm_lvl_to_dev_pwr_mode(hba->spm_lvl); 10615 link_state = ufs_get_pm_lvl_to_link_pwr_state(hba->spm_lvl); 10616 res = pm_runtime_suspended(dev) && 10617 hba->curr_dev_pwr_mode == dev_pwr_mode && 10618 hba->uic_link_state == link_state && 10619 !hba->dev_info.b_rpm_dev_flush_capable; 10620 spin_unlock_irqrestore(&dev->power.lock, flags); 10621 10622 return res; 10623 } 10624 10625 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm) 10626 { 10627 struct ufs_hba *hba = dev_get_drvdata(dev); 10628 int ret; 10629 10630 /* 10631 * SCSI assumes that runtime-pm and system-pm for scsi drivers 10632 * are same. And it doesn't wake up the device for system-suspend 10633 * if it's runtime suspended. But ufs doesn't follow that. 10634 * Refer ufshcd_resume_complete() 10635 */ 10636 if (hba->ufs_device_wlun) { 10637 /* Prevent runtime suspend */ 10638 ufshcd_rpm_get_noresume(hba); 10639 /* 10640 * Check if already runtime suspended in same state as system 10641 * suspend would be. 10642 */ 10643 if (!rpm_ok_for_spm || !ufshcd_rpm_ok_for_spm(hba)) { 10644 /* RPM state is not ok for SPM, so runtime resume */ 10645 ret = ufshcd_rpm_resume(hba); 10646 if (ret < 0 && ret != -EACCES) { 10647 ufshcd_rpm_put(hba); 10648 return ret; 10649 } 10650 } 10651 hba->complete_put = true; 10652 } 10653 return 0; 10654 } 10655 EXPORT_SYMBOL_GPL(__ufshcd_suspend_prepare); 10656 10657 int ufshcd_suspend_prepare(struct device *dev) 10658 { 10659 return __ufshcd_suspend_prepare(dev, true); 10660 } 10661 EXPORT_SYMBOL_GPL(ufshcd_suspend_prepare); 10662 10663 #ifdef CONFIG_PM_SLEEP 10664 static int ufshcd_wl_poweroff(struct device *dev) 10665 { 10666 struct scsi_device *sdev = to_scsi_device(dev); 10667 struct ufs_hba *hba = shost_priv(sdev->host); 10668 10669 __ufshcd_wl_suspend(hba, UFS_SHUTDOWN_PM); 10670 return 0; 10671 } 10672 #endif 10673 10674 static int ufshcd_wl_probe(struct device *dev) 10675 { 10676 struct scsi_device *sdev = to_scsi_device(dev); 10677 10678 if (!is_device_wlun(sdev)) 10679 return -ENODEV; 10680 10681 blk_pm_runtime_init(sdev->request_queue, dev); 10682 pm_runtime_set_autosuspend_delay(dev, 0); 10683 pm_runtime_allow(dev); 10684 10685 return 0; 10686 } 10687 10688 static int ufshcd_wl_remove(struct device *dev) 10689 { 10690 pm_runtime_forbid(dev); 10691 return 0; 10692 } 10693 10694 static const struct dev_pm_ops ufshcd_wl_pm_ops = { 10695 #ifdef CONFIG_PM_SLEEP 10696 .suspend = ufshcd_wl_suspend, 10697 .resume = ufshcd_wl_resume, 10698 .freeze = ufshcd_wl_suspend, 10699 .thaw = ufshcd_wl_resume, 10700 .poweroff = ufshcd_wl_poweroff, 10701 .restore = ufshcd_wl_resume, 10702 #endif 10703 SET_RUNTIME_PM_OPS(ufshcd_wl_runtime_suspend, ufshcd_wl_runtime_resume, NULL) 10704 }; 10705 10706 static void ufshcd_check_header_layout(void) 10707 { 10708 /* 10709 * gcc compilers before version 10 cannot do constant-folding for 10710 * sub-byte bitfields. Hence skip the layout checks for gcc 9 and 10711 * before. 10712 */ 10713 if (IS_ENABLED(CONFIG_CC_IS_GCC) && CONFIG_GCC_VERSION < 100000) 10714 return; 10715 10716 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10717 .cci = 3})[0] != 3); 10718 10719 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10720 .ehs_length = 2})[1] != 2); 10721 10722 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10723 .enable_crypto = 1})[2] 10724 != 0x80); 10725 10726 BUILD_BUG_ON((((u8 *)&(struct request_desc_header){ 10727 .command_type = 5, 10728 .data_direction = 3, 10729 .interrupt = 1, 10730 })[3]) != ((5 << 4) | (3 << 1) | 1)); 10731 10732 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10733 .dunl = cpu_to_le32(0xdeadbeef)})[1] != 10734 cpu_to_le32(0xdeadbeef)); 10735 10736 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10737 .ocs = 4})[8] != 4); 10738 10739 BUILD_BUG_ON(((u8 *)&(struct request_desc_header){ 10740 .cds = 5})[9] != 5); 10741 10742 BUILD_BUG_ON(((__le32 *)&(struct request_desc_header){ 10743 .dunu = cpu_to_le32(0xbadcafe)})[3] != 10744 cpu_to_le32(0xbadcafe)); 10745 10746 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10747 .iid = 0xf })[4] != 0xf0); 10748 10749 BUILD_BUG_ON(((u8 *)&(struct utp_upiu_header){ 10750 .command_set_type = 0xf })[4] != 0xf); 10751 } 10752 10753 /* 10754 * ufs_dev_wlun_template - describes ufs device wlun 10755 * ufs-device wlun - used to send pm commands 10756 * All luns are consumers of ufs-device wlun. 10757 * 10758 * Currently, no sd driver is present for wluns. 10759 * Hence the no specific pm operations are performed. 10760 * With ufs design, SSU should be sent to ufs-device wlun. 10761 * Hence register a scsi driver for ufs wluns only. 10762 */ 10763 static struct scsi_driver ufs_dev_wlun_template = { 10764 .gendrv = { 10765 .name = "ufs_device_wlun", 10766 .owner = THIS_MODULE, 10767 .probe = ufshcd_wl_probe, 10768 .remove = ufshcd_wl_remove, 10769 .pm = &ufshcd_wl_pm_ops, 10770 .shutdown = ufshcd_wl_shutdown, 10771 }, 10772 }; 10773 10774 static int __init ufshcd_core_init(void) 10775 { 10776 int ret; 10777 10778 ufshcd_check_header_layout(); 10779 10780 ufs_debugfs_init(); 10781 10782 ret = scsi_register_driver(&ufs_dev_wlun_template.gendrv); 10783 if (ret) 10784 ufs_debugfs_exit(); 10785 return ret; 10786 } 10787 10788 static void __exit ufshcd_core_exit(void) 10789 { 10790 ufs_debugfs_exit(); 10791 scsi_unregister_driver(&ufs_dev_wlun_template.gendrv); 10792 } 10793 10794 module_init(ufshcd_core_init); 10795 module_exit(ufshcd_core_exit); 10796 10797 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 10798 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 10799 MODULE_DESCRIPTION("Generic UFS host controller driver Core"); 10800 MODULE_SOFTDEP("pre: governor_simpleondemand"); 10801 MODULE_LICENSE("GPL"); 10802