1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/tty_flip.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/of.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/delay.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/console.h> 27 #include <linux/pm_qos.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sys_soc.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 #define OMAP_UART_REGSHIFT 2 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39 #define OMAP_DMA_TX_KICK (1 << 2) 40 /* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45 #define UART_HAS_EFR2 BIT(4) 46 #define UART_HAS_RHR_IT_DIS BIT(5) 47 #define UART_RX_TIMEOUT_QUIRK BIT(6) 48 #define UART_HAS_NATIVE_RS485 BIT(7) 49 50 #define OMAP_UART_FCR_RX_TRIG 6 51 #define OMAP_UART_FCR_TX_TRIG 4 52 53 /* SCR register bitmasks */ 54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 56 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 57 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 58 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 59 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 60 61 /* MVR register bitmasks */ 62 #define OMAP_UART_MVR_SCHEME_SHIFT 30 63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 65 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 66 #define OMAP_UART_MVR_MAJ_MASK 0x700 67 #define OMAP_UART_MVR_MAJ_SHIFT 8 68 #define OMAP_UART_MVR_MIN_MASK 0x3f 69 70 /* SYSC register bitmasks */ 71 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 72 73 /* SYSS register bitmasks */ 74 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 75 76 #define UART_TI752_TLR_TX 0 77 #define UART_TI752_TLR_RX 4 78 79 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 80 #define TRIGGER_FCR_MASK(x) (x & 3) 81 82 /* Enable XON/XOFF flow control on output */ 83 #define OMAP_UART_SW_TX 0x08 84 /* Enable XON/XOFF flow control on input */ 85 #define OMAP_UART_SW_RX 0x02 86 87 #define OMAP_UART_WER_MOD_WKUP 0x7f 88 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 89 90 #define TX_TRIGGER 1 91 #define RX_TRIGGER 48 92 93 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 94 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 95 96 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 97 98 #define OMAP_UART_REV_46 0x0406 99 #define OMAP_UART_REV_52 0x0502 100 #define OMAP_UART_REV_63 0x0603 101 102 /* Interrupt Enable Register 2 */ 103 #define UART_OMAP_IER2 0x1B 104 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 105 106 /* Mode Definition Register 3 */ 107 #define UART_OMAP_MDR3 0x20 108 #define UART_OMAP_MDR3_DIR_POL BIT(3) 109 #define UART_OMAP_MDR3_DIR_EN BIT(4) 110 111 /* Enhanced features register 2 */ 112 #define UART_OMAP_EFR2 0x23 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 114 115 /* RX FIFO occupancy indicator */ 116 #define UART_OMAP_RX_LVL 0x19 117 118 struct omap8250_priv { 119 void __iomem *membase; 120 int line; 121 u8 habit; 122 u8 mdr1; 123 u8 mdr3; 124 u8 efr; 125 u8 scr; 126 u8 wer; 127 u8 xon; 128 u8 xoff; 129 u8 delayed_restore; 130 u16 quot; 131 132 u8 tx_trigger; 133 u8 rx_trigger; 134 atomic_t active; 135 bool is_suspending; 136 int wakeirq; 137 int wakeups_enabled; 138 u32 latency; 139 u32 calc_latency; 140 struct pm_qos_request pm_qos_request; 141 struct work_struct qos_work; 142 struct uart_8250_dma omap8250_dma; 143 spinlock_t rx_dma_lock; 144 bool rx_dma_broken; 145 bool throttled; 146 }; 147 148 struct omap8250_dma_params { 149 u32 rx_size; 150 u8 rx_trigger; 151 u8 tx_trigger; 152 }; 153 154 struct omap8250_platdata { 155 struct omap8250_dma_params *dma_params; 156 u8 habit; 157 }; 158 159 #ifdef CONFIG_SERIAL_8250_DMA 160 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 161 #else 162 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 163 #endif 164 165 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 166 { 167 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 168 } 169 170 /* 171 * Called on runtime PM resume path from omap8250_restore_regs(), and 172 * omap8250_set_mctrl(). 173 */ 174 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 175 { 176 struct uart_8250_port *up = up_to_u8250p(port); 177 struct omap8250_priv *priv = up->port.private_data; 178 u8 lcr; 179 180 serial8250_do_set_mctrl(port, mctrl); 181 182 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 183 /* 184 * Turn off autoRTS if RTS is lowered and restore autoRTS 185 * setting if RTS is raised 186 */ 187 lcr = serial_in(up, UART_LCR); 188 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 189 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 190 priv->efr |= UART_EFR_RTS; 191 else 192 priv->efr &= ~UART_EFR_RTS; 193 serial_out(up, UART_EFR, priv->efr); 194 serial_out(up, UART_LCR, lcr); 195 } 196 } 197 198 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 199 { 200 int err; 201 202 err = pm_runtime_resume_and_get(port->dev); 203 if (err) 204 return; 205 206 __omap8250_set_mctrl(port, mctrl); 207 208 pm_runtime_mark_last_busy(port->dev); 209 pm_runtime_put_autosuspend(port->dev); 210 } 211 212 /* 213 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 214 * The access to uart register after MDR1 Access 215 * causes UART to corrupt data. 216 * 217 * Need a delay = 218 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 219 * give 10 times as much 220 */ 221 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 222 struct omap8250_priv *priv) 223 { 224 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 225 udelay(2); 226 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 227 UART_FCR_CLEAR_RCVR); 228 } 229 230 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 231 struct omap8250_priv *priv) 232 { 233 unsigned int uartclk = port->uartclk; 234 unsigned int div_13, div_16; 235 unsigned int abs_d13, abs_d16; 236 237 /* 238 * Old custom speed handling. 239 */ 240 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 241 priv->quot = port->custom_divisor & UART_DIV_MAX; 242 /* 243 * I assume that nobody is using this. But hey, if somebody 244 * would like to specify the divisor _and_ the mode then the 245 * driver is ready and waiting for it. 246 */ 247 if (port->custom_divisor & (1 << 16)) 248 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 249 else 250 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 251 return; 252 } 253 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 254 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 255 256 if (!div_13) 257 div_13 = 1; 258 if (!div_16) 259 div_16 = 1; 260 261 abs_d13 = abs(baud - uartclk / 13 / div_13); 262 abs_d16 = abs(baud - uartclk / 16 / div_16); 263 264 if (abs_d13 >= abs_d16) { 265 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 266 priv->quot = div_16; 267 } else { 268 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 269 priv->quot = div_13; 270 } 271 } 272 273 static void omap8250_update_scr(struct uart_8250_port *up, 274 struct omap8250_priv *priv) 275 { 276 u8 old_scr; 277 278 old_scr = serial_in(up, UART_OMAP_SCR); 279 if (old_scr == priv->scr) 280 return; 281 282 /* 283 * The manual recommends not to enable the DMA mode selector in the SCR 284 * (instead of the FCR) register _and_ selecting the DMA mode as one 285 * register write because this may lead to malfunction. 286 */ 287 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 288 serial_out(up, UART_OMAP_SCR, 289 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 290 serial_out(up, UART_OMAP_SCR, priv->scr); 291 } 292 293 static void omap8250_update_mdr1(struct uart_8250_port *up, 294 struct omap8250_priv *priv) 295 { 296 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 297 omap_8250_mdr1_errataset(up, priv); 298 else 299 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 300 } 301 302 static void omap8250_restore_regs(struct uart_8250_port *up) 303 { 304 struct omap8250_priv *priv = up->port.private_data; 305 struct uart_8250_dma *dma = up->dma; 306 u8 mcr = serial8250_in_MCR(up); 307 308 /* Port locked to synchronize UART_IER access against the console. */ 309 lockdep_assert_held_once(&up->port.lock); 310 311 if (dma && dma->tx_running) { 312 /* 313 * TCSANOW requests the change to occur immediately however if 314 * we have a TX-DMA operation in progress then it has been 315 * observed that it might stall and never complete. Therefore we 316 * delay DMA completes to prevent this hang from happen. 317 */ 318 priv->delayed_restore = 1; 319 return; 320 } 321 322 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 323 serial_out(up, UART_EFR, UART_EFR_ECB); 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 326 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 327 serial_out(up, UART_FCR, up->fcr); 328 329 omap8250_update_scr(up, priv); 330 331 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 332 333 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 334 OMAP_UART_TCR_HALT(52)); 335 serial_out(up, UART_TI752_TLR, 336 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 337 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 338 339 serial_out(up, UART_LCR, 0); 340 341 /* drop TCR + TLR access, we setup XON/XOFF later */ 342 serial8250_out_MCR(up, mcr); 343 344 serial_out(up, UART_IER, up->ier); 345 346 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 347 serial_dl_write(up, priv->quot); 348 349 serial_out(up, UART_EFR, priv->efr); 350 351 /* Configure flow control */ 352 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 353 serial_out(up, UART_XON1, priv->xon); 354 serial_out(up, UART_XOFF1, priv->xoff); 355 356 serial_out(up, UART_LCR, up->lcr); 357 358 omap8250_update_mdr1(up, priv); 359 360 __omap8250_set_mctrl(&up->port, up->port.mctrl); 361 362 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 363 364 if (up->port.rs485.flags & SER_RS485_ENABLED && 365 up->port.rs485_config == serial8250_em485_config) 366 serial8250_em485_stop_tx(up); 367 } 368 369 /* 370 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 371 * some differences in how we want to handle flow control. 372 */ 373 static void omap_8250_set_termios(struct uart_port *port, 374 struct ktermios *termios, 375 const struct ktermios *old) 376 { 377 struct uart_8250_port *up = up_to_u8250p(port); 378 struct omap8250_priv *priv = up->port.private_data; 379 unsigned char cval = 0; 380 unsigned int baud; 381 382 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 383 384 if (termios->c_cflag & CSTOPB) 385 cval |= UART_LCR_STOP; 386 if (termios->c_cflag & PARENB) 387 cval |= UART_LCR_PARITY; 388 if (!(termios->c_cflag & PARODD)) 389 cval |= UART_LCR_EPAR; 390 if (termios->c_cflag & CMSPAR) 391 cval |= UART_LCR_SPAR; 392 393 /* 394 * Ask the core to calculate the divisor for us. 395 */ 396 baud = uart_get_baud_rate(port, termios, old, 397 port->uartclk / 16 / UART_DIV_MAX, 398 port->uartclk / 13); 399 omap_8250_get_divisor(port, baud, priv); 400 401 /* 402 * Ok, we're now changing the port state. Do it with 403 * interrupts disabled. 404 */ 405 pm_runtime_get_sync(port->dev); 406 uart_port_lock_irq(port); 407 408 /* 409 * Update the per-port timeout. 410 */ 411 uart_update_timeout(port, termios->c_cflag, baud); 412 413 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 414 if (termios->c_iflag & INPCK) 415 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 416 if (termios->c_iflag & (IGNBRK | PARMRK)) 417 up->port.read_status_mask |= UART_LSR_BI; 418 419 /* 420 * Characters to ignore 421 */ 422 up->port.ignore_status_mask = 0; 423 if (termios->c_iflag & IGNPAR) 424 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 425 if (termios->c_iflag & IGNBRK) { 426 up->port.ignore_status_mask |= UART_LSR_BI; 427 /* 428 * If we're ignoring parity and break indicators, 429 * ignore overruns too (for real raw support). 430 */ 431 if (termios->c_iflag & IGNPAR) 432 up->port.ignore_status_mask |= UART_LSR_OE; 433 } 434 435 /* 436 * ignore all characters if CREAD is not set 437 */ 438 if ((termios->c_cflag & CREAD) == 0) 439 up->port.ignore_status_mask |= UART_LSR_DR; 440 441 /* 442 * Modem status interrupts 443 */ 444 up->ier &= ~UART_IER_MSI; 445 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 446 up->ier |= UART_IER_MSI; 447 448 up->lcr = cval; 449 /* Up to here it was mostly serial8250_do_set_termios() */ 450 451 /* 452 * We enable TRIG_GRANU for RX and TX and additionally we set 453 * SCR_TX_EMPTY bit. The result is the following: 454 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 455 * - less than RX_TRIGGER number of bytes will also cause an interrupt 456 * once the UART decides that there no new bytes arriving. 457 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 458 * empty - the trigger level is ignored here. 459 * 460 * Once DMA is enabled: 461 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 462 * bytes in the TX FIFO. On each assert the DMA engine will move 463 * TX_TRIGGER bytes into the FIFO. 464 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 465 * the FIFO and move RX_TRIGGER bytes. 466 * This is because threshold and trigger values are the same. 467 */ 468 up->fcr = UART_FCR_ENABLE_FIFO; 469 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 470 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 471 472 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 473 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 474 475 if (up->dma) 476 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 477 OMAP_UART_SCR_DMAMODE_CTL; 478 479 priv->xon = termios->c_cc[VSTART]; 480 priv->xoff = termios->c_cc[VSTOP]; 481 482 priv->efr = 0; 483 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 484 485 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 486 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 487 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 488 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 489 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 490 priv->efr |= UART_EFR_CTS; 491 } else if (up->port.flags & UPF_SOFT_FLOW) { 492 /* 493 * OMAP rx s/w flow control is borked; the transmitter remains 494 * stuck off even if rx flow control is subsequently disabled 495 */ 496 497 /* 498 * IXOFF Flag: 499 * Enable XON/XOFF flow control on output. 500 * Transmit XON1, XOFF1 501 */ 502 if (termios->c_iflag & IXOFF) { 503 up->port.status |= UPSTAT_AUTOXOFF; 504 priv->efr |= OMAP_UART_SW_TX; 505 } 506 } 507 omap8250_restore_regs(up); 508 509 uart_port_unlock_irq(&up->port); 510 pm_runtime_mark_last_busy(port->dev); 511 pm_runtime_put_autosuspend(port->dev); 512 513 /* calculate wakeup latency constraint */ 514 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 515 priv->latency = priv->calc_latency; 516 517 schedule_work(&priv->qos_work); 518 519 /* Don't rewrite B0 */ 520 if (tty_termios_baud_rate(termios)) 521 tty_termios_encode_baud_rate(termios, baud, baud); 522 } 523 524 /* same as 8250 except that we may have extra flow bits set in EFR */ 525 static void omap_8250_pm(struct uart_port *port, unsigned int state, 526 unsigned int oldstate) 527 { 528 struct uart_8250_port *up = up_to_u8250p(port); 529 u8 efr; 530 531 pm_runtime_get_sync(port->dev); 532 533 /* Synchronize UART_IER access against the console. */ 534 uart_port_lock_irq(port); 535 536 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 537 efr = serial_in(up, UART_EFR); 538 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 539 serial_out(up, UART_LCR, 0); 540 541 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 542 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 543 serial_out(up, UART_EFR, efr); 544 serial_out(up, UART_LCR, 0); 545 546 uart_port_unlock_irq(port); 547 548 pm_runtime_mark_last_busy(port->dev); 549 pm_runtime_put_autosuspend(port->dev); 550 } 551 552 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 553 struct omap8250_priv *priv) 554 { 555 static const struct soc_device_attribute k3_soc_devices[] = { 556 { .family = "AM65X", }, 557 { .family = "J721E", .revision = "SR1.0" }, 558 { /* sentinel */ } 559 }; 560 u32 mvr, scheme; 561 u16 revision, major, minor; 562 563 mvr = uart_read(priv, UART_OMAP_MVER); 564 565 /* Check revision register scheme */ 566 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 567 568 switch (scheme) { 569 case 0: /* Legacy Scheme: OMAP2/3 */ 570 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 571 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 572 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 573 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 574 break; 575 case 1: 576 /* New Scheme: OMAP4+ */ 577 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 578 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 579 OMAP_UART_MVR_MAJ_SHIFT; 580 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 581 break; 582 default: 583 dev_warn(up->port.dev, 584 "Unknown revision, defaulting to highest\n"); 585 /* highest possible revision */ 586 major = 0xff; 587 minor = 0xff; 588 } 589 /* normalize revision for the driver */ 590 revision = UART_BUILD_REVISION(major, minor); 591 592 switch (revision) { 593 case OMAP_UART_REV_46: 594 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 595 break; 596 case OMAP_UART_REV_52: 597 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 598 OMAP_UART_WER_HAS_TX_WAKEUP; 599 break; 600 case OMAP_UART_REV_63: 601 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 602 OMAP_UART_WER_HAS_TX_WAKEUP; 603 break; 604 default: 605 break; 606 } 607 608 /* 609 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 610 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 611 * to enable errata workaround. 612 */ 613 if (soc_device_match(k3_soc_devices)) 614 priv->habit &= ~UART_HAS_RHR_IT_DIS; 615 } 616 617 static void omap8250_uart_qos_work(struct work_struct *work) 618 { 619 struct omap8250_priv *priv; 620 621 priv = container_of(work, struct omap8250_priv, qos_work); 622 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 623 } 624 625 #ifdef CONFIG_SERIAL_8250_DMA 626 static int omap_8250_dma_handle_irq(struct uart_port *port); 627 #endif 628 629 static irqreturn_t omap8250_irq(int irq, void *dev_id) 630 { 631 struct omap8250_priv *priv = dev_id; 632 struct uart_8250_port *up = serial8250_get_port(priv->line); 633 struct uart_port *port = &up->port; 634 unsigned int iir, lsr; 635 int ret; 636 637 pm_runtime_get_noresume(port->dev); 638 639 /* Shallow idle state wake-up to an IO interrupt? */ 640 if (atomic_add_unless(&priv->active, 1, 1)) { 641 priv->latency = priv->calc_latency; 642 schedule_work(&priv->qos_work); 643 } 644 645 #ifdef CONFIG_SERIAL_8250_DMA 646 if (up->dma) { 647 ret = omap_8250_dma_handle_irq(port); 648 pm_runtime_mark_last_busy(port->dev); 649 pm_runtime_put(port->dev); 650 return IRQ_RETVAL(ret); 651 } 652 #endif 653 654 lsr = serial_port_in(port, UART_LSR); 655 iir = serial_port_in(port, UART_IIR); 656 ret = serial8250_handle_irq(port, iir); 657 658 /* 659 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 660 * FIFO has been drained, in which case a dummy read of RX FIFO 661 * is required to clear RX TIMEOUT condition. 662 */ 663 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 664 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 665 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 666 serial_port_in(port, UART_RX); 667 } 668 669 /* Stop processing interrupts on input overrun */ 670 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 671 unsigned long delay; 672 673 /* Synchronize UART_IER access against the console. */ 674 uart_port_lock(port); 675 up->ier = port->serial_in(port, UART_IER); 676 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 677 port->ops->stop_rx(port); 678 } else { 679 /* Keep restarting the timer until 680 * the input overrun subsides. 681 */ 682 cancel_delayed_work(&up->overrun_backoff); 683 } 684 uart_port_unlock(port); 685 686 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 687 schedule_delayed_work(&up->overrun_backoff, delay); 688 } 689 690 pm_runtime_mark_last_busy(port->dev); 691 pm_runtime_put(port->dev); 692 693 return IRQ_RETVAL(ret); 694 } 695 696 static int omap_8250_startup(struct uart_port *port) 697 { 698 struct uart_8250_port *up = up_to_u8250p(port); 699 struct omap8250_priv *priv = port->private_data; 700 struct uart_8250_dma *dma = &priv->omap8250_dma; 701 int ret; 702 703 if (priv->wakeirq) { 704 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 705 if (ret) 706 return ret; 707 } 708 709 pm_runtime_get_sync(port->dev); 710 711 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 712 713 serial_out(up, UART_LCR, UART_LCR_WLEN8); 714 715 up->lsr_saved_flags = 0; 716 up->msr_saved_flags = 0; 717 718 /* Disable DMA for console UART */ 719 if (dma->fn && !uart_console(port)) { 720 up->dma = &priv->omap8250_dma; 721 ret = serial8250_request_dma(up); 722 if (ret) { 723 dev_warn_ratelimited(port->dev, 724 "failed to request DMA\n"); 725 up->dma = NULL; 726 } 727 } else { 728 up->dma = NULL; 729 } 730 731 /* Synchronize UART_IER access against the console. */ 732 uart_port_lock_irq(port); 733 up->ier = UART_IER_RLSI | UART_IER_RDI; 734 serial_out(up, UART_IER, up->ier); 735 uart_port_unlock_irq(port); 736 737 #ifdef CONFIG_PM 738 up->capabilities |= UART_CAP_RPM; 739 #endif 740 741 /* Enable module level wake up */ 742 priv->wer = OMAP_UART_WER_MOD_WKUP; 743 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 744 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 745 serial_out(up, UART_OMAP_WER, priv->wer); 746 747 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 748 uart_port_lock_irq(port); 749 up->dma->rx_dma(up); 750 uart_port_unlock_irq(port); 751 } 752 753 enable_irq(up->port.irq); 754 755 pm_runtime_mark_last_busy(port->dev); 756 pm_runtime_put_autosuspend(port->dev); 757 return 0; 758 } 759 760 static void omap_8250_shutdown(struct uart_port *port) 761 { 762 struct uart_8250_port *up = up_to_u8250p(port); 763 struct omap8250_priv *priv = port->private_data; 764 765 flush_work(&priv->qos_work); 766 if (up->dma) 767 omap_8250_rx_dma_flush(up); 768 769 pm_runtime_get_sync(port->dev); 770 771 serial_out(up, UART_OMAP_WER, 0); 772 if (priv->habit & UART_HAS_EFR2) 773 serial_out(up, UART_OMAP_EFR2, 0x0); 774 775 /* Synchronize UART_IER access against the console. */ 776 uart_port_lock_irq(port); 777 up->ier = 0; 778 serial_out(up, UART_IER, 0); 779 uart_port_unlock_irq(port); 780 disable_irq_nosync(up->port.irq); 781 dev_pm_clear_wake_irq(port->dev); 782 783 serial8250_release_dma(up); 784 up->dma = NULL; 785 786 /* 787 * Disable break condition and FIFOs 788 */ 789 if (up->lcr & UART_LCR_SBC) 790 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 791 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 792 793 pm_runtime_mark_last_busy(port->dev); 794 pm_runtime_put_autosuspend(port->dev); 795 } 796 797 static void omap_8250_throttle(struct uart_port *port) 798 { 799 struct omap8250_priv *priv = port->private_data; 800 unsigned long flags; 801 802 pm_runtime_get_sync(port->dev); 803 804 uart_port_lock_irqsave(port, &flags); 805 port->ops->stop_rx(port); 806 priv->throttled = true; 807 uart_port_unlock_irqrestore(port, flags); 808 809 pm_runtime_mark_last_busy(port->dev); 810 pm_runtime_put_autosuspend(port->dev); 811 } 812 813 static void omap_8250_unthrottle(struct uart_port *port) 814 { 815 struct omap8250_priv *priv = port->private_data; 816 struct uart_8250_port *up = up_to_u8250p(port); 817 unsigned long flags; 818 819 pm_runtime_get_sync(port->dev); 820 821 /* Synchronize UART_IER access against the console. */ 822 uart_port_lock_irqsave(port, &flags); 823 priv->throttled = false; 824 if (up->dma) 825 up->dma->rx_dma(up); 826 up->ier |= UART_IER_RLSI | UART_IER_RDI; 827 port->read_status_mask |= UART_LSR_DR; 828 serial_out(up, UART_IER, up->ier); 829 uart_port_unlock_irqrestore(port, flags); 830 831 pm_runtime_mark_last_busy(port->dev); 832 pm_runtime_put_autosuspend(port->dev); 833 } 834 835 static int omap8250_rs485_config(struct uart_port *port, 836 struct ktermios *termios, 837 struct serial_rs485 *rs485) 838 { 839 struct omap8250_priv *priv = port->private_data; 840 struct uart_8250_port *up = up_to_u8250p(port); 841 u32 fixed_delay_rts_before_send = 0; 842 u32 fixed_delay_rts_after_send = 0; 843 unsigned int baud; 844 845 /* 846 * There is a fixed delay of 3 bit clock cycles after the TX shift 847 * register is going empty to allow time for the stop bit to transition 848 * through the transceiver before direction is changed to receive. 849 * 850 * Additionally there appears to be a 1 bit clock delay between writing 851 * to the THR register and transmission of the start bit, per page 8783 852 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 853 */ 854 if (priv->quot) { 855 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 856 baud = port->uartclk / (16 * priv->quot); 857 else 858 baud = port->uartclk / (13 * priv->quot); 859 860 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 861 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 862 } 863 864 /* 865 * Fall back to RS485 software emulation if the UART is missing 866 * hardware support, if the device tree specifies an mctrl_gpio 867 * (indicates that RTS is unavailable due to a pinmux conflict) 868 * or if the requested delays exceed the fixed hardware delays. 869 */ 870 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 871 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 872 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 873 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 874 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 875 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 876 877 port->rs485_config = serial8250_em485_config; 878 return serial8250_em485_config(port, termios, rs485); 879 } 880 881 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 882 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 883 884 if (rs485->flags & SER_RS485_ENABLED) 885 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 886 else 887 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 888 889 /* 890 * Retain same polarity semantics as RS485 software emulation, 891 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 892 */ 893 if (rs485->flags & SER_RS485_RTS_ON_SEND) 894 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 895 else 896 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 897 898 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 899 900 return 0; 901 } 902 903 #ifdef CONFIG_SERIAL_8250_DMA 904 static int omap_8250_rx_dma(struct uart_8250_port *p); 905 906 /* Must be called while priv->rx_dma_lock is held */ 907 static void __dma_rx_do_complete(struct uart_8250_port *p) 908 { 909 struct uart_8250_dma *dma = p->dma; 910 struct tty_port *tty_port = &p->port.state->port; 911 struct omap8250_priv *priv = p->port.private_data; 912 struct dma_chan *rxchan = dma->rxchan; 913 dma_cookie_t cookie; 914 struct dma_tx_state state; 915 int count; 916 int ret; 917 u32 reg; 918 919 if (!dma->rx_running) 920 goto out; 921 922 cookie = dma->rx_cookie; 923 dma->rx_running = 0; 924 925 /* Re-enable RX FIFO interrupt now that transfer is complete */ 926 if (priv->habit & UART_HAS_RHR_IT_DIS) { 927 reg = serial_in(p, UART_OMAP_IER2); 928 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 929 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 930 } 931 932 dmaengine_tx_status(rxchan, cookie, &state); 933 934 count = dma->rx_size - state.residue + state.in_flight_bytes; 935 if (count < dma->rx_size) { 936 dmaengine_terminate_async(rxchan); 937 938 /* 939 * Poll for teardown to complete which guarantees in 940 * flight data is drained. 941 */ 942 if (state.in_flight_bytes) { 943 int poll_count = 25; 944 945 while (dmaengine_tx_status(rxchan, cookie, NULL) && 946 poll_count--) 947 cpu_relax(); 948 949 if (poll_count == -1) 950 dev_err(p->port.dev, "teardown incomplete\n"); 951 } 952 } 953 if (!count) 954 goto out; 955 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 956 957 p->port.icount.rx += ret; 958 p->port.icount.buf_overrun += count - ret; 959 out: 960 961 tty_flip_buffer_push(tty_port); 962 } 963 964 static void __dma_rx_complete(void *param) 965 { 966 struct uart_8250_port *p = param; 967 struct omap8250_priv *priv = p->port.private_data; 968 struct uart_8250_dma *dma = p->dma; 969 struct dma_tx_state state; 970 unsigned long flags; 971 972 /* Synchronize UART_IER access against the console. */ 973 uart_port_lock_irqsave(&p->port, &flags); 974 975 /* 976 * If the tx status is not DMA_COMPLETE, then this is a delayed 977 * completion callback. A previous RX timeout flush would have 978 * already pushed the data, so exit. 979 */ 980 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 981 DMA_COMPLETE) { 982 uart_port_unlock_irqrestore(&p->port, flags); 983 return; 984 } 985 __dma_rx_do_complete(p); 986 if (!priv->throttled) { 987 p->ier |= UART_IER_RLSI | UART_IER_RDI; 988 serial_out(p, UART_IER, p->ier); 989 if (!(priv->habit & UART_HAS_EFR2)) 990 omap_8250_rx_dma(p); 991 } 992 993 uart_port_unlock_irqrestore(&p->port, flags); 994 } 995 996 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 997 { 998 struct omap8250_priv *priv = p->port.private_data; 999 struct uart_8250_dma *dma = p->dma; 1000 struct dma_tx_state state; 1001 unsigned long flags; 1002 int ret; 1003 1004 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1005 1006 if (!dma->rx_running) { 1007 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1008 return; 1009 } 1010 1011 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1012 if (ret == DMA_IN_PROGRESS) { 1013 ret = dmaengine_pause(dma->rxchan); 1014 if (WARN_ON_ONCE(ret)) 1015 priv->rx_dma_broken = true; 1016 } 1017 __dma_rx_do_complete(p); 1018 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1019 } 1020 1021 static int omap_8250_rx_dma(struct uart_8250_port *p) 1022 { 1023 struct omap8250_priv *priv = p->port.private_data; 1024 struct uart_8250_dma *dma = p->dma; 1025 int err = 0; 1026 struct dma_async_tx_descriptor *desc; 1027 unsigned long flags; 1028 u32 reg; 1029 1030 /* Port locked to synchronize UART_IER access against the console. */ 1031 lockdep_assert_held_once(&p->port.lock); 1032 1033 if (priv->rx_dma_broken) 1034 return -EINVAL; 1035 1036 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1037 1038 if (dma->rx_running) { 1039 enum dma_status state; 1040 1041 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1042 if (state == DMA_COMPLETE) { 1043 /* 1044 * Disable RX interrupts to allow RX DMA completion 1045 * callback to run. 1046 */ 1047 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1048 serial_out(p, UART_IER, p->ier); 1049 } 1050 goto out; 1051 } 1052 1053 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1054 dma->rx_size, DMA_DEV_TO_MEM, 1055 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1056 if (!desc) { 1057 err = -EBUSY; 1058 goto out; 1059 } 1060 1061 dma->rx_running = 1; 1062 desc->callback = __dma_rx_complete; 1063 desc->callback_param = p; 1064 1065 dma->rx_cookie = dmaengine_submit(desc); 1066 1067 /* 1068 * Disable RX FIFO interrupt while RX DMA is enabled, else 1069 * spurious interrupt may be raised when data is in the RX FIFO 1070 * but is yet to be drained by DMA. 1071 */ 1072 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1073 reg = serial_in(p, UART_OMAP_IER2); 1074 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1075 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 1076 } 1077 1078 dma_async_issue_pending(dma->rxchan); 1079 out: 1080 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1081 return err; 1082 } 1083 1084 static int omap_8250_tx_dma(struct uart_8250_port *p); 1085 1086 static void omap_8250_dma_tx_complete(void *param) 1087 { 1088 struct uart_8250_port *p = param; 1089 struct uart_8250_dma *dma = p->dma; 1090 struct circ_buf *xmit = &p->port.state->xmit; 1091 unsigned long flags; 1092 bool en_thri = false; 1093 struct omap8250_priv *priv = p->port.private_data; 1094 1095 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1096 UART_XMIT_SIZE, DMA_TO_DEVICE); 1097 1098 uart_port_lock_irqsave(&p->port, &flags); 1099 1100 dma->tx_running = 0; 1101 1102 uart_xmit_advance(&p->port, dma->tx_size); 1103 1104 if (priv->delayed_restore) { 1105 priv->delayed_restore = 0; 1106 omap8250_restore_regs(p); 1107 } 1108 1109 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1110 uart_write_wakeup(&p->port); 1111 1112 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1113 int ret; 1114 1115 ret = omap_8250_tx_dma(p); 1116 if (ret) 1117 en_thri = true; 1118 } else if (p->capabilities & UART_CAP_RPM) { 1119 en_thri = true; 1120 } 1121 1122 if (en_thri) { 1123 dma->tx_err = 1; 1124 serial8250_set_THRI(p); 1125 } 1126 1127 uart_port_unlock_irqrestore(&p->port, flags); 1128 } 1129 1130 static int omap_8250_tx_dma(struct uart_8250_port *p) 1131 { 1132 struct uart_8250_dma *dma = p->dma; 1133 struct omap8250_priv *priv = p->port.private_data; 1134 struct circ_buf *xmit = &p->port.state->xmit; 1135 struct dma_async_tx_descriptor *desc; 1136 unsigned int skip_byte = 0; 1137 int ret; 1138 1139 if (dma->tx_running) 1140 return 0; 1141 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1142 1143 /* 1144 * Even if no data, we need to return an error for the two cases 1145 * below so serial8250_tx_chars() is invoked and properly clears 1146 * THRI and/or runtime suspend. 1147 */ 1148 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1149 ret = -EBUSY; 1150 goto err; 1151 } 1152 serial8250_clear_THRI(p); 1153 return 0; 1154 } 1155 1156 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1157 if (priv->habit & OMAP_DMA_TX_KICK) { 1158 u8 tx_lvl; 1159 1160 /* 1161 * We need to put the first byte into the FIFO in order to start 1162 * the DMA transfer. For transfers smaller than four bytes we 1163 * don't bother doing DMA at all. It seem not matter if there 1164 * are still bytes in the FIFO from the last transfer (in case 1165 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1166 * leaving the FIFO seem not to trigger the DMA transfer. It is 1167 * really the byte that we put into the FIFO. 1168 * If the FIFO is already full then we most likely got here from 1169 * omap_8250_dma_tx_complete(). And this means the DMA engine 1170 * just completed its work. We don't have to wait the complete 1171 * 86us at 115200,8n1 but around 60us (not to mention lower 1172 * baudrates). So in that case we take the interrupt and try 1173 * again with an empty FIFO. 1174 */ 1175 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1176 if (tx_lvl == p->tx_loadsz) { 1177 ret = -EBUSY; 1178 goto err; 1179 } 1180 if (dma->tx_size < 4) { 1181 ret = -EINVAL; 1182 goto err; 1183 } 1184 skip_byte = 1; 1185 } 1186 1187 desc = dmaengine_prep_slave_single(dma->txchan, 1188 dma->tx_addr + xmit->tail + skip_byte, 1189 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1190 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1191 if (!desc) { 1192 ret = -EBUSY; 1193 goto err; 1194 } 1195 1196 dma->tx_running = 1; 1197 1198 desc->callback = omap_8250_dma_tx_complete; 1199 desc->callback_param = p; 1200 1201 dma->tx_cookie = dmaengine_submit(desc); 1202 1203 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1204 UART_XMIT_SIZE, DMA_TO_DEVICE); 1205 1206 dma_async_issue_pending(dma->txchan); 1207 if (dma->tx_err) 1208 dma->tx_err = 0; 1209 1210 serial8250_clear_THRI(p); 1211 if (skip_byte) 1212 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1213 return 0; 1214 err: 1215 dma->tx_err = 1; 1216 return ret; 1217 } 1218 1219 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1220 { 1221 switch (iir & 0x3f) { 1222 case UART_IIR_RLSI: 1223 case UART_IIR_RX_TIMEOUT: 1224 case UART_IIR_RDI: 1225 omap_8250_rx_dma_flush(up); 1226 return true; 1227 } 1228 return omap_8250_rx_dma(up); 1229 } 1230 1231 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1232 { 1233 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1234 (iir & UART_IIR_RDI)) { 1235 if (handle_rx_dma(up, iir)) { 1236 status = serial8250_rx_chars(up, status); 1237 omap_8250_rx_dma(up); 1238 } 1239 } 1240 1241 return status; 1242 } 1243 1244 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1245 u16 status) 1246 { 1247 /* Port locked to synchronize UART_IER access against the console. */ 1248 lockdep_assert_held_once(&up->port.lock); 1249 1250 /* 1251 * Queue a new transfer if FIFO has data. 1252 */ 1253 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1254 (up->ier & UART_IER_RDI)) { 1255 omap_8250_rx_dma(up); 1256 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1257 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1258 /* 1259 * Disable RX timeout, read IIR to clear 1260 * current timeout condition, clear EFR2 to 1261 * periodic timeouts, re-enable interrupts. 1262 */ 1263 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1264 serial_out(up, UART_IER, up->ier); 1265 omap_8250_rx_dma_flush(up); 1266 serial_in(up, UART_IIR); 1267 serial_out(up, UART_OMAP_EFR2, 0x0); 1268 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1269 serial_out(up, UART_IER, up->ier); 1270 } 1271 } 1272 1273 /* 1274 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1275 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1276 * use the default routine in the non-DMA case and this one for with DMA. 1277 */ 1278 static int omap_8250_dma_handle_irq(struct uart_port *port) 1279 { 1280 struct uart_8250_port *up = up_to_u8250p(port); 1281 struct omap8250_priv *priv = up->port.private_data; 1282 u16 status; 1283 u8 iir; 1284 1285 iir = serial_port_in(port, UART_IIR); 1286 if (iir & UART_IIR_NO_INT) { 1287 return IRQ_HANDLED; 1288 } 1289 1290 uart_port_lock(port); 1291 1292 status = serial_port_in(port, UART_LSR); 1293 1294 if (priv->habit & UART_HAS_EFR2) 1295 am654_8250_handle_rx_dma(up, iir, status); 1296 else 1297 status = omap_8250_handle_rx_dma(up, iir, status); 1298 1299 serial8250_modem_status(up); 1300 if (status & UART_LSR_THRE && up->dma->tx_err) { 1301 if (uart_tx_stopped(&up->port) || 1302 uart_circ_empty(&up->port.state->xmit)) { 1303 up->dma->tx_err = 0; 1304 serial8250_tx_chars(up); 1305 } else { 1306 /* 1307 * try again due to an earlier failer which 1308 * might have been resolved by now. 1309 */ 1310 if (omap_8250_tx_dma(up)) 1311 serial8250_tx_chars(up); 1312 } 1313 } 1314 1315 uart_unlock_and_check_sysrq(port); 1316 1317 return 1; 1318 } 1319 1320 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1321 { 1322 return false; 1323 } 1324 1325 #else 1326 1327 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1328 { 1329 return -EINVAL; 1330 } 1331 #endif 1332 1333 static int omap8250_no_handle_irq(struct uart_port *port) 1334 { 1335 /* IRQ has not been requested but handling irq? */ 1336 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1337 return 0; 1338 } 1339 1340 static struct omap8250_dma_params am654_dma = { 1341 .rx_size = SZ_2K, 1342 .rx_trigger = 1, 1343 .tx_trigger = TX_TRIGGER, 1344 }; 1345 1346 static struct omap8250_dma_params am33xx_dma = { 1347 .rx_size = RX_TRIGGER, 1348 .rx_trigger = RX_TRIGGER, 1349 .tx_trigger = TX_TRIGGER, 1350 }; 1351 1352 static struct omap8250_platdata am654_platdata = { 1353 .dma_params = &am654_dma, 1354 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1355 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1356 }; 1357 1358 static struct omap8250_platdata am33xx_platdata = { 1359 .dma_params = &am33xx_dma, 1360 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1361 }; 1362 1363 static struct omap8250_platdata omap4_platdata = { 1364 .dma_params = &am33xx_dma, 1365 .habit = UART_ERRATA_CLOCK_DISABLE, 1366 }; 1367 1368 static const struct of_device_id omap8250_dt_ids[] = { 1369 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1370 { .compatible = "ti,omap2-uart" }, 1371 { .compatible = "ti,omap3-uart" }, 1372 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1373 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1374 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1375 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1376 {}, 1377 }; 1378 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1379 1380 static int omap8250_probe(struct platform_device *pdev) 1381 { 1382 struct device_node *np = pdev->dev.of_node; 1383 struct omap8250_priv *priv; 1384 const struct omap8250_platdata *pdata; 1385 struct uart_8250_port up; 1386 struct resource *regs; 1387 void __iomem *membase; 1388 int irq, ret; 1389 1390 irq = platform_get_irq(pdev, 0); 1391 if (irq < 0) 1392 return irq; 1393 1394 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1395 if (!regs) { 1396 dev_err(&pdev->dev, "missing registers\n"); 1397 return -EINVAL; 1398 } 1399 1400 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1401 if (!priv) 1402 return -ENOMEM; 1403 1404 membase = devm_ioremap(&pdev->dev, regs->start, 1405 resource_size(regs)); 1406 if (!membase) 1407 return -ENODEV; 1408 1409 memset(&up, 0, sizeof(up)); 1410 up.port.dev = &pdev->dev; 1411 up.port.mapbase = regs->start; 1412 up.port.membase = membase; 1413 up.port.irq = irq; 1414 /* 1415 * It claims to be 16C750 compatible however it is a little different. 1416 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1417 * have) is enabled via EFR instead of MCR. The type is set here 8250 1418 * just to get things going. UNKNOWN does not work for a few reasons and 1419 * we don't need our own type since we don't use 8250's set_termios() 1420 * or pm callback. 1421 */ 1422 up.port.type = PORT_8250; 1423 up.port.iotype = UPIO_MEM; 1424 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1425 UPF_HARD_FLOW; 1426 up.port.private_data = priv; 1427 1428 up.port.regshift = OMAP_UART_REGSHIFT; 1429 up.port.fifosize = 64; 1430 up.tx_loadsz = 64; 1431 up.capabilities = UART_CAP_FIFO; 1432 #ifdef CONFIG_PM 1433 /* 1434 * Runtime PM is mostly transparent. However to do it right we need to a 1435 * TX empty interrupt before we can put the device to auto idle. So if 1436 * PM is not enabled we don't add that flag and can spare that one extra 1437 * interrupt in the TX path. 1438 */ 1439 up.capabilities |= UART_CAP_RPM; 1440 #endif 1441 up.port.set_termios = omap_8250_set_termios; 1442 up.port.set_mctrl = omap8250_set_mctrl; 1443 up.port.pm = omap_8250_pm; 1444 up.port.startup = omap_8250_startup; 1445 up.port.shutdown = omap_8250_shutdown; 1446 up.port.throttle = omap_8250_throttle; 1447 up.port.unthrottle = omap_8250_unthrottle; 1448 up.port.rs485_config = omap8250_rs485_config; 1449 /* same rs485_supported for software emulation and native RS485 */ 1450 up.port.rs485_supported = serial8250_em485_supported; 1451 up.rs485_start_tx = serial8250_em485_start_tx; 1452 up.rs485_stop_tx = serial8250_em485_stop_tx; 1453 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1454 1455 ret = of_alias_get_id(np, "serial"); 1456 if (ret < 0) { 1457 dev_err(&pdev->dev, "failed to get alias\n"); 1458 return ret; 1459 } 1460 up.port.line = ret; 1461 1462 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1463 struct clk *clk; 1464 1465 clk = devm_clk_get(&pdev->dev, NULL); 1466 if (IS_ERR(clk)) { 1467 if (PTR_ERR(clk) == -EPROBE_DEFER) 1468 return -EPROBE_DEFER; 1469 } else { 1470 up.port.uartclk = clk_get_rate(clk); 1471 } 1472 } 1473 1474 if (of_property_read_u32(np, "overrun-throttle-ms", 1475 &up.overrun_backoff_time_ms) != 0) 1476 up.overrun_backoff_time_ms = 0; 1477 1478 pdata = of_device_get_match_data(&pdev->dev); 1479 if (pdata) 1480 priv->habit |= pdata->habit; 1481 1482 if (!up.port.uartclk) { 1483 up.port.uartclk = DEFAULT_CLK_SPEED; 1484 dev_warn(&pdev->dev, 1485 "No clock speed specified: using default: %d\n", 1486 DEFAULT_CLK_SPEED); 1487 } 1488 1489 priv->membase = membase; 1490 priv->line = -ENODEV; 1491 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1492 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1493 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1494 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1495 1496 spin_lock_init(&priv->rx_dma_lock); 1497 1498 platform_set_drvdata(pdev, priv); 1499 1500 device_init_wakeup(&pdev->dev, true); 1501 pm_runtime_enable(&pdev->dev); 1502 pm_runtime_use_autosuspend(&pdev->dev); 1503 1504 /* 1505 * Disable runtime PM until autosuspend delay unless specifically 1506 * enabled by the user via sysfs. This is the historic way to 1507 * prevent an unsafe default policy with lossy characters on wake-up. 1508 * For serdev devices this is not needed, the policy can be managed by 1509 * the serdev driver. 1510 */ 1511 if (!of_get_available_child_count(pdev->dev.of_node)) 1512 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1513 1514 pm_runtime_get_sync(&pdev->dev); 1515 1516 omap_serial_fill_features_erratas(&up, priv); 1517 up.port.handle_irq = omap8250_no_handle_irq; 1518 priv->rx_trigger = RX_TRIGGER; 1519 priv->tx_trigger = TX_TRIGGER; 1520 #ifdef CONFIG_SERIAL_8250_DMA 1521 /* 1522 * Oh DMA support. If there are no DMA properties in the DT then 1523 * we will fall back to a generic DMA channel which does not 1524 * really work here. To ensure that we do not get a generic DMA 1525 * channel assigned, we have the the_no_dma_filter_fn() here. 1526 * To avoid "failed to request DMA" messages we check for DMA 1527 * properties in DT. 1528 */ 1529 ret = of_property_count_strings(np, "dma-names"); 1530 if (ret == 2) { 1531 struct omap8250_dma_params *dma_params = NULL; 1532 struct uart_8250_dma *dma = &priv->omap8250_dma; 1533 1534 dma->fn = the_no_dma_filter_fn; 1535 dma->tx_dma = omap_8250_tx_dma; 1536 dma->rx_dma = omap_8250_rx_dma; 1537 if (pdata) 1538 dma_params = pdata->dma_params; 1539 1540 if (dma_params) { 1541 dma->rx_size = dma_params->rx_size; 1542 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1543 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1544 priv->rx_trigger = dma_params->rx_trigger; 1545 priv->tx_trigger = dma_params->tx_trigger; 1546 } else { 1547 dma->rx_size = RX_TRIGGER; 1548 dma->rxconf.src_maxburst = RX_TRIGGER; 1549 dma->txconf.dst_maxburst = TX_TRIGGER; 1550 } 1551 } 1552 #endif 1553 1554 irq_set_status_flags(irq, IRQ_NOAUTOEN); 1555 ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0, 1556 dev_name(&pdev->dev), priv); 1557 if (ret < 0) 1558 return ret; 1559 1560 priv->wakeirq = irq_of_parse_and_map(np, 1); 1561 1562 ret = serial8250_register_8250_port(&up); 1563 if (ret < 0) { 1564 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1565 goto err; 1566 } 1567 priv->line = ret; 1568 pm_runtime_mark_last_busy(&pdev->dev); 1569 pm_runtime_put_autosuspend(&pdev->dev); 1570 return 0; 1571 err: 1572 pm_runtime_dont_use_autosuspend(&pdev->dev); 1573 pm_runtime_put_sync(&pdev->dev); 1574 flush_work(&priv->qos_work); 1575 pm_runtime_disable(&pdev->dev); 1576 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1577 return ret; 1578 } 1579 1580 static int omap8250_remove(struct platform_device *pdev) 1581 { 1582 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1583 struct uart_8250_port *up; 1584 int err; 1585 1586 err = pm_runtime_resume_and_get(&pdev->dev); 1587 if (err) 1588 return err; 1589 1590 up = serial8250_get_port(priv->line); 1591 omap_8250_shutdown(&up->port); 1592 serial8250_unregister_port(priv->line); 1593 priv->line = -ENODEV; 1594 pm_runtime_dont_use_autosuspend(&pdev->dev); 1595 pm_runtime_put_sync(&pdev->dev); 1596 flush_work(&priv->qos_work); 1597 pm_runtime_disable(&pdev->dev); 1598 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1599 device_init_wakeup(&pdev->dev, false); 1600 return 0; 1601 } 1602 1603 static int omap8250_prepare(struct device *dev) 1604 { 1605 struct omap8250_priv *priv = dev_get_drvdata(dev); 1606 1607 if (!priv) 1608 return 0; 1609 priv->is_suspending = true; 1610 return 0; 1611 } 1612 1613 static void omap8250_complete(struct device *dev) 1614 { 1615 struct omap8250_priv *priv = dev_get_drvdata(dev); 1616 1617 if (!priv) 1618 return; 1619 priv->is_suspending = false; 1620 } 1621 1622 static int omap8250_suspend(struct device *dev) 1623 { 1624 struct omap8250_priv *priv = dev_get_drvdata(dev); 1625 struct uart_8250_port *up = serial8250_get_port(priv->line); 1626 int err = 0; 1627 1628 serial8250_suspend_port(priv->line); 1629 1630 err = pm_runtime_resume_and_get(dev); 1631 if (err) 1632 return err; 1633 if (!device_may_wakeup(dev)) 1634 priv->wer = 0; 1635 serial_out(up, UART_OMAP_WER, priv->wer); 1636 if (uart_console(&up->port) && console_suspend_enabled) 1637 err = pm_runtime_force_suspend(dev); 1638 flush_work(&priv->qos_work); 1639 1640 return err; 1641 } 1642 1643 static int omap8250_resume(struct device *dev) 1644 { 1645 struct omap8250_priv *priv = dev_get_drvdata(dev); 1646 struct uart_8250_port *up = serial8250_get_port(priv->line); 1647 int err; 1648 1649 if (uart_console(&up->port) && console_suspend_enabled) { 1650 err = pm_runtime_force_resume(dev); 1651 if (err) 1652 return err; 1653 } 1654 1655 serial8250_resume_port(priv->line); 1656 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1657 pm_runtime_mark_last_busy(dev); 1658 pm_runtime_put_autosuspend(dev); 1659 1660 return 0; 1661 } 1662 1663 static int omap8250_lost_context(struct uart_8250_port *up) 1664 { 1665 u32 val; 1666 1667 val = serial_in(up, UART_OMAP_SCR); 1668 /* 1669 * If we lose context, then SCR is set to its reset value of zero. 1670 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1671 * among other bits, to never set the register back to zero again. 1672 */ 1673 if (!val) 1674 return 1; 1675 return 0; 1676 } 1677 1678 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1679 { 1680 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1681 } 1682 1683 /* TODO: in future, this should happen via API in drivers/reset/ */ 1684 static int omap8250_soft_reset(struct device *dev) 1685 { 1686 struct omap8250_priv *priv = dev_get_drvdata(dev); 1687 int timeout = 100; 1688 int sysc; 1689 int syss; 1690 1691 /* 1692 * At least on omap4, unused uarts may not idle after reset without 1693 * a basic scr dma configuration even with no dma in use. The 1694 * module clkctrl status bits will be 1 instead of 3 blocking idle 1695 * for the whole clockdomain. The softreset below will clear scr, 1696 * and we restore it on resume so this is safe to do on all SoCs 1697 * needing omap8250_soft_reset() quirk. Do it in two writes as 1698 * recommended in the comment for omap8250_update_scr(). 1699 */ 1700 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1701 uart_write(priv, UART_OMAP_SCR, 1702 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1703 1704 sysc = uart_read(priv, UART_OMAP_SYSC); 1705 1706 /* softreset the UART */ 1707 sysc |= OMAP_UART_SYSC_SOFTRESET; 1708 uart_write(priv, UART_OMAP_SYSC, sysc); 1709 1710 /* By experiments, 1us enough for reset complete on AM335x */ 1711 do { 1712 udelay(1); 1713 syss = uart_read(priv, UART_OMAP_SYSS); 1714 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1715 1716 if (!timeout) { 1717 dev_err(dev, "timed out waiting for reset done\n"); 1718 return -ETIMEDOUT; 1719 } 1720 1721 return 0; 1722 } 1723 1724 static int omap8250_runtime_suspend(struct device *dev) 1725 { 1726 struct omap8250_priv *priv = dev_get_drvdata(dev); 1727 struct uart_8250_port *up = NULL; 1728 1729 if (priv->line >= 0) 1730 up = serial8250_get_port(priv->line); 1731 1732 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1733 int ret; 1734 1735 ret = omap8250_soft_reset(dev); 1736 if (ret) 1737 return ret; 1738 1739 if (up) { 1740 /* Restore to UART mode after reset (for wakeup) */ 1741 omap8250_update_mdr1(up, priv); 1742 /* Restore wakeup enable register */ 1743 serial_out(up, UART_OMAP_WER, priv->wer); 1744 } 1745 } 1746 1747 if (up && up->dma && up->dma->rxchan) 1748 omap_8250_rx_dma_flush(up); 1749 1750 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1751 schedule_work(&priv->qos_work); 1752 atomic_set(&priv->active, 0); 1753 1754 return 0; 1755 } 1756 1757 static int omap8250_runtime_resume(struct device *dev) 1758 { 1759 struct omap8250_priv *priv = dev_get_drvdata(dev); 1760 struct uart_8250_port *up = NULL; 1761 1762 /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1763 if (atomic_read(&priv->active)) 1764 return 0; 1765 1766 if (priv->line >= 0) 1767 up = serial8250_get_port(priv->line); 1768 1769 if (up && omap8250_lost_context(up)) { 1770 uart_port_lock_irq(&up->port); 1771 omap8250_restore_regs(up); 1772 uart_port_unlock_irq(&up->port); 1773 } 1774 1775 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1776 uart_port_lock_irq(&up->port); 1777 omap_8250_rx_dma(up); 1778 uart_port_unlock_irq(&up->port); 1779 } 1780 1781 atomic_set(&priv->active, 1); 1782 priv->latency = priv->calc_latency; 1783 schedule_work(&priv->qos_work); 1784 1785 return 0; 1786 } 1787 1788 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1789 static int __init omap8250_console_fixup(void) 1790 { 1791 char *omap_str; 1792 char *options; 1793 u8 idx; 1794 1795 if (strstr(boot_command_line, "console=ttyS")) 1796 /* user set a ttyS based name for the console */ 1797 return 0; 1798 1799 omap_str = strstr(boot_command_line, "console=ttyO"); 1800 if (!omap_str) 1801 /* user did not set ttyO based console, so we don't care */ 1802 return 0; 1803 1804 omap_str += 12; 1805 if ('0' <= *omap_str && *omap_str <= '9') 1806 idx = *omap_str - '0'; 1807 else 1808 return 0; 1809 1810 omap_str++; 1811 if (omap_str[0] == ',') { 1812 omap_str++; 1813 options = omap_str; 1814 } else { 1815 options = NULL; 1816 } 1817 1818 add_preferred_console("ttyS", idx, options); 1819 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1820 idx, idx); 1821 pr_err("This ensures that you still see kernel messages. Please\n"); 1822 pr_err("update your kernel commandline.\n"); 1823 return 0; 1824 } 1825 console_initcall(omap8250_console_fixup); 1826 #endif 1827 1828 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1829 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1830 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1831 omap8250_runtime_resume, NULL) 1832 .prepare = pm_sleep_ptr(omap8250_prepare), 1833 .complete = pm_sleep_ptr(omap8250_complete), 1834 }; 1835 1836 static struct platform_driver omap8250_platform_driver = { 1837 .driver = { 1838 .name = "omap8250", 1839 .pm = pm_ptr(&omap8250_dev_pm_ops), 1840 .of_match_table = omap8250_dt_ids, 1841 }, 1842 .probe = omap8250_probe, 1843 .remove = omap8250_remove, 1844 }; 1845 module_platform_driver(omap8250_platform_driver); 1846 1847 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1848 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1849 MODULE_LICENSE("GPL v2"); 1850