1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_reg.h> 15 #include <linux/tty_flip.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_irq.h> 21 #include <linux/delay.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/console.h> 24 #include <linux/pm_qos.h> 25 #include <linux/dma-mapping.h> 26 27 #include "8250.h" 28 29 #define DEFAULT_CLK_SPEED 48000000 30 31 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 32 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 33 #define OMAP_DMA_TX_KICK (1 << 2) 34 35 #define OMAP_UART_FCR_RX_TRIG 6 36 #define OMAP_UART_FCR_TX_TRIG 4 37 38 /* SCR register bitmasks */ 39 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 40 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 41 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 42 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 43 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 44 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 45 46 /* MVR register bitmasks */ 47 #define OMAP_UART_MVR_SCHEME_SHIFT 30 48 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 49 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 50 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 51 #define OMAP_UART_MVR_MAJ_MASK 0x700 52 #define OMAP_UART_MVR_MAJ_SHIFT 8 53 #define OMAP_UART_MVR_MIN_MASK 0x3f 54 55 #define UART_TI752_TLR_TX 0 56 #define UART_TI752_TLR_RX 4 57 58 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 59 #define TRIGGER_FCR_MASK(x) (x & 3) 60 61 /* Enable XON/XOFF flow control on output */ 62 #define OMAP_UART_SW_TX 0x08 63 /* Enable XON/XOFF flow control on input */ 64 #define OMAP_UART_SW_RX 0x02 65 66 #define OMAP_UART_WER_MOD_WKUP 0x7f 67 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 68 69 #define TX_TRIGGER 1 70 #define RX_TRIGGER 48 71 72 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 73 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 74 75 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 76 77 #define OMAP_UART_REV_46 0x0406 78 #define OMAP_UART_REV_52 0x0502 79 #define OMAP_UART_REV_63 0x0603 80 81 struct omap8250_priv { 82 int line; 83 u8 habit; 84 u8 mdr1; 85 u8 efr; 86 u8 scr; 87 u8 wer; 88 u8 xon; 89 u8 xoff; 90 u8 delayed_restore; 91 u16 quot; 92 93 bool is_suspending; 94 int wakeirq; 95 int wakeups_enabled; 96 u32 latency; 97 u32 calc_latency; 98 struct pm_qos_request pm_qos_request; 99 struct work_struct qos_work; 100 struct uart_8250_dma omap8250_dma; 101 spinlock_t rx_dma_lock; 102 }; 103 104 static u32 uart_read(struct uart_8250_port *up, u32 reg) 105 { 106 return readl(up->port.membase + (reg << up->port.regshift)); 107 } 108 109 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 110 { 111 struct uart_8250_port *up = up_to_u8250p(port); 112 struct omap8250_priv *priv = up->port.private_data; 113 u8 lcr; 114 115 serial8250_do_set_mctrl(port, mctrl); 116 117 /* 118 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 119 * if RTS is raised 120 */ 121 lcr = serial_in(up, UART_LCR); 122 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 123 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 124 priv->efr |= UART_EFR_RTS; 125 else 126 priv->efr &= ~UART_EFR_RTS; 127 serial_out(up, UART_EFR, priv->efr); 128 serial_out(up, UART_LCR, lcr); 129 } 130 131 /* 132 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 133 * The access to uart register after MDR1 Access 134 * causes UART to corrupt data. 135 * 136 * Need a delay = 137 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 138 * give 10 times as much 139 */ 140 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 141 struct omap8250_priv *priv) 142 { 143 u8 timeout = 255; 144 u8 old_mdr1; 145 146 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 147 if (old_mdr1 == priv->mdr1) 148 return; 149 150 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 151 udelay(2); 152 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 153 UART_FCR_CLEAR_RCVR); 154 /* 155 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 156 * TX_FIFO_E bit is 1. 157 */ 158 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 159 (UART_LSR_THRE | UART_LSR_DR))) { 160 timeout--; 161 if (!timeout) { 162 /* Should *never* happen. we warn and carry on */ 163 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 164 serial_in(up, UART_LSR)); 165 break; 166 } 167 udelay(1); 168 } 169 } 170 171 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 172 struct omap8250_priv *priv) 173 { 174 unsigned int uartclk = port->uartclk; 175 unsigned int div_13, div_16; 176 unsigned int abs_d13, abs_d16; 177 178 /* 179 * Old custom speed handling. 180 */ 181 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 182 priv->quot = port->custom_divisor & 0xffff; 183 /* 184 * I assume that nobody is using this. But hey, if somebody 185 * would like to specify the divisor _and_ the mode then the 186 * driver is ready and waiting for it. 187 */ 188 if (port->custom_divisor & (1 << 16)) 189 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 190 else 191 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 192 return; 193 } 194 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 195 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 196 197 if (!div_13) 198 div_13 = 1; 199 if (!div_16) 200 div_16 = 1; 201 202 abs_d13 = abs(baud - uartclk / 13 / div_13); 203 abs_d16 = abs(baud - uartclk / 16 / div_16); 204 205 if (abs_d13 >= abs_d16) { 206 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 207 priv->quot = div_16; 208 } else { 209 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 210 priv->quot = div_13; 211 } 212 } 213 214 static void omap8250_update_scr(struct uart_8250_port *up, 215 struct omap8250_priv *priv) 216 { 217 u8 old_scr; 218 219 old_scr = serial_in(up, UART_OMAP_SCR); 220 if (old_scr == priv->scr) 221 return; 222 223 /* 224 * The manual recommends not to enable the DMA mode selector in the SCR 225 * (instead of the FCR) register _and_ selecting the DMA mode as one 226 * register write because this may lead to malfunction. 227 */ 228 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 229 serial_out(up, UART_OMAP_SCR, 230 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 231 serial_out(up, UART_OMAP_SCR, priv->scr); 232 } 233 234 static void omap8250_restore_regs(struct uart_8250_port *up) 235 { 236 struct omap8250_priv *priv = up->port.private_data; 237 struct uart_8250_dma *dma = up->dma; 238 239 if (dma && dma->tx_running) { 240 /* 241 * TCSANOW requests the change to occur immediately however if 242 * we have a TX-DMA operation in progress then it has been 243 * observed that it might stall and never complete. Therefore we 244 * delay DMA completes to prevent this hang from happen. 245 */ 246 priv->delayed_restore = 1; 247 return; 248 } 249 250 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 251 serial_out(up, UART_EFR, UART_EFR_ECB); 252 253 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 254 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 255 serial_out(up, UART_FCR, up->fcr); 256 257 omap8250_update_scr(up, priv); 258 259 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 260 261 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 262 OMAP_UART_TCR_HALT(52)); 263 serial_out(up, UART_TI752_TLR, 264 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 265 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 266 267 serial_out(up, UART_LCR, 0); 268 269 /* drop TCR + TLR access, we setup XON/XOFF later */ 270 serial_out(up, UART_MCR, up->mcr); 271 serial_out(up, UART_IER, up->ier); 272 273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 274 serial_dl_write(up, priv->quot); 275 276 serial_out(up, UART_EFR, priv->efr); 277 278 /* Configure flow control */ 279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 280 serial_out(up, UART_XON1, priv->xon); 281 serial_out(up, UART_XOFF1, priv->xoff); 282 283 serial_out(up, UART_LCR, up->lcr); 284 /* need mode A for FCR */ 285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 286 omap_8250_mdr1_errataset(up, priv); 287 else 288 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 289 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 290 } 291 292 /* 293 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 294 * some differences in how we want to handle flow control. 295 */ 296 static void omap_8250_set_termios(struct uart_port *port, 297 struct ktermios *termios, 298 struct ktermios *old) 299 { 300 struct uart_8250_port *up = 301 container_of(port, struct uart_8250_port, port); 302 struct omap8250_priv *priv = up->port.private_data; 303 unsigned char cval = 0; 304 unsigned int baud; 305 306 switch (termios->c_cflag & CSIZE) { 307 case CS5: 308 cval = UART_LCR_WLEN5; 309 break; 310 case CS6: 311 cval = UART_LCR_WLEN6; 312 break; 313 case CS7: 314 cval = UART_LCR_WLEN7; 315 break; 316 default: 317 case CS8: 318 cval = UART_LCR_WLEN8; 319 break; 320 } 321 322 if (termios->c_cflag & CSTOPB) 323 cval |= UART_LCR_STOP; 324 if (termios->c_cflag & PARENB) 325 cval |= UART_LCR_PARITY; 326 if (!(termios->c_cflag & PARODD)) 327 cval |= UART_LCR_EPAR; 328 if (termios->c_cflag & CMSPAR) 329 cval |= UART_LCR_SPAR; 330 331 /* 332 * Ask the core to calculate the divisor for us. 333 */ 334 baud = uart_get_baud_rate(port, termios, old, 335 port->uartclk / 16 / 0xffff, 336 port->uartclk / 13); 337 omap_8250_get_divisor(port, baud, priv); 338 339 /* 340 * Ok, we're now changing the port state. Do it with 341 * interrupts disabled. 342 */ 343 pm_runtime_get_sync(port->dev); 344 spin_lock_irq(&port->lock); 345 346 /* 347 * Update the per-port timeout. 348 */ 349 uart_update_timeout(port, termios->c_cflag, baud); 350 351 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 352 if (termios->c_iflag & INPCK) 353 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 354 if (termios->c_iflag & (IGNBRK | PARMRK)) 355 up->port.read_status_mask |= UART_LSR_BI; 356 357 /* 358 * Characters to ignore 359 */ 360 up->port.ignore_status_mask = 0; 361 if (termios->c_iflag & IGNPAR) 362 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 363 if (termios->c_iflag & IGNBRK) { 364 up->port.ignore_status_mask |= UART_LSR_BI; 365 /* 366 * If we're ignoring parity and break indicators, 367 * ignore overruns too (for real raw support). 368 */ 369 if (termios->c_iflag & IGNPAR) 370 up->port.ignore_status_mask |= UART_LSR_OE; 371 } 372 373 /* 374 * ignore all characters if CREAD is not set 375 */ 376 if ((termios->c_cflag & CREAD) == 0) 377 up->port.ignore_status_mask |= UART_LSR_DR; 378 379 /* 380 * Modem status interrupts 381 */ 382 up->ier &= ~UART_IER_MSI; 383 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 384 up->ier |= UART_IER_MSI; 385 386 up->lcr = cval; 387 /* Up to here it was mostly serial8250_do_set_termios() */ 388 389 /* 390 * We enable TRIG_GRANU for RX and TX and additionaly we set 391 * SCR_TX_EMPTY bit. The result is the following: 392 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 393 * - less than RX_TRIGGER number of bytes will also cause an interrupt 394 * once the UART decides that there no new bytes arriving. 395 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 396 * empty - the trigger level is ignored here. 397 * 398 * Once DMA is enabled: 399 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 400 * bytes in the TX FIFO. On each assert the DMA engine will move 401 * TX_TRIGGER bytes into the FIFO. 402 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 403 * the FIFO and move RX_TRIGGER bytes. 404 * This is because threshold and trigger values are the same. 405 */ 406 up->fcr = UART_FCR_ENABLE_FIFO; 407 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 408 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 409 410 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 411 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 412 413 if (up->dma) 414 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 415 OMAP_UART_SCR_DMAMODE_CTL; 416 417 priv->xon = termios->c_cc[VSTART]; 418 priv->xoff = termios->c_cc[VSTOP]; 419 420 priv->efr = 0; 421 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); 422 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 423 424 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 425 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 426 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 427 priv->efr |= UART_EFR_CTS; 428 } else if (up->port.flags & UPF_SOFT_FLOW) { 429 /* 430 * IXON Flag: 431 * Enable XON/XOFF flow control on input. 432 * Receiver compares XON1, XOFF1. 433 */ 434 if (termios->c_iflag & IXON) 435 priv->efr |= OMAP_UART_SW_RX; 436 437 /* 438 * IXOFF Flag: 439 * Enable XON/XOFF flow control on output. 440 * Transmit XON1, XOFF1 441 */ 442 if (termios->c_iflag & IXOFF) { 443 up->port.status |= UPSTAT_AUTOXOFF; 444 priv->efr |= OMAP_UART_SW_TX; 445 } 446 447 /* 448 * IXANY Flag: 449 * Enable any character to restart output. 450 * Operation resumes after receiving any 451 * character after recognition of the XOFF character 452 */ 453 if (termios->c_iflag & IXANY) 454 up->mcr |= UART_MCR_XONANY; 455 } 456 omap8250_restore_regs(up); 457 458 spin_unlock_irq(&up->port.lock); 459 pm_runtime_mark_last_busy(port->dev); 460 pm_runtime_put_autosuspend(port->dev); 461 462 /* calculate wakeup latency constraint */ 463 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 464 priv->latency = priv->calc_latency; 465 466 schedule_work(&priv->qos_work); 467 468 /* Don't rewrite B0 */ 469 if (tty_termios_baud_rate(termios)) 470 tty_termios_encode_baud_rate(termios, baud, baud); 471 } 472 473 /* same as 8250 except that we may have extra flow bits set in EFR */ 474 static void omap_8250_pm(struct uart_port *port, unsigned int state, 475 unsigned int oldstate) 476 { 477 struct uart_8250_port *up = up_to_u8250p(port); 478 u8 efr; 479 480 pm_runtime_get_sync(port->dev); 481 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 482 efr = serial_in(up, UART_EFR); 483 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 484 serial_out(up, UART_LCR, 0); 485 486 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 487 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 488 serial_out(up, UART_EFR, efr); 489 serial_out(up, UART_LCR, 0); 490 491 pm_runtime_mark_last_busy(port->dev); 492 pm_runtime_put_autosuspend(port->dev); 493 } 494 495 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 496 struct omap8250_priv *priv) 497 { 498 u32 mvr, scheme; 499 u16 revision, major, minor; 500 501 mvr = uart_read(up, UART_OMAP_MVER); 502 503 /* Check revision register scheme */ 504 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 505 506 switch (scheme) { 507 case 0: /* Legacy Scheme: OMAP2/3 */ 508 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 509 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 510 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 511 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 512 break; 513 case 1: 514 /* New Scheme: OMAP4+ */ 515 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 516 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 517 OMAP_UART_MVR_MAJ_SHIFT; 518 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 519 break; 520 default: 521 dev_warn(up->port.dev, 522 "Unknown revision, defaulting to highest\n"); 523 /* highest possible revision */ 524 major = 0xff; 525 minor = 0xff; 526 } 527 /* normalize revision for the driver */ 528 revision = UART_BUILD_REVISION(major, minor); 529 530 switch (revision) { 531 case OMAP_UART_REV_46: 532 priv->habit = UART_ERRATA_i202_MDR1_ACCESS; 533 break; 534 case OMAP_UART_REV_52: 535 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 536 OMAP_UART_WER_HAS_TX_WAKEUP; 537 break; 538 case OMAP_UART_REV_63: 539 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 540 OMAP_UART_WER_HAS_TX_WAKEUP; 541 break; 542 default: 543 break; 544 } 545 } 546 547 static void omap8250_uart_qos_work(struct work_struct *work) 548 { 549 struct omap8250_priv *priv; 550 551 priv = container_of(work, struct omap8250_priv, qos_work); 552 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 553 } 554 555 static irqreturn_t omap_wake_irq(int irq, void *dev_id) 556 { 557 struct uart_port *port = dev_id; 558 int ret; 559 560 ret = port->handle_irq(port); 561 if (ret) 562 return IRQ_HANDLED; 563 return IRQ_NONE; 564 } 565 566 #ifdef CONFIG_SERIAL_8250_DMA 567 static int omap_8250_dma_handle_irq(struct uart_port *port); 568 #endif 569 570 static irqreturn_t omap8250_irq(int irq, void *dev_id) 571 { 572 struct uart_port *port = dev_id; 573 struct uart_8250_port *up = up_to_u8250p(port); 574 unsigned int iir; 575 int ret; 576 577 #ifdef CONFIG_SERIAL_8250_DMA 578 if (up->dma) { 579 ret = omap_8250_dma_handle_irq(port); 580 return IRQ_RETVAL(ret); 581 } 582 #endif 583 584 serial8250_rpm_get(up); 585 iir = serial_port_in(port, UART_IIR); 586 ret = serial8250_handle_irq(port, iir); 587 serial8250_rpm_put(up); 588 589 return IRQ_RETVAL(ret); 590 } 591 592 static int omap_8250_startup(struct uart_port *port) 593 { 594 struct uart_8250_port *up = up_to_u8250p(port); 595 struct omap8250_priv *priv = port->private_data; 596 int ret; 597 598 if (priv->wakeirq) { 599 ret = request_irq(priv->wakeirq, omap_wake_irq, 600 port->irqflags, "uart wakeup irq", port); 601 if (ret) 602 return ret; 603 disable_irq(priv->wakeirq); 604 } 605 606 pm_runtime_get_sync(port->dev); 607 608 up->mcr = 0; 609 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 610 611 serial_out(up, UART_LCR, UART_LCR_WLEN8); 612 613 up->lsr_saved_flags = 0; 614 up->msr_saved_flags = 0; 615 616 if (up->dma) { 617 ret = serial8250_request_dma(up); 618 if (ret) { 619 dev_warn_ratelimited(port->dev, 620 "failed to request DMA\n"); 621 up->dma = NULL; 622 } 623 } 624 625 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 626 dev_name(port->dev), port); 627 if (ret < 0) 628 goto err; 629 630 up->ier = UART_IER_RLSI | UART_IER_RDI; 631 serial_out(up, UART_IER, up->ier); 632 633 #ifdef CONFIG_PM 634 up->capabilities |= UART_CAP_RPM; 635 #endif 636 637 /* Enable module level wake up */ 638 priv->wer = OMAP_UART_WER_MOD_WKUP; 639 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 640 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 641 serial_out(up, UART_OMAP_WER, priv->wer); 642 643 if (up->dma) 644 up->dma->rx_dma(up, 0); 645 646 pm_runtime_mark_last_busy(port->dev); 647 pm_runtime_put_autosuspend(port->dev); 648 return 0; 649 err: 650 pm_runtime_mark_last_busy(port->dev); 651 pm_runtime_put_autosuspend(port->dev); 652 if (priv->wakeirq) 653 free_irq(priv->wakeirq, port); 654 return ret; 655 } 656 657 static void omap_8250_shutdown(struct uart_port *port) 658 { 659 struct uart_8250_port *up = up_to_u8250p(port); 660 struct omap8250_priv *priv = port->private_data; 661 662 flush_work(&priv->qos_work); 663 if (up->dma) 664 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 665 666 pm_runtime_get_sync(port->dev); 667 668 serial_out(up, UART_OMAP_WER, 0); 669 670 up->ier = 0; 671 serial_out(up, UART_IER, 0); 672 673 if (up->dma) 674 serial8250_release_dma(up); 675 676 /* 677 * Disable break condition and FIFOs 678 */ 679 if (up->lcr & UART_LCR_SBC) 680 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 681 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 682 683 pm_runtime_mark_last_busy(port->dev); 684 pm_runtime_put_autosuspend(port->dev); 685 686 free_irq(port->irq, port); 687 if (priv->wakeirq) 688 free_irq(priv->wakeirq, port); 689 } 690 691 static void omap_8250_throttle(struct uart_port *port) 692 { 693 unsigned long flags; 694 struct uart_8250_port *up = 695 container_of(port, struct uart_8250_port, port); 696 697 pm_runtime_get_sync(port->dev); 698 699 spin_lock_irqsave(&port->lock, flags); 700 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 701 serial_out(up, UART_IER, up->ier); 702 spin_unlock_irqrestore(&port->lock, flags); 703 704 pm_runtime_mark_last_busy(port->dev); 705 pm_runtime_put_autosuspend(port->dev); 706 } 707 708 static void omap_8250_unthrottle(struct uart_port *port) 709 { 710 unsigned long flags; 711 struct uart_8250_port *up = 712 container_of(port, struct uart_8250_port, port); 713 714 pm_runtime_get_sync(port->dev); 715 716 spin_lock_irqsave(&port->lock, flags); 717 up->ier |= UART_IER_RLSI | UART_IER_RDI; 718 serial_out(up, UART_IER, up->ier); 719 spin_unlock_irqrestore(&port->lock, flags); 720 721 pm_runtime_mark_last_busy(port->dev); 722 pm_runtime_put_autosuspend(port->dev); 723 } 724 725 #ifdef CONFIG_SERIAL_8250_DMA 726 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 727 728 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 729 { 730 struct omap8250_priv *priv = p->port.private_data; 731 struct uart_8250_dma *dma = p->dma; 732 struct tty_port *tty_port = &p->port.state->port; 733 struct dma_tx_state state; 734 int count; 735 unsigned long flags; 736 737 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 738 dma->rx_size, DMA_FROM_DEVICE); 739 740 spin_lock_irqsave(&priv->rx_dma_lock, flags); 741 742 if (!dma->rx_running) 743 goto unlock; 744 745 dma->rx_running = 0; 746 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 747 dmaengine_terminate_all(dma->rxchan); 748 749 count = dma->rx_size - state.residue; 750 751 tty_insert_flip_string(tty_port, dma->rx_buf, count); 752 p->port.icount.rx += count; 753 unlock: 754 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 755 756 if (!error) 757 omap_8250_rx_dma(p, 0); 758 759 tty_flip_buffer_push(tty_port); 760 } 761 762 static void __dma_rx_complete(void *param) 763 { 764 __dma_rx_do_complete(param, false); 765 } 766 767 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 768 { 769 struct omap8250_priv *priv = p->port.private_data; 770 struct uart_8250_dma *dma = p->dma; 771 unsigned long flags; 772 773 spin_lock_irqsave(&priv->rx_dma_lock, flags); 774 775 if (!dma->rx_running) { 776 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 777 return; 778 } 779 780 dmaengine_pause(dma->rxchan); 781 782 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 783 784 __dma_rx_do_complete(p, true); 785 } 786 787 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 788 { 789 struct omap8250_priv *priv = p->port.private_data; 790 struct uart_8250_dma *dma = p->dma; 791 int err = 0; 792 struct dma_async_tx_descriptor *desc; 793 unsigned long flags; 794 795 switch (iir & 0x3f) { 796 case UART_IIR_RLSI: 797 /* 8250_core handles errors and break interrupts */ 798 omap_8250_rx_dma_flush(p); 799 return -EIO; 800 case UART_IIR_RX_TIMEOUT: 801 /* 802 * If RCVR FIFO trigger level was not reached, complete the 803 * transfer and let 8250_core copy the remaining data. 804 */ 805 omap_8250_rx_dma_flush(p); 806 return -ETIMEDOUT; 807 case UART_IIR_RDI: 808 /* 809 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 810 * a DMA transfer programmed but it didn't work. One reason is 811 * that we were too slow and there were too many bytes in the 812 * FIFO, the UART counted wrong and never kicked the DMA engine 813 * to do anything. That means once we receive RDI on OMAP then 814 * the DMA won't do anything soon so we have to cancel the DMA 815 * transfer and purge the FIFO manually. 816 */ 817 omap_8250_rx_dma_flush(p); 818 return -ETIMEDOUT; 819 820 default: 821 break; 822 } 823 824 spin_lock_irqsave(&priv->rx_dma_lock, flags); 825 826 if (dma->rx_running) 827 goto out; 828 829 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 830 dma->rx_size, DMA_DEV_TO_MEM, 831 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 832 if (!desc) { 833 err = -EBUSY; 834 goto out; 835 } 836 837 dma->rx_running = 1; 838 desc->callback = __dma_rx_complete; 839 desc->callback_param = p; 840 841 dma->rx_cookie = dmaengine_submit(desc); 842 843 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 844 dma->rx_size, DMA_FROM_DEVICE); 845 846 dma_async_issue_pending(dma->rxchan); 847 out: 848 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 849 return err; 850 } 851 852 static int omap_8250_tx_dma(struct uart_8250_port *p); 853 854 static void omap_8250_dma_tx_complete(void *param) 855 { 856 struct uart_8250_port *p = param; 857 struct uart_8250_dma *dma = p->dma; 858 struct circ_buf *xmit = &p->port.state->xmit; 859 unsigned long flags; 860 bool en_thri = false; 861 struct omap8250_priv *priv = p->port.private_data; 862 863 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 864 UART_XMIT_SIZE, DMA_TO_DEVICE); 865 866 spin_lock_irqsave(&p->port.lock, flags); 867 868 dma->tx_running = 0; 869 870 xmit->tail += dma->tx_size; 871 xmit->tail &= UART_XMIT_SIZE - 1; 872 p->port.icount.tx += dma->tx_size; 873 874 if (priv->delayed_restore) { 875 priv->delayed_restore = 0; 876 omap8250_restore_regs(p); 877 } 878 879 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 880 uart_write_wakeup(&p->port); 881 882 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 883 int ret; 884 885 ret = omap_8250_tx_dma(p); 886 if (ret) 887 en_thri = true; 888 889 } else if (p->capabilities & UART_CAP_RPM) { 890 en_thri = true; 891 } 892 893 if (en_thri) { 894 dma->tx_err = 1; 895 p->ier |= UART_IER_THRI; 896 serial_port_out(&p->port, UART_IER, p->ier); 897 } 898 899 spin_unlock_irqrestore(&p->port.lock, flags); 900 } 901 902 static int omap_8250_tx_dma(struct uart_8250_port *p) 903 { 904 struct uart_8250_dma *dma = p->dma; 905 struct omap8250_priv *priv = p->port.private_data; 906 struct circ_buf *xmit = &p->port.state->xmit; 907 struct dma_async_tx_descriptor *desc; 908 unsigned int skip_byte = 0; 909 int ret; 910 911 if (dma->tx_running) 912 return 0; 913 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 914 915 /* 916 * Even if no data, we need to return an error for the two cases 917 * below so serial8250_tx_chars() is invoked and properly clears 918 * THRI and/or runtime suspend. 919 */ 920 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 921 ret = -EBUSY; 922 goto err; 923 } 924 if (p->ier & UART_IER_THRI) { 925 p->ier &= ~UART_IER_THRI; 926 serial_out(p, UART_IER, p->ier); 927 } 928 return 0; 929 } 930 931 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 932 if (priv->habit & OMAP_DMA_TX_KICK) { 933 u8 tx_lvl; 934 935 /* 936 * We need to put the first byte into the FIFO in order to start 937 * the DMA transfer. For transfers smaller than four bytes we 938 * don't bother doing DMA at all. It seem not matter if there 939 * are still bytes in the FIFO from the last transfer (in case 940 * we got here directly from omap_8250_dma_tx_complete()). Bytes 941 * leaving the FIFO seem not to trigger the DMA transfer. It is 942 * really the byte that we put into the FIFO. 943 * If the FIFO is already full then we most likely got here from 944 * omap_8250_dma_tx_complete(). And this means the DMA engine 945 * just completed its work. We don't have to wait the complete 946 * 86us at 115200,8n1 but around 60us (not to mention lower 947 * baudrates). So in that case we take the interrupt and try 948 * again with an empty FIFO. 949 */ 950 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 951 if (tx_lvl == p->tx_loadsz) { 952 ret = -EBUSY; 953 goto err; 954 } 955 if (dma->tx_size < 4) { 956 ret = -EINVAL; 957 goto err; 958 } 959 skip_byte = 1; 960 } 961 962 desc = dmaengine_prep_slave_single(dma->txchan, 963 dma->tx_addr + xmit->tail + skip_byte, 964 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 965 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 966 if (!desc) { 967 ret = -EBUSY; 968 goto err; 969 } 970 971 dma->tx_running = 1; 972 973 desc->callback = omap_8250_dma_tx_complete; 974 desc->callback_param = p; 975 976 dma->tx_cookie = dmaengine_submit(desc); 977 978 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 979 UART_XMIT_SIZE, DMA_TO_DEVICE); 980 981 dma_async_issue_pending(dma->txchan); 982 if (dma->tx_err) 983 dma->tx_err = 0; 984 985 if (p->ier & UART_IER_THRI) { 986 p->ier &= ~UART_IER_THRI; 987 serial_out(p, UART_IER, p->ier); 988 } 989 if (skip_byte) 990 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 991 return 0; 992 err: 993 dma->tx_err = 1; 994 return ret; 995 } 996 997 /* 998 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 999 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1000 * use the default routine in the non-DMA case and this one for with DMA. 1001 */ 1002 static int omap_8250_dma_handle_irq(struct uart_port *port) 1003 { 1004 struct uart_8250_port *up = up_to_u8250p(port); 1005 unsigned char status; 1006 unsigned long flags; 1007 u8 iir; 1008 int dma_err = 0; 1009 1010 serial8250_rpm_get(up); 1011 1012 iir = serial_port_in(port, UART_IIR); 1013 if (iir & UART_IIR_NO_INT) { 1014 serial8250_rpm_put(up); 1015 return 0; 1016 } 1017 1018 spin_lock_irqsave(&port->lock, flags); 1019 1020 status = serial_port_in(port, UART_LSR); 1021 1022 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1023 1024 dma_err = omap_8250_rx_dma(up, iir); 1025 if (dma_err) { 1026 status = serial8250_rx_chars(up, status); 1027 omap_8250_rx_dma(up, 0); 1028 } 1029 } 1030 serial8250_modem_status(up); 1031 if (status & UART_LSR_THRE && up->dma->tx_err) { 1032 if (uart_tx_stopped(&up->port) || 1033 uart_circ_empty(&up->port.state->xmit)) { 1034 up->dma->tx_err = 0; 1035 serial8250_tx_chars(up); 1036 } else { 1037 /* 1038 * try again due to an earlier failer which 1039 * might have been resolved by now. 1040 */ 1041 dma_err = omap_8250_tx_dma(up); 1042 if (dma_err) 1043 serial8250_tx_chars(up); 1044 } 1045 } 1046 1047 spin_unlock_irqrestore(&port->lock, flags); 1048 serial8250_rpm_put(up); 1049 return 1; 1050 } 1051 1052 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1053 { 1054 return false; 1055 } 1056 1057 #else 1058 1059 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 1060 { 1061 return -EINVAL; 1062 } 1063 #endif 1064 1065 static int omap8250_no_handle_irq(struct uart_port *port) 1066 { 1067 /* IRQ has not been requested but handling irq? */ 1068 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1069 return 0; 1070 } 1071 1072 static int omap8250_probe(struct platform_device *pdev) 1073 { 1074 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1075 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1076 struct omap8250_priv *priv; 1077 struct uart_8250_port up; 1078 int ret; 1079 void __iomem *membase; 1080 1081 if (!regs || !irq) { 1082 dev_err(&pdev->dev, "missing registers or irq\n"); 1083 return -EINVAL; 1084 } 1085 1086 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1087 if (!priv) 1088 return -ENOMEM; 1089 1090 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1091 resource_size(regs)); 1092 if (!membase) 1093 return -ENODEV; 1094 1095 memset(&up, 0, sizeof(up)); 1096 up.port.dev = &pdev->dev; 1097 up.port.mapbase = regs->start; 1098 up.port.membase = membase; 1099 up.port.irq = irq->start; 1100 /* 1101 * It claims to be 16C750 compatible however it is a little different. 1102 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1103 * have) is enabled via EFR instead of MCR. The type is set here 8250 1104 * just to get things going. UNKNOWN does not work for a few reasons and 1105 * we don't need our own type since we don't use 8250's set_termios() 1106 * or pm callback. 1107 */ 1108 up.port.type = PORT_8250; 1109 up.port.iotype = UPIO_MEM; 1110 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1111 UPF_HARD_FLOW; 1112 up.port.private_data = priv; 1113 1114 up.port.regshift = 2; 1115 up.port.fifosize = 64; 1116 up.tx_loadsz = 64; 1117 up.capabilities = UART_CAP_FIFO; 1118 #ifdef CONFIG_PM 1119 /* 1120 * Runtime PM is mostly transparent. However to do it right we need to a 1121 * TX empty interrupt before we can put the device to auto idle. So if 1122 * PM is not enabled we don't add that flag and can spare that one extra 1123 * interrupt in the TX path. 1124 */ 1125 up.capabilities |= UART_CAP_RPM; 1126 #endif 1127 up.port.set_termios = omap_8250_set_termios; 1128 up.port.set_mctrl = omap8250_set_mctrl; 1129 up.port.pm = omap_8250_pm; 1130 up.port.startup = omap_8250_startup; 1131 up.port.shutdown = omap_8250_shutdown; 1132 up.port.throttle = omap_8250_throttle; 1133 up.port.unthrottle = omap_8250_unthrottle; 1134 1135 if (pdev->dev.of_node) { 1136 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1137 1138 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1139 &up.port.uartclk); 1140 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1141 } else { 1142 ret = pdev->id; 1143 } 1144 if (ret < 0) { 1145 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1146 return ret; 1147 } 1148 up.port.line = ret; 1149 1150 if (!up.port.uartclk) { 1151 up.port.uartclk = DEFAULT_CLK_SPEED; 1152 dev_warn(&pdev->dev, 1153 "No clock speed specified: using default: %d\n", 1154 DEFAULT_CLK_SPEED); 1155 } 1156 1157 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1158 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1159 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1160 priv->latency); 1161 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1162 1163 spin_lock_init(&priv->rx_dma_lock); 1164 1165 device_init_wakeup(&pdev->dev, true); 1166 pm_runtime_use_autosuspend(&pdev->dev); 1167 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1168 1169 pm_runtime_irq_safe(&pdev->dev); 1170 pm_runtime_enable(&pdev->dev); 1171 1172 pm_runtime_get_sync(&pdev->dev); 1173 1174 omap_serial_fill_features_erratas(&up, priv); 1175 up.port.handle_irq = omap8250_no_handle_irq; 1176 #ifdef CONFIG_SERIAL_8250_DMA 1177 if (pdev->dev.of_node) { 1178 /* 1179 * Oh DMA support. If there are no DMA properties in the DT then 1180 * we will fall back to a generic DMA channel which does not 1181 * really work here. To ensure that we do not get a generic DMA 1182 * channel assigned, we have the the_no_dma_filter_fn() here. 1183 * To avoid "failed to request DMA" messages we check for DMA 1184 * properties in DT. 1185 */ 1186 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1187 if (ret == 2) { 1188 up.dma = &priv->omap8250_dma; 1189 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1190 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1191 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1192 priv->omap8250_dma.rx_size = RX_TRIGGER; 1193 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1194 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1195 1196 if (of_machine_is_compatible("ti,am33xx")) 1197 priv->habit |= OMAP_DMA_TX_KICK; 1198 } 1199 } 1200 #endif 1201 ret = serial8250_register_8250_port(&up); 1202 if (ret < 0) { 1203 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1204 goto err; 1205 } 1206 priv->line = ret; 1207 platform_set_drvdata(pdev, priv); 1208 pm_runtime_mark_last_busy(&pdev->dev); 1209 pm_runtime_put_autosuspend(&pdev->dev); 1210 return 0; 1211 err: 1212 pm_runtime_put(&pdev->dev); 1213 pm_runtime_disable(&pdev->dev); 1214 return ret; 1215 } 1216 1217 static int omap8250_remove(struct platform_device *pdev) 1218 { 1219 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1220 1221 pm_runtime_put_sync(&pdev->dev); 1222 pm_runtime_disable(&pdev->dev); 1223 serial8250_unregister_port(priv->line); 1224 pm_qos_remove_request(&priv->pm_qos_request); 1225 device_init_wakeup(&pdev->dev, false); 1226 return 0; 1227 } 1228 1229 #ifdef CONFIG_PM 1230 1231 static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, 1232 bool enable) 1233 { 1234 if (!priv->wakeirq) 1235 return; 1236 1237 if (enable) 1238 enable_irq(priv->wakeirq); 1239 else 1240 disable_irq_nosync(priv->wakeirq); 1241 } 1242 1243 static void omap8250_enable_wakeup(struct omap8250_priv *priv, 1244 bool enable) 1245 { 1246 if (enable == priv->wakeups_enabled) 1247 return; 1248 1249 omap8250_enable_wakeirq(priv, enable); 1250 priv->wakeups_enabled = enable; 1251 } 1252 #endif 1253 1254 #ifdef CONFIG_PM_SLEEP 1255 static int omap8250_prepare(struct device *dev) 1256 { 1257 struct omap8250_priv *priv = dev_get_drvdata(dev); 1258 1259 if (!priv) 1260 return 0; 1261 priv->is_suspending = true; 1262 return 0; 1263 } 1264 1265 static void omap8250_complete(struct device *dev) 1266 { 1267 struct omap8250_priv *priv = dev_get_drvdata(dev); 1268 1269 if (!priv) 1270 return; 1271 priv->is_suspending = false; 1272 } 1273 1274 static int omap8250_suspend(struct device *dev) 1275 { 1276 struct omap8250_priv *priv = dev_get_drvdata(dev); 1277 1278 serial8250_suspend_port(priv->line); 1279 flush_work(&priv->qos_work); 1280 1281 if (device_may_wakeup(dev)) 1282 omap8250_enable_wakeup(priv, true); 1283 else 1284 omap8250_enable_wakeup(priv, false); 1285 return 0; 1286 } 1287 1288 static int omap8250_resume(struct device *dev) 1289 { 1290 struct omap8250_priv *priv = dev_get_drvdata(dev); 1291 1292 if (device_may_wakeup(dev)) 1293 omap8250_enable_wakeup(priv, false); 1294 1295 serial8250_resume_port(priv->line); 1296 return 0; 1297 } 1298 #else 1299 #define omap8250_prepare NULL 1300 #define omap8250_complete NULL 1301 #endif 1302 1303 #ifdef CONFIG_PM 1304 static int omap8250_lost_context(struct uart_8250_port *up) 1305 { 1306 u32 val; 1307 1308 val = serial_in(up, UART_OMAP_MDR1); 1309 /* 1310 * If we lose context, then MDR1 is set to its reset value which is 1311 * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x 1312 * or 16x but never to disable again. 1313 */ 1314 if (val == UART_OMAP_MDR1_DISABLE) 1315 return 1; 1316 return 0; 1317 } 1318 1319 static int omap8250_runtime_suspend(struct device *dev) 1320 { 1321 struct omap8250_priv *priv = dev_get_drvdata(dev); 1322 struct uart_8250_port *up; 1323 1324 up = serial8250_get_port(priv->line); 1325 /* 1326 * When using 'no_console_suspend', the console UART must not be 1327 * suspended. Since driver suspend is managed by runtime suspend, 1328 * preventing runtime suspend (by returning error) will keep device 1329 * active during suspend. 1330 */ 1331 if (priv->is_suspending && !console_suspend_enabled) { 1332 if (uart_console(&up->port)) 1333 return -EBUSY; 1334 } 1335 1336 omap8250_enable_wakeup(priv, true); 1337 if (up->dma) 1338 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1339 1340 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1341 schedule_work(&priv->qos_work); 1342 1343 return 0; 1344 } 1345 1346 static int omap8250_runtime_resume(struct device *dev) 1347 { 1348 struct omap8250_priv *priv = dev_get_drvdata(dev); 1349 struct uart_8250_port *up; 1350 int loss_cntx; 1351 1352 /* In case runtime-pm tries this before we are setup */ 1353 if (!priv) 1354 return 0; 1355 1356 up = serial8250_get_port(priv->line); 1357 omap8250_enable_wakeup(priv, false); 1358 loss_cntx = omap8250_lost_context(up); 1359 1360 if (loss_cntx) 1361 omap8250_restore_regs(up); 1362 1363 if (up->dma) 1364 omap_8250_rx_dma(up, 0); 1365 1366 priv->latency = priv->calc_latency; 1367 schedule_work(&priv->qos_work); 1368 return 0; 1369 } 1370 #endif 1371 1372 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1373 static int __init omap8250_console_fixup(void) 1374 { 1375 char *omap_str; 1376 char *options; 1377 u8 idx; 1378 1379 if (strstr(boot_command_line, "console=ttyS")) 1380 /* user set a ttyS based name for the console */ 1381 return 0; 1382 1383 omap_str = strstr(boot_command_line, "console=ttyO"); 1384 if (!omap_str) 1385 /* user did not set ttyO based console, so we don't care */ 1386 return 0; 1387 1388 omap_str += 12; 1389 if ('0' <= *omap_str && *omap_str <= '9') 1390 idx = *omap_str - '0'; 1391 else 1392 return 0; 1393 1394 omap_str++; 1395 if (omap_str[0] == ',') { 1396 omap_str++; 1397 options = omap_str; 1398 } else { 1399 options = NULL; 1400 } 1401 1402 add_preferred_console("ttyS", idx, options); 1403 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1404 idx, idx); 1405 pr_err("This ensures that you still see kernel messages. Please\n"); 1406 pr_err("update your kernel commandline.\n"); 1407 return 0; 1408 } 1409 console_initcall(omap8250_console_fixup); 1410 #endif 1411 1412 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1413 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1414 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1415 omap8250_runtime_resume, NULL) 1416 .prepare = omap8250_prepare, 1417 .complete = omap8250_complete, 1418 }; 1419 1420 static const struct of_device_id omap8250_dt_ids[] = { 1421 { .compatible = "ti,omap2-uart" }, 1422 { .compatible = "ti,omap3-uart" }, 1423 { .compatible = "ti,omap4-uart" }, 1424 {}, 1425 }; 1426 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1427 1428 static struct platform_driver omap8250_platform_driver = { 1429 .driver = { 1430 .name = "omap8250", 1431 .pm = &omap8250_dev_pm_ops, 1432 .of_match_table = omap8250_dt_ids, 1433 }, 1434 .probe = omap8250_probe, 1435 .remove = omap8250_remove, 1436 }; 1437 module_platform_driver(omap8250_platform_driver); 1438 1439 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1440 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1441 MODULE_LICENSE("GPL v2"); 1442