1 /* 2 * Sonics Silicon Backplane 3 * Broadcom EXTIF core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org> 8 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net> 9 * 10 * Licensed under the GNU/GPL. See COPYING for details. 11 */ 12 13 #include <linux/serial.h> 14 #include <linux/serial_core.h> 15 #include <linux/serial_reg.h> 16 17 #include "ssb_private.h" 18 19 20 static inline u32 extif_read32(struct ssb_extif *extif, u16 offset) 21 { 22 return ssb_read32(extif->dev, offset); 23 } 24 25 static inline void extif_write32(struct ssb_extif *extif, u16 offset, u32 value) 26 { 27 ssb_write32(extif->dev, offset, value); 28 } 29 30 static inline void extif_write32_masked(struct ssb_extif *extif, u16 offset, 31 u32 mask, u32 value) 32 { 33 value &= mask; 34 value |= extif_read32(extif, offset) & ~mask; 35 extif_write32(extif, offset, value); 36 } 37 38 #ifdef CONFIG_SSB_SERIAL 39 static bool serial_exists(u8 *regs) 40 { 41 u8 save_mcr, msr = 0; 42 43 if (regs) { 44 save_mcr = regs[UART_MCR]; 45 regs[UART_MCR] = (UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS); 46 msr = regs[UART_MSR] & (UART_MSR_DCD | UART_MSR_RI 47 | UART_MSR_CTS | UART_MSR_DSR); 48 regs[UART_MCR] = save_mcr; 49 } 50 return (msr == (UART_MSR_DCD | UART_MSR_CTS)); 51 } 52 53 int ssb_extif_serial_init(struct ssb_extif *extif, struct ssb_serial_port *ports) 54 { 55 u32 i, nr_ports = 0; 56 57 /* Disable GPIO interrupt initially */ 58 extif_write32(extif, SSB_EXTIF_GPIO_INTPOL, 0); 59 extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 0); 60 61 for (i = 0; i < 2; i++) { 62 void __iomem *uart_regs; 63 64 uart_regs = ioremap_nocache(SSB_EUART, 16); 65 if (uart_regs) { 66 uart_regs += (i * 8); 67 68 if (serial_exists(uart_regs) && ports) { 69 extif_write32(extif, SSB_EXTIF_GPIO_INTMASK, 2); 70 71 nr_ports++; 72 ports[i].regs = uart_regs; 73 ports[i].irq = 2; 74 ports[i].baud_base = 13500000; 75 ports[i].reg_shift = 0; 76 } 77 iounmap(uart_regs); 78 } 79 } 80 return nr_ports; 81 } 82 #endif /* CONFIG_SSB_SERIAL */ 83 84 void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns) 85 { 86 u32 tmp; 87 88 /* Initialize extif so we can get to the LEDs and external UART */ 89 extif_write32(extif, SSB_EXTIF_PROG_CFG, SSB_EXTCFG_EN); 90 91 /* Set timing for the flash */ 92 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; 93 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; 94 tmp |= DIV_ROUND_UP(120, ns); 95 extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); 96 97 /* Set programmable interface timing for external uart */ 98 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; 99 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; 100 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; 101 tmp |= DIV_ROUND_UP(120, ns); 102 extif_write32(extif, SSB_EXTIF_PROG_WAITCNT, tmp); 103 } 104 105 void ssb_extif_get_clockcontrol(struct ssb_extif *extif, 106 u32 *pll_type, u32 *n, u32 *m) 107 { 108 *pll_type = SSB_PLLTYPE_1; 109 *n = extif_read32(extif, SSB_EXTIF_CLOCK_N); 110 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB); 111 } 112 113 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) 114 { 115 return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask; 116 } 117 118 void ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) 119 { 120 return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0), 121 mask, value); 122 } 123 124 void ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) 125 { 126 return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0), 127 mask, value); 128 } 129 130