12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 23558fe90SMaxime Ripard /* 33558fe90SMaxime Ripard * Copyright (C) 2012 - 2014 Allwinner Tech 43558fe90SMaxime Ripard * Pan Nan <pannan@allwinnertech.com> 53558fe90SMaxime Ripard * 63558fe90SMaxime Ripard * Copyright (C) 2014 Maxime Ripard 73558fe90SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 83558fe90SMaxime Ripard */ 93558fe90SMaxime Ripard 103558fe90SMaxime Ripard #include <linux/clk.h> 113558fe90SMaxime Ripard #include <linux/delay.h> 123558fe90SMaxime Ripard #include <linux/device.h> 133558fe90SMaxime Ripard #include <linux/interrupt.h> 143558fe90SMaxime Ripard #include <linux/io.h> 153558fe90SMaxime Ripard #include <linux/module.h> 1610565dfdSMilo Kim #include <linux/of_device.h> 173558fe90SMaxime Ripard #include <linux/platform_device.h> 183558fe90SMaxime Ripard #include <linux/pm_runtime.h> 193558fe90SMaxime Ripard #include <linux/reset.h> 203558fe90SMaxime Ripard 213558fe90SMaxime Ripard #include <linux/spi/spi.h> 223558fe90SMaxime Ripard 233558fe90SMaxime Ripard #define SUN6I_FIFO_DEPTH 128 2410565dfdSMilo Kim #define SUN8I_FIFO_DEPTH 64 253558fe90SMaxime Ripard 263558fe90SMaxime Ripard #define SUN6I_GBL_CTL_REG 0x04 273558fe90SMaxime Ripard #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 283558fe90SMaxime Ripard #define SUN6I_GBL_CTL_MASTER BIT(1) 293558fe90SMaxime Ripard #define SUN6I_GBL_CTL_TP BIT(7) 303558fe90SMaxime Ripard #define SUN6I_GBL_CTL_RST BIT(31) 313558fe90SMaxime Ripard 323558fe90SMaxime Ripard #define SUN6I_TFR_CTL_REG 0x08 333558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPHA BIT(0) 343558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPOL BIT(1) 353558fe90SMaxime Ripard #define SUN6I_TFR_CTL_SPOL BIT(2) 36d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS_MASK 0x30 37d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 383558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 393558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 403558fe90SMaxime Ripard #define SUN6I_TFR_CTL_DHB BIT(8) 413558fe90SMaxime Ripard #define SUN6I_TFR_CTL_FBS BIT(12) 423558fe90SMaxime Ripard #define SUN6I_TFR_CTL_XCH BIT(31) 433558fe90SMaxime Ripard 443558fe90SMaxime Ripard #define SUN6I_INT_CTL_REG 0x10 45913f536cSIcenowy Zheng #define SUN6I_INT_CTL_RF_RDY BIT(0) 46913f536cSIcenowy Zheng #define SUN6I_INT_CTL_TF_ERQ BIT(4) 473558fe90SMaxime Ripard #define SUN6I_INT_CTL_RF_OVF BIT(8) 483558fe90SMaxime Ripard #define SUN6I_INT_CTL_TC BIT(12) 493558fe90SMaxime Ripard 503558fe90SMaxime Ripard #define SUN6I_INT_STA_REG 0x14 513558fe90SMaxime Ripard 523558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_REG 0x18 53913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 54913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 553558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_RF_RST BIT(15) 56913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 57913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 583558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_TF_RST BIT(31) 593558fe90SMaxime Ripard 603558fe90SMaxime Ripard #define SUN6I_FIFO_STA_REG 0x1c 613558fe90SMaxime Ripard #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f 623558fe90SMaxime Ripard #define SUN6I_FIFO_STA_RF_CNT_BITS 0 633558fe90SMaxime Ripard #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f 643558fe90SMaxime Ripard #define SUN6I_FIFO_STA_TF_CNT_BITS 16 653558fe90SMaxime Ripard 663558fe90SMaxime Ripard #define SUN6I_CLK_CTL_REG 0x24 673558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2_MASK 0xff 683558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 693558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1_MASK 0xf 703558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 713558fe90SMaxime Ripard #define SUN6I_CLK_CTL_DRS BIT(12) 723558fe90SMaxime Ripard 73913f536cSIcenowy Zheng #define SUN6I_MAX_XFER_SIZE 0xffffff 74913f536cSIcenowy Zheng 753558fe90SMaxime Ripard #define SUN6I_BURST_CNT_REG 0x30 76913f536cSIcenowy Zheng #define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) 773558fe90SMaxime Ripard 783558fe90SMaxime Ripard #define SUN6I_XMIT_CNT_REG 0x34 79913f536cSIcenowy Zheng #define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) 803558fe90SMaxime Ripard 813558fe90SMaxime Ripard #define SUN6I_BURST_CTL_CNT_REG 0x38 82913f536cSIcenowy Zheng #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE) 833558fe90SMaxime Ripard 843558fe90SMaxime Ripard #define SUN6I_TXDATA_REG 0x200 853558fe90SMaxime Ripard #define SUN6I_RXDATA_REG 0x300 863558fe90SMaxime Ripard 873558fe90SMaxime Ripard struct sun6i_spi { 883558fe90SMaxime Ripard struct spi_master *master; 893558fe90SMaxime Ripard void __iomem *base_addr; 903558fe90SMaxime Ripard struct clk *hclk; 913558fe90SMaxime Ripard struct clk *mclk; 923558fe90SMaxime Ripard struct reset_control *rstc; 933558fe90SMaxime Ripard 943558fe90SMaxime Ripard struct completion done; 953558fe90SMaxime Ripard 963558fe90SMaxime Ripard const u8 *tx_buf; 973558fe90SMaxime Ripard u8 *rx_buf; 983558fe90SMaxime Ripard int len; 9910565dfdSMilo Kim unsigned long fifo_depth; 1003558fe90SMaxime Ripard }; 1013558fe90SMaxime Ripard 1023558fe90SMaxime Ripard static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 1033558fe90SMaxime Ripard { 1043558fe90SMaxime Ripard return readl(sspi->base_addr + reg); 1053558fe90SMaxime Ripard } 1063558fe90SMaxime Ripard 1073558fe90SMaxime Ripard static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 1083558fe90SMaxime Ripard { 1093558fe90SMaxime Ripard writel(value, sspi->base_addr + reg); 1103558fe90SMaxime Ripard } 1113558fe90SMaxime Ripard 112913f536cSIcenowy Zheng static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 113913f536cSIcenowy Zheng { 114913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 115913f536cSIcenowy Zheng 116913f536cSIcenowy Zheng reg >>= SUN6I_FIFO_STA_TF_CNT_BITS; 117913f536cSIcenowy Zheng 118913f536cSIcenowy Zheng return reg & SUN6I_FIFO_STA_TF_CNT_MASK; 119913f536cSIcenowy Zheng } 120913f536cSIcenowy Zheng 121913f536cSIcenowy Zheng static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask) 122913f536cSIcenowy Zheng { 123913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 124913f536cSIcenowy Zheng 125913f536cSIcenowy Zheng reg |= mask; 126913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 127913f536cSIcenowy Zheng } 128913f536cSIcenowy Zheng 129913f536cSIcenowy Zheng static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) 130913f536cSIcenowy Zheng { 131913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 132913f536cSIcenowy Zheng 133913f536cSIcenowy Zheng reg &= ~mask; 134913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 135913f536cSIcenowy Zheng } 136913f536cSIcenowy Zheng 1373558fe90SMaxime Ripard static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 1383558fe90SMaxime Ripard { 1393558fe90SMaxime Ripard u32 reg, cnt; 1403558fe90SMaxime Ripard u8 byte; 1413558fe90SMaxime Ripard 1423558fe90SMaxime Ripard /* See how much data is available */ 1433558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 1443558fe90SMaxime Ripard reg &= SUN6I_FIFO_STA_RF_CNT_MASK; 1453558fe90SMaxime Ripard cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; 1463558fe90SMaxime Ripard 1473558fe90SMaxime Ripard if (len > cnt) 1483558fe90SMaxime Ripard len = cnt; 1493558fe90SMaxime Ripard 1503558fe90SMaxime Ripard while (len--) { 1513558fe90SMaxime Ripard byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 1523558fe90SMaxime Ripard if (sspi->rx_buf) 1533558fe90SMaxime Ripard *sspi->rx_buf++ = byte; 1543558fe90SMaxime Ripard } 1553558fe90SMaxime Ripard } 1563558fe90SMaxime Ripard 1573558fe90SMaxime Ripard static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) 1583558fe90SMaxime Ripard { 159913f536cSIcenowy Zheng u32 cnt; 1603558fe90SMaxime Ripard u8 byte; 1613558fe90SMaxime Ripard 162913f536cSIcenowy Zheng /* See how much data we can fit */ 163913f536cSIcenowy Zheng cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); 164913f536cSIcenowy Zheng 165913f536cSIcenowy Zheng len = min3(len, (int)cnt, sspi->len); 1663558fe90SMaxime Ripard 1673558fe90SMaxime Ripard while (len--) { 1683558fe90SMaxime Ripard byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 1693558fe90SMaxime Ripard writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 1703558fe90SMaxime Ripard sspi->len--; 1713558fe90SMaxime Ripard } 1723558fe90SMaxime Ripard } 1733558fe90SMaxime Ripard 1743558fe90SMaxime Ripard static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 1753558fe90SMaxime Ripard { 1763558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 1773558fe90SMaxime Ripard u32 reg; 1783558fe90SMaxime Ripard 1793558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 1803558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_MASK; 1813558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 1823558fe90SMaxime Ripard 1833558fe90SMaxime Ripard if (enable) 1843558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_LEVEL; 1853558fe90SMaxime Ripard else 1863558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 1873558fe90SMaxime Ripard 1883558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 1893558fe90SMaxime Ripard } 1903558fe90SMaxime Ripard 191794912cfSMichal Suchanek static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 192794912cfSMichal Suchanek { 1933288d5cbSIcenowy Zheng return SUN6I_MAX_XFER_SIZE - 1; 194794912cfSMichal Suchanek } 1953558fe90SMaxime Ripard 1963558fe90SMaxime Ripard static int sun6i_spi_transfer_one(struct spi_master *master, 1973558fe90SMaxime Ripard struct spi_device *spi, 1983558fe90SMaxime Ripard struct spi_transfer *tfr) 1993558fe90SMaxime Ripard { 2003558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 2013558fe90SMaxime Ripard unsigned int mclk_rate, div, timeout; 202719bd654SMichal Suchanek unsigned int start, end, tx_time; 203913f536cSIcenowy Zheng unsigned int trig_level; 2043558fe90SMaxime Ripard unsigned int tx_len = 0; 2053558fe90SMaxime Ripard int ret = 0; 2063558fe90SMaxime Ripard u32 reg; 2073558fe90SMaxime Ripard 208913f536cSIcenowy Zheng if (tfr->len > SUN6I_MAX_XFER_SIZE) 2093558fe90SMaxime Ripard return -EINVAL; 2103558fe90SMaxime Ripard 2113558fe90SMaxime Ripard reinit_completion(&sspi->done); 2123558fe90SMaxime Ripard sspi->tx_buf = tfr->tx_buf; 2133558fe90SMaxime Ripard sspi->rx_buf = tfr->rx_buf; 2143558fe90SMaxime Ripard sspi->len = tfr->len; 2153558fe90SMaxime Ripard 2163558fe90SMaxime Ripard /* Clear pending interrupts */ 2173558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 2183558fe90SMaxime Ripard 2193558fe90SMaxime Ripard /* Reset FIFO */ 2203558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 2213558fe90SMaxime Ripard SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 2223558fe90SMaxime Ripard 2233558fe90SMaxime Ripard /* 224913f536cSIcenowy Zheng * Setup FIFO interrupt trigger level 225913f536cSIcenowy Zheng * Here we choose 3/4 of the full fifo depth, as it's the hardcoded 226913f536cSIcenowy Zheng * value used in old generation of Allwinner SPI controller. 227913f536cSIcenowy Zheng * (See spi-sun4i.c) 228913f536cSIcenowy Zheng */ 229913f536cSIcenowy Zheng trig_level = sspi->fifo_depth / 4 * 3; 230913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 231913f536cSIcenowy Zheng (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | 232913f536cSIcenowy Zheng (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS)); 233913f536cSIcenowy Zheng 234913f536cSIcenowy Zheng /* 2353558fe90SMaxime Ripard * Setup the transfer control register: Chip Select, 2363558fe90SMaxime Ripard * polarities, etc. 2373558fe90SMaxime Ripard */ 2383558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 2393558fe90SMaxime Ripard 2403558fe90SMaxime Ripard if (spi->mode & SPI_CPOL) 2413558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPOL; 2423558fe90SMaxime Ripard else 2433558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPOL; 2443558fe90SMaxime Ripard 2453558fe90SMaxime Ripard if (spi->mode & SPI_CPHA) 2463558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPHA; 2473558fe90SMaxime Ripard else 2483558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPHA; 2493558fe90SMaxime Ripard 2503558fe90SMaxime Ripard if (spi->mode & SPI_LSB_FIRST) 2513558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_FBS; 2523558fe90SMaxime Ripard else 2533558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_FBS; 2543558fe90SMaxime Ripard 2553558fe90SMaxime Ripard /* 2563558fe90SMaxime Ripard * If it's a TX only transfer, we don't want to fill the RX 2573558fe90SMaxime Ripard * FIFO with bogus data 2583558fe90SMaxime Ripard */ 2593558fe90SMaxime Ripard if (sspi->rx_buf) 2603558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_DHB; 2613558fe90SMaxime Ripard else 2623558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_DHB; 2633558fe90SMaxime Ripard 2643558fe90SMaxime Ripard /* We want to control the chip select manually */ 2653558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_MANUAL; 2663558fe90SMaxime Ripard 2673558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 2683558fe90SMaxime Ripard 2693558fe90SMaxime Ripard /* Ensure that we have a parent clock fast enough */ 2703558fe90SMaxime Ripard mclk_rate = clk_get_rate(sspi->mclk); 27147284e3eSMarcus Weseloh if (mclk_rate < (2 * tfr->speed_hz)) { 27247284e3eSMarcus Weseloh clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 2733558fe90SMaxime Ripard mclk_rate = clk_get_rate(sspi->mclk); 2743558fe90SMaxime Ripard } 2753558fe90SMaxime Ripard 2763558fe90SMaxime Ripard /* 2773558fe90SMaxime Ripard * Setup clock divider. 2783558fe90SMaxime Ripard * 2793558fe90SMaxime Ripard * We have two choices there. Either we can use the clock 2803558fe90SMaxime Ripard * divide rate 1, which is calculated thanks to this formula: 2813558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 ^ cdr) 2823558fe90SMaxime Ripard * Or we can use CDR2, which is calculated with the formula: 2833558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 2843558fe90SMaxime Ripard * Wether we use the former or the latter is set through the 2853558fe90SMaxime Ripard * DRS bit. 2863558fe90SMaxime Ripard * 2873558fe90SMaxime Ripard * First try CDR2, and if we can't reach the expected 2883558fe90SMaxime Ripard * frequency, fall back to CDR1. 2893558fe90SMaxime Ripard */ 29047284e3eSMarcus Weseloh div = mclk_rate / (2 * tfr->speed_hz); 2913558fe90SMaxime Ripard if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 2923558fe90SMaxime Ripard if (div > 0) 2933558fe90SMaxime Ripard div--; 2943558fe90SMaxime Ripard 2953558fe90SMaxime Ripard reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; 2963558fe90SMaxime Ripard } else { 29747284e3eSMarcus Weseloh div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); 2983558fe90SMaxime Ripard reg = SUN6I_CLK_CTL_CDR1(div); 2993558fe90SMaxime Ripard } 3003558fe90SMaxime Ripard 3013558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 3023558fe90SMaxime Ripard 3033558fe90SMaxime Ripard /* Setup the transfer now... */ 3043558fe90SMaxime Ripard if (sspi->tx_buf) 3053558fe90SMaxime Ripard tx_len = tfr->len; 3063558fe90SMaxime Ripard 3073558fe90SMaxime Ripard /* Setup the counters */ 3083558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); 3093558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len)); 3103558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, 3113558fe90SMaxime Ripard SUN6I_BURST_CTL_CNT_STC(tx_len)); 3123558fe90SMaxime Ripard 3133558fe90SMaxime Ripard /* Fill the TX FIFO */ 31410565dfdSMilo Kim sun6i_spi_fill_fifo(sspi, sspi->fifo_depth); 3153558fe90SMaxime Ripard 3163558fe90SMaxime Ripard /* Enable the interrupts */ 3173558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 318913f536cSIcenowy Zheng sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC | 319913f536cSIcenowy Zheng SUN6I_INT_CTL_RF_RDY); 320913f536cSIcenowy Zheng if (tx_len > sspi->fifo_depth) 321913f536cSIcenowy Zheng sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 3223558fe90SMaxime Ripard 3233558fe90SMaxime Ripard /* Start the transfer */ 3243558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 3253558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 3263558fe90SMaxime Ripard 327719bd654SMichal Suchanek tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 328719bd654SMichal Suchanek start = jiffies; 3293558fe90SMaxime Ripard timeout = wait_for_completion_timeout(&sspi->done, 330719bd654SMichal Suchanek msecs_to_jiffies(tx_time)); 331719bd654SMichal Suchanek end = jiffies; 3323558fe90SMaxime Ripard if (!timeout) { 333719bd654SMichal Suchanek dev_warn(&master->dev, 334719bd654SMichal Suchanek "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 335719bd654SMichal Suchanek dev_name(&spi->dev), tfr->len, tfr->speed_hz, 336719bd654SMichal Suchanek jiffies_to_msecs(end - start), tx_time); 3373558fe90SMaxime Ripard ret = -ETIMEDOUT; 3383558fe90SMaxime Ripard goto out; 3393558fe90SMaxime Ripard } 3403558fe90SMaxime Ripard 3413558fe90SMaxime Ripard out: 3423558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 3433558fe90SMaxime Ripard 3443558fe90SMaxime Ripard return ret; 3453558fe90SMaxime Ripard } 3463558fe90SMaxime Ripard 3473558fe90SMaxime Ripard static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 3483558fe90SMaxime Ripard { 3493558fe90SMaxime Ripard struct sun6i_spi *sspi = dev_id; 3503558fe90SMaxime Ripard u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 3513558fe90SMaxime Ripard 3523558fe90SMaxime Ripard /* Transfer complete */ 3533558fe90SMaxime Ripard if (status & SUN6I_INT_CTL_TC) { 3543558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 355913f536cSIcenowy Zheng sun6i_spi_drain_fifo(sspi, sspi->fifo_depth); 3563558fe90SMaxime Ripard complete(&sspi->done); 3573558fe90SMaxime Ripard return IRQ_HANDLED; 3583558fe90SMaxime Ripard } 3593558fe90SMaxime Ripard 360913f536cSIcenowy Zheng /* Receive FIFO 3/4 full */ 361913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_RF_RDY) { 362913f536cSIcenowy Zheng sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 363913f536cSIcenowy Zheng /* Only clear the interrupt _after_ draining the FIFO */ 364913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); 365913f536cSIcenowy Zheng return IRQ_HANDLED; 366913f536cSIcenowy Zheng } 367913f536cSIcenowy Zheng 368913f536cSIcenowy Zheng /* Transmit FIFO 3/4 empty */ 369913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_TF_ERQ) { 370913f536cSIcenowy Zheng sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); 371913f536cSIcenowy Zheng 372913f536cSIcenowy Zheng if (!sspi->len) 373913f536cSIcenowy Zheng /* nothing left to transmit */ 374913f536cSIcenowy Zheng sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 375913f536cSIcenowy Zheng 376913f536cSIcenowy Zheng /* Only clear the interrupt _after_ re-seeding the FIFO */ 377913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); 378913f536cSIcenowy Zheng 379913f536cSIcenowy Zheng return IRQ_HANDLED; 380913f536cSIcenowy Zheng } 381913f536cSIcenowy Zheng 3823558fe90SMaxime Ripard return IRQ_NONE; 3833558fe90SMaxime Ripard } 3843558fe90SMaxime Ripard 3853558fe90SMaxime Ripard static int sun6i_spi_runtime_resume(struct device *dev) 3863558fe90SMaxime Ripard { 3873558fe90SMaxime Ripard struct spi_master *master = dev_get_drvdata(dev); 3883558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 3893558fe90SMaxime Ripard int ret; 3903558fe90SMaxime Ripard 3913558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->hclk); 3923558fe90SMaxime Ripard if (ret) { 3933558fe90SMaxime Ripard dev_err(dev, "Couldn't enable AHB clock\n"); 3943558fe90SMaxime Ripard goto out; 3953558fe90SMaxime Ripard } 3963558fe90SMaxime Ripard 3973558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->mclk); 3983558fe90SMaxime Ripard if (ret) { 3993558fe90SMaxime Ripard dev_err(dev, "Couldn't enable module clock\n"); 4003558fe90SMaxime Ripard goto err; 4013558fe90SMaxime Ripard } 4023558fe90SMaxime Ripard 4033558fe90SMaxime Ripard ret = reset_control_deassert(sspi->rstc); 4043558fe90SMaxime Ripard if (ret) { 4053558fe90SMaxime Ripard dev_err(dev, "Couldn't deassert the device from reset\n"); 4063558fe90SMaxime Ripard goto err2; 4073558fe90SMaxime Ripard } 4083558fe90SMaxime Ripard 4093558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 4103558fe90SMaxime Ripard SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 4113558fe90SMaxime Ripard 4123558fe90SMaxime Ripard return 0; 4133558fe90SMaxime Ripard 4143558fe90SMaxime Ripard err2: 4153558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk); 4163558fe90SMaxime Ripard err: 4173558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk); 4183558fe90SMaxime Ripard out: 4193558fe90SMaxime Ripard return ret; 4203558fe90SMaxime Ripard } 4213558fe90SMaxime Ripard 4223558fe90SMaxime Ripard static int sun6i_spi_runtime_suspend(struct device *dev) 4233558fe90SMaxime Ripard { 4243558fe90SMaxime Ripard struct spi_master *master = dev_get_drvdata(dev); 4253558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 4263558fe90SMaxime Ripard 4273558fe90SMaxime Ripard reset_control_assert(sspi->rstc); 4283558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk); 4293558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk); 4303558fe90SMaxime Ripard 4313558fe90SMaxime Ripard return 0; 4323558fe90SMaxime Ripard } 4333558fe90SMaxime Ripard 4343558fe90SMaxime Ripard static int sun6i_spi_probe(struct platform_device *pdev) 4353558fe90SMaxime Ripard { 4363558fe90SMaxime Ripard struct spi_master *master; 4373558fe90SMaxime Ripard struct sun6i_spi *sspi; 4383558fe90SMaxime Ripard int ret = 0, irq; 4393558fe90SMaxime Ripard 4403558fe90SMaxime Ripard master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 4413558fe90SMaxime Ripard if (!master) { 4423558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 4433558fe90SMaxime Ripard return -ENOMEM; 4443558fe90SMaxime Ripard } 4453558fe90SMaxime Ripard 4463558fe90SMaxime Ripard platform_set_drvdata(pdev, master); 4473558fe90SMaxime Ripard sspi = spi_master_get_devdata(master); 4483558fe90SMaxime Ripard 4497c7c31f7SYueHaibing sspi->base_addr = devm_platform_ioremap_resource(pdev, 0); 4503558fe90SMaxime Ripard if (IS_ERR(sspi->base_addr)) { 4513558fe90SMaxime Ripard ret = PTR_ERR(sspi->base_addr); 4523558fe90SMaxime Ripard goto err_free_master; 4533558fe90SMaxime Ripard } 4543558fe90SMaxime Ripard 4553558fe90SMaxime Ripard irq = platform_get_irq(pdev, 0); 4563558fe90SMaxime Ripard if (irq < 0) { 4573558fe90SMaxime Ripard ret = -ENXIO; 4583558fe90SMaxime Ripard goto err_free_master; 4593558fe90SMaxime Ripard } 4603558fe90SMaxime Ripard 4613558fe90SMaxime Ripard ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 4623558fe90SMaxime Ripard 0, "sun6i-spi", sspi); 4633558fe90SMaxime Ripard if (ret) { 4643558fe90SMaxime Ripard dev_err(&pdev->dev, "Cannot request IRQ\n"); 4653558fe90SMaxime Ripard goto err_free_master; 4663558fe90SMaxime Ripard } 4673558fe90SMaxime Ripard 4683558fe90SMaxime Ripard sspi->master = master; 46910565dfdSMilo Kim sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); 47010565dfdSMilo Kim 4710b06d8cfSMichal Suchanek master->max_speed_hz = 100 * 1000 * 1000; 4720b06d8cfSMichal Suchanek master->min_speed_hz = 3 * 1000; 473*74750e06SAlistair Francis master->use_gpio_descriptors = true; 4743558fe90SMaxime Ripard master->set_cs = sun6i_spi_set_cs; 4753558fe90SMaxime Ripard master->transfer_one = sun6i_spi_transfer_one; 4763558fe90SMaxime Ripard master->num_chipselect = 4; 4773558fe90SMaxime Ripard master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 478743a46b8SAxel Lin master->bits_per_word_mask = SPI_BPW_MASK(8); 4793558fe90SMaxime Ripard master->dev.of_node = pdev->dev.of_node; 4803558fe90SMaxime Ripard master->auto_runtime_pm = true; 481794912cfSMichal Suchanek master->max_transfer_size = sun6i_spi_max_transfer_size; 4823558fe90SMaxime Ripard 4833558fe90SMaxime Ripard sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 4843558fe90SMaxime Ripard if (IS_ERR(sspi->hclk)) { 4853558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 4863558fe90SMaxime Ripard ret = PTR_ERR(sspi->hclk); 4873558fe90SMaxime Ripard goto err_free_master; 4883558fe90SMaxime Ripard } 4893558fe90SMaxime Ripard 4903558fe90SMaxime Ripard sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 4913558fe90SMaxime Ripard if (IS_ERR(sspi->mclk)) { 4923558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire module clock\n"); 4933558fe90SMaxime Ripard ret = PTR_ERR(sspi->mclk); 4943558fe90SMaxime Ripard goto err_free_master; 4953558fe90SMaxime Ripard } 4963558fe90SMaxime Ripard 4973558fe90SMaxime Ripard init_completion(&sspi->done); 4983558fe90SMaxime Ripard 49936bc7491SPhilipp Zabel sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 5003558fe90SMaxime Ripard if (IS_ERR(sspi->rstc)) { 5013558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't get reset controller\n"); 5023558fe90SMaxime Ripard ret = PTR_ERR(sspi->rstc); 5033558fe90SMaxime Ripard goto err_free_master; 5043558fe90SMaxime Ripard } 5053558fe90SMaxime Ripard 5063558fe90SMaxime Ripard /* 5073558fe90SMaxime Ripard * This wake-up/shutdown pattern is to be able to have the 5083558fe90SMaxime Ripard * device woken up, even if runtime_pm is disabled 5093558fe90SMaxime Ripard */ 5103558fe90SMaxime Ripard ret = sun6i_spi_runtime_resume(&pdev->dev); 5113558fe90SMaxime Ripard if (ret) { 5123558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't resume the device\n"); 5133558fe90SMaxime Ripard goto err_free_master; 5143558fe90SMaxime Ripard } 5153558fe90SMaxime Ripard 5163558fe90SMaxime Ripard pm_runtime_set_active(&pdev->dev); 5173558fe90SMaxime Ripard pm_runtime_enable(&pdev->dev); 5183558fe90SMaxime Ripard pm_runtime_idle(&pdev->dev); 5193558fe90SMaxime Ripard 5203558fe90SMaxime Ripard ret = devm_spi_register_master(&pdev->dev, master); 5213558fe90SMaxime Ripard if (ret) { 5223558fe90SMaxime Ripard dev_err(&pdev->dev, "cannot register SPI master\n"); 5233558fe90SMaxime Ripard goto err_pm_disable; 5243558fe90SMaxime Ripard } 5253558fe90SMaxime Ripard 5263558fe90SMaxime Ripard return 0; 5273558fe90SMaxime Ripard 5283558fe90SMaxime Ripard err_pm_disable: 5293558fe90SMaxime Ripard pm_runtime_disable(&pdev->dev); 5303558fe90SMaxime Ripard sun6i_spi_runtime_suspend(&pdev->dev); 5313558fe90SMaxime Ripard err_free_master: 5323558fe90SMaxime Ripard spi_master_put(master); 5333558fe90SMaxime Ripard return ret; 5343558fe90SMaxime Ripard } 5353558fe90SMaxime Ripard 5363558fe90SMaxime Ripard static int sun6i_spi_remove(struct platform_device *pdev) 5373558fe90SMaxime Ripard { 5382d9bbd02STobias Jordan pm_runtime_force_suspend(&pdev->dev); 5393558fe90SMaxime Ripard 5403558fe90SMaxime Ripard return 0; 5413558fe90SMaxime Ripard } 5423558fe90SMaxime Ripard 5433558fe90SMaxime Ripard static const struct of_device_id sun6i_spi_match[] = { 54410565dfdSMilo Kim { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, 54510565dfdSMilo Kim { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, 5463558fe90SMaxime Ripard {} 5473558fe90SMaxime Ripard }; 5483558fe90SMaxime Ripard MODULE_DEVICE_TABLE(of, sun6i_spi_match); 5493558fe90SMaxime Ripard 5503558fe90SMaxime Ripard static const struct dev_pm_ops sun6i_spi_pm_ops = { 5513558fe90SMaxime Ripard .runtime_resume = sun6i_spi_runtime_resume, 5523558fe90SMaxime Ripard .runtime_suspend = sun6i_spi_runtime_suspend, 5533558fe90SMaxime Ripard }; 5543558fe90SMaxime Ripard 5553558fe90SMaxime Ripard static struct platform_driver sun6i_spi_driver = { 5563558fe90SMaxime Ripard .probe = sun6i_spi_probe, 5573558fe90SMaxime Ripard .remove = sun6i_spi_remove, 5583558fe90SMaxime Ripard .driver = { 5593558fe90SMaxime Ripard .name = "sun6i-spi", 5603558fe90SMaxime Ripard .of_match_table = sun6i_spi_match, 5613558fe90SMaxime Ripard .pm = &sun6i_spi_pm_ops, 5623558fe90SMaxime Ripard }, 5633558fe90SMaxime Ripard }; 5643558fe90SMaxime Ripard module_platform_driver(sun6i_spi_driver); 5653558fe90SMaxime Ripard 5663558fe90SMaxime Ripard MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 5673558fe90SMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 5683558fe90SMaxime Ripard MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 5693558fe90SMaxime Ripard MODULE_LICENSE("GPL"); 570