12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 23558fe90SMaxime Ripard /* 33558fe90SMaxime Ripard * Copyright (C) 2012 - 2014 Allwinner Tech 43558fe90SMaxime Ripard * Pan Nan <pannan@allwinnertech.com> 53558fe90SMaxime Ripard * 63558fe90SMaxime Ripard * Copyright (C) 2014 Maxime Ripard 73558fe90SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 83558fe90SMaxime Ripard */ 93558fe90SMaxime Ripard 109a3ef9dfSMarc Kleine-Budde #include <linux/bitfield.h> 113558fe90SMaxime Ripard #include <linux/clk.h> 123558fe90SMaxime Ripard #include <linux/delay.h> 133558fe90SMaxime Ripard #include <linux/device.h> 143558fe90SMaxime Ripard #include <linux/interrupt.h> 153558fe90SMaxime Ripard #include <linux/io.h> 163558fe90SMaxime Ripard #include <linux/module.h> 1710565dfdSMilo Kim #include <linux/of_device.h> 183558fe90SMaxime Ripard #include <linux/platform_device.h> 193558fe90SMaxime Ripard #include <linux/pm_runtime.h> 203558fe90SMaxime Ripard #include <linux/reset.h> 21*345980a3SAlexander Kochetkov #include <linux/dmaengine.h> 223558fe90SMaxime Ripard 233558fe90SMaxime Ripard #include <linux/spi/spi.h> 243558fe90SMaxime Ripard 253558fe90SMaxime Ripard #define SUN6I_FIFO_DEPTH 128 2610565dfdSMilo Kim #define SUN8I_FIFO_DEPTH 64 273558fe90SMaxime Ripard 283558fe90SMaxime Ripard #define SUN6I_GBL_CTL_REG 0x04 293558fe90SMaxime Ripard #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 303558fe90SMaxime Ripard #define SUN6I_GBL_CTL_MASTER BIT(1) 313558fe90SMaxime Ripard #define SUN6I_GBL_CTL_TP BIT(7) 323558fe90SMaxime Ripard #define SUN6I_GBL_CTL_RST BIT(31) 333558fe90SMaxime Ripard 343558fe90SMaxime Ripard #define SUN6I_TFR_CTL_REG 0x08 353558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPHA BIT(0) 363558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPOL BIT(1) 373558fe90SMaxime Ripard #define SUN6I_TFR_CTL_SPOL BIT(2) 38d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS_MASK 0x30 39d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 403558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 413558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 423558fe90SMaxime Ripard #define SUN6I_TFR_CTL_DHB BIT(8) 433558fe90SMaxime Ripard #define SUN6I_TFR_CTL_FBS BIT(12) 443558fe90SMaxime Ripard #define SUN6I_TFR_CTL_XCH BIT(31) 453558fe90SMaxime Ripard 463558fe90SMaxime Ripard #define SUN6I_INT_CTL_REG 0x10 47913f536cSIcenowy Zheng #define SUN6I_INT_CTL_RF_RDY BIT(0) 48913f536cSIcenowy Zheng #define SUN6I_INT_CTL_TF_ERQ BIT(4) 493558fe90SMaxime Ripard #define SUN6I_INT_CTL_RF_OVF BIT(8) 503558fe90SMaxime Ripard #define SUN6I_INT_CTL_TC BIT(12) 513558fe90SMaxime Ripard 523558fe90SMaxime Ripard #define SUN6I_INT_STA_REG 0x14 533558fe90SMaxime Ripard 543558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_REG 0x18 55913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 56*345980a3SAlexander Kochetkov #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8) 57913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 583558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_RF_RST BIT(15) 59913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 60913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 61*345980a3SAlexander Kochetkov #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24) 623558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_TF_RST BIT(31) 633558fe90SMaxime Ripard 643558fe90SMaxime Ripard #define SUN6I_FIFO_STA_REG 0x1c 655197da03SMarc Kleine-Budde #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) 669a3ef9dfSMarc Kleine-Budde #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 673558fe90SMaxime Ripard 683558fe90SMaxime Ripard #define SUN6I_CLK_CTL_REG 0x24 693558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2_MASK 0xff 703558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 713558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1_MASK 0xf 723558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 733558fe90SMaxime Ripard #define SUN6I_CLK_CTL_DRS BIT(12) 743558fe90SMaxime Ripard 75913f536cSIcenowy Zheng #define SUN6I_MAX_XFER_SIZE 0xffffff 76913f536cSIcenowy Zheng 773558fe90SMaxime Ripard #define SUN6I_BURST_CNT_REG 0x30 783558fe90SMaxime Ripard 793558fe90SMaxime Ripard #define SUN6I_XMIT_CNT_REG 0x34 803558fe90SMaxime Ripard 813558fe90SMaxime Ripard #define SUN6I_BURST_CTL_CNT_REG 0x38 823558fe90SMaxime Ripard 833558fe90SMaxime Ripard #define SUN6I_TXDATA_REG 0x200 843558fe90SMaxime Ripard #define SUN6I_RXDATA_REG 0x300 853558fe90SMaxime Ripard 863558fe90SMaxime Ripard struct sun6i_spi { 873558fe90SMaxime Ripard struct spi_master *master; 883558fe90SMaxime Ripard void __iomem *base_addr; 89*345980a3SAlexander Kochetkov dma_addr_t dma_addr_rx; 90*345980a3SAlexander Kochetkov dma_addr_t dma_addr_tx; 913558fe90SMaxime Ripard struct clk *hclk; 923558fe90SMaxime Ripard struct clk *mclk; 933558fe90SMaxime Ripard struct reset_control *rstc; 943558fe90SMaxime Ripard 953558fe90SMaxime Ripard struct completion done; 963558fe90SMaxime Ripard 973558fe90SMaxime Ripard const u8 *tx_buf; 983558fe90SMaxime Ripard u8 *rx_buf; 993558fe90SMaxime Ripard int len; 10010565dfdSMilo Kim unsigned long fifo_depth; 1013558fe90SMaxime Ripard }; 1023558fe90SMaxime Ripard 1033558fe90SMaxime Ripard static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 1043558fe90SMaxime Ripard { 1053558fe90SMaxime Ripard return readl(sspi->base_addr + reg); 1063558fe90SMaxime Ripard } 1073558fe90SMaxime Ripard 1083558fe90SMaxime Ripard static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 1093558fe90SMaxime Ripard { 1103558fe90SMaxime Ripard writel(value, sspi->base_addr + reg); 1113558fe90SMaxime Ripard } 1123558fe90SMaxime Ripard 1135197da03SMarc Kleine-Budde static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) 1145197da03SMarc Kleine-Budde { 1155197da03SMarc Kleine-Budde u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 1165197da03SMarc Kleine-Budde 1175197da03SMarc Kleine-Budde return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); 1185197da03SMarc Kleine-Budde } 1195197da03SMarc Kleine-Budde 120913f536cSIcenowy Zheng static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 121913f536cSIcenowy Zheng { 122913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 123913f536cSIcenowy Zheng 1249a3ef9dfSMarc Kleine-Budde return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 125913f536cSIcenowy Zheng } 126913f536cSIcenowy Zheng 127913f536cSIcenowy Zheng static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) 128913f536cSIcenowy Zheng { 129913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 130913f536cSIcenowy Zheng 131913f536cSIcenowy Zheng reg &= ~mask; 132913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 133913f536cSIcenowy Zheng } 134913f536cSIcenowy Zheng 13592a52ee8SMarc Kleine-Budde static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi) 1363558fe90SMaxime Ripard { 13792a52ee8SMarc Kleine-Budde u32 len; 1383558fe90SMaxime Ripard u8 byte; 1393558fe90SMaxime Ripard 1403558fe90SMaxime Ripard /* See how much data is available */ 14192a52ee8SMarc Kleine-Budde len = sun6i_spi_get_rx_fifo_count(sspi); 1423558fe90SMaxime Ripard 1433558fe90SMaxime Ripard while (len--) { 1443558fe90SMaxime Ripard byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 1453558fe90SMaxime Ripard if (sspi->rx_buf) 1463558fe90SMaxime Ripard *sspi->rx_buf++ = byte; 1473558fe90SMaxime Ripard } 1483558fe90SMaxime Ripard } 1493558fe90SMaxime Ripard 150e4e8ca3fSMarc Kleine-Budde static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) 1513558fe90SMaxime Ripard { 152913f536cSIcenowy Zheng u32 cnt; 153e4e8ca3fSMarc Kleine-Budde int len; 1543558fe90SMaxime Ripard u8 byte; 1553558fe90SMaxime Ripard 156913f536cSIcenowy Zheng /* See how much data we can fit */ 157913f536cSIcenowy Zheng cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); 158913f536cSIcenowy Zheng 159e4e8ca3fSMarc Kleine-Budde len = min((int)cnt, sspi->len); 1603558fe90SMaxime Ripard 1613558fe90SMaxime Ripard while (len--) { 1623558fe90SMaxime Ripard byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 1633558fe90SMaxime Ripard writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 1643558fe90SMaxime Ripard sspi->len--; 1653558fe90SMaxime Ripard } 1663558fe90SMaxime Ripard } 1673558fe90SMaxime Ripard 1683558fe90SMaxime Ripard static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 1693558fe90SMaxime Ripard { 1703558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 1713558fe90SMaxime Ripard u32 reg; 1723558fe90SMaxime Ripard 1733558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 1743558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_MASK; 1753558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 1763558fe90SMaxime Ripard 1773558fe90SMaxime Ripard if (enable) 1783558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_LEVEL; 1793558fe90SMaxime Ripard else 1803558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 1813558fe90SMaxime Ripard 1823558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 1833558fe90SMaxime Ripard } 1843558fe90SMaxime Ripard 185794912cfSMichal Suchanek static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 186794912cfSMichal Suchanek { 1873288d5cbSIcenowy Zheng return SUN6I_MAX_XFER_SIZE - 1; 188794912cfSMichal Suchanek } 1893558fe90SMaxime Ripard 190*345980a3SAlexander Kochetkov static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi, 191*345980a3SAlexander Kochetkov struct spi_transfer *tfr) 192*345980a3SAlexander Kochetkov { 193*345980a3SAlexander Kochetkov struct dma_async_tx_descriptor *rxdesc, *txdesc; 194*345980a3SAlexander Kochetkov struct spi_master *master = sspi->master; 195*345980a3SAlexander Kochetkov 196*345980a3SAlexander Kochetkov rxdesc = NULL; 197*345980a3SAlexander Kochetkov if (tfr->rx_buf) { 198*345980a3SAlexander Kochetkov struct dma_slave_config rxconf = { 199*345980a3SAlexander Kochetkov .direction = DMA_DEV_TO_MEM, 200*345980a3SAlexander Kochetkov .src_addr = sspi->dma_addr_rx, 201*345980a3SAlexander Kochetkov .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 202*345980a3SAlexander Kochetkov .src_maxburst = 8, 203*345980a3SAlexander Kochetkov }; 204*345980a3SAlexander Kochetkov 205*345980a3SAlexander Kochetkov dmaengine_slave_config(master->dma_rx, &rxconf); 206*345980a3SAlexander Kochetkov 207*345980a3SAlexander Kochetkov rxdesc = dmaengine_prep_slave_sg(master->dma_rx, 208*345980a3SAlexander Kochetkov tfr->rx_sg.sgl, 209*345980a3SAlexander Kochetkov tfr->rx_sg.nents, 210*345980a3SAlexander Kochetkov DMA_DEV_TO_MEM, 211*345980a3SAlexander Kochetkov DMA_PREP_INTERRUPT); 212*345980a3SAlexander Kochetkov if (!rxdesc) 213*345980a3SAlexander Kochetkov return -EINVAL; 214*345980a3SAlexander Kochetkov } 215*345980a3SAlexander Kochetkov 216*345980a3SAlexander Kochetkov txdesc = NULL; 217*345980a3SAlexander Kochetkov if (tfr->tx_buf) { 218*345980a3SAlexander Kochetkov struct dma_slave_config txconf = { 219*345980a3SAlexander Kochetkov .direction = DMA_MEM_TO_DEV, 220*345980a3SAlexander Kochetkov .dst_addr = sspi->dma_addr_tx, 221*345980a3SAlexander Kochetkov .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 222*345980a3SAlexander Kochetkov .dst_maxburst = 8, 223*345980a3SAlexander Kochetkov }; 224*345980a3SAlexander Kochetkov 225*345980a3SAlexander Kochetkov dmaengine_slave_config(master->dma_tx, &txconf); 226*345980a3SAlexander Kochetkov 227*345980a3SAlexander Kochetkov txdesc = dmaengine_prep_slave_sg(master->dma_tx, 228*345980a3SAlexander Kochetkov tfr->tx_sg.sgl, 229*345980a3SAlexander Kochetkov tfr->tx_sg.nents, 230*345980a3SAlexander Kochetkov DMA_MEM_TO_DEV, 231*345980a3SAlexander Kochetkov DMA_PREP_INTERRUPT); 232*345980a3SAlexander Kochetkov if (!txdesc) { 233*345980a3SAlexander Kochetkov if (rxdesc) 234*345980a3SAlexander Kochetkov dmaengine_terminate_sync(master->dma_rx); 235*345980a3SAlexander Kochetkov return -EINVAL; 236*345980a3SAlexander Kochetkov } 237*345980a3SAlexander Kochetkov } 238*345980a3SAlexander Kochetkov 239*345980a3SAlexander Kochetkov if (tfr->rx_buf) { 240*345980a3SAlexander Kochetkov dmaengine_submit(rxdesc); 241*345980a3SAlexander Kochetkov dma_async_issue_pending(master->dma_rx); 242*345980a3SAlexander Kochetkov } 243*345980a3SAlexander Kochetkov 244*345980a3SAlexander Kochetkov if (tfr->tx_buf) { 245*345980a3SAlexander Kochetkov dmaengine_submit(txdesc); 246*345980a3SAlexander Kochetkov dma_async_issue_pending(master->dma_tx); 247*345980a3SAlexander Kochetkov } 248*345980a3SAlexander Kochetkov 249*345980a3SAlexander Kochetkov return 0; 250*345980a3SAlexander Kochetkov } 251*345980a3SAlexander Kochetkov 2523558fe90SMaxime Ripard static int sun6i_spi_transfer_one(struct spi_master *master, 2533558fe90SMaxime Ripard struct spi_device *spi, 2543558fe90SMaxime Ripard struct spi_transfer *tfr) 2553558fe90SMaxime Ripard { 2563558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 257ed7815dbSMarc Kleine-Budde unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; 258719bd654SMichal Suchanek unsigned int start, end, tx_time; 259913f536cSIcenowy Zheng unsigned int trig_level; 2607716fa80SMarc Kleine-Budde unsigned int tx_len = 0, rx_len = 0; 261*345980a3SAlexander Kochetkov bool use_dma; 2623558fe90SMaxime Ripard int ret = 0; 2633558fe90SMaxime Ripard u32 reg; 2643558fe90SMaxime Ripard 265913f536cSIcenowy Zheng if (tfr->len > SUN6I_MAX_XFER_SIZE) 2663558fe90SMaxime Ripard return -EINVAL; 2673558fe90SMaxime Ripard 2683558fe90SMaxime Ripard reinit_completion(&sspi->done); 2693558fe90SMaxime Ripard sspi->tx_buf = tfr->tx_buf; 2703558fe90SMaxime Ripard sspi->rx_buf = tfr->rx_buf; 2713558fe90SMaxime Ripard sspi->len = tfr->len; 272*345980a3SAlexander Kochetkov use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; 2733558fe90SMaxime Ripard 2743558fe90SMaxime Ripard /* Clear pending interrupts */ 2753558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 2763558fe90SMaxime Ripard 2773558fe90SMaxime Ripard /* Reset FIFO */ 2783558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 2793558fe90SMaxime Ripard SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 2803558fe90SMaxime Ripard 281*345980a3SAlexander Kochetkov reg = 0; 282*345980a3SAlexander Kochetkov 283*345980a3SAlexander Kochetkov if (!use_dma) { 2843558fe90SMaxime Ripard /* 285913f536cSIcenowy Zheng * Setup FIFO interrupt trigger level 286*345980a3SAlexander Kochetkov * Here we choose 3/4 of the full fifo depth, as it's 287*345980a3SAlexander Kochetkov * the hardcoded value used in old generation of Allwinner 288*345980a3SAlexander Kochetkov * SPI controller. (See spi-sun4i.c) 289913f536cSIcenowy Zheng */ 290913f536cSIcenowy Zheng trig_level = sspi->fifo_depth / 4 * 3; 291*345980a3SAlexander Kochetkov } else { 292*345980a3SAlexander Kochetkov /* 293*345980a3SAlexander Kochetkov * Setup FIFO DMA request trigger level 294*345980a3SAlexander Kochetkov * We choose 1/2 of the full fifo depth, that value will 295*345980a3SAlexander Kochetkov * be used as DMA burst length. 296*345980a3SAlexander Kochetkov */ 297*345980a3SAlexander Kochetkov trig_level = sspi->fifo_depth / 2; 298*345980a3SAlexander Kochetkov 299*345980a3SAlexander Kochetkov if (tfr->tx_buf) 300*345980a3SAlexander Kochetkov reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; 301*345980a3SAlexander Kochetkov if (tfr->rx_buf) 302*345980a3SAlexander Kochetkov reg |= SUN6I_FIFO_CTL_RF_DRQ_EN; 303*345980a3SAlexander Kochetkov } 304*345980a3SAlexander Kochetkov 305*345980a3SAlexander Kochetkov reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | 306*345980a3SAlexander Kochetkov (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS); 307*345980a3SAlexander Kochetkov 308*345980a3SAlexander Kochetkov sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); 309913f536cSIcenowy Zheng 310913f536cSIcenowy Zheng /* 3113558fe90SMaxime Ripard * Setup the transfer control register: Chip Select, 3123558fe90SMaxime Ripard * polarities, etc. 3133558fe90SMaxime Ripard */ 3143558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 3153558fe90SMaxime Ripard 3163558fe90SMaxime Ripard if (spi->mode & SPI_CPOL) 3173558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPOL; 3183558fe90SMaxime Ripard else 3193558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPOL; 3203558fe90SMaxime Ripard 3213558fe90SMaxime Ripard if (spi->mode & SPI_CPHA) 3223558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPHA; 3233558fe90SMaxime Ripard else 3243558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPHA; 3253558fe90SMaxime Ripard 3263558fe90SMaxime Ripard if (spi->mode & SPI_LSB_FIRST) 3273558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_FBS; 3283558fe90SMaxime Ripard else 3293558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_FBS; 3303558fe90SMaxime Ripard 3313558fe90SMaxime Ripard /* 3323558fe90SMaxime Ripard * If it's a TX only transfer, we don't want to fill the RX 3333558fe90SMaxime Ripard * FIFO with bogus data 3343558fe90SMaxime Ripard */ 3357716fa80SMarc Kleine-Budde if (sspi->rx_buf) { 3363558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_DHB; 3377716fa80SMarc Kleine-Budde rx_len = tfr->len; 3387716fa80SMarc Kleine-Budde } else { 3393558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_DHB; 3407716fa80SMarc Kleine-Budde } 3413558fe90SMaxime Ripard 3423558fe90SMaxime Ripard /* We want to control the chip select manually */ 3433558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_MANUAL; 3443558fe90SMaxime Ripard 3453558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 3463558fe90SMaxime Ripard 3473558fe90SMaxime Ripard /* Ensure that we have a parent clock fast enough */ 3483558fe90SMaxime Ripard mclk_rate = clk_get_rate(sspi->mclk); 34947284e3eSMarcus Weseloh if (mclk_rate < (2 * tfr->speed_hz)) { 35047284e3eSMarcus Weseloh clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 3513558fe90SMaxime Ripard mclk_rate = clk_get_rate(sspi->mclk); 3523558fe90SMaxime Ripard } 3533558fe90SMaxime Ripard 3543558fe90SMaxime Ripard /* 3553558fe90SMaxime Ripard * Setup clock divider. 3563558fe90SMaxime Ripard * 3573558fe90SMaxime Ripard * We have two choices there. Either we can use the clock 3583558fe90SMaxime Ripard * divide rate 1, which is calculated thanks to this formula: 3593558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 ^ cdr) 3603558fe90SMaxime Ripard * Or we can use CDR2, which is calculated with the formula: 3613558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 3623558fe90SMaxime Ripard * Wether we use the former or the latter is set through the 3633558fe90SMaxime Ripard * DRS bit. 3643558fe90SMaxime Ripard * 3653558fe90SMaxime Ripard * First try CDR2, and if we can't reach the expected 3663558fe90SMaxime Ripard * frequency, fall back to CDR1. 3673558fe90SMaxime Ripard */ 368ed7815dbSMarc Kleine-Budde div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); 369ed7815dbSMarc Kleine-Budde div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); 370ed7815dbSMarc Kleine-Budde if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 371ed7815dbSMarc Kleine-Budde reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; 3720bc7b8a2SMarc Kleine-Budde tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); 3733558fe90SMaxime Ripard } else { 374ed7815dbSMarc Kleine-Budde div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); 3753558fe90SMaxime Ripard reg = SUN6I_CLK_CTL_CDR1(div); 3760bc7b8a2SMarc Kleine-Budde tfr->effective_speed_hz = mclk_rate / (1 << div); 3773558fe90SMaxime Ripard } 3783558fe90SMaxime Ripard 3793558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 3803558fe90SMaxime Ripard 3813558fe90SMaxime Ripard /* Setup the transfer now... */ 3823558fe90SMaxime Ripard if (sspi->tx_buf) 3833558fe90SMaxime Ripard tx_len = tfr->len; 3843558fe90SMaxime Ripard 3853558fe90SMaxime Ripard /* Setup the counters */ 3862130be57SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); 3872130be57SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); 3882130be57SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); 3893558fe90SMaxime Ripard 390*345980a3SAlexander Kochetkov if (!use_dma) { 3913558fe90SMaxime Ripard /* Fill the TX FIFO */ 392e4e8ca3fSMarc Kleine-Budde sun6i_spi_fill_fifo(sspi); 393*345980a3SAlexander Kochetkov } else { 394*345980a3SAlexander Kochetkov ret = sun6i_spi_prepare_dma(sspi, tfr); 395*345980a3SAlexander Kochetkov if (ret) { 396*345980a3SAlexander Kochetkov dev_warn(&master->dev, 397*345980a3SAlexander Kochetkov "%s: prepare DMA failed, ret=%d", 398*345980a3SAlexander Kochetkov dev_name(&spi->dev), ret); 399*345980a3SAlexander Kochetkov return ret; 400*345980a3SAlexander Kochetkov } 401*345980a3SAlexander Kochetkov } 4023558fe90SMaxime Ripard 4033558fe90SMaxime Ripard /* Enable the interrupts */ 4047716fa80SMarc Kleine-Budde reg = SUN6I_INT_CTL_TC; 4054e7390e9SMarc Kleine-Budde 406*345980a3SAlexander Kochetkov if (!use_dma) { 4077716fa80SMarc Kleine-Budde if (rx_len > sspi->fifo_depth) 4087716fa80SMarc Kleine-Budde reg |= SUN6I_INT_CTL_RF_RDY; 409913f536cSIcenowy Zheng if (tx_len > sspi->fifo_depth) 4104e7390e9SMarc Kleine-Budde reg |= SUN6I_INT_CTL_TF_ERQ; 411*345980a3SAlexander Kochetkov } 4124e7390e9SMarc Kleine-Budde 4134e7390e9SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 4143558fe90SMaxime Ripard 4153558fe90SMaxime Ripard /* Start the transfer */ 4163558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 4173558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 4183558fe90SMaxime Ripard 419719bd654SMichal Suchanek tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 420719bd654SMichal Suchanek start = jiffies; 4213558fe90SMaxime Ripard timeout = wait_for_completion_timeout(&sspi->done, 422719bd654SMichal Suchanek msecs_to_jiffies(tx_time)); 423719bd654SMichal Suchanek end = jiffies; 4243558fe90SMaxime Ripard if (!timeout) { 425719bd654SMichal Suchanek dev_warn(&master->dev, 426719bd654SMichal Suchanek "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 427719bd654SMichal Suchanek dev_name(&spi->dev), tfr->len, tfr->speed_hz, 428719bd654SMichal Suchanek jiffies_to_msecs(end - start), tx_time); 4293558fe90SMaxime Ripard ret = -ETIMEDOUT; 4303558fe90SMaxime Ripard } 4313558fe90SMaxime Ripard 4323558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 4333558fe90SMaxime Ripard 434*345980a3SAlexander Kochetkov if (ret && use_dma) { 435*345980a3SAlexander Kochetkov dmaengine_terminate_sync(master->dma_rx); 436*345980a3SAlexander Kochetkov dmaengine_terminate_sync(master->dma_tx); 437*345980a3SAlexander Kochetkov } 438*345980a3SAlexander Kochetkov 4393558fe90SMaxime Ripard return ret; 4403558fe90SMaxime Ripard } 4413558fe90SMaxime Ripard 4423558fe90SMaxime Ripard static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 4433558fe90SMaxime Ripard { 4443558fe90SMaxime Ripard struct sun6i_spi *sspi = dev_id; 4453558fe90SMaxime Ripard u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 4463558fe90SMaxime Ripard 4473558fe90SMaxime Ripard /* Transfer complete */ 4483558fe90SMaxime Ripard if (status & SUN6I_INT_CTL_TC) { 4493558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 45092a52ee8SMarc Kleine-Budde sun6i_spi_drain_fifo(sspi); 4513558fe90SMaxime Ripard complete(&sspi->done); 4523558fe90SMaxime Ripard return IRQ_HANDLED; 4533558fe90SMaxime Ripard } 4543558fe90SMaxime Ripard 455913f536cSIcenowy Zheng /* Receive FIFO 3/4 full */ 456913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_RF_RDY) { 45792a52ee8SMarc Kleine-Budde sun6i_spi_drain_fifo(sspi); 458913f536cSIcenowy Zheng /* Only clear the interrupt _after_ draining the FIFO */ 459913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); 460913f536cSIcenowy Zheng return IRQ_HANDLED; 461913f536cSIcenowy Zheng } 462913f536cSIcenowy Zheng 463913f536cSIcenowy Zheng /* Transmit FIFO 3/4 empty */ 464913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_TF_ERQ) { 465e4e8ca3fSMarc Kleine-Budde sun6i_spi_fill_fifo(sspi); 466913f536cSIcenowy Zheng 467913f536cSIcenowy Zheng if (!sspi->len) 468913f536cSIcenowy Zheng /* nothing left to transmit */ 469913f536cSIcenowy Zheng sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 470913f536cSIcenowy Zheng 471913f536cSIcenowy Zheng /* Only clear the interrupt _after_ re-seeding the FIFO */ 472913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); 473913f536cSIcenowy Zheng 474913f536cSIcenowy Zheng return IRQ_HANDLED; 475913f536cSIcenowy Zheng } 476913f536cSIcenowy Zheng 4773558fe90SMaxime Ripard return IRQ_NONE; 4783558fe90SMaxime Ripard } 4793558fe90SMaxime Ripard 4803558fe90SMaxime Ripard static int sun6i_spi_runtime_resume(struct device *dev) 4813558fe90SMaxime Ripard { 4823558fe90SMaxime Ripard struct spi_master *master = dev_get_drvdata(dev); 4833558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 4843558fe90SMaxime Ripard int ret; 4853558fe90SMaxime Ripard 4863558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->hclk); 4873558fe90SMaxime Ripard if (ret) { 4883558fe90SMaxime Ripard dev_err(dev, "Couldn't enable AHB clock\n"); 4893558fe90SMaxime Ripard goto out; 4903558fe90SMaxime Ripard } 4913558fe90SMaxime Ripard 4923558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->mclk); 4933558fe90SMaxime Ripard if (ret) { 4943558fe90SMaxime Ripard dev_err(dev, "Couldn't enable module clock\n"); 4953558fe90SMaxime Ripard goto err; 4963558fe90SMaxime Ripard } 4973558fe90SMaxime Ripard 4983558fe90SMaxime Ripard ret = reset_control_deassert(sspi->rstc); 4993558fe90SMaxime Ripard if (ret) { 5003558fe90SMaxime Ripard dev_err(dev, "Couldn't deassert the device from reset\n"); 5013558fe90SMaxime Ripard goto err2; 5023558fe90SMaxime Ripard } 5033558fe90SMaxime Ripard 5043558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 5053558fe90SMaxime Ripard SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 5063558fe90SMaxime Ripard 5073558fe90SMaxime Ripard return 0; 5083558fe90SMaxime Ripard 5093558fe90SMaxime Ripard err2: 5103558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk); 5113558fe90SMaxime Ripard err: 5123558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk); 5133558fe90SMaxime Ripard out: 5143558fe90SMaxime Ripard return ret; 5153558fe90SMaxime Ripard } 5163558fe90SMaxime Ripard 5173558fe90SMaxime Ripard static int sun6i_spi_runtime_suspend(struct device *dev) 5183558fe90SMaxime Ripard { 5193558fe90SMaxime Ripard struct spi_master *master = dev_get_drvdata(dev); 5203558fe90SMaxime Ripard struct sun6i_spi *sspi = spi_master_get_devdata(master); 5213558fe90SMaxime Ripard 5223558fe90SMaxime Ripard reset_control_assert(sspi->rstc); 5233558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk); 5243558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk); 5253558fe90SMaxime Ripard 5263558fe90SMaxime Ripard return 0; 5273558fe90SMaxime Ripard } 5283558fe90SMaxime Ripard 529*345980a3SAlexander Kochetkov static bool sun6i_spi_can_dma(struct spi_master *master, 530*345980a3SAlexander Kochetkov struct spi_device *spi, 531*345980a3SAlexander Kochetkov struct spi_transfer *xfer) 532*345980a3SAlexander Kochetkov { 533*345980a3SAlexander Kochetkov struct sun6i_spi *sspi = spi_master_get_devdata(master); 534*345980a3SAlexander Kochetkov 535*345980a3SAlexander Kochetkov /* 536*345980a3SAlexander Kochetkov * If the number of spi words to transfer is less or equal than 537*345980a3SAlexander Kochetkov * the fifo length we can just fill the fifo and wait for a single 538*345980a3SAlexander Kochetkov * irq, so don't bother setting up dma 539*345980a3SAlexander Kochetkov */ 540*345980a3SAlexander Kochetkov return xfer->len > sspi->fifo_depth; 541*345980a3SAlexander Kochetkov } 542*345980a3SAlexander Kochetkov 5433558fe90SMaxime Ripard static int sun6i_spi_probe(struct platform_device *pdev) 5443558fe90SMaxime Ripard { 5453558fe90SMaxime Ripard struct spi_master *master; 5463558fe90SMaxime Ripard struct sun6i_spi *sspi; 547*345980a3SAlexander Kochetkov struct resource *mem; 5483558fe90SMaxime Ripard int ret = 0, irq; 5493558fe90SMaxime Ripard 5503558fe90SMaxime Ripard master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 5513558fe90SMaxime Ripard if (!master) { 5523558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 5533558fe90SMaxime Ripard return -ENOMEM; 5543558fe90SMaxime Ripard } 5553558fe90SMaxime Ripard 5563558fe90SMaxime Ripard platform_set_drvdata(pdev, master); 5573558fe90SMaxime Ripard sspi = spi_master_get_devdata(master); 5583558fe90SMaxime Ripard 559*345980a3SAlexander Kochetkov sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 5603558fe90SMaxime Ripard if (IS_ERR(sspi->base_addr)) { 5613558fe90SMaxime Ripard ret = PTR_ERR(sspi->base_addr); 5623558fe90SMaxime Ripard goto err_free_master; 5633558fe90SMaxime Ripard } 5643558fe90SMaxime Ripard 5653558fe90SMaxime Ripard irq = platform_get_irq(pdev, 0); 5663558fe90SMaxime Ripard if (irq < 0) { 5673558fe90SMaxime Ripard ret = -ENXIO; 5683558fe90SMaxime Ripard goto err_free_master; 5693558fe90SMaxime Ripard } 5703558fe90SMaxime Ripard 5713558fe90SMaxime Ripard ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 5723558fe90SMaxime Ripard 0, "sun6i-spi", sspi); 5733558fe90SMaxime Ripard if (ret) { 5743558fe90SMaxime Ripard dev_err(&pdev->dev, "Cannot request IRQ\n"); 5753558fe90SMaxime Ripard goto err_free_master; 5763558fe90SMaxime Ripard } 5773558fe90SMaxime Ripard 5783558fe90SMaxime Ripard sspi->master = master; 57910565dfdSMilo Kim sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); 58010565dfdSMilo Kim 5810b06d8cfSMichal Suchanek master->max_speed_hz = 100 * 1000 * 1000; 5820b06d8cfSMichal Suchanek master->min_speed_hz = 3 * 1000; 58374750e06SAlistair Francis master->use_gpio_descriptors = true; 5843558fe90SMaxime Ripard master->set_cs = sun6i_spi_set_cs; 5853558fe90SMaxime Ripard master->transfer_one = sun6i_spi_transfer_one; 5863558fe90SMaxime Ripard master->num_chipselect = 4; 5873558fe90SMaxime Ripard master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 588743a46b8SAxel Lin master->bits_per_word_mask = SPI_BPW_MASK(8); 5893558fe90SMaxime Ripard master->dev.of_node = pdev->dev.of_node; 5903558fe90SMaxime Ripard master->auto_runtime_pm = true; 591794912cfSMichal Suchanek master->max_transfer_size = sun6i_spi_max_transfer_size; 5923558fe90SMaxime Ripard 5933558fe90SMaxime Ripard sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 5943558fe90SMaxime Ripard if (IS_ERR(sspi->hclk)) { 5953558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 5963558fe90SMaxime Ripard ret = PTR_ERR(sspi->hclk); 5973558fe90SMaxime Ripard goto err_free_master; 5983558fe90SMaxime Ripard } 5993558fe90SMaxime Ripard 6003558fe90SMaxime Ripard sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 6013558fe90SMaxime Ripard if (IS_ERR(sspi->mclk)) { 6023558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire module clock\n"); 6033558fe90SMaxime Ripard ret = PTR_ERR(sspi->mclk); 6043558fe90SMaxime Ripard goto err_free_master; 6053558fe90SMaxime Ripard } 6063558fe90SMaxime Ripard 6073558fe90SMaxime Ripard init_completion(&sspi->done); 6083558fe90SMaxime Ripard 60936bc7491SPhilipp Zabel sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 6103558fe90SMaxime Ripard if (IS_ERR(sspi->rstc)) { 6113558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't get reset controller\n"); 6123558fe90SMaxime Ripard ret = PTR_ERR(sspi->rstc); 6133558fe90SMaxime Ripard goto err_free_master; 6143558fe90SMaxime Ripard } 6153558fe90SMaxime Ripard 616*345980a3SAlexander Kochetkov master->dma_tx = dma_request_chan(&pdev->dev, "tx"); 617*345980a3SAlexander Kochetkov if (IS_ERR(master->dma_tx)) { 618*345980a3SAlexander Kochetkov /* Check tx to see if we need defer probing driver */ 619*345980a3SAlexander Kochetkov if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { 620*345980a3SAlexander Kochetkov ret = -EPROBE_DEFER; 621*345980a3SAlexander Kochetkov goto err_free_master; 622*345980a3SAlexander Kochetkov } 623*345980a3SAlexander Kochetkov dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); 624*345980a3SAlexander Kochetkov master->dma_tx = NULL; 625*345980a3SAlexander Kochetkov } 626*345980a3SAlexander Kochetkov 627*345980a3SAlexander Kochetkov master->dma_rx = dma_request_chan(&pdev->dev, "rx"); 628*345980a3SAlexander Kochetkov if (IS_ERR(master->dma_rx)) { 629*345980a3SAlexander Kochetkov if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { 630*345980a3SAlexander Kochetkov ret = -EPROBE_DEFER; 631*345980a3SAlexander Kochetkov goto err_free_dma_tx; 632*345980a3SAlexander Kochetkov } 633*345980a3SAlexander Kochetkov dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); 634*345980a3SAlexander Kochetkov master->dma_rx = NULL; 635*345980a3SAlexander Kochetkov } 636*345980a3SAlexander Kochetkov 637*345980a3SAlexander Kochetkov if (master->dma_tx && master->dma_rx) { 638*345980a3SAlexander Kochetkov sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; 639*345980a3SAlexander Kochetkov sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; 640*345980a3SAlexander Kochetkov master->can_dma = sun6i_spi_can_dma; 641*345980a3SAlexander Kochetkov } 642*345980a3SAlexander Kochetkov 6433558fe90SMaxime Ripard /* 6443558fe90SMaxime Ripard * This wake-up/shutdown pattern is to be able to have the 6453558fe90SMaxime Ripard * device woken up, even if runtime_pm is disabled 6463558fe90SMaxime Ripard */ 6473558fe90SMaxime Ripard ret = sun6i_spi_runtime_resume(&pdev->dev); 6483558fe90SMaxime Ripard if (ret) { 6493558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't resume the device\n"); 650*345980a3SAlexander Kochetkov goto err_free_dma_rx; 6513558fe90SMaxime Ripard } 6523558fe90SMaxime Ripard 6533558fe90SMaxime Ripard pm_runtime_set_active(&pdev->dev); 6543558fe90SMaxime Ripard pm_runtime_enable(&pdev->dev); 6553558fe90SMaxime Ripard pm_runtime_idle(&pdev->dev); 6563558fe90SMaxime Ripard 6573558fe90SMaxime Ripard ret = devm_spi_register_master(&pdev->dev, master); 6583558fe90SMaxime Ripard if (ret) { 6593558fe90SMaxime Ripard dev_err(&pdev->dev, "cannot register SPI master\n"); 6603558fe90SMaxime Ripard goto err_pm_disable; 6613558fe90SMaxime Ripard } 6623558fe90SMaxime Ripard 6633558fe90SMaxime Ripard return 0; 6643558fe90SMaxime Ripard 6653558fe90SMaxime Ripard err_pm_disable: 6663558fe90SMaxime Ripard pm_runtime_disable(&pdev->dev); 6673558fe90SMaxime Ripard sun6i_spi_runtime_suspend(&pdev->dev); 668*345980a3SAlexander Kochetkov err_free_dma_rx: 669*345980a3SAlexander Kochetkov if (master->dma_rx) 670*345980a3SAlexander Kochetkov dma_release_channel(master->dma_rx); 671*345980a3SAlexander Kochetkov err_free_dma_tx: 672*345980a3SAlexander Kochetkov if (master->dma_tx) 673*345980a3SAlexander Kochetkov dma_release_channel(master->dma_tx); 6743558fe90SMaxime Ripard err_free_master: 6753558fe90SMaxime Ripard spi_master_put(master); 6763558fe90SMaxime Ripard return ret; 6773558fe90SMaxime Ripard } 6783558fe90SMaxime Ripard 6793558fe90SMaxime Ripard static int sun6i_spi_remove(struct platform_device *pdev) 6803558fe90SMaxime Ripard { 681*345980a3SAlexander Kochetkov struct spi_master *master = platform_get_drvdata(pdev); 682*345980a3SAlexander Kochetkov 6832d9bbd02STobias Jordan pm_runtime_force_suspend(&pdev->dev); 6843558fe90SMaxime Ripard 685*345980a3SAlexander Kochetkov if (master->dma_tx) 686*345980a3SAlexander Kochetkov dma_release_channel(master->dma_tx); 687*345980a3SAlexander Kochetkov if (master->dma_rx) 688*345980a3SAlexander Kochetkov dma_release_channel(master->dma_rx); 6893558fe90SMaxime Ripard return 0; 6903558fe90SMaxime Ripard } 6913558fe90SMaxime Ripard 6923558fe90SMaxime Ripard static const struct of_device_id sun6i_spi_match[] = { 69310565dfdSMilo Kim { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, 69410565dfdSMilo Kim { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, 6953558fe90SMaxime Ripard {} 6963558fe90SMaxime Ripard }; 6973558fe90SMaxime Ripard MODULE_DEVICE_TABLE(of, sun6i_spi_match); 6983558fe90SMaxime Ripard 6993558fe90SMaxime Ripard static const struct dev_pm_ops sun6i_spi_pm_ops = { 7003558fe90SMaxime Ripard .runtime_resume = sun6i_spi_runtime_resume, 7013558fe90SMaxime Ripard .runtime_suspend = sun6i_spi_runtime_suspend, 7023558fe90SMaxime Ripard }; 7033558fe90SMaxime Ripard 7043558fe90SMaxime Ripard static struct platform_driver sun6i_spi_driver = { 7053558fe90SMaxime Ripard .probe = sun6i_spi_probe, 7063558fe90SMaxime Ripard .remove = sun6i_spi_remove, 7073558fe90SMaxime Ripard .driver = { 7083558fe90SMaxime Ripard .name = "sun6i-spi", 7093558fe90SMaxime Ripard .of_match_table = sun6i_spi_match, 7103558fe90SMaxime Ripard .pm = &sun6i_spi_pm_ops, 7113558fe90SMaxime Ripard }, 7123558fe90SMaxime Ripard }; 7133558fe90SMaxime Ripard module_platform_driver(sun6i_spi_driver); 7143558fe90SMaxime Ripard 7153558fe90SMaxime Ripard MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 7163558fe90SMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 7173558fe90SMaxime Ripard MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 7183558fe90SMaxime Ripard MODULE_LICENSE("GPL"); 719