12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
23558fe90SMaxime Ripard /*
33558fe90SMaxime Ripard * Copyright (C) 2012 - 2014 Allwinner Tech
43558fe90SMaxime Ripard * Pan Nan <pannan@allwinnertech.com>
53558fe90SMaxime Ripard *
63558fe90SMaxime Ripard * Copyright (C) 2014 Maxime Ripard
73558fe90SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com>
83558fe90SMaxime Ripard */
93558fe90SMaxime Ripard
109a3ef9dfSMarc Kleine-Budde #include <linux/bitfield.h>
113558fe90SMaxime Ripard #include <linux/clk.h>
123558fe90SMaxime Ripard #include <linux/delay.h>
133558fe90SMaxime Ripard #include <linux/device.h>
143558fe90SMaxime Ripard #include <linux/interrupt.h>
153558fe90SMaxime Ripard #include <linux/io.h>
163558fe90SMaxime Ripard #include <linux/module.h>
17749396cbSRob Herring #include <linux/of.h>
183558fe90SMaxime Ripard #include <linux/platform_device.h>
193558fe90SMaxime Ripard #include <linux/pm_runtime.h>
203558fe90SMaxime Ripard #include <linux/reset.h>
21345980a3SAlexander Kochetkov #include <linux/dmaengine.h>
223558fe90SMaxime Ripard
233558fe90SMaxime Ripard #include <linux/spi/spi.h>
243558fe90SMaxime Ripard
25ae0f18beSAlexander Kochetkov #define SUN6I_AUTOSUSPEND_TIMEOUT 2000
26ae0f18beSAlexander Kochetkov
273558fe90SMaxime Ripard #define SUN6I_FIFO_DEPTH 128
2810565dfdSMilo Kim #define SUN8I_FIFO_DEPTH 64
293558fe90SMaxime Ripard
303558fe90SMaxime Ripard #define SUN6I_GBL_CTL_REG 0x04
313558fe90SMaxime Ripard #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
323558fe90SMaxime Ripard #define SUN6I_GBL_CTL_MASTER BIT(1)
333558fe90SMaxime Ripard #define SUN6I_GBL_CTL_TP BIT(7)
343558fe90SMaxime Ripard #define SUN6I_GBL_CTL_RST BIT(31)
353558fe90SMaxime Ripard
363558fe90SMaxime Ripard #define SUN6I_TFR_CTL_REG 0x08
373558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPHA BIT(0)
383558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CPOL BIT(1)
393558fe90SMaxime Ripard #define SUN6I_TFR_CTL_SPOL BIT(2)
40d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS_MASK 0x30
41d31ad46fSAxel Lin #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
423558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
433558fe90SMaxime Ripard #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
443558fe90SMaxime Ripard #define SUN6I_TFR_CTL_DHB BIT(8)
458e886ac8SMaksim Kiselev #define SUN6I_TFR_CTL_SDC BIT(11)
463558fe90SMaxime Ripard #define SUN6I_TFR_CTL_FBS BIT(12)
478e886ac8SMaksim Kiselev #define SUN6I_TFR_CTL_SDM BIT(13)
483558fe90SMaxime Ripard #define SUN6I_TFR_CTL_XCH BIT(31)
493558fe90SMaxime Ripard
503558fe90SMaxime Ripard #define SUN6I_INT_CTL_REG 0x10
51913f536cSIcenowy Zheng #define SUN6I_INT_CTL_RF_RDY BIT(0)
52913f536cSIcenowy Zheng #define SUN6I_INT_CTL_TF_ERQ BIT(4)
533558fe90SMaxime Ripard #define SUN6I_INT_CTL_RF_OVF BIT(8)
543558fe90SMaxime Ripard #define SUN6I_INT_CTL_TC BIT(12)
553558fe90SMaxime Ripard
563558fe90SMaxime Ripard #define SUN6I_INT_STA_REG 0x14
573558fe90SMaxime Ripard
583558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_REG 0x18
59913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
60345980a3SAlexander Kochetkov #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
61913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
623558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_RF_RST BIT(15)
63913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
64913f536cSIcenowy Zheng #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
65345980a3SAlexander Kochetkov #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
663558fe90SMaxime Ripard #define SUN6I_FIFO_CTL_TF_RST BIT(31)
673558fe90SMaxime Ripard
683558fe90SMaxime Ripard #define SUN6I_FIFO_STA_REG 0x1c
695197da03SMarc Kleine-Budde #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
709a3ef9dfSMarc Kleine-Budde #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
713558fe90SMaxime Ripard
723558fe90SMaxime Ripard #define SUN6I_CLK_CTL_REG 0x24
733558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2_MASK 0xff
743558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
753558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1_MASK 0xf
763558fe90SMaxime Ripard #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
773558fe90SMaxime Ripard #define SUN6I_CLK_CTL_DRS BIT(12)
783558fe90SMaxime Ripard
79913f536cSIcenowy Zheng #define SUN6I_MAX_XFER_SIZE 0xffffff
80913f536cSIcenowy Zheng
813558fe90SMaxime Ripard #define SUN6I_BURST_CNT_REG 0x30
823558fe90SMaxime Ripard
833558fe90SMaxime Ripard #define SUN6I_XMIT_CNT_REG 0x34
843558fe90SMaxime Ripard
853558fe90SMaxime Ripard #define SUN6I_BURST_CTL_CNT_REG 0x38
860605d9fbSMaksim Kiselev #define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0)
870605d9fbSMaksim Kiselev #define SUN6I_BURST_CTL_CNT_DRM BIT(28)
880605d9fbSMaksim Kiselev #define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)
893558fe90SMaxime Ripard
903558fe90SMaxime Ripard #define SUN6I_TXDATA_REG 0x200
913558fe90SMaxime Ripard #define SUN6I_RXDATA_REG 0x300
923558fe90SMaxime Ripard
93b00c0d89SIcenowy Zheng struct sun6i_spi_cfg {
94b00c0d89SIcenowy Zheng unsigned long fifo_depth;
958e886ac8SMaksim Kiselev bool has_clk_ctl;
960605d9fbSMaksim Kiselev u32 mode_bits;
97b00c0d89SIcenowy Zheng };
98b00c0d89SIcenowy Zheng
993558fe90SMaxime Ripard struct sun6i_spi {
1009f55bb79SYang Yingliang struct spi_controller *host;
1013558fe90SMaxime Ripard void __iomem *base_addr;
102345980a3SAlexander Kochetkov dma_addr_t dma_addr_rx;
103345980a3SAlexander Kochetkov dma_addr_t dma_addr_tx;
1043558fe90SMaxime Ripard struct clk *hclk;
1053558fe90SMaxime Ripard struct clk *mclk;
1063558fe90SMaxime Ripard struct reset_control *rstc;
1073558fe90SMaxime Ripard
1083558fe90SMaxime Ripard struct completion done;
1091f11f420STobias Schramm struct completion dma_rx_done;
1103558fe90SMaxime Ripard
1113558fe90SMaxime Ripard const u8 *tx_buf;
1123558fe90SMaxime Ripard u8 *rx_buf;
1133558fe90SMaxime Ripard int len;
114b00c0d89SIcenowy Zheng const struct sun6i_spi_cfg *cfg;
1153558fe90SMaxime Ripard };
1163558fe90SMaxime Ripard
sun6i_spi_read(struct sun6i_spi * sspi,u32 reg)1173558fe90SMaxime Ripard static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
1183558fe90SMaxime Ripard {
1193558fe90SMaxime Ripard return readl(sspi->base_addr + reg);
1203558fe90SMaxime Ripard }
1213558fe90SMaxime Ripard
sun6i_spi_write(struct sun6i_spi * sspi,u32 reg,u32 value)1223558fe90SMaxime Ripard static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
1233558fe90SMaxime Ripard {
1243558fe90SMaxime Ripard writel(value, sspi->base_addr + reg);
1253558fe90SMaxime Ripard }
1263558fe90SMaxime Ripard
sun6i_spi_get_rx_fifo_count(struct sun6i_spi * sspi)1275197da03SMarc Kleine-Budde static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
1285197da03SMarc Kleine-Budde {
1295197da03SMarc Kleine-Budde u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
1305197da03SMarc Kleine-Budde
1315197da03SMarc Kleine-Budde return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
1325197da03SMarc Kleine-Budde }
1335197da03SMarc Kleine-Budde
sun6i_spi_get_tx_fifo_count(struct sun6i_spi * sspi)134913f536cSIcenowy Zheng static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
135913f536cSIcenowy Zheng {
136913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
137913f536cSIcenowy Zheng
1389a3ef9dfSMarc Kleine-Budde return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
139913f536cSIcenowy Zheng }
140913f536cSIcenowy Zheng
sun6i_spi_disable_interrupt(struct sun6i_spi * sspi,u32 mask)141913f536cSIcenowy Zheng static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
142913f536cSIcenowy Zheng {
143913f536cSIcenowy Zheng u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
144913f536cSIcenowy Zheng
145913f536cSIcenowy Zheng reg &= ~mask;
146913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
147913f536cSIcenowy Zheng }
148913f536cSIcenowy Zheng
sun6i_spi_drain_fifo(struct sun6i_spi * sspi)14992a52ee8SMarc Kleine-Budde static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
1503558fe90SMaxime Ripard {
15192a52ee8SMarc Kleine-Budde u32 len;
1523558fe90SMaxime Ripard u8 byte;
1533558fe90SMaxime Ripard
1543558fe90SMaxime Ripard /* See how much data is available */
15592a52ee8SMarc Kleine-Budde len = sun6i_spi_get_rx_fifo_count(sspi);
1563558fe90SMaxime Ripard
1573558fe90SMaxime Ripard while (len--) {
1583558fe90SMaxime Ripard byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
1593558fe90SMaxime Ripard if (sspi->rx_buf)
1603558fe90SMaxime Ripard *sspi->rx_buf++ = byte;
1613558fe90SMaxime Ripard }
1623558fe90SMaxime Ripard }
1633558fe90SMaxime Ripard
sun6i_spi_fill_fifo(struct sun6i_spi * sspi)164e4e8ca3fSMarc Kleine-Budde static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
1653558fe90SMaxime Ripard {
166913f536cSIcenowy Zheng u32 cnt;
167e4e8ca3fSMarc Kleine-Budde int len;
1683558fe90SMaxime Ripard u8 byte;
1693558fe90SMaxime Ripard
170913f536cSIcenowy Zheng /* See how much data we can fit */
171b00c0d89SIcenowy Zheng cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
172913f536cSIcenowy Zheng
173e4e8ca3fSMarc Kleine-Budde len = min((int)cnt, sspi->len);
1743558fe90SMaxime Ripard
1753558fe90SMaxime Ripard while (len--) {
1763558fe90SMaxime Ripard byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
1773558fe90SMaxime Ripard writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
1783558fe90SMaxime Ripard sspi->len--;
1793558fe90SMaxime Ripard }
1803558fe90SMaxime Ripard }
1813558fe90SMaxime Ripard
sun6i_spi_set_cs(struct spi_device * spi,bool enable)1823558fe90SMaxime Ripard static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
1833558fe90SMaxime Ripard {
1849f55bb79SYang Yingliang struct sun6i_spi *sspi = spi_controller_get_devdata(spi->controller);
1853558fe90SMaxime Ripard u32 reg;
1863558fe90SMaxime Ripard
1873558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
1883558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_MASK;
1899e264f3fSAmit Kumar Mahapatra via Alsa-devel reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));
1903558fe90SMaxime Ripard
1913558fe90SMaxime Ripard if (enable)
1923558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_LEVEL;
1933558fe90SMaxime Ripard else
1943558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
1953558fe90SMaxime Ripard
1963558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
1973558fe90SMaxime Ripard }
1983558fe90SMaxime Ripard
sun6i_spi_max_transfer_size(struct spi_device * spi)199794912cfSMichal Suchanek static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
200794912cfSMichal Suchanek {
2013288d5cbSIcenowy Zheng return SUN6I_MAX_XFER_SIZE - 1;
202794912cfSMichal Suchanek }
2033558fe90SMaxime Ripard
sun6i_spi_dma_rx_cb(void * param)2041f11f420STobias Schramm static void sun6i_spi_dma_rx_cb(void *param)
2051f11f420STobias Schramm {
2061f11f420STobias Schramm struct sun6i_spi *sspi = param;
2071f11f420STobias Schramm
2081f11f420STobias Schramm complete(&sspi->dma_rx_done);
2091f11f420STobias Schramm }
2101f11f420STobias Schramm
sun6i_spi_prepare_dma(struct sun6i_spi * sspi,struct spi_transfer * tfr)211345980a3SAlexander Kochetkov static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
212345980a3SAlexander Kochetkov struct spi_transfer *tfr)
213345980a3SAlexander Kochetkov {
214345980a3SAlexander Kochetkov struct dma_async_tx_descriptor *rxdesc, *txdesc;
2159f55bb79SYang Yingliang struct spi_controller *host = sspi->host;
216345980a3SAlexander Kochetkov
217345980a3SAlexander Kochetkov rxdesc = NULL;
218345980a3SAlexander Kochetkov if (tfr->rx_buf) {
219345980a3SAlexander Kochetkov struct dma_slave_config rxconf = {
220345980a3SAlexander Kochetkov .direction = DMA_DEV_TO_MEM,
221345980a3SAlexander Kochetkov .src_addr = sspi->dma_addr_rx,
222171f8a49STobias Schramm .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
223345980a3SAlexander Kochetkov .src_maxburst = 8,
224345980a3SAlexander Kochetkov };
225345980a3SAlexander Kochetkov
2269f55bb79SYang Yingliang dmaengine_slave_config(host->dma_rx, &rxconf);
227345980a3SAlexander Kochetkov
2289f55bb79SYang Yingliang rxdesc = dmaengine_prep_slave_sg(host->dma_rx,
229345980a3SAlexander Kochetkov tfr->rx_sg.sgl,
230345980a3SAlexander Kochetkov tfr->rx_sg.nents,
231345980a3SAlexander Kochetkov DMA_DEV_TO_MEM,
232345980a3SAlexander Kochetkov DMA_PREP_INTERRUPT);
233345980a3SAlexander Kochetkov if (!rxdesc)
234345980a3SAlexander Kochetkov return -EINVAL;
2351f11f420STobias Schramm rxdesc->callback_param = sspi;
2361f11f420STobias Schramm rxdesc->callback = sun6i_spi_dma_rx_cb;
237345980a3SAlexander Kochetkov }
238345980a3SAlexander Kochetkov
239345980a3SAlexander Kochetkov txdesc = NULL;
240345980a3SAlexander Kochetkov if (tfr->tx_buf) {
241345980a3SAlexander Kochetkov struct dma_slave_config txconf = {
242345980a3SAlexander Kochetkov .direction = DMA_MEM_TO_DEV,
243345980a3SAlexander Kochetkov .dst_addr = sspi->dma_addr_tx,
244345980a3SAlexander Kochetkov .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
245345980a3SAlexander Kochetkov .dst_maxburst = 8,
246345980a3SAlexander Kochetkov };
247345980a3SAlexander Kochetkov
2489f55bb79SYang Yingliang dmaengine_slave_config(host->dma_tx, &txconf);
249345980a3SAlexander Kochetkov
2509f55bb79SYang Yingliang txdesc = dmaengine_prep_slave_sg(host->dma_tx,
251345980a3SAlexander Kochetkov tfr->tx_sg.sgl,
252345980a3SAlexander Kochetkov tfr->tx_sg.nents,
253345980a3SAlexander Kochetkov DMA_MEM_TO_DEV,
254345980a3SAlexander Kochetkov DMA_PREP_INTERRUPT);
255345980a3SAlexander Kochetkov if (!txdesc) {
256345980a3SAlexander Kochetkov if (rxdesc)
2579f55bb79SYang Yingliang dmaengine_terminate_sync(host->dma_rx);
258345980a3SAlexander Kochetkov return -EINVAL;
259345980a3SAlexander Kochetkov }
260345980a3SAlexander Kochetkov }
261345980a3SAlexander Kochetkov
262345980a3SAlexander Kochetkov if (tfr->rx_buf) {
263345980a3SAlexander Kochetkov dmaengine_submit(rxdesc);
2649f55bb79SYang Yingliang dma_async_issue_pending(host->dma_rx);
265345980a3SAlexander Kochetkov }
266345980a3SAlexander Kochetkov
267345980a3SAlexander Kochetkov if (tfr->tx_buf) {
268345980a3SAlexander Kochetkov dmaengine_submit(txdesc);
2699f55bb79SYang Yingliang dma_async_issue_pending(host->dma_tx);
270345980a3SAlexander Kochetkov }
271345980a3SAlexander Kochetkov
272345980a3SAlexander Kochetkov return 0;
273345980a3SAlexander Kochetkov }
274345980a3SAlexander Kochetkov
sun6i_spi_transfer_one(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * tfr)2759f55bb79SYang Yingliang static int sun6i_spi_transfer_one(struct spi_controller *host,
2763558fe90SMaxime Ripard struct spi_device *spi,
2773558fe90SMaxime Ripard struct spi_transfer *tfr)
2783558fe90SMaxime Ripard {
2799f55bb79SYang Yingliang struct sun6i_spi *sspi = spi_controller_get_devdata(host);
280*83a3f1baSWolfram Sang unsigned int div, div_cdr1, div_cdr2;
281*83a3f1baSWolfram Sang unsigned long time_left;
282719bd654SMichal Suchanek unsigned int start, end, tx_time;
283913f536cSIcenowy Zheng unsigned int trig_level;
2840605d9fbSMaksim Kiselev unsigned int tx_len = 0, rx_len = 0, nbits = 0;
285345980a3SAlexander Kochetkov bool use_dma;
2863558fe90SMaxime Ripard int ret = 0;
2873558fe90SMaxime Ripard u32 reg;
2883558fe90SMaxime Ripard
289913f536cSIcenowy Zheng if (tfr->len > SUN6I_MAX_XFER_SIZE)
2903558fe90SMaxime Ripard return -EINVAL;
2913558fe90SMaxime Ripard
2923558fe90SMaxime Ripard reinit_completion(&sspi->done);
2931f11f420STobias Schramm reinit_completion(&sspi->dma_rx_done);
2943558fe90SMaxime Ripard sspi->tx_buf = tfr->tx_buf;
2953558fe90SMaxime Ripard sspi->rx_buf = tfr->rx_buf;
2963558fe90SMaxime Ripard sspi->len = tfr->len;
2979f55bb79SYang Yingliang use_dma = host->can_dma ? host->can_dma(host, spi, tfr) : false;
2983558fe90SMaxime Ripard
2993558fe90SMaxime Ripard /* Clear pending interrupts */
3003558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
3013558fe90SMaxime Ripard
3023558fe90SMaxime Ripard /* Reset FIFO */
3033558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
3043558fe90SMaxime Ripard SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
3053558fe90SMaxime Ripard
306345980a3SAlexander Kochetkov reg = 0;
307345980a3SAlexander Kochetkov
308345980a3SAlexander Kochetkov if (!use_dma) {
3093558fe90SMaxime Ripard /*
310913f536cSIcenowy Zheng * Setup FIFO interrupt trigger level
311345980a3SAlexander Kochetkov * Here we choose 3/4 of the full fifo depth, as it's
312345980a3SAlexander Kochetkov * the hardcoded value used in old generation of Allwinner
313345980a3SAlexander Kochetkov * SPI controller. (See spi-sun4i.c)
314913f536cSIcenowy Zheng */
315b00c0d89SIcenowy Zheng trig_level = sspi->cfg->fifo_depth / 4 * 3;
316345980a3SAlexander Kochetkov } else {
317345980a3SAlexander Kochetkov /*
318345980a3SAlexander Kochetkov * Setup FIFO DMA request trigger level
319345980a3SAlexander Kochetkov * We choose 1/2 of the full fifo depth, that value will
320345980a3SAlexander Kochetkov * be used as DMA burst length.
321345980a3SAlexander Kochetkov */
322b00c0d89SIcenowy Zheng trig_level = sspi->cfg->fifo_depth / 2;
323345980a3SAlexander Kochetkov
324345980a3SAlexander Kochetkov if (tfr->tx_buf)
325345980a3SAlexander Kochetkov reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
326345980a3SAlexander Kochetkov if (tfr->rx_buf)
327345980a3SAlexander Kochetkov reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
328345980a3SAlexander Kochetkov }
329345980a3SAlexander Kochetkov
330345980a3SAlexander Kochetkov reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
331345980a3SAlexander Kochetkov (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
332345980a3SAlexander Kochetkov
333345980a3SAlexander Kochetkov sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
334913f536cSIcenowy Zheng
335913f536cSIcenowy Zheng /*
3363558fe90SMaxime Ripard * Setup the transfer control register: Chip Select,
3373558fe90SMaxime Ripard * polarities, etc.
3383558fe90SMaxime Ripard */
3393558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
3403558fe90SMaxime Ripard
3413558fe90SMaxime Ripard if (spi->mode & SPI_CPOL)
3423558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPOL;
3433558fe90SMaxime Ripard else
3443558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPOL;
3453558fe90SMaxime Ripard
3463558fe90SMaxime Ripard if (spi->mode & SPI_CPHA)
3473558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CPHA;
3483558fe90SMaxime Ripard else
3493558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_CPHA;
3503558fe90SMaxime Ripard
3513558fe90SMaxime Ripard if (spi->mode & SPI_LSB_FIRST)
3523558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_FBS;
3533558fe90SMaxime Ripard else
3543558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_FBS;
3553558fe90SMaxime Ripard
3563558fe90SMaxime Ripard /*
3573558fe90SMaxime Ripard * If it's a TX only transfer, we don't want to fill the RX
3583558fe90SMaxime Ripard * FIFO with bogus data
3593558fe90SMaxime Ripard */
3607716fa80SMarc Kleine-Budde if (sspi->rx_buf) {
3613558fe90SMaxime Ripard reg &= ~SUN6I_TFR_CTL_DHB;
3627716fa80SMarc Kleine-Budde rx_len = tfr->len;
3637716fa80SMarc Kleine-Budde } else {
3643558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_DHB;
3657716fa80SMarc Kleine-Budde }
3663558fe90SMaxime Ripard
3673558fe90SMaxime Ripard /* We want to control the chip select manually */
3683558fe90SMaxime Ripard reg |= SUN6I_TFR_CTL_CS_MANUAL;
3693558fe90SMaxime Ripard
3703558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
3713558fe90SMaxime Ripard
3728e886ac8SMaksim Kiselev if (sspi->cfg->has_clk_ctl) {
3738e886ac8SMaksim Kiselev unsigned int mclk_rate = clk_get_rate(sspi->mclk);
3748e886ac8SMaksim Kiselev
3753558fe90SMaxime Ripard /* Ensure that we have a parent clock fast enough */
37647284e3eSMarcus Weseloh if (mclk_rate < (2 * tfr->speed_hz)) {
37747284e3eSMarcus Weseloh clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
3783558fe90SMaxime Ripard mclk_rate = clk_get_rate(sspi->mclk);
3793558fe90SMaxime Ripard }
3803558fe90SMaxime Ripard
3813558fe90SMaxime Ripard /*
3823558fe90SMaxime Ripard * Setup clock divider.
3833558fe90SMaxime Ripard *
3843558fe90SMaxime Ripard * We have two choices there. Either we can use the clock
3853558fe90SMaxime Ripard * divide rate 1, which is calculated thanks to this formula:
3863558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 ^ cdr)
3873558fe90SMaxime Ripard * Or we can use CDR2, which is calculated with the formula:
3883558fe90SMaxime Ripard * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
3893558fe90SMaxime Ripard * Wether we use the former or the latter is set through the
3903558fe90SMaxime Ripard * DRS bit.
3913558fe90SMaxime Ripard *
3923558fe90SMaxime Ripard * First try CDR2, and if we can't reach the expected
3933558fe90SMaxime Ripard * frequency, fall back to CDR1.
3943558fe90SMaxime Ripard */
395ed7815dbSMarc Kleine-Budde div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
396ed7815dbSMarc Kleine-Budde div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
397ed7815dbSMarc Kleine-Budde if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
398ed7815dbSMarc Kleine-Budde reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
3990bc7b8a2SMarc Kleine-Budde tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
4003558fe90SMaxime Ripard } else {
401ed7815dbSMarc Kleine-Budde div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
4023558fe90SMaxime Ripard reg = SUN6I_CLK_CTL_CDR1(div);
4030bc7b8a2SMarc Kleine-Budde tfr->effective_speed_hz = mclk_rate / (1 << div);
4043558fe90SMaxime Ripard }
4053558fe90SMaxime Ripard
4063558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
4078e886ac8SMaksim Kiselev } else {
4088e886ac8SMaksim Kiselev clk_set_rate(sspi->mclk, tfr->speed_hz);
4098e886ac8SMaksim Kiselev tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
4108e886ac8SMaksim Kiselev
4118e886ac8SMaksim Kiselev /*
4128e886ac8SMaksim Kiselev * Configure work mode.
4138e886ac8SMaksim Kiselev *
4148e886ac8SMaksim Kiselev * There are three work modes depending on the controller clock
4158e886ac8SMaksim Kiselev * frequency:
4168e886ac8SMaksim Kiselev * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0
4178e886ac8SMaksim Kiselev * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0
4188e886ac8SMaksim Kiselev * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1
4198e886ac8SMaksim Kiselev */
4208e886ac8SMaksim Kiselev reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
4218e886ac8SMaksim Kiselev reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC);
4228e886ac8SMaksim Kiselev
4238e886ac8SMaksim Kiselev if (tfr->effective_speed_hz <= 24000000)
4248e886ac8SMaksim Kiselev reg |= SUN6I_TFR_CTL_SDM;
4258e886ac8SMaksim Kiselev else if (tfr->effective_speed_hz >= 80000000)
4268e886ac8SMaksim Kiselev reg |= SUN6I_TFR_CTL_SDC;
4278e886ac8SMaksim Kiselev
4288e886ac8SMaksim Kiselev sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
4298e886ac8SMaksim Kiselev }
4308e886ac8SMaksim Kiselev
4310d7993b2SMirko Vogt /* Finally enable the bus - doing so before might raise SCK to HIGH */
4320d7993b2SMirko Vogt reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
4330d7993b2SMirko Vogt reg |= SUN6I_GBL_CTL_BUS_ENABLE;
4340d7993b2SMirko Vogt sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
4353558fe90SMaxime Ripard
4363558fe90SMaxime Ripard /* Setup the transfer now... */
4370605d9fbSMaksim Kiselev if (sspi->tx_buf) {
4383558fe90SMaxime Ripard tx_len = tfr->len;
4390605d9fbSMaksim Kiselev nbits = tfr->tx_nbits;
4400605d9fbSMaksim Kiselev } else if (tfr->rx_buf) {
4410605d9fbSMaksim Kiselev nbits = tfr->rx_nbits;
4420605d9fbSMaksim Kiselev }
4430605d9fbSMaksim Kiselev
4440605d9fbSMaksim Kiselev switch (nbits) {
4450605d9fbSMaksim Kiselev case SPI_NBITS_DUAL:
4460605d9fbSMaksim Kiselev reg = SUN6I_BURST_CTL_CNT_DRM;
4470605d9fbSMaksim Kiselev break;
4480605d9fbSMaksim Kiselev case SPI_NBITS_QUAD:
4490605d9fbSMaksim Kiselev reg = SUN6I_BURST_CTL_CNT_QUAD_EN;
4500605d9fbSMaksim Kiselev break;
4510605d9fbSMaksim Kiselev case SPI_NBITS_SINGLE:
4520605d9fbSMaksim Kiselev default:
4530605d9fbSMaksim Kiselev reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len);
4540605d9fbSMaksim Kiselev }
4553558fe90SMaxime Ripard
4563558fe90SMaxime Ripard /* Setup the counters */
4570605d9fbSMaksim Kiselev sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
4582130be57SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
4592130be57SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
4603558fe90SMaxime Ripard
461345980a3SAlexander Kochetkov if (!use_dma) {
4623558fe90SMaxime Ripard /* Fill the TX FIFO */
463e4e8ca3fSMarc Kleine-Budde sun6i_spi_fill_fifo(sspi);
464345980a3SAlexander Kochetkov } else {
465345980a3SAlexander Kochetkov ret = sun6i_spi_prepare_dma(sspi, tfr);
466345980a3SAlexander Kochetkov if (ret) {
4679f55bb79SYang Yingliang dev_warn(&host->dev,
468345980a3SAlexander Kochetkov "%s: prepare DMA failed, ret=%d",
469345980a3SAlexander Kochetkov dev_name(&spi->dev), ret);
470345980a3SAlexander Kochetkov return ret;
471345980a3SAlexander Kochetkov }
472345980a3SAlexander Kochetkov }
4733558fe90SMaxime Ripard
4743558fe90SMaxime Ripard /* Enable the interrupts */
4757716fa80SMarc Kleine-Budde reg = SUN6I_INT_CTL_TC;
4764e7390e9SMarc Kleine-Budde
477345980a3SAlexander Kochetkov if (!use_dma) {
478b00c0d89SIcenowy Zheng if (rx_len > sspi->cfg->fifo_depth)
4797716fa80SMarc Kleine-Budde reg |= SUN6I_INT_CTL_RF_RDY;
480b00c0d89SIcenowy Zheng if (tx_len > sspi->cfg->fifo_depth)
4814e7390e9SMarc Kleine-Budde reg |= SUN6I_INT_CTL_TF_ERQ;
482345980a3SAlexander Kochetkov }
4834e7390e9SMarc Kleine-Budde
4844e7390e9SMarc Kleine-Budde sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
4853558fe90SMaxime Ripard
4863558fe90SMaxime Ripard /* Start the transfer */
4873558fe90SMaxime Ripard reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
4883558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
4893558fe90SMaxime Ripard
4909f55bb79SYang Yingliang tx_time = spi_controller_xfer_timeout(host, tfr);
491719bd654SMichal Suchanek start = jiffies;
492*83a3f1baSWolfram Sang time_left = wait_for_completion_timeout(&sspi->done,
493719bd654SMichal Suchanek msecs_to_jiffies(tx_time));
4941f11f420STobias Schramm
4951f11f420STobias Schramm if (!use_dma) {
4961f11f420STobias Schramm sun6i_spi_drain_fifo(sspi);
4971f11f420STobias Schramm } else {
498*83a3f1baSWolfram Sang if (time_left && rx_len) {
4991f11f420STobias Schramm /*
5001f11f420STobias Schramm * Even though RX on the peripheral side has finished
5011f11f420STobias Schramm * RX DMA might still be in flight
5021f11f420STobias Schramm */
503*83a3f1baSWolfram Sang time_left = wait_for_completion_timeout(&sspi->dma_rx_done,
504*83a3f1baSWolfram Sang time_left);
505*83a3f1baSWolfram Sang if (!time_left)
5069f55bb79SYang Yingliang dev_warn(&host->dev, "RX DMA timeout\n");
5071f11f420STobias Schramm }
5081f11f420STobias Schramm }
5091f11f420STobias Schramm
510719bd654SMichal Suchanek end = jiffies;
511*83a3f1baSWolfram Sang if (!time_left) {
5129f55bb79SYang Yingliang dev_warn(&host->dev,
513719bd654SMichal Suchanek "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
514719bd654SMichal Suchanek dev_name(&spi->dev), tfr->len, tfr->speed_hz,
515719bd654SMichal Suchanek jiffies_to_msecs(end - start), tx_time);
5163558fe90SMaxime Ripard ret = -ETIMEDOUT;
5173558fe90SMaxime Ripard }
5183558fe90SMaxime Ripard
5193558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
5203558fe90SMaxime Ripard
521345980a3SAlexander Kochetkov if (ret && use_dma) {
5229f55bb79SYang Yingliang dmaengine_terminate_sync(host->dma_rx);
5239f55bb79SYang Yingliang dmaengine_terminate_sync(host->dma_tx);
524345980a3SAlexander Kochetkov }
525345980a3SAlexander Kochetkov
5263558fe90SMaxime Ripard return ret;
5273558fe90SMaxime Ripard }
5283558fe90SMaxime Ripard
sun6i_spi_handler(int irq,void * dev_id)5293558fe90SMaxime Ripard static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
5303558fe90SMaxime Ripard {
5313558fe90SMaxime Ripard struct sun6i_spi *sspi = dev_id;
5323558fe90SMaxime Ripard u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
5333558fe90SMaxime Ripard
5343558fe90SMaxime Ripard /* Transfer complete */
5353558fe90SMaxime Ripard if (status & SUN6I_INT_CTL_TC) {
5363558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
5373558fe90SMaxime Ripard complete(&sspi->done);
5383558fe90SMaxime Ripard return IRQ_HANDLED;
5393558fe90SMaxime Ripard }
5403558fe90SMaxime Ripard
541913f536cSIcenowy Zheng /* Receive FIFO 3/4 full */
542913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_RF_RDY) {
54392a52ee8SMarc Kleine-Budde sun6i_spi_drain_fifo(sspi);
544913f536cSIcenowy Zheng /* Only clear the interrupt _after_ draining the FIFO */
545913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
546913f536cSIcenowy Zheng return IRQ_HANDLED;
547913f536cSIcenowy Zheng }
548913f536cSIcenowy Zheng
549913f536cSIcenowy Zheng /* Transmit FIFO 3/4 empty */
550913f536cSIcenowy Zheng if (status & SUN6I_INT_CTL_TF_ERQ) {
551e4e8ca3fSMarc Kleine-Budde sun6i_spi_fill_fifo(sspi);
552913f536cSIcenowy Zheng
553913f536cSIcenowy Zheng if (!sspi->len)
554913f536cSIcenowy Zheng /* nothing left to transmit */
555913f536cSIcenowy Zheng sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
556913f536cSIcenowy Zheng
557913f536cSIcenowy Zheng /* Only clear the interrupt _after_ re-seeding the FIFO */
558913f536cSIcenowy Zheng sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
559913f536cSIcenowy Zheng
560913f536cSIcenowy Zheng return IRQ_HANDLED;
561913f536cSIcenowy Zheng }
562913f536cSIcenowy Zheng
5633558fe90SMaxime Ripard return IRQ_NONE;
5643558fe90SMaxime Ripard }
5653558fe90SMaxime Ripard
sun6i_spi_runtime_resume(struct device * dev)5663558fe90SMaxime Ripard static int sun6i_spi_runtime_resume(struct device *dev)
5673558fe90SMaxime Ripard {
5689f55bb79SYang Yingliang struct spi_controller *host = dev_get_drvdata(dev);
5699f55bb79SYang Yingliang struct sun6i_spi *sspi = spi_controller_get_devdata(host);
5703558fe90SMaxime Ripard int ret;
5713558fe90SMaxime Ripard
5723558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->hclk);
5733558fe90SMaxime Ripard if (ret) {
5743558fe90SMaxime Ripard dev_err(dev, "Couldn't enable AHB clock\n");
5753558fe90SMaxime Ripard goto out;
5763558fe90SMaxime Ripard }
5773558fe90SMaxime Ripard
5783558fe90SMaxime Ripard ret = clk_prepare_enable(sspi->mclk);
5793558fe90SMaxime Ripard if (ret) {
5803558fe90SMaxime Ripard dev_err(dev, "Couldn't enable module clock\n");
5813558fe90SMaxime Ripard goto err;
5823558fe90SMaxime Ripard }
5833558fe90SMaxime Ripard
5843558fe90SMaxime Ripard ret = reset_control_deassert(sspi->rstc);
5853558fe90SMaxime Ripard if (ret) {
5863558fe90SMaxime Ripard dev_err(dev, "Couldn't deassert the device from reset\n");
5873558fe90SMaxime Ripard goto err2;
5883558fe90SMaxime Ripard }
5893558fe90SMaxime Ripard
5903558fe90SMaxime Ripard sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
5910d7993b2SMirko Vogt SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
5923558fe90SMaxime Ripard
5933558fe90SMaxime Ripard return 0;
5943558fe90SMaxime Ripard
5953558fe90SMaxime Ripard err2:
5963558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk);
5973558fe90SMaxime Ripard err:
5983558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk);
5993558fe90SMaxime Ripard out:
6003558fe90SMaxime Ripard return ret;
6013558fe90SMaxime Ripard }
6023558fe90SMaxime Ripard
sun6i_spi_runtime_suspend(struct device * dev)6033558fe90SMaxime Ripard static int sun6i_spi_runtime_suspend(struct device *dev)
6043558fe90SMaxime Ripard {
6059f55bb79SYang Yingliang struct spi_controller *host = dev_get_drvdata(dev);
6069f55bb79SYang Yingliang struct sun6i_spi *sspi = spi_controller_get_devdata(host);
6073558fe90SMaxime Ripard
6083558fe90SMaxime Ripard reset_control_assert(sspi->rstc);
6093558fe90SMaxime Ripard clk_disable_unprepare(sspi->mclk);
6103558fe90SMaxime Ripard clk_disable_unprepare(sspi->hclk);
6113558fe90SMaxime Ripard
6123558fe90SMaxime Ripard return 0;
6133558fe90SMaxime Ripard }
6143558fe90SMaxime Ripard
sun6i_spi_can_dma(struct spi_controller * host,struct spi_device * spi,struct spi_transfer * xfer)6159f55bb79SYang Yingliang static bool sun6i_spi_can_dma(struct spi_controller *host,
616345980a3SAlexander Kochetkov struct spi_device *spi,
617345980a3SAlexander Kochetkov struct spi_transfer *xfer)
618345980a3SAlexander Kochetkov {
6199f55bb79SYang Yingliang struct sun6i_spi *sspi = spi_controller_get_devdata(host);
620345980a3SAlexander Kochetkov
621345980a3SAlexander Kochetkov /*
622345980a3SAlexander Kochetkov * If the number of spi words to transfer is less or equal than
623345980a3SAlexander Kochetkov * the fifo length we can just fill the fifo and wait for a single
624345980a3SAlexander Kochetkov * irq, so don't bother setting up dma
625345980a3SAlexander Kochetkov */
626b00c0d89SIcenowy Zheng return xfer->len > sspi->cfg->fifo_depth;
627345980a3SAlexander Kochetkov }
628345980a3SAlexander Kochetkov
sun6i_spi_probe(struct platform_device * pdev)6293558fe90SMaxime Ripard static int sun6i_spi_probe(struct platform_device *pdev)
6303558fe90SMaxime Ripard {
6319f55bb79SYang Yingliang struct spi_controller *host;
6323558fe90SMaxime Ripard struct sun6i_spi *sspi;
633345980a3SAlexander Kochetkov struct resource *mem;
6343558fe90SMaxime Ripard int ret = 0, irq;
6353558fe90SMaxime Ripard
6369f55bb79SYang Yingliang host = spi_alloc_host(&pdev->dev, sizeof(struct sun6i_spi));
6379f55bb79SYang Yingliang if (!host) {
6389f55bb79SYang Yingliang dev_err(&pdev->dev, "Unable to allocate SPI Host\n");
6393558fe90SMaxime Ripard return -ENOMEM;
6403558fe90SMaxime Ripard }
6413558fe90SMaxime Ripard
6429f55bb79SYang Yingliang platform_set_drvdata(pdev, host);
6439f55bb79SYang Yingliang sspi = spi_controller_get_devdata(host);
6443558fe90SMaxime Ripard
645345980a3SAlexander Kochetkov sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
6463558fe90SMaxime Ripard if (IS_ERR(sspi->base_addr)) {
6473558fe90SMaxime Ripard ret = PTR_ERR(sspi->base_addr);
6489f55bb79SYang Yingliang goto err_free_host;
6493558fe90SMaxime Ripard }
6503558fe90SMaxime Ripard
6513558fe90SMaxime Ripard irq = platform_get_irq(pdev, 0);
6523558fe90SMaxime Ripard if (irq < 0) {
6533558fe90SMaxime Ripard ret = -ENXIO;
6549f55bb79SYang Yingliang goto err_free_host;
6553558fe90SMaxime Ripard }
6563558fe90SMaxime Ripard
6573558fe90SMaxime Ripard ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
6583558fe90SMaxime Ripard 0, "sun6i-spi", sspi);
6593558fe90SMaxime Ripard if (ret) {
6603558fe90SMaxime Ripard dev_err(&pdev->dev, "Cannot request IRQ\n");
6619f55bb79SYang Yingliang goto err_free_host;
6623558fe90SMaxime Ripard }
6633558fe90SMaxime Ripard
6649f55bb79SYang Yingliang sspi->host = host;
665b00c0d89SIcenowy Zheng sspi->cfg = of_device_get_match_data(&pdev->dev);
66610565dfdSMilo Kim
6679f55bb79SYang Yingliang host->max_speed_hz = 100 * 1000 * 1000;
6689f55bb79SYang Yingliang host->min_speed_hz = 3 * 1000;
6699f55bb79SYang Yingliang host->use_gpio_descriptors = true;
6709f55bb79SYang Yingliang host->set_cs = sun6i_spi_set_cs;
6719f55bb79SYang Yingliang host->transfer_one = sun6i_spi_transfer_one;
6729f55bb79SYang Yingliang host->num_chipselect = 4;
6739f55bb79SYang Yingliang host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
6740605d9fbSMaksim Kiselev sspi->cfg->mode_bits;
6759f55bb79SYang Yingliang host->bits_per_word_mask = SPI_BPW_MASK(8);
6769f55bb79SYang Yingliang host->dev.of_node = pdev->dev.of_node;
6779f55bb79SYang Yingliang host->auto_runtime_pm = true;
6789f55bb79SYang Yingliang host->max_transfer_size = sun6i_spi_max_transfer_size;
6793558fe90SMaxime Ripard
6803558fe90SMaxime Ripard sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
6813558fe90SMaxime Ripard if (IS_ERR(sspi->hclk)) {
6823558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
6833558fe90SMaxime Ripard ret = PTR_ERR(sspi->hclk);
6849f55bb79SYang Yingliang goto err_free_host;
6853558fe90SMaxime Ripard }
6863558fe90SMaxime Ripard
6873558fe90SMaxime Ripard sspi->mclk = devm_clk_get(&pdev->dev, "mod");
6883558fe90SMaxime Ripard if (IS_ERR(sspi->mclk)) {
6893558fe90SMaxime Ripard dev_err(&pdev->dev, "Unable to acquire module clock\n");
6903558fe90SMaxime Ripard ret = PTR_ERR(sspi->mclk);
6919f55bb79SYang Yingliang goto err_free_host;
6923558fe90SMaxime Ripard }
6933558fe90SMaxime Ripard
6943558fe90SMaxime Ripard init_completion(&sspi->done);
6951f11f420STobias Schramm init_completion(&sspi->dma_rx_done);
6963558fe90SMaxime Ripard
69736bc7491SPhilipp Zabel sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
6983558fe90SMaxime Ripard if (IS_ERR(sspi->rstc)) {
6993558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't get reset controller\n");
7003558fe90SMaxime Ripard ret = PTR_ERR(sspi->rstc);
7019f55bb79SYang Yingliang goto err_free_host;
7023558fe90SMaxime Ripard }
7033558fe90SMaxime Ripard
7049f55bb79SYang Yingliang host->dma_tx = dma_request_chan(&pdev->dev, "tx");
7059f55bb79SYang Yingliang if (IS_ERR(host->dma_tx)) {
706345980a3SAlexander Kochetkov /* Check tx to see if we need defer probing driver */
7079f55bb79SYang Yingliang if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER) {
708345980a3SAlexander Kochetkov ret = -EPROBE_DEFER;
7099f55bb79SYang Yingliang goto err_free_host;
710345980a3SAlexander Kochetkov }
711345980a3SAlexander Kochetkov dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
7129f55bb79SYang Yingliang host->dma_tx = NULL;
713345980a3SAlexander Kochetkov }
714345980a3SAlexander Kochetkov
7159f55bb79SYang Yingliang host->dma_rx = dma_request_chan(&pdev->dev, "rx");
7169f55bb79SYang Yingliang if (IS_ERR(host->dma_rx)) {
7179f55bb79SYang Yingliang if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER) {
718345980a3SAlexander Kochetkov ret = -EPROBE_DEFER;
719345980a3SAlexander Kochetkov goto err_free_dma_tx;
720345980a3SAlexander Kochetkov }
721345980a3SAlexander Kochetkov dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
7229f55bb79SYang Yingliang host->dma_rx = NULL;
723345980a3SAlexander Kochetkov }
724345980a3SAlexander Kochetkov
7259f55bb79SYang Yingliang if (host->dma_tx && host->dma_rx) {
726345980a3SAlexander Kochetkov sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
727345980a3SAlexander Kochetkov sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
7289f55bb79SYang Yingliang host->can_dma = sun6i_spi_can_dma;
729345980a3SAlexander Kochetkov }
730345980a3SAlexander Kochetkov
7313558fe90SMaxime Ripard /*
7323558fe90SMaxime Ripard * This wake-up/shutdown pattern is to be able to have the
7333558fe90SMaxime Ripard * device woken up, even if runtime_pm is disabled
7343558fe90SMaxime Ripard */
7353558fe90SMaxime Ripard ret = sun6i_spi_runtime_resume(&pdev->dev);
7363558fe90SMaxime Ripard if (ret) {
7373558fe90SMaxime Ripard dev_err(&pdev->dev, "Couldn't resume the device\n");
738345980a3SAlexander Kochetkov goto err_free_dma_rx;
7393558fe90SMaxime Ripard }
7403558fe90SMaxime Ripard
741ae0f18beSAlexander Kochetkov pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
742ae0f18beSAlexander Kochetkov pm_runtime_use_autosuspend(&pdev->dev);
7433558fe90SMaxime Ripard pm_runtime_set_active(&pdev->dev);
7443558fe90SMaxime Ripard pm_runtime_enable(&pdev->dev);
7453558fe90SMaxime Ripard
7469f55bb79SYang Yingliang ret = devm_spi_register_controller(&pdev->dev, host);
7473558fe90SMaxime Ripard if (ret) {
7489f55bb79SYang Yingliang dev_err(&pdev->dev, "cannot register SPI host\n");
7493558fe90SMaxime Ripard goto err_pm_disable;
7503558fe90SMaxime Ripard }
7513558fe90SMaxime Ripard
7523558fe90SMaxime Ripard return 0;
7533558fe90SMaxime Ripard
7543558fe90SMaxime Ripard err_pm_disable:
7553558fe90SMaxime Ripard pm_runtime_disable(&pdev->dev);
7563558fe90SMaxime Ripard sun6i_spi_runtime_suspend(&pdev->dev);
757345980a3SAlexander Kochetkov err_free_dma_rx:
7589f55bb79SYang Yingliang if (host->dma_rx)
7599f55bb79SYang Yingliang dma_release_channel(host->dma_rx);
760345980a3SAlexander Kochetkov err_free_dma_tx:
7619f55bb79SYang Yingliang if (host->dma_tx)
7629f55bb79SYang Yingliang dma_release_channel(host->dma_tx);
7639f55bb79SYang Yingliang err_free_host:
7649f55bb79SYang Yingliang spi_controller_put(host);
7653558fe90SMaxime Ripard return ret;
7663558fe90SMaxime Ripard }
7673558fe90SMaxime Ripard
sun6i_spi_remove(struct platform_device * pdev)768edf69ab9SUwe Kleine-König static void sun6i_spi_remove(struct platform_device *pdev)
7693558fe90SMaxime Ripard {
7709f55bb79SYang Yingliang struct spi_controller *host = platform_get_drvdata(pdev);
771345980a3SAlexander Kochetkov
7722d9bbd02STobias Jordan pm_runtime_force_suspend(&pdev->dev);
7733558fe90SMaxime Ripard
7749f55bb79SYang Yingliang if (host->dma_tx)
7759f55bb79SYang Yingliang dma_release_channel(host->dma_tx);
7769f55bb79SYang Yingliang if (host->dma_rx)
7779f55bb79SYang Yingliang dma_release_channel(host->dma_rx);
7783558fe90SMaxime Ripard }
7793558fe90SMaxime Ripard
780b00c0d89SIcenowy Zheng static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = {
781b00c0d89SIcenowy Zheng .fifo_depth = SUN6I_FIFO_DEPTH,
7828e886ac8SMaksim Kiselev .has_clk_ctl = true,
783b00c0d89SIcenowy Zheng };
784b00c0d89SIcenowy Zheng
785b00c0d89SIcenowy Zheng static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = {
786b00c0d89SIcenowy Zheng .fifo_depth = SUN8I_FIFO_DEPTH,
7878e886ac8SMaksim Kiselev .has_clk_ctl = true,
788b00c0d89SIcenowy Zheng };
789b00c0d89SIcenowy Zheng
790046484cbSMaksim Kiselev static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
791046484cbSMaksim Kiselev .fifo_depth = SUN8I_FIFO_DEPTH,
79225453d79SMaksim Kiselev .mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD,
793046484cbSMaksim Kiselev };
794046484cbSMaksim Kiselev
7953558fe90SMaxime Ripard static const struct of_device_id sun6i_spi_match[] = {
796b00c0d89SIcenowy Zheng { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
797b00c0d89SIcenowy Zheng { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
798046484cbSMaksim Kiselev {
799046484cbSMaksim Kiselev .compatible = "allwinner,sun50i-r329-spi",
800046484cbSMaksim Kiselev .data = &sun50i_r329_spi_cfg
801046484cbSMaksim Kiselev },
8023558fe90SMaxime Ripard {}
8033558fe90SMaxime Ripard };
8043558fe90SMaxime Ripard MODULE_DEVICE_TABLE(of, sun6i_spi_match);
8053558fe90SMaxime Ripard
8063558fe90SMaxime Ripard static const struct dev_pm_ops sun6i_spi_pm_ops = {
8073558fe90SMaxime Ripard .runtime_resume = sun6i_spi_runtime_resume,
8083558fe90SMaxime Ripard .runtime_suspend = sun6i_spi_runtime_suspend,
8093558fe90SMaxime Ripard };
8103558fe90SMaxime Ripard
8113558fe90SMaxime Ripard static struct platform_driver sun6i_spi_driver = {
8123558fe90SMaxime Ripard .probe = sun6i_spi_probe,
813edf69ab9SUwe Kleine-König .remove_new = sun6i_spi_remove,
8143558fe90SMaxime Ripard .driver = {
8153558fe90SMaxime Ripard .name = "sun6i-spi",
8163558fe90SMaxime Ripard .of_match_table = sun6i_spi_match,
8173558fe90SMaxime Ripard .pm = &sun6i_spi_pm_ops,
8183558fe90SMaxime Ripard },
8193558fe90SMaxime Ripard };
8203558fe90SMaxime Ripard module_platform_driver(sun6i_spi_driver);
8213558fe90SMaxime Ripard
8223558fe90SMaxime Ripard MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
8233558fe90SMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
8243558fe90SMaxime Ripard MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
8253558fe90SMaxime Ripard MODULE_LICENSE("GPL");
826