1 /* 2 * drivers/soc/tegra/pmc.c 3 * 4 * Copyright (c) 2010 Google, Inc 5 * 6 * Author: 7 * Colin Cross <ccross@google.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #define pr_fmt(fmt) "tegra-pmc: " fmt 21 22 #include <linux/kernel.h> 23 #include <linux/clk.h> 24 #include <linux/clk/tegra.h> 25 #include <linux/debugfs.h> 26 #include <linux/delay.h> 27 #include <linux/err.h> 28 #include <linux/export.h> 29 #include <linux/init.h> 30 #include <linux/io.h> 31 #include <linux/iopoll.h> 32 #include <linux/of.h> 33 #include <linux/of_address.h> 34 #include <linux/of_platform.h> 35 #include <linux/platform_device.h> 36 #include <linux/pm_domain.h> 37 #include <linux/reboot.h> 38 #include <linux/reset.h> 39 #include <linux/seq_file.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 43 #include <soc/tegra/common.h> 44 #include <soc/tegra/fuse.h> 45 #include <soc/tegra/pmc.h> 46 47 #define PMC_CNTRL 0x0 48 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */ 49 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ 50 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ 51 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ 52 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ 53 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ 54 #define PMC_CNTRL_MAIN_RST BIT(4) 55 56 #define DPD_SAMPLE 0x020 57 #define DPD_SAMPLE_ENABLE BIT(0) 58 #define DPD_SAMPLE_DISABLE (0 << 0) 59 60 #define PWRGATE_TOGGLE 0x30 61 #define PWRGATE_TOGGLE_START BIT(8) 62 63 #define REMOVE_CLAMPING 0x34 64 65 #define PWRGATE_STATUS 0x38 66 67 #define PMC_PWR_DET 0x48 68 69 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31) 70 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) 71 #define PMC_SCRATCH0_MODE_RCM BIT(1) 72 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ 73 PMC_SCRATCH0_MODE_BOOTLOADER | \ 74 PMC_SCRATCH0_MODE_RCM) 75 76 #define PMC_CPUPWRGOOD_TIMER 0xc8 77 #define PMC_CPUPWROFF_TIMER 0xcc 78 79 #define PMC_PWR_DET_VALUE 0xe4 80 81 #define PMC_SCRATCH41 0x140 82 83 #define PMC_SENSOR_CTRL 0x1b0 84 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) 85 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) 86 87 #define PMC_RST_STATUS 0x1b4 88 #define PMC_RST_STATUS_POR 0 89 #define PMC_RST_STATUS_WATCHDOG 1 90 #define PMC_RST_STATUS_SENSOR 2 91 #define PMC_RST_STATUS_SW_MAIN 3 92 #define PMC_RST_STATUS_LP0 4 93 #define PMC_RST_STATUS_AOTAG 5 94 95 #define IO_DPD_REQ 0x1b8 96 #define IO_DPD_REQ_CODE_IDLE (0U << 30) 97 #define IO_DPD_REQ_CODE_OFF (1U << 30) 98 #define IO_DPD_REQ_CODE_ON (2U << 30) 99 #define IO_DPD_REQ_CODE_MASK (3U << 30) 100 101 #define IO_DPD_STATUS 0x1bc 102 #define IO_DPD2_REQ 0x1c0 103 #define IO_DPD2_STATUS 0x1c4 104 #define SEL_DPD_TIM 0x1c8 105 106 #define PMC_SCRATCH54 0x258 107 #define PMC_SCRATCH54_DATA_SHIFT 8 108 #define PMC_SCRATCH54_ADDR_SHIFT 0 109 110 #define PMC_SCRATCH55 0x25c 111 #define PMC_SCRATCH55_RESET_TEGRA BIT(31) 112 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 113 #define PMC_SCRATCH55_PINMUX_SHIFT 24 114 #define PMC_SCRATCH55_16BITOP BIT(15) 115 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 116 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 117 118 #define GPU_RG_CNTRL 0x2d4 119 120 /* Tegra186 and later */ 121 #define WAKE_AOWAKE_CTRL 0x4f4 122 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0) 123 124 struct tegra_powergate { 125 struct generic_pm_domain genpd; 126 struct tegra_pmc *pmc; 127 unsigned int id; 128 struct clk **clks; 129 unsigned int num_clks; 130 struct reset_control *reset; 131 }; 132 133 struct tegra_io_pad_soc { 134 enum tegra_io_pad id; 135 unsigned int dpd; 136 unsigned int voltage; 137 }; 138 139 struct tegra_pmc_regs { 140 unsigned int scratch0; 141 unsigned int dpd_req; 142 unsigned int dpd_status; 143 unsigned int dpd2_req; 144 unsigned int dpd2_status; 145 }; 146 147 struct tegra_pmc_soc { 148 unsigned int num_powergates; 149 const char *const *powergates; 150 unsigned int num_cpu_powergates; 151 const u8 *cpu_powergates; 152 153 bool has_tsense_reset; 154 bool has_gpu_clamps; 155 bool needs_mbist_war; 156 157 const struct tegra_io_pad_soc *io_pads; 158 unsigned int num_io_pads; 159 160 const struct tegra_pmc_regs *regs; 161 void (*init)(struct tegra_pmc *pmc); 162 void (*setup_irq_polarity)(struct tegra_pmc *pmc, 163 struct device_node *np, 164 bool invert); 165 }; 166 167 /** 168 * struct tegra_pmc - NVIDIA Tegra PMC 169 * @dev: pointer to PMC device structure 170 * @base: pointer to I/O remapped register region 171 * @clk: pointer to pclk clock 172 * @soc: pointer to SoC data structure 173 * @debugfs: pointer to debugfs entry 174 * @rate: currently configured rate of pclk 175 * @suspend_mode: lowest suspend mode available 176 * @cpu_good_time: CPU power good time (in microseconds) 177 * @cpu_off_time: CPU power off time (in microsecends) 178 * @core_osc_time: core power good OSC time (in microseconds) 179 * @core_pmu_time: core power good PMU time (in microseconds) 180 * @core_off_time: core power off time (in microseconds) 181 * @corereq_high: core power request is active-high 182 * @sysclkreq_high: system clock request is active-high 183 * @combined_req: combined power request for CPU & core 184 * @cpu_pwr_good_en: CPU power good signal is enabled 185 * @lp0_vec_phys: physical base address of the LP0 warm boot code 186 * @lp0_vec_size: size of the LP0 warm boot code 187 * @powergates_available: Bitmap of available power gates 188 * @powergates_lock: mutex for power gate register access 189 */ 190 struct tegra_pmc { 191 struct device *dev; 192 void __iomem *base; 193 void __iomem *wake; 194 void __iomem *aotag; 195 void __iomem *scratch; 196 struct clk *clk; 197 struct dentry *debugfs; 198 199 const struct tegra_pmc_soc *soc; 200 201 unsigned long rate; 202 203 enum tegra_suspend_mode suspend_mode; 204 u32 cpu_good_time; 205 u32 cpu_off_time; 206 u32 core_osc_time; 207 u32 core_pmu_time; 208 u32 core_off_time; 209 bool corereq_high; 210 bool sysclkreq_high; 211 bool combined_req; 212 bool cpu_pwr_good_en; 213 u32 lp0_vec_phys; 214 u32 lp0_vec_size; 215 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX); 216 217 struct mutex powergates_lock; 218 }; 219 220 static struct tegra_pmc *pmc = &(struct tegra_pmc) { 221 .base = NULL, 222 .suspend_mode = TEGRA_SUSPEND_NONE, 223 }; 224 225 static inline struct tegra_powergate * 226 to_powergate(struct generic_pm_domain *domain) 227 { 228 return container_of(domain, struct tegra_powergate, genpd); 229 } 230 231 static u32 tegra_pmc_readl(unsigned long offset) 232 { 233 return readl(pmc->base + offset); 234 } 235 236 static void tegra_pmc_writel(u32 value, unsigned long offset) 237 { 238 writel(value, pmc->base + offset); 239 } 240 241 static inline bool tegra_powergate_state(int id) 242 { 243 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 244 return (tegra_pmc_readl(GPU_RG_CNTRL) & 0x1) == 0; 245 else 246 return (tegra_pmc_readl(PWRGATE_STATUS) & BIT(id)) != 0; 247 } 248 249 static inline bool tegra_powergate_is_valid(int id) 250 { 251 return (pmc->soc && pmc->soc->powergates[id]); 252 } 253 254 static inline bool tegra_powergate_is_available(int id) 255 { 256 return test_bit(id, pmc->powergates_available); 257 } 258 259 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) 260 { 261 unsigned int i; 262 263 if (!pmc || !pmc->soc || !name) 264 return -EINVAL; 265 266 for (i = 0; i < pmc->soc->num_powergates; i++) { 267 if (!tegra_powergate_is_valid(i)) 268 continue; 269 270 if (!strcmp(name, pmc->soc->powergates[i])) 271 return i; 272 } 273 274 return -ENODEV; 275 } 276 277 /** 278 * tegra_powergate_set() - set the state of a partition 279 * @id: partition ID 280 * @new_state: new state of the partition 281 */ 282 static int tegra_powergate_set(unsigned int id, bool new_state) 283 { 284 bool status; 285 int err; 286 287 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) 288 return -EINVAL; 289 290 mutex_lock(&pmc->powergates_lock); 291 292 if (tegra_powergate_state(id) == new_state) { 293 mutex_unlock(&pmc->powergates_lock); 294 return 0; 295 } 296 297 tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); 298 299 err = readx_poll_timeout(tegra_powergate_state, id, status, 300 status == new_state, 10, 100000); 301 302 mutex_unlock(&pmc->powergates_lock); 303 304 return err; 305 } 306 307 static int __tegra_powergate_remove_clamping(unsigned int id) 308 { 309 u32 mask; 310 311 mutex_lock(&pmc->powergates_lock); 312 313 /* 314 * On Tegra124 and later, the clamps for the GPU are controlled by a 315 * separate register (with different semantics). 316 */ 317 if (id == TEGRA_POWERGATE_3D) { 318 if (pmc->soc->has_gpu_clamps) { 319 tegra_pmc_writel(0, GPU_RG_CNTRL); 320 goto out; 321 } 322 } 323 324 /* 325 * Tegra 2 has a bug where PCIE and VDE clamping masks are 326 * swapped relatively to the partition ids 327 */ 328 if (id == TEGRA_POWERGATE_VDEC) 329 mask = (1 << TEGRA_POWERGATE_PCIE); 330 else if (id == TEGRA_POWERGATE_PCIE) 331 mask = (1 << TEGRA_POWERGATE_VDEC); 332 else 333 mask = (1 << id); 334 335 tegra_pmc_writel(mask, REMOVE_CLAMPING); 336 337 out: 338 mutex_unlock(&pmc->powergates_lock); 339 340 return 0; 341 } 342 343 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg) 344 { 345 unsigned int i; 346 347 for (i = 0; i < pg->num_clks; i++) 348 clk_disable_unprepare(pg->clks[i]); 349 } 350 351 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 352 { 353 unsigned int i; 354 int err; 355 356 for (i = 0; i < pg->num_clks; i++) { 357 err = clk_prepare_enable(pg->clks[i]); 358 if (err) 359 goto out; 360 } 361 362 return 0; 363 364 out: 365 while (i--) 366 clk_disable_unprepare(pg->clks[i]); 367 368 return err; 369 } 370 371 int __weak tegra210_clk_handle_mbist_war(unsigned int id) 372 { 373 return 0; 374 } 375 376 static int tegra_powergate_power_up(struct tegra_powergate *pg, 377 bool disable_clocks) 378 { 379 int err; 380 381 err = reset_control_assert(pg->reset); 382 if (err) 383 return err; 384 385 usleep_range(10, 20); 386 387 err = tegra_powergate_set(pg->id, true); 388 if (err < 0) 389 return err; 390 391 usleep_range(10, 20); 392 393 err = tegra_powergate_enable_clocks(pg); 394 if (err) 395 goto disable_clks; 396 397 usleep_range(10, 20); 398 399 err = __tegra_powergate_remove_clamping(pg->id); 400 if (err) 401 goto disable_clks; 402 403 usleep_range(10, 20); 404 405 err = reset_control_deassert(pg->reset); 406 if (err) 407 goto powergate_off; 408 409 usleep_range(10, 20); 410 411 if (pg->pmc->soc->needs_mbist_war) 412 err = tegra210_clk_handle_mbist_war(pg->id); 413 if (err) 414 goto disable_clks; 415 416 if (disable_clocks) 417 tegra_powergate_disable_clocks(pg); 418 419 return 0; 420 421 disable_clks: 422 tegra_powergate_disable_clocks(pg); 423 usleep_range(10, 20); 424 425 powergate_off: 426 tegra_powergate_set(pg->id, false); 427 428 return err; 429 } 430 431 static int tegra_powergate_power_down(struct tegra_powergate *pg) 432 { 433 int err; 434 435 err = tegra_powergate_enable_clocks(pg); 436 if (err) 437 return err; 438 439 usleep_range(10, 20); 440 441 err = reset_control_assert(pg->reset); 442 if (err) 443 goto disable_clks; 444 445 usleep_range(10, 20); 446 447 tegra_powergate_disable_clocks(pg); 448 449 usleep_range(10, 20); 450 451 err = tegra_powergate_set(pg->id, false); 452 if (err) 453 goto assert_resets; 454 455 return 0; 456 457 assert_resets: 458 tegra_powergate_enable_clocks(pg); 459 usleep_range(10, 20); 460 reset_control_deassert(pg->reset); 461 usleep_range(10, 20); 462 463 disable_clks: 464 tegra_powergate_disable_clocks(pg); 465 466 return err; 467 } 468 469 static int tegra_genpd_power_on(struct generic_pm_domain *domain) 470 { 471 struct tegra_powergate *pg = to_powergate(domain); 472 int err; 473 474 err = tegra_powergate_power_up(pg, true); 475 if (err) 476 pr_err("failed to turn on PM domain %s: %d\n", pg->genpd.name, 477 err); 478 479 return err; 480 } 481 482 static int tegra_genpd_power_off(struct generic_pm_domain *domain) 483 { 484 struct tegra_powergate *pg = to_powergate(domain); 485 int err; 486 487 err = tegra_powergate_power_down(pg); 488 if (err) 489 pr_err("failed to turn off PM domain %s: %d\n", 490 pg->genpd.name, err); 491 492 return err; 493 } 494 495 /** 496 * tegra_powergate_power_on() - power on partition 497 * @id: partition ID 498 */ 499 int tegra_powergate_power_on(unsigned int id) 500 { 501 if (!tegra_powergate_is_available(id)) 502 return -EINVAL; 503 504 return tegra_powergate_set(id, true); 505 } 506 507 /** 508 * tegra_powergate_power_off() - power off partition 509 * @id: partition ID 510 */ 511 int tegra_powergate_power_off(unsigned int id) 512 { 513 if (!tegra_powergate_is_available(id)) 514 return -EINVAL; 515 516 return tegra_powergate_set(id, false); 517 } 518 EXPORT_SYMBOL(tegra_powergate_power_off); 519 520 /** 521 * tegra_powergate_is_powered() - check if partition is powered 522 * @id: partition ID 523 */ 524 int tegra_powergate_is_powered(unsigned int id) 525 { 526 int status; 527 528 if (!tegra_powergate_is_valid(id)) 529 return -EINVAL; 530 531 mutex_lock(&pmc->powergates_lock); 532 status = tegra_powergate_state(id); 533 mutex_unlock(&pmc->powergates_lock); 534 535 return status; 536 } 537 538 /** 539 * tegra_powergate_remove_clamping() - remove power clamps for partition 540 * @id: partition ID 541 */ 542 int tegra_powergate_remove_clamping(unsigned int id) 543 { 544 if (!tegra_powergate_is_available(id)) 545 return -EINVAL; 546 547 return __tegra_powergate_remove_clamping(id); 548 } 549 EXPORT_SYMBOL(tegra_powergate_remove_clamping); 550 551 /** 552 * tegra_powergate_sequence_power_up() - power up partition 553 * @id: partition ID 554 * @clk: clock for partition 555 * @rst: reset for partition 556 * 557 * Must be called with clk disabled, and returns with clk enabled. 558 */ 559 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk, 560 struct reset_control *rst) 561 { 562 struct tegra_powergate *pg; 563 int err; 564 565 if (!tegra_powergate_is_available(id)) 566 return -EINVAL; 567 568 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 569 if (!pg) 570 return -ENOMEM; 571 572 pg->id = id; 573 pg->clks = &clk; 574 pg->num_clks = 1; 575 pg->reset = rst; 576 pg->pmc = pmc; 577 578 err = tegra_powergate_power_up(pg, false); 579 if (err) 580 pr_err("failed to turn on partition %d: %d\n", id, err); 581 582 kfree(pg); 583 584 return err; 585 } 586 EXPORT_SYMBOL(tegra_powergate_sequence_power_up); 587 588 #ifdef CONFIG_SMP 589 /** 590 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID 591 * @cpuid: CPU partition ID 592 * 593 * Returns the partition ID corresponding to the CPU partition ID or a 594 * negative error code on failure. 595 */ 596 static int tegra_get_cpu_powergate_id(unsigned int cpuid) 597 { 598 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) 599 return pmc->soc->cpu_powergates[cpuid]; 600 601 return -EINVAL; 602 } 603 604 /** 605 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered 606 * @cpuid: CPU partition ID 607 */ 608 bool tegra_pmc_cpu_is_powered(unsigned int cpuid) 609 { 610 int id; 611 612 id = tegra_get_cpu_powergate_id(cpuid); 613 if (id < 0) 614 return false; 615 616 return tegra_powergate_is_powered(id); 617 } 618 619 /** 620 * tegra_pmc_cpu_power_on() - power on CPU partition 621 * @cpuid: CPU partition ID 622 */ 623 int tegra_pmc_cpu_power_on(unsigned int cpuid) 624 { 625 int id; 626 627 id = tegra_get_cpu_powergate_id(cpuid); 628 if (id < 0) 629 return id; 630 631 return tegra_powergate_set(id, true); 632 } 633 634 /** 635 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition 636 * @cpuid: CPU partition ID 637 */ 638 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid) 639 { 640 int id; 641 642 id = tegra_get_cpu_powergate_id(cpuid); 643 if (id < 0) 644 return id; 645 646 return tegra_powergate_remove_clamping(id); 647 } 648 #endif /* CONFIG_SMP */ 649 650 static int tegra_pmc_restart_notify(struct notifier_block *this, 651 unsigned long action, void *data) 652 { 653 const char *cmd = data; 654 u32 value; 655 656 value = readl(pmc->scratch + pmc->soc->regs->scratch0); 657 value &= ~PMC_SCRATCH0_MODE_MASK; 658 659 if (cmd) { 660 if (strcmp(cmd, "recovery") == 0) 661 value |= PMC_SCRATCH0_MODE_RECOVERY; 662 663 if (strcmp(cmd, "bootloader") == 0) 664 value |= PMC_SCRATCH0_MODE_BOOTLOADER; 665 666 if (strcmp(cmd, "forced-recovery") == 0) 667 value |= PMC_SCRATCH0_MODE_RCM; 668 } 669 670 writel(value, pmc->scratch + pmc->soc->regs->scratch0); 671 672 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */ 673 value = tegra_pmc_readl(PMC_CNTRL); 674 value |= PMC_CNTRL_MAIN_RST; 675 tegra_pmc_writel(value, PMC_CNTRL); 676 677 return NOTIFY_DONE; 678 } 679 680 static struct notifier_block tegra_pmc_restart_handler = { 681 .notifier_call = tegra_pmc_restart_notify, 682 .priority = 128, 683 }; 684 685 static int powergate_show(struct seq_file *s, void *data) 686 { 687 unsigned int i; 688 int status; 689 690 seq_printf(s, " powergate powered\n"); 691 seq_printf(s, "------------------\n"); 692 693 for (i = 0; i < pmc->soc->num_powergates; i++) { 694 status = tegra_powergate_is_powered(i); 695 if (status < 0) 696 continue; 697 698 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], 699 status ? "yes" : "no"); 700 } 701 702 return 0; 703 } 704 705 static int powergate_open(struct inode *inode, struct file *file) 706 { 707 return single_open(file, powergate_show, inode->i_private); 708 } 709 710 static const struct file_operations powergate_fops = { 711 .open = powergate_open, 712 .read = seq_read, 713 .llseek = seq_lseek, 714 .release = single_release, 715 }; 716 717 static int tegra_powergate_debugfs_init(void) 718 { 719 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, 720 &powergate_fops); 721 if (!pmc->debugfs) 722 return -ENOMEM; 723 724 return 0; 725 } 726 727 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg, 728 struct device_node *np) 729 { 730 struct clk *clk; 731 unsigned int i, count; 732 int err; 733 734 count = of_count_phandle_with_args(np, "clocks", "#clock-cells"); 735 if (count == 0) 736 return -ENODEV; 737 738 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); 739 if (!pg->clks) 740 return -ENOMEM; 741 742 for (i = 0; i < count; i++) { 743 pg->clks[i] = of_clk_get(np, i); 744 if (IS_ERR(pg->clks[i])) { 745 err = PTR_ERR(pg->clks[i]); 746 goto err; 747 } 748 } 749 750 pg->num_clks = count; 751 752 return 0; 753 754 err: 755 while (i--) 756 clk_put(pg->clks[i]); 757 758 kfree(pg->clks); 759 760 return err; 761 } 762 763 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg, 764 struct device_node *np, bool off) 765 { 766 int err; 767 768 pg->reset = of_reset_control_array_get_exclusive(np); 769 if (IS_ERR(pg->reset)) { 770 err = PTR_ERR(pg->reset); 771 pr_err("failed to get device resets: %d\n", err); 772 return err; 773 } 774 775 if (off) 776 err = reset_control_assert(pg->reset); 777 else 778 err = reset_control_deassert(pg->reset); 779 780 if (err) 781 reset_control_put(pg->reset); 782 783 return err; 784 } 785 786 static void tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) 787 { 788 struct tegra_powergate *pg; 789 int id, err; 790 bool off; 791 792 pg = kzalloc(sizeof(*pg), GFP_KERNEL); 793 if (!pg) 794 return; 795 796 id = tegra_powergate_lookup(pmc, np->name); 797 if (id < 0) { 798 pr_err("powergate lookup failed for %s: %d\n", np->name, id); 799 goto free_mem; 800 } 801 802 /* 803 * Clear the bit for this powergate so it cannot be managed 804 * directly via the legacy APIs for controlling powergates. 805 */ 806 clear_bit(id, pmc->powergates_available); 807 808 pg->id = id; 809 pg->genpd.name = np->name; 810 pg->genpd.power_off = tegra_genpd_power_off; 811 pg->genpd.power_on = tegra_genpd_power_on; 812 pg->pmc = pmc; 813 814 off = !tegra_powergate_is_powered(pg->id); 815 816 err = tegra_powergate_of_get_clks(pg, np); 817 if (err < 0) { 818 pr_err("failed to get clocks for %s: %d\n", np->name, err); 819 goto set_available; 820 } 821 822 err = tegra_powergate_of_get_resets(pg, np, off); 823 if (err < 0) { 824 pr_err("failed to get resets for %s: %d\n", np->name, err); 825 goto remove_clks; 826 } 827 828 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) { 829 if (off) 830 WARN_ON(tegra_powergate_power_up(pg, true)); 831 832 goto remove_resets; 833 } 834 835 /* 836 * FIXME: If XHCI is enabled for Tegra, then power-up the XUSB 837 * host and super-speed partitions. Once the XHCI driver 838 * manages the partitions itself this code can be removed. Note 839 * that we don't register these partitions with the genpd core 840 * to avoid it from powering down the partitions as they appear 841 * to be unused. 842 */ 843 if (IS_ENABLED(CONFIG_USB_XHCI_TEGRA) && 844 (id == TEGRA_POWERGATE_XUSBA || id == TEGRA_POWERGATE_XUSBC)) { 845 if (off) 846 WARN_ON(tegra_powergate_power_up(pg, true)); 847 848 goto remove_resets; 849 } 850 851 err = pm_genpd_init(&pg->genpd, NULL, off); 852 if (err < 0) { 853 pr_err("failed to initialise PM domain %s: %d\n", np->name, 854 err); 855 goto remove_resets; 856 } 857 858 err = of_genpd_add_provider_simple(np, &pg->genpd); 859 if (err < 0) { 860 pr_err("failed to add PM domain provider for %s: %d\n", 861 np->name, err); 862 goto remove_genpd; 863 } 864 865 pr_debug("added PM domain %s\n", pg->genpd.name); 866 867 return; 868 869 remove_genpd: 870 pm_genpd_remove(&pg->genpd); 871 872 remove_resets: 873 reset_control_put(pg->reset); 874 875 remove_clks: 876 while (pg->num_clks--) 877 clk_put(pg->clks[pg->num_clks]); 878 879 kfree(pg->clks); 880 881 set_available: 882 set_bit(id, pmc->powergates_available); 883 884 free_mem: 885 kfree(pg); 886 } 887 888 static void tegra_powergate_init(struct tegra_pmc *pmc, 889 struct device_node *parent) 890 { 891 struct device_node *np, *child; 892 unsigned int i; 893 894 /* Create a bitmap of the available and valid partitions */ 895 for (i = 0; i < pmc->soc->num_powergates; i++) 896 if (pmc->soc->powergates[i]) 897 set_bit(i, pmc->powergates_available); 898 899 np = of_get_child_by_name(parent, "powergates"); 900 if (!np) 901 return; 902 903 for_each_child_of_node(np, child) 904 tegra_powergate_add(pmc, child); 905 906 of_node_put(np); 907 } 908 909 static const struct tegra_io_pad_soc * 910 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) 911 { 912 unsigned int i; 913 914 for (i = 0; i < pmc->soc->num_io_pads; i++) 915 if (pmc->soc->io_pads[i].id == id) 916 return &pmc->soc->io_pads[i]; 917 918 return NULL; 919 } 920 921 static int tegra_io_pad_prepare(enum tegra_io_pad id, unsigned long *request, 922 unsigned long *status, u32 *mask) 923 { 924 const struct tegra_io_pad_soc *pad; 925 unsigned long rate, value; 926 927 pad = tegra_io_pad_find(pmc, id); 928 if (!pad) { 929 pr_err("invalid I/O pad ID %u\n", id); 930 return -ENOENT; 931 } 932 933 if (pad->dpd == UINT_MAX) 934 return -ENOTSUPP; 935 936 *mask = BIT(pad->dpd % 32); 937 938 if (pad->dpd < 32) { 939 *status = pmc->soc->regs->dpd_status; 940 *request = pmc->soc->regs->dpd_req; 941 } else { 942 *status = pmc->soc->regs->dpd2_status; 943 *request = pmc->soc->regs->dpd2_req; 944 } 945 946 if (pmc->clk) { 947 rate = clk_get_rate(pmc->clk); 948 if (!rate) { 949 pr_err("failed to get clock rate\n"); 950 return -ENODEV; 951 } 952 953 tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE); 954 955 /* must be at least 200 ns, in APB (PCLK) clock cycles */ 956 value = DIV_ROUND_UP(1000000000, rate); 957 value = DIV_ROUND_UP(200, value); 958 tegra_pmc_writel(value, SEL_DPD_TIM); 959 } 960 961 return 0; 962 } 963 964 static int tegra_io_pad_poll(unsigned long offset, u32 mask, 965 u32 val, unsigned long timeout) 966 { 967 u32 value; 968 969 timeout = jiffies + msecs_to_jiffies(timeout); 970 971 while (time_after(timeout, jiffies)) { 972 value = tegra_pmc_readl(offset); 973 if ((value & mask) == val) 974 return 0; 975 976 usleep_range(250, 1000); 977 } 978 979 return -ETIMEDOUT; 980 } 981 982 static void tegra_io_pad_unprepare(void) 983 { 984 if (pmc->clk) 985 tegra_pmc_writel(DPD_SAMPLE_DISABLE, DPD_SAMPLE); 986 } 987 988 /** 989 * tegra_io_pad_power_enable() - enable power to I/O pad 990 * @id: Tegra I/O pad ID for which to enable power 991 * 992 * Returns: 0 on success or a negative error code on failure. 993 */ 994 int tegra_io_pad_power_enable(enum tegra_io_pad id) 995 { 996 unsigned long request, status; 997 u32 mask; 998 int err; 999 1000 mutex_lock(&pmc->powergates_lock); 1001 1002 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1003 if (err < 0) { 1004 pr_err("failed to prepare I/O pad: %d\n", err); 1005 goto unlock; 1006 } 1007 1008 tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | mask, request); 1009 1010 err = tegra_io_pad_poll(status, mask, 0, 250); 1011 if (err < 0) { 1012 pr_err("failed to enable I/O pad: %d\n", err); 1013 goto unlock; 1014 } 1015 1016 tegra_io_pad_unprepare(); 1017 1018 unlock: 1019 mutex_unlock(&pmc->powergates_lock); 1020 return err; 1021 } 1022 EXPORT_SYMBOL(tegra_io_pad_power_enable); 1023 1024 /** 1025 * tegra_io_pad_power_disable() - disable power to I/O pad 1026 * @id: Tegra I/O pad ID for which to disable power 1027 * 1028 * Returns: 0 on success or a negative error code on failure. 1029 */ 1030 int tegra_io_pad_power_disable(enum tegra_io_pad id) 1031 { 1032 unsigned long request, status; 1033 u32 mask; 1034 int err; 1035 1036 mutex_lock(&pmc->powergates_lock); 1037 1038 err = tegra_io_pad_prepare(id, &request, &status, &mask); 1039 if (err < 0) { 1040 pr_err("failed to prepare I/O pad: %d\n", err); 1041 goto unlock; 1042 } 1043 1044 tegra_pmc_writel(IO_DPD_REQ_CODE_ON | mask, request); 1045 1046 err = tegra_io_pad_poll(status, mask, mask, 250); 1047 if (err < 0) { 1048 pr_err("failed to disable I/O pad: %d\n", err); 1049 goto unlock; 1050 } 1051 1052 tegra_io_pad_unprepare(); 1053 1054 unlock: 1055 mutex_unlock(&pmc->powergates_lock); 1056 return err; 1057 } 1058 EXPORT_SYMBOL(tegra_io_pad_power_disable); 1059 1060 int tegra_io_pad_set_voltage(enum tegra_io_pad id, 1061 enum tegra_io_pad_voltage voltage) 1062 { 1063 const struct tegra_io_pad_soc *pad; 1064 u32 value; 1065 1066 pad = tegra_io_pad_find(pmc, id); 1067 if (!pad) 1068 return -ENOENT; 1069 1070 if (pad->voltage == UINT_MAX) 1071 return -ENOTSUPP; 1072 1073 mutex_lock(&pmc->powergates_lock); 1074 1075 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ 1076 value = tegra_pmc_readl(PMC_PWR_DET); 1077 value |= BIT(pad->voltage); 1078 tegra_pmc_writel(value, PMC_PWR_DET); 1079 1080 /* update I/O voltage */ 1081 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1082 1083 if (voltage == TEGRA_IO_PAD_1800000UV) 1084 value &= ~BIT(pad->voltage); 1085 else 1086 value |= BIT(pad->voltage); 1087 1088 tegra_pmc_writel(value, PMC_PWR_DET_VALUE); 1089 1090 mutex_unlock(&pmc->powergates_lock); 1091 1092 usleep_range(100, 250); 1093 1094 return 0; 1095 } 1096 EXPORT_SYMBOL(tegra_io_pad_set_voltage); 1097 1098 int tegra_io_pad_get_voltage(enum tegra_io_pad id) 1099 { 1100 const struct tegra_io_pad_soc *pad; 1101 u32 value; 1102 1103 pad = tegra_io_pad_find(pmc, id); 1104 if (!pad) 1105 return -ENOENT; 1106 1107 if (pad->voltage == UINT_MAX) 1108 return -ENOTSUPP; 1109 1110 value = tegra_pmc_readl(PMC_PWR_DET_VALUE); 1111 1112 if ((value & BIT(pad->voltage)) == 0) 1113 return TEGRA_IO_PAD_1800000UV; 1114 1115 return TEGRA_IO_PAD_3300000UV; 1116 } 1117 EXPORT_SYMBOL(tegra_io_pad_get_voltage); 1118 1119 /** 1120 * tegra_io_rail_power_on() - enable power to I/O rail 1121 * @id: Tegra I/O pad ID for which to enable power 1122 * 1123 * See also: tegra_io_pad_power_enable() 1124 */ 1125 int tegra_io_rail_power_on(unsigned int id) 1126 { 1127 return tegra_io_pad_power_enable(id); 1128 } 1129 EXPORT_SYMBOL(tegra_io_rail_power_on); 1130 1131 /** 1132 * tegra_io_rail_power_off() - disable power to I/O rail 1133 * @id: Tegra I/O pad ID for which to disable power 1134 * 1135 * See also: tegra_io_pad_power_disable() 1136 */ 1137 int tegra_io_rail_power_off(unsigned int id) 1138 { 1139 return tegra_io_pad_power_disable(id); 1140 } 1141 EXPORT_SYMBOL(tegra_io_rail_power_off); 1142 1143 #ifdef CONFIG_PM_SLEEP 1144 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) 1145 { 1146 return pmc->suspend_mode; 1147 } 1148 1149 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) 1150 { 1151 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) 1152 return; 1153 1154 pmc->suspend_mode = mode; 1155 } 1156 1157 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode) 1158 { 1159 unsigned long long rate = 0; 1160 u32 value; 1161 1162 switch (mode) { 1163 case TEGRA_SUSPEND_LP1: 1164 rate = 32768; 1165 break; 1166 1167 case TEGRA_SUSPEND_LP2: 1168 rate = clk_get_rate(pmc->clk); 1169 break; 1170 1171 default: 1172 break; 1173 } 1174 1175 if (WARN_ON_ONCE(rate == 0)) 1176 rate = 100000000; 1177 1178 if (rate != pmc->rate) { 1179 u64 ticks; 1180 1181 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; 1182 do_div(ticks, USEC_PER_SEC); 1183 tegra_pmc_writel(ticks, PMC_CPUPWRGOOD_TIMER); 1184 1185 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; 1186 do_div(ticks, USEC_PER_SEC); 1187 tegra_pmc_writel(ticks, PMC_CPUPWROFF_TIMER); 1188 1189 wmb(); 1190 1191 pmc->rate = rate; 1192 } 1193 1194 value = tegra_pmc_readl(PMC_CNTRL); 1195 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0; 1196 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1197 tegra_pmc_writel(value, PMC_CNTRL); 1198 } 1199 #endif 1200 1201 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) 1202 { 1203 u32 value, values[2]; 1204 1205 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { 1206 } else { 1207 switch (value) { 1208 case 0: 1209 pmc->suspend_mode = TEGRA_SUSPEND_LP0; 1210 break; 1211 1212 case 1: 1213 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1214 break; 1215 1216 case 2: 1217 pmc->suspend_mode = TEGRA_SUSPEND_LP2; 1218 break; 1219 1220 default: 1221 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1222 break; 1223 } 1224 } 1225 1226 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); 1227 1228 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) 1229 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1230 1231 pmc->cpu_good_time = value; 1232 1233 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) 1234 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1235 1236 pmc->cpu_off_time = value; 1237 1238 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", 1239 values, ARRAY_SIZE(values))) 1240 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1241 1242 pmc->core_osc_time = values[0]; 1243 pmc->core_pmu_time = values[1]; 1244 1245 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) 1246 pmc->suspend_mode = TEGRA_SUSPEND_NONE; 1247 1248 pmc->core_off_time = value; 1249 1250 pmc->corereq_high = of_property_read_bool(np, 1251 "nvidia,core-power-req-active-high"); 1252 1253 pmc->sysclkreq_high = of_property_read_bool(np, 1254 "nvidia,sys-clock-req-active-high"); 1255 1256 pmc->combined_req = of_property_read_bool(np, 1257 "nvidia,combined-power-req"); 1258 1259 pmc->cpu_pwr_good_en = of_property_read_bool(np, 1260 "nvidia,cpu-pwr-good-en"); 1261 1262 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, 1263 ARRAY_SIZE(values))) 1264 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) 1265 pmc->suspend_mode = TEGRA_SUSPEND_LP1; 1266 1267 pmc->lp0_vec_phys = values[0]; 1268 pmc->lp0_vec_size = values[1]; 1269 1270 return 0; 1271 } 1272 1273 static void tegra_pmc_init(struct tegra_pmc *pmc) 1274 { 1275 if (pmc->soc->init) 1276 pmc->soc->init(pmc); 1277 } 1278 1279 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) 1280 { 1281 static const char disabled[] = "emergency thermal reset disabled"; 1282 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux; 1283 struct device *dev = pmc->dev; 1284 struct device_node *np; 1285 u32 value, checksum; 1286 1287 if (!pmc->soc->has_tsense_reset) 1288 return; 1289 1290 np = of_find_node_by_name(pmc->dev->of_node, "i2c-thermtrip"); 1291 if (!np) { 1292 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); 1293 return; 1294 } 1295 1296 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { 1297 dev_err(dev, "I2C controller ID missing, %s.\n", disabled); 1298 goto out; 1299 } 1300 1301 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { 1302 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); 1303 goto out; 1304 } 1305 1306 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { 1307 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); 1308 goto out; 1309 } 1310 1311 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { 1312 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); 1313 goto out; 1314 } 1315 1316 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) 1317 pinmux = 0; 1318 1319 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1320 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE; 1321 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1322 1323 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) | 1324 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT); 1325 tegra_pmc_writel(value, PMC_SCRATCH54); 1326 1327 value = PMC_SCRATCH55_RESET_TEGRA; 1328 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT; 1329 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT; 1330 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT; 1331 1332 /* 1333 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will 1334 * contain the checksum and are currently zero, so they are not added. 1335 */ 1336 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) 1337 + ((value >> 24) & 0xff); 1338 checksum &= 0xff; 1339 checksum = 0x100 - checksum; 1340 1341 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT; 1342 1343 tegra_pmc_writel(value, PMC_SCRATCH55); 1344 1345 value = tegra_pmc_readl(PMC_SENSOR_CTRL); 1346 value |= PMC_SENSOR_CTRL_ENABLE_RST; 1347 tegra_pmc_writel(value, PMC_SENSOR_CTRL); 1348 1349 dev_info(pmc->dev, "emergency thermal reset enabled\n"); 1350 1351 out: 1352 of_node_put(np); 1353 } 1354 1355 static int tegra_pmc_probe(struct platform_device *pdev) 1356 { 1357 void __iomem *base; 1358 struct resource *res; 1359 int err; 1360 1361 /* 1362 * Early initialisation should have configured an initial 1363 * register mapping and setup the soc data pointer. If these 1364 * are not valid then something went badly wrong! 1365 */ 1366 if (WARN_ON(!pmc->base || !pmc->soc)) 1367 return -ENODEV; 1368 1369 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); 1370 if (err < 0) 1371 return err; 1372 1373 /* take over the memory region from the early initialization */ 1374 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1375 base = devm_ioremap_resource(&pdev->dev, res); 1376 if (IS_ERR(base)) 1377 return PTR_ERR(base); 1378 1379 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake"); 1380 if (res) { 1381 pmc->wake = devm_ioremap_resource(&pdev->dev, res); 1382 if (IS_ERR(pmc->wake)) 1383 return PTR_ERR(pmc->wake); 1384 } else { 1385 pmc->wake = base; 1386 } 1387 1388 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag"); 1389 if (res) { 1390 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); 1391 if (IS_ERR(pmc->aotag)) 1392 return PTR_ERR(pmc->aotag); 1393 } else { 1394 pmc->aotag = base; 1395 } 1396 1397 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch"); 1398 if (res) { 1399 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); 1400 if (IS_ERR(pmc->scratch)) 1401 return PTR_ERR(pmc->scratch); 1402 } else { 1403 pmc->scratch = base; 1404 } 1405 1406 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); 1407 if (IS_ERR(pmc->clk)) { 1408 err = PTR_ERR(pmc->clk); 1409 1410 if (err != -ENOENT) { 1411 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); 1412 return err; 1413 } 1414 1415 pmc->clk = NULL; 1416 } 1417 1418 pmc->dev = &pdev->dev; 1419 1420 tegra_pmc_init(pmc); 1421 1422 tegra_pmc_init_tsense_reset(pmc); 1423 1424 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1425 err = tegra_powergate_debugfs_init(); 1426 if (err < 0) 1427 return err; 1428 } 1429 1430 err = register_restart_handler(&tegra_pmc_restart_handler); 1431 if (err) { 1432 debugfs_remove(pmc->debugfs); 1433 dev_err(&pdev->dev, "unable to register restart handler, %d\n", 1434 err); 1435 return err; 1436 } 1437 1438 mutex_lock(&pmc->powergates_lock); 1439 iounmap(pmc->base); 1440 pmc->base = base; 1441 mutex_unlock(&pmc->powergates_lock); 1442 1443 return 0; 1444 } 1445 1446 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1447 static int tegra_pmc_suspend(struct device *dev) 1448 { 1449 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); 1450 1451 return 0; 1452 } 1453 1454 static int tegra_pmc_resume(struct device *dev) 1455 { 1456 tegra_pmc_writel(0x0, PMC_SCRATCH41); 1457 1458 return 0; 1459 } 1460 1461 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume); 1462 1463 #endif 1464 1465 static const char * const tegra20_powergates[] = { 1466 [TEGRA_POWERGATE_CPU] = "cpu", 1467 [TEGRA_POWERGATE_3D] = "3d", 1468 [TEGRA_POWERGATE_VENC] = "venc", 1469 [TEGRA_POWERGATE_VDEC] = "vdec", 1470 [TEGRA_POWERGATE_PCIE] = "pcie", 1471 [TEGRA_POWERGATE_L2] = "l2", 1472 [TEGRA_POWERGATE_MPE] = "mpe", 1473 }; 1474 1475 static const struct tegra_pmc_regs tegra20_pmc_regs = { 1476 .scratch0 = 0x50, 1477 .dpd_req = 0x1b8, 1478 .dpd_status = 0x1bc, 1479 .dpd2_req = 0x1c0, 1480 .dpd2_status = 0x1c4, 1481 }; 1482 1483 static void tegra20_pmc_init(struct tegra_pmc *pmc) 1484 { 1485 u32 value; 1486 1487 /* Always enable CPU power request */ 1488 value = tegra_pmc_readl(PMC_CNTRL); 1489 value |= PMC_CNTRL_CPU_PWRREQ_OE; 1490 tegra_pmc_writel(value, PMC_CNTRL); 1491 1492 value = tegra_pmc_readl(PMC_CNTRL); 1493 1494 if (pmc->sysclkreq_high) 1495 value &= ~PMC_CNTRL_SYSCLK_POLARITY; 1496 else 1497 value |= PMC_CNTRL_SYSCLK_POLARITY; 1498 1499 /* configure the output polarity while the request is tristated */ 1500 tegra_pmc_writel(value, PMC_CNTRL); 1501 1502 /* now enable the request */ 1503 value = tegra_pmc_readl(PMC_CNTRL); 1504 value |= PMC_CNTRL_SYSCLK_OE; 1505 tegra_pmc_writel(value, PMC_CNTRL); 1506 } 1507 1508 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1509 struct device_node *np, 1510 bool invert) 1511 { 1512 u32 value; 1513 1514 value = tegra_pmc_readl(PMC_CNTRL); 1515 1516 if (invert) 1517 value |= PMC_CNTRL_INTR_POLARITY; 1518 else 1519 value &= ~PMC_CNTRL_INTR_POLARITY; 1520 1521 tegra_pmc_writel(value, PMC_CNTRL); 1522 } 1523 1524 static const struct tegra_pmc_soc tegra20_pmc_soc = { 1525 .num_powergates = ARRAY_SIZE(tegra20_powergates), 1526 .powergates = tegra20_powergates, 1527 .num_cpu_powergates = 0, 1528 .cpu_powergates = NULL, 1529 .has_tsense_reset = false, 1530 .has_gpu_clamps = false, 1531 .num_io_pads = 0, 1532 .io_pads = NULL, 1533 .regs = &tegra20_pmc_regs, 1534 .init = tegra20_pmc_init, 1535 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1536 }; 1537 1538 static const char * const tegra30_powergates[] = { 1539 [TEGRA_POWERGATE_CPU] = "cpu0", 1540 [TEGRA_POWERGATE_3D] = "3d0", 1541 [TEGRA_POWERGATE_VENC] = "venc", 1542 [TEGRA_POWERGATE_VDEC] = "vdec", 1543 [TEGRA_POWERGATE_PCIE] = "pcie", 1544 [TEGRA_POWERGATE_L2] = "l2", 1545 [TEGRA_POWERGATE_MPE] = "mpe", 1546 [TEGRA_POWERGATE_HEG] = "heg", 1547 [TEGRA_POWERGATE_SATA] = "sata", 1548 [TEGRA_POWERGATE_CPU1] = "cpu1", 1549 [TEGRA_POWERGATE_CPU2] = "cpu2", 1550 [TEGRA_POWERGATE_CPU3] = "cpu3", 1551 [TEGRA_POWERGATE_CELP] = "celp", 1552 [TEGRA_POWERGATE_3D1] = "3d1", 1553 }; 1554 1555 static const u8 tegra30_cpu_powergates[] = { 1556 TEGRA_POWERGATE_CPU, 1557 TEGRA_POWERGATE_CPU1, 1558 TEGRA_POWERGATE_CPU2, 1559 TEGRA_POWERGATE_CPU3, 1560 }; 1561 1562 static const struct tegra_pmc_soc tegra30_pmc_soc = { 1563 .num_powergates = ARRAY_SIZE(tegra30_powergates), 1564 .powergates = tegra30_powergates, 1565 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 1566 .cpu_powergates = tegra30_cpu_powergates, 1567 .has_tsense_reset = true, 1568 .has_gpu_clamps = false, 1569 .num_io_pads = 0, 1570 .io_pads = NULL, 1571 .regs = &tegra20_pmc_regs, 1572 .init = tegra20_pmc_init, 1573 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1574 }; 1575 1576 static const char * const tegra114_powergates[] = { 1577 [TEGRA_POWERGATE_CPU] = "crail", 1578 [TEGRA_POWERGATE_3D] = "3d", 1579 [TEGRA_POWERGATE_VENC] = "venc", 1580 [TEGRA_POWERGATE_VDEC] = "vdec", 1581 [TEGRA_POWERGATE_MPE] = "mpe", 1582 [TEGRA_POWERGATE_HEG] = "heg", 1583 [TEGRA_POWERGATE_CPU1] = "cpu1", 1584 [TEGRA_POWERGATE_CPU2] = "cpu2", 1585 [TEGRA_POWERGATE_CPU3] = "cpu3", 1586 [TEGRA_POWERGATE_CELP] = "celp", 1587 [TEGRA_POWERGATE_CPU0] = "cpu0", 1588 [TEGRA_POWERGATE_C0NC] = "c0nc", 1589 [TEGRA_POWERGATE_C1NC] = "c1nc", 1590 [TEGRA_POWERGATE_DIS] = "dis", 1591 [TEGRA_POWERGATE_DISB] = "disb", 1592 [TEGRA_POWERGATE_XUSBA] = "xusba", 1593 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1594 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1595 }; 1596 1597 static const u8 tegra114_cpu_powergates[] = { 1598 TEGRA_POWERGATE_CPU0, 1599 TEGRA_POWERGATE_CPU1, 1600 TEGRA_POWERGATE_CPU2, 1601 TEGRA_POWERGATE_CPU3, 1602 }; 1603 1604 static const struct tegra_pmc_soc tegra114_pmc_soc = { 1605 .num_powergates = ARRAY_SIZE(tegra114_powergates), 1606 .powergates = tegra114_powergates, 1607 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 1608 .cpu_powergates = tegra114_cpu_powergates, 1609 .has_tsense_reset = true, 1610 .has_gpu_clamps = false, 1611 .num_io_pads = 0, 1612 .io_pads = NULL, 1613 .regs = &tegra20_pmc_regs, 1614 .init = tegra20_pmc_init, 1615 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1616 }; 1617 1618 static const char * const tegra124_powergates[] = { 1619 [TEGRA_POWERGATE_CPU] = "crail", 1620 [TEGRA_POWERGATE_3D] = "3d", 1621 [TEGRA_POWERGATE_VENC] = "venc", 1622 [TEGRA_POWERGATE_PCIE] = "pcie", 1623 [TEGRA_POWERGATE_VDEC] = "vdec", 1624 [TEGRA_POWERGATE_MPE] = "mpe", 1625 [TEGRA_POWERGATE_HEG] = "heg", 1626 [TEGRA_POWERGATE_SATA] = "sata", 1627 [TEGRA_POWERGATE_CPU1] = "cpu1", 1628 [TEGRA_POWERGATE_CPU2] = "cpu2", 1629 [TEGRA_POWERGATE_CPU3] = "cpu3", 1630 [TEGRA_POWERGATE_CELP] = "celp", 1631 [TEGRA_POWERGATE_CPU0] = "cpu0", 1632 [TEGRA_POWERGATE_C0NC] = "c0nc", 1633 [TEGRA_POWERGATE_C1NC] = "c1nc", 1634 [TEGRA_POWERGATE_SOR] = "sor", 1635 [TEGRA_POWERGATE_DIS] = "dis", 1636 [TEGRA_POWERGATE_DISB] = "disb", 1637 [TEGRA_POWERGATE_XUSBA] = "xusba", 1638 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1639 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1640 [TEGRA_POWERGATE_VIC] = "vic", 1641 [TEGRA_POWERGATE_IRAM] = "iram", 1642 }; 1643 1644 static const u8 tegra124_cpu_powergates[] = { 1645 TEGRA_POWERGATE_CPU0, 1646 TEGRA_POWERGATE_CPU1, 1647 TEGRA_POWERGATE_CPU2, 1648 TEGRA_POWERGATE_CPU3, 1649 }; 1650 1651 static const struct tegra_io_pad_soc tegra124_io_pads[] = { 1652 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1653 { .id = TEGRA_IO_PAD_BB, .dpd = 15, .voltage = UINT_MAX }, 1654 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = UINT_MAX }, 1655 { .id = TEGRA_IO_PAD_COMP, .dpd = 22, .voltage = UINT_MAX }, 1656 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1657 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1658 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1659 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1660 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1661 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1662 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1663 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1664 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1665 { .id = TEGRA_IO_PAD_HV, .dpd = 38, .voltage = UINT_MAX }, 1666 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1667 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1668 { .id = TEGRA_IO_PAD_NAND, .dpd = 13, .voltage = UINT_MAX }, 1669 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1670 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1671 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1672 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1673 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = UINT_MAX }, 1674 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = UINT_MAX }, 1675 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 35, .voltage = UINT_MAX }, 1676 { .id = TEGRA_IO_PAD_SYS_DDC, .dpd = 58, .voltage = UINT_MAX }, 1677 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1678 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1679 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1680 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1681 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1682 }; 1683 1684 static const struct tegra_pmc_soc tegra124_pmc_soc = { 1685 .num_powergates = ARRAY_SIZE(tegra124_powergates), 1686 .powergates = tegra124_powergates, 1687 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 1688 .cpu_powergates = tegra124_cpu_powergates, 1689 .has_tsense_reset = true, 1690 .has_gpu_clamps = true, 1691 .num_io_pads = ARRAY_SIZE(tegra124_io_pads), 1692 .io_pads = tegra124_io_pads, 1693 .regs = &tegra20_pmc_regs, 1694 .init = tegra20_pmc_init, 1695 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1696 }; 1697 1698 static const char * const tegra210_powergates[] = { 1699 [TEGRA_POWERGATE_CPU] = "crail", 1700 [TEGRA_POWERGATE_3D] = "3d", 1701 [TEGRA_POWERGATE_VENC] = "venc", 1702 [TEGRA_POWERGATE_PCIE] = "pcie", 1703 [TEGRA_POWERGATE_MPE] = "mpe", 1704 [TEGRA_POWERGATE_SATA] = "sata", 1705 [TEGRA_POWERGATE_CPU1] = "cpu1", 1706 [TEGRA_POWERGATE_CPU2] = "cpu2", 1707 [TEGRA_POWERGATE_CPU3] = "cpu3", 1708 [TEGRA_POWERGATE_CPU0] = "cpu0", 1709 [TEGRA_POWERGATE_C0NC] = "c0nc", 1710 [TEGRA_POWERGATE_SOR] = "sor", 1711 [TEGRA_POWERGATE_DIS] = "dis", 1712 [TEGRA_POWERGATE_DISB] = "disb", 1713 [TEGRA_POWERGATE_XUSBA] = "xusba", 1714 [TEGRA_POWERGATE_XUSBB] = "xusbb", 1715 [TEGRA_POWERGATE_XUSBC] = "xusbc", 1716 [TEGRA_POWERGATE_VIC] = "vic", 1717 [TEGRA_POWERGATE_IRAM] = "iram", 1718 [TEGRA_POWERGATE_NVDEC] = "nvdec", 1719 [TEGRA_POWERGATE_NVJPG] = "nvjpg", 1720 [TEGRA_POWERGATE_AUD] = "aud", 1721 [TEGRA_POWERGATE_DFD] = "dfd", 1722 [TEGRA_POWERGATE_VE2] = "ve2", 1723 }; 1724 1725 static const u8 tegra210_cpu_powergates[] = { 1726 TEGRA_POWERGATE_CPU0, 1727 TEGRA_POWERGATE_CPU1, 1728 TEGRA_POWERGATE_CPU2, 1729 TEGRA_POWERGATE_CPU3, 1730 }; 1731 1732 static const struct tegra_io_pad_soc tegra210_io_pads[] = { 1733 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = 5 }, 1734 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = 18 }, 1735 { .id = TEGRA_IO_PAD_CAM, .dpd = 36, .voltage = 10 }, 1736 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1737 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1738 { .id = TEGRA_IO_PAD_CSIC, .dpd = 42, .voltage = UINT_MAX }, 1739 { .id = TEGRA_IO_PAD_CSID, .dpd = 43, .voltage = UINT_MAX }, 1740 { .id = TEGRA_IO_PAD_CSIE, .dpd = 44, .voltage = UINT_MAX }, 1741 { .id = TEGRA_IO_PAD_CSIF, .dpd = 45, .voltage = UINT_MAX }, 1742 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = 19 }, 1743 { .id = TEGRA_IO_PAD_DEBUG_NONAO, .dpd = 26, .voltage = UINT_MAX }, 1744 { .id = TEGRA_IO_PAD_DMIC, .dpd = 50, .voltage = 20 }, 1745 { .id = TEGRA_IO_PAD_DP, .dpd = 51, .voltage = UINT_MAX }, 1746 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1747 { .id = TEGRA_IO_PAD_DSIB, .dpd = 39, .voltage = UINT_MAX }, 1748 { .id = TEGRA_IO_PAD_DSIC, .dpd = 40, .voltage = UINT_MAX }, 1749 { .id = TEGRA_IO_PAD_DSID, .dpd = 41, .voltage = UINT_MAX }, 1750 { .id = TEGRA_IO_PAD_EMMC, .dpd = 35, .voltage = UINT_MAX }, 1751 { .id = TEGRA_IO_PAD_EMMC2, .dpd = 37, .voltage = UINT_MAX }, 1752 { .id = TEGRA_IO_PAD_GPIO, .dpd = 27, .voltage = 21 }, 1753 { .id = TEGRA_IO_PAD_HDMI, .dpd = 28, .voltage = UINT_MAX }, 1754 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1755 { .id = TEGRA_IO_PAD_LVDS, .dpd = 57, .voltage = UINT_MAX }, 1756 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1757 { .id = TEGRA_IO_PAD_PEX_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1758 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 5, .voltage = UINT_MAX }, 1759 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1760 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = UINT_MAX, .voltage = 11 }, 1761 { .id = TEGRA_IO_PAD_SDMMC1, .dpd = 33, .voltage = 12 }, 1762 { .id = TEGRA_IO_PAD_SDMMC3, .dpd = 34, .voltage = 13 }, 1763 { .id = TEGRA_IO_PAD_SPI, .dpd = 46, .voltage = 22 }, 1764 { .id = TEGRA_IO_PAD_SPI_HV, .dpd = 47, .voltage = 23 }, 1765 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = 2 }, 1766 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1767 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1768 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1769 { .id = TEGRA_IO_PAD_USB3, .dpd = 18, .voltage = UINT_MAX }, 1770 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1771 }; 1772 1773 static const struct tegra_pmc_soc tegra210_pmc_soc = { 1774 .num_powergates = ARRAY_SIZE(tegra210_powergates), 1775 .powergates = tegra210_powergates, 1776 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates), 1777 .cpu_powergates = tegra210_cpu_powergates, 1778 .has_tsense_reset = true, 1779 .has_gpu_clamps = true, 1780 .needs_mbist_war = true, 1781 .num_io_pads = ARRAY_SIZE(tegra210_io_pads), 1782 .io_pads = tegra210_io_pads, 1783 .regs = &tegra20_pmc_regs, 1784 .init = tegra20_pmc_init, 1785 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity, 1786 }; 1787 1788 static const struct tegra_io_pad_soc tegra186_io_pads[] = { 1789 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX }, 1790 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX }, 1791 { .id = TEGRA_IO_PAD_DSI, .dpd = 2, .voltage = UINT_MAX }, 1792 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX }, 1793 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX }, 1794 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX }, 1795 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX }, 1796 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX }, 1797 { .id = TEGRA_IO_PAD_USB0, .dpd = 9, .voltage = UINT_MAX }, 1798 { .id = TEGRA_IO_PAD_USB1, .dpd = 10, .voltage = UINT_MAX }, 1799 { .id = TEGRA_IO_PAD_USB2, .dpd = 11, .voltage = UINT_MAX }, 1800 { .id = TEGRA_IO_PAD_USB_BIAS, .dpd = 12, .voltage = UINT_MAX }, 1801 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX }, 1802 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX }, 1803 { .id = TEGRA_IO_PAD_HSIC, .dpd = 19, .voltage = UINT_MAX }, 1804 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX }, 1805 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX }, 1806 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX }, 1807 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX }, 1808 { .id = TEGRA_IO_PAD_SDMMC2_HV, .dpd = 34, .voltage = UINT_MAX }, 1809 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX }, 1810 { .id = TEGRA_IO_PAD_CAM, .dpd = 38, .voltage = UINT_MAX }, 1811 { .id = TEGRA_IO_PAD_DSIB, .dpd = 40, .voltage = UINT_MAX }, 1812 { .id = TEGRA_IO_PAD_DSIC, .dpd = 41, .voltage = UINT_MAX }, 1813 { .id = TEGRA_IO_PAD_DSID, .dpd = 42, .voltage = UINT_MAX }, 1814 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX }, 1815 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX }, 1816 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX }, 1817 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX }, 1818 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX }, 1819 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX }, 1820 { .id = TEGRA_IO_PAD_DMIC_HV, .dpd = 52, .voltage = UINT_MAX }, 1821 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX }, 1822 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX }, 1823 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX }, 1824 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX }, 1825 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX }, 1826 }; 1827 1828 static const struct tegra_pmc_regs tegra186_pmc_regs = { 1829 .scratch0 = 0x2000, 1830 .dpd_req = 0x74, 1831 .dpd_status = 0x78, 1832 .dpd2_req = 0x7c, 1833 .dpd2_status = 0x80, 1834 }; 1835 1836 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, 1837 struct device_node *np, 1838 bool invert) 1839 { 1840 struct resource regs; 1841 void __iomem *wake; 1842 u32 value; 1843 int index; 1844 1845 index = of_property_match_string(np, "reg-names", "wake"); 1846 if (index < 0) { 1847 pr_err("failed to find PMC wake registers\n"); 1848 return; 1849 } 1850 1851 of_address_to_resource(np, index, ®s); 1852 1853 wake = ioremap_nocache(regs.start, resource_size(®s)); 1854 if (!wake) { 1855 pr_err("failed to map PMC wake registers\n"); 1856 return; 1857 } 1858 1859 value = readl(wake + WAKE_AOWAKE_CTRL); 1860 1861 if (invert) 1862 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY; 1863 else 1864 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY; 1865 1866 writel(value, wake + WAKE_AOWAKE_CTRL); 1867 1868 iounmap(wake); 1869 } 1870 1871 static const struct tegra_pmc_soc tegra186_pmc_soc = { 1872 .num_powergates = 0, 1873 .powergates = NULL, 1874 .num_cpu_powergates = 0, 1875 .cpu_powergates = NULL, 1876 .has_tsense_reset = false, 1877 .has_gpu_clamps = false, 1878 .num_io_pads = ARRAY_SIZE(tegra186_io_pads), 1879 .io_pads = tegra186_io_pads, 1880 .regs = &tegra186_pmc_regs, 1881 .init = NULL, 1882 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity, 1883 }; 1884 1885 static const struct of_device_id tegra_pmc_match[] = { 1886 { .compatible = "nvidia,tegra194-pmc", .data = &tegra186_pmc_soc }, 1887 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc }, 1888 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc }, 1889 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc }, 1890 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc }, 1891 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc }, 1892 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc }, 1893 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc }, 1894 { } 1895 }; 1896 1897 static struct platform_driver tegra_pmc_driver = { 1898 .driver = { 1899 .name = "tegra-pmc", 1900 .suppress_bind_attrs = true, 1901 .of_match_table = tegra_pmc_match, 1902 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) 1903 .pm = &tegra_pmc_pm_ops, 1904 #endif 1905 }, 1906 .probe = tegra_pmc_probe, 1907 }; 1908 builtin_platform_driver(tegra_pmc_driver); 1909 1910 /* 1911 * Early initialization to allow access to registers in the very early boot 1912 * process. 1913 */ 1914 static int __init tegra_pmc_early_init(void) 1915 { 1916 const struct of_device_id *match; 1917 struct device_node *np; 1918 struct resource regs; 1919 bool invert; 1920 1921 mutex_init(&pmc->powergates_lock); 1922 1923 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match); 1924 if (!np) { 1925 /* 1926 * Fall back to legacy initialization for 32-bit ARM only. All 1927 * 64-bit ARM device tree files for Tegra are required to have 1928 * a PMC node. 1929 * 1930 * This is for backwards-compatibility with old device trees 1931 * that didn't contain a PMC node. Note that in this case the 1932 * SoC data can't be matched and therefore powergating is 1933 * disabled. 1934 */ 1935 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) { 1936 pr_warn("DT node not found, powergating disabled\n"); 1937 1938 regs.start = 0x7000e400; 1939 regs.end = 0x7000e7ff; 1940 regs.flags = IORESOURCE_MEM; 1941 1942 pr_warn("Using memory region %pR\n", ®s); 1943 } else { 1944 /* 1945 * At this point we're not running on Tegra, so play 1946 * nice with multi-platform kernels. 1947 */ 1948 return 0; 1949 } 1950 } else { 1951 /* 1952 * Extract information from the device tree if we've found a 1953 * matching node. 1954 */ 1955 if (of_address_to_resource(np, 0, ®s) < 0) { 1956 pr_err("failed to get PMC registers\n"); 1957 of_node_put(np); 1958 return -ENXIO; 1959 } 1960 } 1961 1962 pmc->base = ioremap_nocache(regs.start, resource_size(®s)); 1963 if (!pmc->base) { 1964 pr_err("failed to map PMC registers\n"); 1965 of_node_put(np); 1966 return -ENXIO; 1967 } 1968 1969 if (np) { 1970 pmc->soc = match->data; 1971 1972 tegra_powergate_init(pmc, np); 1973 1974 /* 1975 * Invert the interrupt polarity if a PMC device tree node 1976 * exists and contains the nvidia,invert-interrupt property. 1977 */ 1978 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); 1979 1980 pmc->soc->setup_irq_polarity(pmc, np, invert); 1981 1982 of_node_put(np); 1983 } 1984 1985 return 0; 1986 } 1987 early_initcall(tegra_pmc_early_init); 1988