1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2a2686766SThierry Reding /*
3a2686766SThierry Reding * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved.
4a2686766SThierry Reding */
5a2686766SThierry Reding
6b8818de9SDmitry Osipenko #define dev_fmt(fmt) "tegra-soc: " fmt
7b8818de9SDmitry Osipenko
8b8818de9SDmitry Osipenko #include <linux/clk.h>
9b8818de9SDmitry Osipenko #include <linux/device.h>
10b8818de9SDmitry Osipenko #include <linux/export.h>
11a2686766SThierry Reding #include <linux/of.h>
12b8818de9SDmitry Osipenko #include <linux/pm_opp.h>
13006da96cSDmitry Osipenko #include <linux/pm_runtime.h>
14a2686766SThierry Reding
15a2686766SThierry Reding #include <soc/tegra/common.h>
16b8818de9SDmitry Osipenko #include <soc/tegra/fuse.h>
17a2686766SThierry Reding
18a2686766SThierry Reding static const struct of_device_id tegra_machine_match[] = {
19a2686766SThierry Reding { .compatible = "nvidia,tegra20", },
20a2686766SThierry Reding { .compatible = "nvidia,tegra30", },
21a2686766SThierry Reding { .compatible = "nvidia,tegra114", },
22a2686766SThierry Reding { .compatible = "nvidia,tegra124", },
23ad09c8c2SThierry Reding { .compatible = "nvidia,tegra132", },
243a369982SThierry Reding { .compatible = "nvidia,tegra210", },
25a2686766SThierry Reding { }
26a2686766SThierry Reding };
27a2686766SThierry Reding
soc_is_tegra(void)28a2686766SThierry Reding bool soc_is_tegra(void)
29a2686766SThierry Reding {
309eb40fa2SYangtao Li const struct of_device_id *match;
31a2686766SThierry Reding struct device_node *root;
32a2686766SThierry Reding
33a2686766SThierry Reding root = of_find_node_by_path("/");
34a2686766SThierry Reding if (!root)
35a2686766SThierry Reding return false;
36a2686766SThierry Reding
379eb40fa2SYangtao Li match = of_match_node(tegra_machine_match, root);
389eb40fa2SYangtao Li of_node_put(root);
399eb40fa2SYangtao Li
409eb40fa2SYangtao Li return match != NULL;
41a2686766SThierry Reding }
42b8818de9SDmitry Osipenko
tegra_core_dev_init_opp_state(struct device * dev)43b8818de9SDmitry Osipenko static int tegra_core_dev_init_opp_state(struct device *dev)
44b8818de9SDmitry Osipenko {
45b8818de9SDmitry Osipenko unsigned long rate;
46b8818de9SDmitry Osipenko struct clk *clk;
47006da96cSDmitry Osipenko bool rpm_enabled;
48b8818de9SDmitry Osipenko int err;
49b8818de9SDmitry Osipenko
50b8818de9SDmitry Osipenko clk = devm_clk_get(dev, NULL);
51b8818de9SDmitry Osipenko if (IS_ERR(clk)) {
52b8818de9SDmitry Osipenko dev_err(dev, "failed to get clk: %pe\n", clk);
53b8818de9SDmitry Osipenko return PTR_ERR(clk);
54b8818de9SDmitry Osipenko }
55b8818de9SDmitry Osipenko
56b8818de9SDmitry Osipenko rate = clk_get_rate(clk);
57b8818de9SDmitry Osipenko if (!rate) {
58b8818de9SDmitry Osipenko dev_err(dev, "failed to get clk rate\n");
59b8818de9SDmitry Osipenko return -EINVAL;
60b8818de9SDmitry Osipenko }
61b8818de9SDmitry Osipenko
62006da96cSDmitry Osipenko /*
63006da96cSDmitry Osipenko * Runtime PM of the device must be enabled in order to set up
64006da96cSDmitry Osipenko * GENPD's performance properly because GENPD core checks whether
65006da96cSDmitry Osipenko * device is suspended and this check doesn't work while RPM is
66006da96cSDmitry Osipenko * disabled. This makes sure the OPP vote below gets cached in
67006da96cSDmitry Osipenko * GENPD for the device. Instead, the vote is done the next time
68006da96cSDmitry Osipenko * the device gets runtime resumed.
69006da96cSDmitry Osipenko */
70006da96cSDmitry Osipenko rpm_enabled = pm_runtime_enabled(dev);
71006da96cSDmitry Osipenko if (!rpm_enabled)
72006da96cSDmitry Osipenko pm_runtime_enable(dev);
73006da96cSDmitry Osipenko
74006da96cSDmitry Osipenko /* should never happen in practice */
75006da96cSDmitry Osipenko if (!pm_runtime_enabled(dev)) {
76006da96cSDmitry Osipenko dev_WARN(dev, "failed to enable runtime PM\n");
77006da96cSDmitry Osipenko pm_runtime_disable(dev);
78006da96cSDmitry Osipenko return -EINVAL;
79006da96cSDmitry Osipenko }
80006da96cSDmitry Osipenko
81b8818de9SDmitry Osipenko /* first dummy rate-setting initializes voltage vote */
82b8818de9SDmitry Osipenko err = dev_pm_opp_set_rate(dev, rate);
83006da96cSDmitry Osipenko
84006da96cSDmitry Osipenko if (!rpm_enabled)
85006da96cSDmitry Osipenko pm_runtime_disable(dev);
86006da96cSDmitry Osipenko
87b8818de9SDmitry Osipenko if (err) {
88b8818de9SDmitry Osipenko dev_err(dev, "failed to initialize OPP clock: %d\n", err);
89b8818de9SDmitry Osipenko return err;
90b8818de9SDmitry Osipenko }
91b8818de9SDmitry Osipenko
92b8818de9SDmitry Osipenko return 0;
93b8818de9SDmitry Osipenko }
94b8818de9SDmitry Osipenko
95b8818de9SDmitry Osipenko /**
96b8818de9SDmitry Osipenko * devm_tegra_core_dev_init_opp_table() - initialize OPP table
97b8818de9SDmitry Osipenko * @dev: device for which OPP table is initialized
98b8818de9SDmitry Osipenko * @params: pointer to the OPP table configuration
99b8818de9SDmitry Osipenko *
100b8818de9SDmitry Osipenko * This function will initialize OPP table and sync OPP state of a Tegra SoC
101b8818de9SDmitry Osipenko * core device.
102b8818de9SDmitry Osipenko *
103b8818de9SDmitry Osipenko * Return: 0 on success or errorno.
104b8818de9SDmitry Osipenko */
devm_tegra_core_dev_init_opp_table(struct device * dev,struct tegra_core_opp_params * params)105b8818de9SDmitry Osipenko int devm_tegra_core_dev_init_opp_table(struct device *dev,
106b8818de9SDmitry Osipenko struct tegra_core_opp_params *params)
107b8818de9SDmitry Osipenko {
108b8818de9SDmitry Osipenko u32 hw_version;
109b8818de9SDmitry Osipenko int err;
110*25a18559SViresh Kumar /*
111*25a18559SViresh Kumar * The clk's connection id to set is NULL and this is a NULL terminated
112*25a18559SViresh Kumar * array, hence two NULL entries.
113*25a18559SViresh Kumar */
114*25a18559SViresh Kumar const char *clk_names[] = { NULL, NULL };
115*25a18559SViresh Kumar struct dev_pm_opp_config config = {
116*25a18559SViresh Kumar /*
117*25a18559SViresh Kumar * For some devices we don't have any OPP table in the DT, and
118*25a18559SViresh Kumar * in order to use the same code path for all the devices, we
119*25a18559SViresh Kumar * create a dummy OPP table for them via this. The dummy OPP
120*25a18559SViresh Kumar * table is only capable of doing clk_set_rate() on invocation
121*25a18559SViresh Kumar * of dev_pm_opp_set_rate() and doesn't provide any other
122*25a18559SViresh Kumar * functionality.
123*25a18559SViresh Kumar */
124*25a18559SViresh Kumar .clk_names = clk_names,
125*25a18559SViresh Kumar };
126*25a18559SViresh Kumar
127*25a18559SViresh Kumar if (of_machine_is_compatible("nvidia,tegra20")) {
128*25a18559SViresh Kumar hw_version = BIT(tegra_sku_info.soc_process_id);
129*25a18559SViresh Kumar config.supported_hw = &hw_version;
130*25a18559SViresh Kumar config.supported_hw_count = 1;
131*25a18559SViresh Kumar } else if (of_machine_is_compatible("nvidia,tegra30")) {
132*25a18559SViresh Kumar hw_version = BIT(tegra_sku_info.soc_speedo_id);
133*25a18559SViresh Kumar config.supported_hw = &hw_version;
134*25a18559SViresh Kumar config.supported_hw_count = 1;
135*25a18559SViresh Kumar }
136*25a18559SViresh Kumar
137*25a18559SViresh Kumar err = devm_pm_opp_set_config(dev, &config);
138*25a18559SViresh Kumar if (err) {
139*25a18559SViresh Kumar dev_err(dev, "failed to set OPP config: %d\n", err);
140*25a18559SViresh Kumar return err;
141*25a18559SViresh Kumar }
142b8818de9SDmitry Osipenko
143a6db3b92SViresh Kumar /*
144*25a18559SViresh Kumar * Tegra114+ doesn't support OPP yet, return early for non tegra20/30
145*25a18559SViresh Kumar * case.
146a6db3b92SViresh Kumar */
147*25a18559SViresh Kumar if (!config.supported_hw)
148b8818de9SDmitry Osipenko return -ENODEV;
149b8818de9SDmitry Osipenko
150b8818de9SDmitry Osipenko /*
151b8818de9SDmitry Osipenko * Older device-trees have an empty OPP table, we will get
152b8818de9SDmitry Osipenko * -ENODEV from devm_pm_opp_of_add_table() in this case.
153b8818de9SDmitry Osipenko */
154b8818de9SDmitry Osipenko err = devm_pm_opp_of_add_table(dev);
155b8818de9SDmitry Osipenko if (err) {
15666209e6fSDmitry Osipenko if (err != -ENODEV)
157b8818de9SDmitry Osipenko dev_err(dev, "failed to add OPP table: %d\n", err);
158b8818de9SDmitry Osipenko
159b8818de9SDmitry Osipenko return err;
160b8818de9SDmitry Osipenko }
161b8818de9SDmitry Osipenko
162b8818de9SDmitry Osipenko if (params->init_state) {
163b8818de9SDmitry Osipenko err = tegra_core_dev_init_opp_state(dev);
164b8818de9SDmitry Osipenko if (err)
165b8818de9SDmitry Osipenko return err;
166b8818de9SDmitry Osipenko }
167b8818de9SDmitry Osipenko
168b8818de9SDmitry Osipenko return 0;
169b8818de9SDmitry Osipenko }
170b8818de9SDmitry Osipenko EXPORT_SYMBOL_GPL(devm_tegra_core_dev_init_opp_table);
171