1*c89105c9SRoy Pledge /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2*c89105c9SRoy Pledge /* 3*c89105c9SRoy Pledge * Copyright 2013-2016 Freescale Semiconductor Inc. 4*c89105c9SRoy Pledge * Copyright 2016 NXP 5*c89105c9SRoy Pledge * 6*c89105c9SRoy Pledge */ 7*c89105c9SRoy Pledge #ifndef _FSL_DPIO_CMD_H 8*c89105c9SRoy Pledge #define _FSL_DPIO_CMD_H 9*c89105c9SRoy Pledge 10*c89105c9SRoy Pledge /* DPIO Version */ 11*c89105c9SRoy Pledge #define DPIO_VER_MAJOR 4 12*c89105c9SRoy Pledge #define DPIO_VER_MINOR 2 13*c89105c9SRoy Pledge 14*c89105c9SRoy Pledge /* Command Versioning */ 15*c89105c9SRoy Pledge 16*c89105c9SRoy Pledge #define DPIO_CMD_ID_OFFSET 4 17*c89105c9SRoy Pledge #define DPIO_CMD_BASE_VERSION 1 18*c89105c9SRoy Pledge 19*c89105c9SRoy Pledge #define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION) 20*c89105c9SRoy Pledge 21*c89105c9SRoy Pledge /* Command IDs */ 22*c89105c9SRoy Pledge #define DPIO_CMDID_CLOSE DPIO_CMD(0x800) 23*c89105c9SRoy Pledge #define DPIO_CMDID_OPEN DPIO_CMD(0x803) 24*c89105c9SRoy Pledge #define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03) 25*c89105c9SRoy Pledge #define DPIO_CMDID_ENABLE DPIO_CMD(0x002) 26*c89105c9SRoy Pledge #define DPIO_CMDID_DISABLE DPIO_CMD(0x003) 27*c89105c9SRoy Pledge #define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004) 28*c89105c9SRoy Pledge 29*c89105c9SRoy Pledge struct dpio_cmd_open { 30*c89105c9SRoy Pledge __le32 dpio_id; 31*c89105c9SRoy Pledge }; 32*c89105c9SRoy Pledge 33*c89105c9SRoy Pledge #define DPIO_CHANNEL_MODE_MASK 0x3 34*c89105c9SRoy Pledge 35*c89105c9SRoy Pledge struct dpio_rsp_get_attr { 36*c89105c9SRoy Pledge /* cmd word 0 */ 37*c89105c9SRoy Pledge __le32 id; 38*c89105c9SRoy Pledge __le16 qbman_portal_id; 39*c89105c9SRoy Pledge u8 num_priorities; 40*c89105c9SRoy Pledge u8 channel_mode; 41*c89105c9SRoy Pledge /* cmd word 1 */ 42*c89105c9SRoy Pledge __le64 qbman_portal_ce_addr; 43*c89105c9SRoy Pledge /* cmd word 2 */ 44*c89105c9SRoy Pledge __le64 qbman_portal_ci_addr; 45*c89105c9SRoy Pledge /* cmd word 3 */ 46*c89105c9SRoy Pledge __le32 qbman_version; 47*c89105c9SRoy Pledge }; 48*c89105c9SRoy Pledge 49*c89105c9SRoy Pledge #endif /* _FSL_DPIO_CMD_H */ 50