1c89105c9SRoy Pledge /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */ 2c89105c9SRoy Pledge /* 3c89105c9SRoy Pledge * Copyright 2013-2016 Freescale Semiconductor Inc. 4c89105c9SRoy Pledge * Copyright 2016 NXP 5c89105c9SRoy Pledge * 6c89105c9SRoy Pledge */ 7c89105c9SRoy Pledge #ifndef _FSL_DPIO_CMD_H 8c89105c9SRoy Pledge #define _FSL_DPIO_CMD_H 9c89105c9SRoy Pledge 10c89105c9SRoy Pledge /* DPIO Version */ 11c89105c9SRoy Pledge #define DPIO_VER_MAJOR 4 12c89105c9SRoy Pledge #define DPIO_VER_MINOR 2 13c89105c9SRoy Pledge 14c89105c9SRoy Pledge /* Command Versioning */ 15c89105c9SRoy Pledge 16c89105c9SRoy Pledge #define DPIO_CMD_ID_OFFSET 4 17c89105c9SRoy Pledge #define DPIO_CMD_BASE_VERSION 1 18c89105c9SRoy Pledge 19c89105c9SRoy Pledge #define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION) 20c89105c9SRoy Pledge 21c89105c9SRoy Pledge /* Command IDs */ 22c89105c9SRoy Pledge #define DPIO_CMDID_CLOSE DPIO_CMD(0x800) 23c89105c9SRoy Pledge #define DPIO_CMDID_OPEN DPIO_CMD(0x803) 24c89105c9SRoy Pledge #define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03) 25c89105c9SRoy Pledge #define DPIO_CMDID_ENABLE DPIO_CMD(0x002) 26c89105c9SRoy Pledge #define DPIO_CMDID_DISABLE DPIO_CMD(0x003) 27c89105c9SRoy Pledge #define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004) 28*11c8bac9SRoy Pledge #define DPIO_CMDID_RESET DPIO_CMD(0x005) 29c89105c9SRoy Pledge 30c89105c9SRoy Pledge struct dpio_cmd_open { 31c89105c9SRoy Pledge __le32 dpio_id; 32c89105c9SRoy Pledge }; 33c89105c9SRoy Pledge 34c89105c9SRoy Pledge #define DPIO_CHANNEL_MODE_MASK 0x3 35c89105c9SRoy Pledge 36c89105c9SRoy Pledge struct dpio_rsp_get_attr { 37c89105c9SRoy Pledge /* cmd word 0 */ 38c89105c9SRoy Pledge __le32 id; 39c89105c9SRoy Pledge __le16 qbman_portal_id; 40c89105c9SRoy Pledge u8 num_priorities; 41c89105c9SRoy Pledge u8 channel_mode; 42c89105c9SRoy Pledge /* cmd word 1 */ 43c89105c9SRoy Pledge __le64 qbman_portal_ce_addr; 44c89105c9SRoy Pledge /* cmd word 2 */ 45c89105c9SRoy Pledge __le64 qbman_portal_ci_addr; 46c89105c9SRoy Pledge /* cmd word 3 */ 47c89105c9SRoy Pledge __le32 qbman_version; 48c89105c9SRoy Pledge }; 49c89105c9SRoy Pledge 50c89105c9SRoy Pledge #endif /* _FSL_DPIO_CMD_H */ 51