1 /* 2 * QLogic iSCSI HBA Driver 3 * Copyright (c) 2003-2010 QLogic Corporation 4 * 5 * See LICENSE.qla4xxx for copyright and licensing details. 6 */ 7 #include <linux/delay.h> 8 #include <linux/io.h> 9 #include <linux/pci.h> 10 #include "ql4_def.h" 11 #include "ql4_glbl.h" 12 13 #include <asm-generic/io-64-nonatomic-lo-hi.h> 14 15 #define MASK(n) DMA_BIT_MASK(n) 16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff)) 17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff)) 18 #define MS_WIN(addr) (addr & 0x0ffc0000) 19 #define QLA82XX_PCI_MN_2M (0) 20 #define QLA82XX_PCI_MS_2M (0x80000) 21 #define QLA82XX_PCI_OCM0_2M (0xc0000) 22 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) 23 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) 24 25 /* CRB window related */ 26 #define CRB_BLK(off) ((off >> 20) & 0x3f) 27 #define CRB_SUBBLK(off) ((off >> 16) & 0xf) 28 #define CRB_WINDOW_2M (0x130060) 29 #define CRB_HI(off) ((qla4_8xxx_crb_hub_agt[CRB_BLK(off)] << 20) | \ 30 ((off) & 0xf0000)) 31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) 32 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) 33 #define CRB_INDIRECT_2M (0x1e0000UL) 34 35 static inline void __iomem * 36 qla4_8xxx_pci_base_offsetfset(struct scsi_qla_host *ha, unsigned long off) 37 { 38 if ((off < ha->first_page_group_end) && 39 (off >= ha->first_page_group_start)) 40 return (void __iomem *)(ha->nx_pcibase + off); 41 42 return NULL; 43 } 44 45 #define MAX_CRB_XFORM 60 46 static unsigned long crb_addr_xform[MAX_CRB_XFORM]; 47 static int qla4_8xxx_crb_table_initialized; 48 49 #define qla4_8xxx_crb_addr_transform(name) \ 50 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ 51 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) 52 static void 53 qla4_8xxx_crb_addr_transform_setup(void) 54 { 55 qla4_8xxx_crb_addr_transform(XDMA); 56 qla4_8xxx_crb_addr_transform(TIMR); 57 qla4_8xxx_crb_addr_transform(SRE); 58 qla4_8xxx_crb_addr_transform(SQN3); 59 qla4_8xxx_crb_addr_transform(SQN2); 60 qla4_8xxx_crb_addr_transform(SQN1); 61 qla4_8xxx_crb_addr_transform(SQN0); 62 qla4_8xxx_crb_addr_transform(SQS3); 63 qla4_8xxx_crb_addr_transform(SQS2); 64 qla4_8xxx_crb_addr_transform(SQS1); 65 qla4_8xxx_crb_addr_transform(SQS0); 66 qla4_8xxx_crb_addr_transform(RPMX7); 67 qla4_8xxx_crb_addr_transform(RPMX6); 68 qla4_8xxx_crb_addr_transform(RPMX5); 69 qla4_8xxx_crb_addr_transform(RPMX4); 70 qla4_8xxx_crb_addr_transform(RPMX3); 71 qla4_8xxx_crb_addr_transform(RPMX2); 72 qla4_8xxx_crb_addr_transform(RPMX1); 73 qla4_8xxx_crb_addr_transform(RPMX0); 74 qla4_8xxx_crb_addr_transform(ROMUSB); 75 qla4_8xxx_crb_addr_transform(SN); 76 qla4_8xxx_crb_addr_transform(QMN); 77 qla4_8xxx_crb_addr_transform(QMS); 78 qla4_8xxx_crb_addr_transform(PGNI); 79 qla4_8xxx_crb_addr_transform(PGND); 80 qla4_8xxx_crb_addr_transform(PGN3); 81 qla4_8xxx_crb_addr_transform(PGN2); 82 qla4_8xxx_crb_addr_transform(PGN1); 83 qla4_8xxx_crb_addr_transform(PGN0); 84 qla4_8xxx_crb_addr_transform(PGSI); 85 qla4_8xxx_crb_addr_transform(PGSD); 86 qla4_8xxx_crb_addr_transform(PGS3); 87 qla4_8xxx_crb_addr_transform(PGS2); 88 qla4_8xxx_crb_addr_transform(PGS1); 89 qla4_8xxx_crb_addr_transform(PGS0); 90 qla4_8xxx_crb_addr_transform(PS); 91 qla4_8xxx_crb_addr_transform(PH); 92 qla4_8xxx_crb_addr_transform(NIU); 93 qla4_8xxx_crb_addr_transform(I2Q); 94 qla4_8xxx_crb_addr_transform(EG); 95 qla4_8xxx_crb_addr_transform(MN); 96 qla4_8xxx_crb_addr_transform(MS); 97 qla4_8xxx_crb_addr_transform(CAS2); 98 qla4_8xxx_crb_addr_transform(CAS1); 99 qla4_8xxx_crb_addr_transform(CAS0); 100 qla4_8xxx_crb_addr_transform(CAM); 101 qla4_8xxx_crb_addr_transform(C2C1); 102 qla4_8xxx_crb_addr_transform(C2C0); 103 qla4_8xxx_crb_addr_transform(SMB); 104 qla4_8xxx_crb_addr_transform(OCM0); 105 qla4_8xxx_crb_addr_transform(I2C0); 106 107 qla4_8xxx_crb_table_initialized = 1; 108 } 109 110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = { 111 {{{0, 0, 0, 0} } }, /* 0: PCI */ 112 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */ 113 {1, 0x0110000, 0x0120000, 0x130000}, 114 {1, 0x0120000, 0x0122000, 0x124000}, 115 {1, 0x0130000, 0x0132000, 0x126000}, 116 {1, 0x0140000, 0x0142000, 0x128000}, 117 {1, 0x0150000, 0x0152000, 0x12a000}, 118 {1, 0x0160000, 0x0170000, 0x110000}, 119 {1, 0x0170000, 0x0172000, 0x12e000}, 120 {0, 0x0000000, 0x0000000, 0x000000}, 121 {0, 0x0000000, 0x0000000, 0x000000}, 122 {0, 0x0000000, 0x0000000, 0x000000}, 123 {0, 0x0000000, 0x0000000, 0x000000}, 124 {0, 0x0000000, 0x0000000, 0x000000}, 125 {0, 0x0000000, 0x0000000, 0x000000}, 126 {1, 0x01e0000, 0x01e0800, 0x122000}, 127 {0, 0x0000000, 0x0000000, 0x000000} } }, 128 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */ 129 {{{0, 0, 0, 0} } }, /* 3: */ 130 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */ 131 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */ 132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */ 133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */ 134 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */ 135 {0, 0x0000000, 0x0000000, 0x000000}, 136 {0, 0x0000000, 0x0000000, 0x000000}, 137 {0, 0x0000000, 0x0000000, 0x000000}, 138 {0, 0x0000000, 0x0000000, 0x000000}, 139 {0, 0x0000000, 0x0000000, 0x000000}, 140 {0, 0x0000000, 0x0000000, 0x000000}, 141 {0, 0x0000000, 0x0000000, 0x000000}, 142 {0, 0x0000000, 0x0000000, 0x000000}, 143 {0, 0x0000000, 0x0000000, 0x000000}, 144 {0, 0x0000000, 0x0000000, 0x000000}, 145 {0, 0x0000000, 0x0000000, 0x000000}, 146 {0, 0x0000000, 0x0000000, 0x000000}, 147 {0, 0x0000000, 0x0000000, 0x000000}, 148 {0, 0x0000000, 0x0000000, 0x000000}, 149 {1, 0x08f0000, 0x08f2000, 0x172000} } }, 150 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/ 151 {0, 0x0000000, 0x0000000, 0x000000}, 152 {0, 0x0000000, 0x0000000, 0x000000}, 153 {0, 0x0000000, 0x0000000, 0x000000}, 154 {0, 0x0000000, 0x0000000, 0x000000}, 155 {0, 0x0000000, 0x0000000, 0x000000}, 156 {0, 0x0000000, 0x0000000, 0x000000}, 157 {0, 0x0000000, 0x0000000, 0x000000}, 158 {0, 0x0000000, 0x0000000, 0x000000}, 159 {0, 0x0000000, 0x0000000, 0x000000}, 160 {0, 0x0000000, 0x0000000, 0x000000}, 161 {0, 0x0000000, 0x0000000, 0x000000}, 162 {0, 0x0000000, 0x0000000, 0x000000}, 163 {0, 0x0000000, 0x0000000, 0x000000}, 164 {0, 0x0000000, 0x0000000, 0x000000}, 165 {1, 0x09f0000, 0x09f2000, 0x176000} } }, 166 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/ 167 {0, 0x0000000, 0x0000000, 0x000000}, 168 {0, 0x0000000, 0x0000000, 0x000000}, 169 {0, 0x0000000, 0x0000000, 0x000000}, 170 {0, 0x0000000, 0x0000000, 0x000000}, 171 {0, 0x0000000, 0x0000000, 0x000000}, 172 {0, 0x0000000, 0x0000000, 0x000000}, 173 {0, 0x0000000, 0x0000000, 0x000000}, 174 {0, 0x0000000, 0x0000000, 0x000000}, 175 {0, 0x0000000, 0x0000000, 0x000000}, 176 {0, 0x0000000, 0x0000000, 0x000000}, 177 {0, 0x0000000, 0x0000000, 0x000000}, 178 {0, 0x0000000, 0x0000000, 0x000000}, 179 {0, 0x0000000, 0x0000000, 0x000000}, 180 {0, 0x0000000, 0x0000000, 0x000000}, 181 {1, 0x0af0000, 0x0af2000, 0x17a000} } }, 182 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/ 183 {0, 0x0000000, 0x0000000, 0x000000}, 184 {0, 0x0000000, 0x0000000, 0x000000}, 185 {0, 0x0000000, 0x0000000, 0x000000}, 186 {0, 0x0000000, 0x0000000, 0x000000}, 187 {0, 0x0000000, 0x0000000, 0x000000}, 188 {0, 0x0000000, 0x0000000, 0x000000}, 189 {0, 0x0000000, 0x0000000, 0x000000}, 190 {0, 0x0000000, 0x0000000, 0x000000}, 191 {0, 0x0000000, 0x0000000, 0x000000}, 192 {0, 0x0000000, 0x0000000, 0x000000}, 193 {0, 0x0000000, 0x0000000, 0x000000}, 194 {0, 0x0000000, 0x0000000, 0x000000}, 195 {0, 0x0000000, 0x0000000, 0x000000}, 196 {0, 0x0000000, 0x0000000, 0x000000}, 197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, 198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */ 199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */ 200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */ 201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */ 202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */ 203 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */ 204 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */ 205 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */ 206 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */ 207 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */ 208 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */ 209 {{{0, 0, 0, 0} } }, /* 23: */ 210 {{{0, 0, 0, 0} } }, /* 24: */ 211 {{{0, 0, 0, 0} } }, /* 25: */ 212 {{{0, 0, 0, 0} } }, /* 26: */ 213 {{{0, 0, 0, 0} } }, /* 27: */ 214 {{{0, 0, 0, 0} } }, /* 28: */ 215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */ 216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */ 217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */ 218 {{{0} } }, /* 32: PCI */ 219 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */ 220 {1, 0x2110000, 0x2120000, 0x130000}, 221 {1, 0x2120000, 0x2122000, 0x124000}, 222 {1, 0x2130000, 0x2132000, 0x126000}, 223 {1, 0x2140000, 0x2142000, 0x128000}, 224 {1, 0x2150000, 0x2152000, 0x12a000}, 225 {1, 0x2160000, 0x2170000, 0x110000}, 226 {1, 0x2170000, 0x2172000, 0x12e000}, 227 {0, 0x0000000, 0x0000000, 0x000000}, 228 {0, 0x0000000, 0x0000000, 0x000000}, 229 {0, 0x0000000, 0x0000000, 0x000000}, 230 {0, 0x0000000, 0x0000000, 0x000000}, 231 {0, 0x0000000, 0x0000000, 0x000000}, 232 {0, 0x0000000, 0x0000000, 0x000000}, 233 {0, 0x0000000, 0x0000000, 0x000000}, 234 {0, 0x0000000, 0x0000000, 0x000000} } }, 235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */ 236 {{{0} } }, /* 35: */ 237 {{{0} } }, /* 36: */ 238 {{{0} } }, /* 37: */ 239 {{{0} } }, /* 38: */ 240 {{{0} } }, /* 39: */ 241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */ 242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */ 243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */ 244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */ 245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */ 246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */ 247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */ 248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */ 249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */ 250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */ 251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */ 252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */ 253 {{{0} } }, /* 52: */ 254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */ 255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */ 256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */ 257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */ 258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */ 259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */ 260 {{{0} } }, /* 59: I2C0 */ 261 {{{0} } }, /* 60: I2C1 */ 262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },/* 61: LPC */ 263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */ 264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */ 265 }; 266 267 /* 268 * top 12 bits of crb internal address (hub, agent) 269 */ 270 static unsigned qla4_8xxx_crb_hub_agt[64] = { 271 0, 272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN, 274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS, 275 0, 276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, 277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, 278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, 279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, 280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, 281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, 282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, 283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, 287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, 289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, 290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, 291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, 292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, 293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, 294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, 295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, 296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, 297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, 298 0, 299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, 300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN, 301 0, 302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG, 303 0, 304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS, 305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, 306 0, 307 0, 308 0, 309 0, 310 0, 311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, 312 0, 313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, 314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, 315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, 316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, 317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, 318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, 319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, 320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, 321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, 322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, 323 0, 324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, 325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, 326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, 327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, 328 0, 329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, 330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, 331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, 332 0, 333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, 334 0, 335 }; 336 337 /* Device states */ 338 static char *qdev_state[] = { 339 "Unknown", 340 "Cold", 341 "Initializing", 342 "Ready", 343 "Need Reset", 344 "Need Quiescent", 345 "Failed", 346 "Quiescent", 347 }; 348 349 /* 350 * In: 'off' is offset from CRB space in 128M pci map 351 * Out: 'off' is 2M pci map addr 352 * side effect: lock crb window 353 */ 354 static void 355 qla4_8xxx_pci_set_crbwindow_2M(struct scsi_qla_host *ha, ulong *off) 356 { 357 u32 win_read; 358 359 ha->crb_win = CRB_HI(*off); 360 writel(ha->crb_win, 361 (void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 362 363 /* Read back value to make sure write has gone through before trying 364 * to use it. */ 365 win_read = readl((void __iomem *)(CRB_WINDOW_2M + ha->nx_pcibase)); 366 if (win_read != ha->crb_win) { 367 DEBUG2(ql4_printk(KERN_INFO, ha, 368 "%s: Written crbwin (0x%x) != Read crbwin (0x%x)," 369 " off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); 370 } 371 *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; 372 } 373 374 void 375 qla4_8xxx_wr_32(struct scsi_qla_host *ha, ulong off, u32 data) 376 { 377 unsigned long flags = 0; 378 int rv; 379 380 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 381 382 BUG_ON(rv == -1); 383 384 if (rv == 1) { 385 write_lock_irqsave(&ha->hw_lock, flags); 386 qla4_8xxx_crb_win_lock(ha); 387 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 388 } 389 390 writel(data, (void __iomem *)off); 391 392 if (rv == 1) { 393 qla4_8xxx_crb_win_unlock(ha); 394 write_unlock_irqrestore(&ha->hw_lock, flags); 395 } 396 } 397 398 int 399 qla4_8xxx_rd_32(struct scsi_qla_host *ha, ulong off) 400 { 401 unsigned long flags = 0; 402 int rv; 403 u32 data; 404 405 rv = qla4_8xxx_pci_get_crb_addr_2M(ha, &off); 406 407 BUG_ON(rv == -1); 408 409 if (rv == 1) { 410 write_lock_irqsave(&ha->hw_lock, flags); 411 qla4_8xxx_crb_win_lock(ha); 412 qla4_8xxx_pci_set_crbwindow_2M(ha, &off); 413 } 414 data = readl((void __iomem *)off); 415 416 if (rv == 1) { 417 qla4_8xxx_crb_win_unlock(ha); 418 write_unlock_irqrestore(&ha->hw_lock, flags); 419 } 420 return data; 421 } 422 423 #define CRB_WIN_LOCK_TIMEOUT 100000000 424 425 int qla4_8xxx_crb_win_lock(struct scsi_qla_host *ha) 426 { 427 int i; 428 int done = 0, timeout = 0; 429 430 while (!done) { 431 /* acquire semaphore3 from PCI HW block */ 432 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); 433 if (done == 1) 434 break; 435 if (timeout >= CRB_WIN_LOCK_TIMEOUT) 436 return -1; 437 438 timeout++; 439 440 /* Yield CPU */ 441 if (!in_interrupt()) 442 schedule(); 443 else { 444 for (i = 0; i < 20; i++) 445 cpu_relax(); /*This a nop instr on i386*/ 446 } 447 } 448 qla4_8xxx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->func_num); 449 return 0; 450 } 451 452 void qla4_8xxx_crb_win_unlock(struct scsi_qla_host *ha) 453 { 454 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); 455 } 456 457 #define IDC_LOCK_TIMEOUT 100000000 458 459 /** 460 * qla4_8xxx_idc_lock - hw_lock 461 * @ha: pointer to adapter structure 462 * 463 * General purpose lock used to synchronize access to 464 * CRB_DEV_STATE, CRB_DEV_REF_COUNT, etc. 465 **/ 466 int qla4_8xxx_idc_lock(struct scsi_qla_host *ha) 467 { 468 int i; 469 int done = 0, timeout = 0; 470 471 while (!done) { 472 /* acquire semaphore5 from PCI HW block */ 473 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); 474 if (done == 1) 475 break; 476 if (timeout >= IDC_LOCK_TIMEOUT) 477 return -1; 478 479 timeout++; 480 481 /* Yield CPU */ 482 if (!in_interrupt()) 483 schedule(); 484 else { 485 for (i = 0; i < 20; i++) 486 cpu_relax(); /*This a nop instr on i386*/ 487 } 488 } 489 return 0; 490 } 491 492 void qla4_8xxx_idc_unlock(struct scsi_qla_host *ha) 493 { 494 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); 495 } 496 497 int 498 qla4_8xxx_pci_get_crb_addr_2M(struct scsi_qla_host *ha, ulong *off) 499 { 500 struct crb_128M_2M_sub_block_map *m; 501 502 if (*off >= QLA82XX_CRB_MAX) 503 return -1; 504 505 if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { 506 *off = (*off - QLA82XX_PCI_CAMQM) + 507 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; 508 return 0; 509 } 510 511 if (*off < QLA82XX_PCI_CRBSPACE) 512 return -1; 513 514 *off -= QLA82XX_PCI_CRBSPACE; 515 /* 516 * Try direct map 517 */ 518 519 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; 520 521 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { 522 *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; 523 return 0; 524 } 525 526 /* 527 * Not in direct map, use crb window 528 */ 529 return 1; 530 } 531 532 /* PCI Windowing for DDR regions. */ 533 #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ 534 (((addr) <= (high)) && ((addr) >= (low))) 535 536 /* 537 * check memory access boundary. 538 * used by test agent. support ddr access only for now 539 */ 540 static unsigned long 541 qla4_8xxx_pci_mem_bound_check(struct scsi_qla_host *ha, 542 unsigned long long addr, int size) 543 { 544 if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 545 QLA82XX_ADDR_DDR_NET_MAX) || 546 !QLA82XX_ADDR_IN_RANGE(addr + size - 1, 547 QLA82XX_ADDR_DDR_NET, QLA82XX_ADDR_DDR_NET_MAX) || 548 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) { 549 return 0; 550 } 551 return 1; 552 } 553 554 static int qla4_8xxx_pci_set_window_warning_count; 555 556 static unsigned long 557 qla4_8xxx_pci_set_window(struct scsi_qla_host *ha, unsigned long long addr) 558 { 559 int window; 560 u32 win_read; 561 562 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 563 QLA82XX_ADDR_DDR_NET_MAX)) { 564 /* DDR network side */ 565 window = MN_WIN(addr); 566 ha->ddr_mn_window = window; 567 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 568 QLA82XX_PCI_CRBSPACE, window); 569 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 570 QLA82XX_PCI_CRBSPACE); 571 if ((win_read << 17) != window) { 572 ql4_printk(KERN_WARNING, ha, 573 "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", 574 __func__, window, win_read); 575 } 576 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; 577 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 578 QLA82XX_ADDR_OCM0_MAX)) { 579 unsigned int temp1; 580 /* if bits 19:18&17:11 are on */ 581 if ((addr & 0x00ff800) == 0xff800) { 582 printk("%s: QM access not handled.\n", __func__); 583 addr = -1UL; 584 } 585 586 window = OCM_WIN(addr); 587 ha->ddr_mn_window = window; 588 qla4_8xxx_wr_32(ha, ha->mn_win_crb | 589 QLA82XX_PCI_CRBSPACE, window); 590 win_read = qla4_8xxx_rd_32(ha, ha->mn_win_crb | 591 QLA82XX_PCI_CRBSPACE); 592 temp1 = ((window & 0x1FF) << 7) | 593 ((window & 0x0FFFE0000) >> 17); 594 if (win_read != temp1) { 595 printk("%s: Written OCMwin (0x%x) != Read" 596 " OCMwin (0x%x)\n", __func__, temp1, win_read); 597 } 598 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; 599 600 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 601 QLA82XX_P3_ADDR_QDR_NET_MAX)) { 602 /* QDR network side */ 603 window = MS_WIN(addr); 604 ha->qdr_sn_window = window; 605 qla4_8xxx_wr_32(ha, ha->ms_win_crb | 606 QLA82XX_PCI_CRBSPACE, window); 607 win_read = qla4_8xxx_rd_32(ha, 608 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); 609 if (win_read != window) { 610 printk("%s: Written MSwin (0x%x) != Read " 611 "MSwin (0x%x)\n", __func__, window, win_read); 612 } 613 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; 614 615 } else { 616 /* 617 * peg gdb frequently accesses memory that doesn't exist, 618 * this limits the chit chat so debugging isn't slowed down. 619 */ 620 if ((qla4_8xxx_pci_set_window_warning_count++ < 8) || 621 (qla4_8xxx_pci_set_window_warning_count%64 == 0)) { 622 printk("%s: Warning:%s Unknown address range!\n", 623 __func__, DRIVER_NAME); 624 } 625 addr = -1UL; 626 } 627 return addr; 628 } 629 630 /* check if address is in the same windows as the previous access */ 631 static int qla4_8xxx_pci_is_same_window(struct scsi_qla_host *ha, 632 unsigned long long addr) 633 { 634 int window; 635 unsigned long long qdr_max; 636 637 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; 638 639 if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, 640 QLA82XX_ADDR_DDR_NET_MAX)) { 641 /* DDR network side */ 642 BUG(); /* MN access can not come here */ 643 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, 644 QLA82XX_ADDR_OCM0_MAX)) { 645 return 1; 646 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, 647 QLA82XX_ADDR_OCM1_MAX)) { 648 return 1; 649 } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, 650 qdr_max)) { 651 /* QDR network side */ 652 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; 653 if (ha->qdr_sn_window == window) 654 return 1; 655 } 656 657 return 0; 658 } 659 660 static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha, 661 u64 off, void *data, int size) 662 { 663 unsigned long flags; 664 void __iomem *addr; 665 int ret = 0; 666 u64 start; 667 void __iomem *mem_ptr = NULL; 668 unsigned long mem_base; 669 unsigned long mem_page; 670 671 write_lock_irqsave(&ha->hw_lock, flags); 672 673 /* 674 * If attempting to access unknown address or straddle hw windows, 675 * do not access. 676 */ 677 start = qla4_8xxx_pci_set_window(ha, off); 678 if ((start == -1UL) || 679 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 680 write_unlock_irqrestore(&ha->hw_lock, flags); 681 printk(KERN_ERR"%s out of bound pci memory access. " 682 "offset is 0x%llx\n", DRIVER_NAME, off); 683 return -1; 684 } 685 686 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 687 if (!addr) { 688 write_unlock_irqrestore(&ha->hw_lock, flags); 689 mem_base = pci_resource_start(ha->pdev, 0); 690 mem_page = start & PAGE_MASK; 691 /* Map two pages whenever user tries to access addresses in two 692 consecutive pages. 693 */ 694 if (mem_page != ((start + size - 1) & PAGE_MASK)) 695 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); 696 else 697 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 698 699 if (mem_ptr == NULL) { 700 *(u8 *)data = 0; 701 return -1; 702 } 703 addr = mem_ptr; 704 addr += start & (PAGE_SIZE - 1); 705 write_lock_irqsave(&ha->hw_lock, flags); 706 } 707 708 switch (size) { 709 case 1: 710 *(u8 *)data = readb(addr); 711 break; 712 case 2: 713 *(u16 *)data = readw(addr); 714 break; 715 case 4: 716 *(u32 *)data = readl(addr); 717 break; 718 case 8: 719 *(u64 *)data = readq(addr); 720 break; 721 default: 722 ret = -1; 723 break; 724 } 725 write_unlock_irqrestore(&ha->hw_lock, flags); 726 727 if (mem_ptr) 728 iounmap(mem_ptr); 729 return ret; 730 } 731 732 static int 733 qla4_8xxx_pci_mem_write_direct(struct scsi_qla_host *ha, u64 off, 734 void *data, int size) 735 { 736 unsigned long flags; 737 void __iomem *addr; 738 int ret = 0; 739 u64 start; 740 void __iomem *mem_ptr = NULL; 741 unsigned long mem_base; 742 unsigned long mem_page; 743 744 write_lock_irqsave(&ha->hw_lock, flags); 745 746 /* 747 * If attempting to access unknown address or straddle hw windows, 748 * do not access. 749 */ 750 start = qla4_8xxx_pci_set_window(ha, off); 751 if ((start == -1UL) || 752 (qla4_8xxx_pci_is_same_window(ha, off + size - 1) == 0)) { 753 write_unlock_irqrestore(&ha->hw_lock, flags); 754 printk(KERN_ERR"%s out of bound pci memory access. " 755 "offset is 0x%llx\n", DRIVER_NAME, off); 756 return -1; 757 } 758 759 addr = qla4_8xxx_pci_base_offsetfset(ha, start); 760 if (!addr) { 761 write_unlock_irqrestore(&ha->hw_lock, flags); 762 mem_base = pci_resource_start(ha->pdev, 0); 763 mem_page = start & PAGE_MASK; 764 /* Map two pages whenever user tries to access addresses in two 765 consecutive pages. 766 */ 767 if (mem_page != ((start + size - 1) & PAGE_MASK)) 768 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); 769 else 770 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); 771 if (mem_ptr == NULL) 772 return -1; 773 774 addr = mem_ptr; 775 addr += start & (PAGE_SIZE - 1); 776 write_lock_irqsave(&ha->hw_lock, flags); 777 } 778 779 switch (size) { 780 case 1: 781 writeb(*(u8 *)data, addr); 782 break; 783 case 2: 784 writew(*(u16 *)data, addr); 785 break; 786 case 4: 787 writel(*(u32 *)data, addr); 788 break; 789 case 8: 790 writeq(*(u64 *)data, addr); 791 break; 792 default: 793 ret = -1; 794 break; 795 } 796 write_unlock_irqrestore(&ha->hw_lock, flags); 797 if (mem_ptr) 798 iounmap(mem_ptr); 799 return ret; 800 } 801 802 #define MTU_FUDGE_FACTOR 100 803 804 static unsigned long 805 qla4_8xxx_decode_crb_addr(unsigned long addr) 806 { 807 int i; 808 unsigned long base_addr, offset, pci_base; 809 810 if (!qla4_8xxx_crb_table_initialized) 811 qla4_8xxx_crb_addr_transform_setup(); 812 813 pci_base = ADDR_ERROR; 814 base_addr = addr & 0xfff00000; 815 offset = addr & 0x000fffff; 816 817 for (i = 0; i < MAX_CRB_XFORM; i++) { 818 if (crb_addr_xform[i] == base_addr) { 819 pci_base = i << 20; 820 break; 821 } 822 } 823 if (pci_base == ADDR_ERROR) 824 return pci_base; 825 else 826 return pci_base + offset; 827 } 828 829 static long rom_max_timeout = 100; 830 static long qla4_8xxx_rom_lock_timeout = 100; 831 832 static int 833 qla4_8xxx_rom_lock(struct scsi_qla_host *ha) 834 { 835 int i; 836 int done = 0, timeout = 0; 837 838 while (!done) { 839 /* acquire semaphore2 from PCI HW block */ 840 841 done = qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); 842 if (done == 1) 843 break; 844 if (timeout >= qla4_8xxx_rom_lock_timeout) { 845 ql4_printk(KERN_WARNING, ha, 846 "%s: Failed to acquire rom lock", __func__); 847 return -1; 848 } 849 850 timeout++; 851 852 /* Yield CPU */ 853 if (!in_interrupt()) 854 schedule(); 855 else { 856 for (i = 0; i < 20; i++) 857 cpu_relax(); /*This a nop instr on i386*/ 858 } 859 } 860 qla4_8xxx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); 861 return 0; 862 } 863 864 static void 865 qla4_8xxx_rom_unlock(struct scsi_qla_host *ha) 866 { 867 qla4_8xxx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); 868 } 869 870 static int 871 qla4_8xxx_wait_rom_done(struct scsi_qla_host *ha) 872 { 873 long timeout = 0; 874 long done = 0 ; 875 876 while (done == 0) { 877 done = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); 878 done &= 2; 879 timeout++; 880 if (timeout >= rom_max_timeout) { 881 printk("%s: Timeout reached waiting for rom done", 882 DRIVER_NAME); 883 return -1; 884 } 885 } 886 return 0; 887 } 888 889 static int 890 qla4_8xxx_do_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 891 { 892 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); 893 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 894 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); 895 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); 896 if (qla4_8xxx_wait_rom_done(ha)) { 897 printk("%s: Error waiting for rom done\n", DRIVER_NAME); 898 return -1; 899 } 900 /* reset abyte_cnt and dummy_byte_cnt */ 901 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); 902 udelay(10); 903 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); 904 905 *valp = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); 906 return 0; 907 } 908 909 static int 910 qla4_8xxx_rom_fast_read(struct scsi_qla_host *ha, int addr, int *valp) 911 { 912 int ret, loops = 0; 913 914 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 915 udelay(100); 916 loops++; 917 } 918 if (loops >= 50000) { 919 printk("%s: qla4_8xxx_rom_lock failed\n", DRIVER_NAME); 920 return -1; 921 } 922 ret = qla4_8xxx_do_rom_fast_read(ha, addr, valp); 923 qla4_8xxx_rom_unlock(ha); 924 return ret; 925 } 926 927 /** 928 * This routine does CRB initialize sequence 929 * to put the ISP into operational state 930 **/ 931 static int 932 qla4_8xxx_pinit_from_rom(struct scsi_qla_host *ha, int verbose) 933 { 934 int addr, val; 935 int i ; 936 struct crb_addr_pair *buf; 937 unsigned long off; 938 unsigned offset, n; 939 940 struct crb_addr_pair { 941 long addr; 942 long data; 943 }; 944 945 /* Halt all the indiviual PEGs and other blocks of the ISP */ 946 qla4_8xxx_rom_lock(ha); 947 948 /* disable all I2Q */ 949 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0); 950 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0); 951 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0); 952 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0); 953 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0); 954 qla4_8xxx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0); 955 956 /* disable all niu interrupts */ 957 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff); 958 /* disable xge rx/tx */ 959 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00); 960 /* disable xg1 rx/tx */ 961 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00); 962 /* disable sideband mac */ 963 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00); 964 /* disable ap0 mac */ 965 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00); 966 /* disable ap1 mac */ 967 qla4_8xxx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00); 968 969 /* halt sre */ 970 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000); 971 qla4_8xxx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1))); 972 973 /* halt epg */ 974 qla4_8xxx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1); 975 976 /* halt timers */ 977 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0); 978 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0); 979 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0); 980 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0); 981 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0); 982 qla4_8xxx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0); 983 984 /* halt pegs */ 985 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1); 986 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1); 987 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1); 988 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1); 989 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1); 990 msleep(5); 991 992 /* big hammer */ 993 if (test_bit(DPC_RESET_HA, &ha->dpc_flags)) 994 /* don't reset CAM block on reset */ 995 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); 996 else 997 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); 998 999 /* reset ms */ 1000 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1001 val |= (1 << 1); 1002 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1003 1004 msleep(20); 1005 /* unreset ms */ 1006 val = qla4_8xxx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4); 1007 val &= ~(1 << 1); 1008 qla4_8xxx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val); 1009 msleep(20); 1010 1011 qla4_8xxx_rom_unlock(ha); 1012 1013 /* Read the signature value from the flash. 1014 * Offset 0: Contain signature (0xcafecafe) 1015 * Offset 4: Offset and number of addr/value pairs 1016 * that present in CRB initialize sequence 1017 */ 1018 if (qla4_8xxx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || 1019 qla4_8xxx_rom_fast_read(ha, 4, &n) != 0) { 1020 ql4_printk(KERN_WARNING, ha, 1021 "[ERROR] Reading crb_init area: n: %08x\n", n); 1022 return -1; 1023 } 1024 1025 /* Offset in flash = lower 16 bits 1026 * Number of enteries = upper 16 bits 1027 */ 1028 offset = n & 0xffffU; 1029 n = (n >> 16) & 0xffffU; 1030 1031 /* number of addr/value pair should not exceed 1024 enteries */ 1032 if (n >= 1024) { 1033 ql4_printk(KERN_WARNING, ha, 1034 "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", 1035 DRIVER_NAME, __func__, n); 1036 return -1; 1037 } 1038 1039 ql4_printk(KERN_INFO, ha, 1040 "%s: %d CRB init values found in ROM.\n", DRIVER_NAME, n); 1041 1042 buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); 1043 if (buf == NULL) { 1044 ql4_printk(KERN_WARNING, ha, 1045 "%s: [ERROR] Unable to malloc memory.\n", DRIVER_NAME); 1046 return -1; 1047 } 1048 1049 for (i = 0; i < n; i++) { 1050 if (qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || 1051 qla4_8xxx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 1052 0) { 1053 kfree(buf); 1054 return -1; 1055 } 1056 1057 buf[i].addr = addr; 1058 buf[i].data = val; 1059 } 1060 1061 for (i = 0; i < n; i++) { 1062 /* Translate internal CRB initialization 1063 * address to PCI bus address 1064 */ 1065 off = qla4_8xxx_decode_crb_addr((unsigned long)buf[i].addr) + 1066 QLA82XX_PCI_CRBSPACE; 1067 /* Not all CRB addr/value pair to be written, 1068 * some of them are skipped 1069 */ 1070 1071 /* skip if LS bit is set*/ 1072 if (off & 0x1) { 1073 DEBUG2(ql4_printk(KERN_WARNING, ha, 1074 "Skip CRB init replay for offset = 0x%lx\n", off)); 1075 continue; 1076 } 1077 1078 /* skipping cold reboot MAGIC */ 1079 if (off == QLA82XX_CAM_RAM(0x1fc)) 1080 continue; 1081 1082 /* do not reset PCI */ 1083 if (off == (ROMUSB_GLB + 0xbc)) 1084 continue; 1085 1086 /* skip core clock, so that firmware can increase the clock */ 1087 if (off == (ROMUSB_GLB + 0xc8)) 1088 continue; 1089 1090 /* skip the function enable register */ 1091 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) 1092 continue; 1093 1094 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) 1095 continue; 1096 1097 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) 1098 continue; 1099 1100 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) 1101 continue; 1102 1103 if (off == ADDR_ERROR) { 1104 ql4_printk(KERN_WARNING, ha, 1105 "%s: [ERROR] Unknown addr: 0x%08lx\n", 1106 DRIVER_NAME, buf[i].addr); 1107 continue; 1108 } 1109 1110 qla4_8xxx_wr_32(ha, off, buf[i].data); 1111 1112 /* ISP requires much bigger delay to settle down, 1113 * else crb_window returns 0xffffffff 1114 */ 1115 if (off == QLA82XX_ROMUSB_GLB_SW_RESET) 1116 msleep(1000); 1117 1118 /* ISP requires millisec delay between 1119 * successive CRB register updation 1120 */ 1121 msleep(1); 1122 } 1123 1124 kfree(buf); 1125 1126 /* Resetting the data and instruction cache */ 1127 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); 1128 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); 1129 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); 1130 1131 /* Clear all protocol processing engines */ 1132 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); 1133 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); 1134 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); 1135 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); 1136 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); 1137 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); 1138 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); 1139 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); 1140 1141 return 0; 1142 } 1143 1144 static int 1145 qla4_8xxx_load_from_flash(struct scsi_qla_host *ha, uint32_t image_start) 1146 { 1147 int i, rval = 0; 1148 long size = 0; 1149 long flashaddr, memaddr; 1150 u64 data; 1151 u32 high, low; 1152 1153 flashaddr = memaddr = ha->hw.flt_region_bootload; 1154 size = (image_start - flashaddr) / 8; 1155 1156 DEBUG2(printk("scsi%ld: %s: bootldr=0x%lx, fw_image=0x%x\n", 1157 ha->host_no, __func__, flashaddr, image_start)); 1158 1159 for (i = 0; i < size; i++) { 1160 if ((qla4_8xxx_rom_fast_read(ha, flashaddr, (int *)&low)) || 1161 (qla4_8xxx_rom_fast_read(ha, flashaddr + 4, 1162 (int *)&high))) { 1163 rval = -1; 1164 goto exit_load_from_flash; 1165 } 1166 data = ((u64)high << 32) | low ; 1167 rval = qla4_8xxx_pci_mem_write_2M(ha, memaddr, &data, 8); 1168 if (rval) 1169 goto exit_load_from_flash; 1170 1171 flashaddr += 8; 1172 memaddr += 8; 1173 1174 if (i % 0x1000 == 0) 1175 msleep(1); 1176 1177 } 1178 1179 udelay(100); 1180 1181 read_lock(&ha->hw_lock); 1182 qla4_8xxx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); 1183 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); 1184 read_unlock(&ha->hw_lock); 1185 1186 exit_load_from_flash: 1187 return rval; 1188 } 1189 1190 static int qla4_8xxx_load_fw(struct scsi_qla_host *ha, uint32_t image_start) 1191 { 1192 u32 rst; 1193 1194 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1195 if (qla4_8xxx_pinit_from_rom(ha, 0) != QLA_SUCCESS) { 1196 printk(KERN_WARNING "%s: Error during CRB Initialization\n", 1197 __func__); 1198 return QLA_ERROR; 1199 } 1200 1201 udelay(500); 1202 1203 /* at this point, QM is in reset. This could be a problem if there are 1204 * incoming d* transition queue messages. QM/PCIE could wedge. 1205 * To get around this, QM is brought out of reset. 1206 */ 1207 1208 rst = qla4_8xxx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); 1209 /* unreset qm */ 1210 rst &= ~(1 << 28); 1211 qla4_8xxx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); 1212 1213 if (qla4_8xxx_load_from_flash(ha, image_start)) { 1214 printk("%s: Error trying to load fw from flash!\n", __func__); 1215 return QLA_ERROR; 1216 } 1217 1218 return QLA_SUCCESS; 1219 } 1220 1221 int 1222 qla4_8xxx_pci_mem_read_2M(struct scsi_qla_host *ha, 1223 u64 off, void *data, int size) 1224 { 1225 int i, j = 0, k, start, end, loop, sz[2], off0[2]; 1226 int shift_amount; 1227 uint32_t temp; 1228 uint64_t off8, val, mem_crb, word[2] = {0, 0}; 1229 1230 /* 1231 * If not MN, go check for MS or invalid. 1232 */ 1233 1234 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1235 mem_crb = QLA82XX_CRB_QDR_NET; 1236 else { 1237 mem_crb = QLA82XX_CRB_DDR_NET; 1238 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1239 return qla4_8xxx_pci_mem_read_direct(ha, 1240 off, data, size); 1241 } 1242 1243 1244 off8 = off & 0xfffffff0; 1245 off0[0] = off & 0xf; 1246 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); 1247 shift_amount = 4; 1248 1249 loop = ((off0[0] + size - 1) >> shift_amount) + 1; 1250 off0[1] = 0; 1251 sz[1] = size - sz[0]; 1252 1253 for (i = 0; i < loop; i++) { 1254 temp = off8 + (i << shift_amount); 1255 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); 1256 temp = 0; 1257 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); 1258 temp = MIU_TA_CTL_ENABLE; 1259 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1260 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; 1261 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); 1262 1263 for (j = 0; j < MAX_CTL_CHECK; j++) { 1264 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1265 if ((temp & MIU_TA_CTL_BUSY) == 0) 1266 break; 1267 } 1268 1269 if (j >= MAX_CTL_CHECK) { 1270 if (printk_ratelimit()) 1271 ql4_printk(KERN_ERR, ha, 1272 "failed to read through agent\n"); 1273 break; 1274 } 1275 1276 start = off0[i] >> 2; 1277 end = (off0[i] + sz[i] - 1) >> 2; 1278 for (k = start; k <= end; k++) { 1279 temp = qla4_8xxx_rd_32(ha, 1280 mem_crb + MIU_TEST_AGT_RDDATA(k)); 1281 word[i] |= ((uint64_t)temp << (32 * (k & 1))); 1282 } 1283 } 1284 1285 if (j >= MAX_CTL_CHECK) 1286 return -1; 1287 1288 if ((off0[0] & 7) == 0) { 1289 val = word[0]; 1290 } else { 1291 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | 1292 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); 1293 } 1294 1295 switch (size) { 1296 case 1: 1297 *(uint8_t *)data = val; 1298 break; 1299 case 2: 1300 *(uint16_t *)data = val; 1301 break; 1302 case 4: 1303 *(uint32_t *)data = val; 1304 break; 1305 case 8: 1306 *(uint64_t *)data = val; 1307 break; 1308 } 1309 return 0; 1310 } 1311 1312 int 1313 qla4_8xxx_pci_mem_write_2M(struct scsi_qla_host *ha, 1314 u64 off, void *data, int size) 1315 { 1316 int i, j, ret = 0, loop, sz[2], off0; 1317 int scale, shift_amount, startword; 1318 uint32_t temp; 1319 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; 1320 1321 /* 1322 * If not MN, go check for MS or invalid. 1323 */ 1324 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) 1325 mem_crb = QLA82XX_CRB_QDR_NET; 1326 else { 1327 mem_crb = QLA82XX_CRB_DDR_NET; 1328 if (qla4_8xxx_pci_mem_bound_check(ha, off, size) == 0) 1329 return qla4_8xxx_pci_mem_write_direct(ha, 1330 off, data, size); 1331 } 1332 1333 off0 = off & 0x7; 1334 sz[0] = (size < (8 - off0)) ? size : (8 - off0); 1335 sz[1] = size - sz[0]; 1336 1337 off8 = off & 0xfffffff0; 1338 loop = (((off & 0xf) + size - 1) >> 4) + 1; 1339 shift_amount = 4; 1340 scale = 2; 1341 startword = (off & 0xf)/8; 1342 1343 for (i = 0; i < loop; i++) { 1344 if (qla4_8xxx_pci_mem_read_2M(ha, off8 + 1345 (i << shift_amount), &word[i * scale], 8)) 1346 return -1; 1347 } 1348 1349 switch (size) { 1350 case 1: 1351 tmpw = *((uint8_t *)data); 1352 break; 1353 case 2: 1354 tmpw = *((uint16_t *)data); 1355 break; 1356 case 4: 1357 tmpw = *((uint32_t *)data); 1358 break; 1359 case 8: 1360 default: 1361 tmpw = *((uint64_t *)data); 1362 break; 1363 } 1364 1365 if (sz[0] == 8) 1366 word[startword] = tmpw; 1367 else { 1368 word[startword] &= 1369 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); 1370 word[startword] |= tmpw << (off0 * 8); 1371 } 1372 1373 if (sz[1] != 0) { 1374 word[startword+1] &= ~(~0ULL << (sz[1] * 8)); 1375 word[startword+1] |= tmpw >> (sz[0] * 8); 1376 } 1377 1378 for (i = 0; i < loop; i++) { 1379 temp = off8 + (i << shift_amount); 1380 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); 1381 temp = 0; 1382 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); 1383 temp = word[i * scale] & 0xffffffff; 1384 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); 1385 temp = (word[i * scale] >> 32) & 0xffffffff; 1386 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); 1387 temp = word[i*scale + 1] & 0xffffffff; 1388 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_LO, 1389 temp); 1390 temp = (word[i*scale + 1] >> 32) & 0xffffffff; 1391 qla4_8xxx_wr_32(ha, mem_crb + MIU_TEST_AGT_WRDATA_UPPER_HI, 1392 temp); 1393 1394 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1395 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1396 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; 1397 qla4_8xxx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); 1398 1399 for (j = 0; j < MAX_CTL_CHECK; j++) { 1400 temp = qla4_8xxx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); 1401 if ((temp & MIU_TA_CTL_BUSY) == 0) 1402 break; 1403 } 1404 1405 if (j >= MAX_CTL_CHECK) { 1406 if (printk_ratelimit()) 1407 ql4_printk(KERN_ERR, ha, 1408 "failed to write through agent\n"); 1409 ret = -1; 1410 break; 1411 } 1412 } 1413 1414 return ret; 1415 } 1416 1417 static int qla4_8xxx_cmdpeg_ready(struct scsi_qla_host *ha, int pegtune_val) 1418 { 1419 u32 val = 0; 1420 int retries = 60; 1421 1422 if (!pegtune_val) { 1423 do { 1424 val = qla4_8xxx_rd_32(ha, CRB_CMDPEG_STATE); 1425 if ((val == PHAN_INITIALIZE_COMPLETE) || 1426 (val == PHAN_INITIALIZE_ACK)) 1427 return 0; 1428 set_current_state(TASK_UNINTERRUPTIBLE); 1429 schedule_timeout(500); 1430 1431 } while (--retries); 1432 1433 if (!retries) { 1434 pegtune_val = qla4_8xxx_rd_32(ha, 1435 QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); 1436 printk(KERN_WARNING "%s: init failed, " 1437 "pegtune_val = %x\n", __func__, pegtune_val); 1438 return -1; 1439 } 1440 } 1441 return 0; 1442 } 1443 1444 static int qla4_8xxx_rcvpeg_ready(struct scsi_qla_host *ha) 1445 { 1446 uint32_t state = 0; 1447 int loops = 0; 1448 1449 /* Window 1 call */ 1450 read_lock(&ha->hw_lock); 1451 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1452 read_unlock(&ha->hw_lock); 1453 1454 while ((state != PHAN_PEG_RCV_INITIALIZED) && (loops < 30000)) { 1455 udelay(100); 1456 /* Window 1 call */ 1457 read_lock(&ha->hw_lock); 1458 state = qla4_8xxx_rd_32(ha, CRB_RCVPEG_STATE); 1459 read_unlock(&ha->hw_lock); 1460 1461 loops++; 1462 } 1463 1464 if (loops >= 30000) { 1465 DEBUG2(ql4_printk(KERN_INFO, ha, 1466 "Receive Peg initialization not complete: 0x%x.\n", state)); 1467 return QLA_ERROR; 1468 } 1469 1470 return QLA_SUCCESS; 1471 } 1472 1473 void 1474 qla4_8xxx_set_drv_active(struct scsi_qla_host *ha) 1475 { 1476 uint32_t drv_active; 1477 1478 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1479 drv_active |= (1 << (ha->func_num * 4)); 1480 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1481 } 1482 1483 void 1484 qla4_8xxx_clear_drv_active(struct scsi_qla_host *ha) 1485 { 1486 uint32_t drv_active; 1487 1488 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1489 drv_active &= ~(1 << (ha->func_num * 4)); 1490 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); 1491 } 1492 1493 static inline int 1494 qla4_8xxx_need_reset(struct scsi_qla_host *ha) 1495 { 1496 uint32_t drv_state, drv_active; 1497 int rval; 1498 1499 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1500 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1501 rval = drv_state & (1 << (ha->func_num * 4)); 1502 if ((test_bit(AF_EEH_BUSY, &ha->flags)) && drv_active) 1503 rval = 1; 1504 1505 return rval; 1506 } 1507 1508 static inline void 1509 qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha) 1510 { 1511 uint32_t drv_state; 1512 1513 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1514 drv_state |= (1 << (ha->func_num * 4)); 1515 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1516 } 1517 1518 static inline void 1519 qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha) 1520 { 1521 uint32_t drv_state; 1522 1523 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1524 drv_state &= ~(1 << (ha->func_num * 4)); 1525 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); 1526 } 1527 1528 static inline void 1529 qla4_8xxx_set_qsnt_ready(struct scsi_qla_host *ha) 1530 { 1531 uint32_t qsnt_state; 1532 1533 qsnt_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1534 qsnt_state |= (2 << (ha->func_num * 4)); 1535 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); 1536 } 1537 1538 1539 static int 1540 qla4_8xxx_start_firmware(struct scsi_qla_host *ha, uint32_t image_start) 1541 { 1542 int pcie_cap; 1543 uint16_t lnk; 1544 1545 /* scrub dma mask expansion register */ 1546 qla4_8xxx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); 1547 1548 /* Overwrite stale initialization register values */ 1549 qla4_8xxx_wr_32(ha, CRB_CMDPEG_STATE, 0); 1550 qla4_8xxx_wr_32(ha, CRB_RCVPEG_STATE, 0); 1551 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); 1552 qla4_8xxx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); 1553 1554 if (qla4_8xxx_load_fw(ha, image_start) != QLA_SUCCESS) { 1555 printk("%s: Error trying to start fw!\n", __func__); 1556 return QLA_ERROR; 1557 } 1558 1559 /* Handshake with the card before we register the devices. */ 1560 if (qla4_8xxx_cmdpeg_ready(ha, 0) != QLA_SUCCESS) { 1561 printk("%s: Error during card handshake!\n", __func__); 1562 return QLA_ERROR; 1563 } 1564 1565 /* Negotiated Link width */ 1566 pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); 1567 pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); 1568 ha->link_width = (lnk >> 4) & 0x3f; 1569 1570 /* Synchronize with Receive peg */ 1571 return qla4_8xxx_rcvpeg_ready(ha); 1572 } 1573 1574 static int 1575 qla4_8xxx_try_start_fw(struct scsi_qla_host *ha) 1576 { 1577 int rval = QLA_ERROR; 1578 1579 /* 1580 * FW Load priority: 1581 * 1) Operational firmware residing in flash. 1582 * 2) Fail 1583 */ 1584 1585 ql4_printk(KERN_INFO, ha, 1586 "FW: Retrieving flash offsets from FLT/FDT ...\n"); 1587 rval = qla4_8xxx_get_flash_info(ha); 1588 if (rval != QLA_SUCCESS) 1589 return rval; 1590 1591 ql4_printk(KERN_INFO, ha, 1592 "FW: Attempting to load firmware from flash...\n"); 1593 rval = qla4_8xxx_start_firmware(ha, ha->hw.flt_region_fw); 1594 1595 if (rval != QLA_SUCCESS) { 1596 ql4_printk(KERN_ERR, ha, "FW: Load firmware from flash" 1597 " FAILED...\n"); 1598 return rval; 1599 } 1600 1601 return rval; 1602 } 1603 1604 static void qla4_8xxx_rom_lock_recovery(struct scsi_qla_host *ha) 1605 { 1606 if (qla4_8xxx_rom_lock(ha)) { 1607 /* Someone else is holding the lock. */ 1608 dev_info(&ha->pdev->dev, "Resetting rom_lock\n"); 1609 } 1610 1611 /* 1612 * Either we got the lock, or someone 1613 * else died while holding it. 1614 * In either case, unlock. 1615 */ 1616 qla4_8xxx_rom_unlock(ha); 1617 } 1618 1619 /** 1620 * qla4_8xxx_device_bootstrap - Initialize device, set DEV_READY, start fw 1621 * @ha: pointer to adapter structure 1622 * 1623 * Note: IDC lock must be held upon entry 1624 **/ 1625 static int 1626 qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha) 1627 { 1628 int rval = QLA_ERROR; 1629 int i, timeout; 1630 uint32_t old_count, count; 1631 int need_reset = 0, peg_stuck = 1; 1632 1633 need_reset = qla4_8xxx_need_reset(ha); 1634 1635 old_count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1636 1637 for (i = 0; i < 10; i++) { 1638 timeout = msleep_interruptible(200); 1639 if (timeout) { 1640 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1641 QLA82XX_DEV_FAILED); 1642 return rval; 1643 } 1644 1645 count = qla4_8xxx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); 1646 if (count != old_count) 1647 peg_stuck = 0; 1648 } 1649 1650 if (need_reset) { 1651 /* We are trying to perform a recovery here. */ 1652 if (peg_stuck) 1653 qla4_8xxx_rom_lock_recovery(ha); 1654 goto dev_initialize; 1655 } else { 1656 /* Start of day for this ha context. */ 1657 if (peg_stuck) { 1658 /* Either we are the first or recovery in progress. */ 1659 qla4_8xxx_rom_lock_recovery(ha); 1660 goto dev_initialize; 1661 } else { 1662 /* Firmware already running. */ 1663 rval = QLA_SUCCESS; 1664 goto dev_ready; 1665 } 1666 } 1667 1668 dev_initialize: 1669 /* set to DEV_INITIALIZING */ 1670 ql4_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); 1671 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); 1672 1673 /* Driver that sets device state to initializating sets IDC version */ 1674 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); 1675 1676 qla4_8xxx_idc_unlock(ha); 1677 rval = qla4_8xxx_try_start_fw(ha); 1678 qla4_8xxx_idc_lock(ha); 1679 1680 if (rval != QLA_SUCCESS) { 1681 ql4_printk(KERN_INFO, ha, "HW State: FAILED\n"); 1682 qla4_8xxx_clear_drv_active(ha); 1683 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); 1684 return rval; 1685 } 1686 1687 dev_ready: 1688 ql4_printk(KERN_INFO, ha, "HW State: READY\n"); 1689 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); 1690 1691 return rval; 1692 } 1693 1694 /** 1695 * qla4_8xxx_need_reset_handler - Code to start reset sequence 1696 * @ha: pointer to adapter structure 1697 * 1698 * Note: IDC lock must be held upon entry 1699 **/ 1700 static void 1701 qla4_8xxx_need_reset_handler(struct scsi_qla_host *ha) 1702 { 1703 uint32_t dev_state, drv_state, drv_active; 1704 unsigned long reset_timeout; 1705 1706 ql4_printk(KERN_INFO, ha, 1707 "Performing ISP error recovery\n"); 1708 1709 if (test_and_clear_bit(AF_ONLINE, &ha->flags)) { 1710 qla4_8xxx_idc_unlock(ha); 1711 ha->isp_ops->disable_intrs(ha); 1712 qla4_8xxx_idc_lock(ha); 1713 } 1714 1715 qla4_8xxx_set_rst_ready(ha); 1716 1717 /* wait for 10 seconds for reset ack from all functions */ 1718 reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); 1719 1720 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1721 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1722 1723 ql4_printk(KERN_INFO, ha, 1724 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 1725 __func__, ha->host_no, drv_state, drv_active); 1726 1727 while (drv_state != drv_active) { 1728 if (time_after_eq(jiffies, reset_timeout)) { 1729 printk("%s: RESET TIMEOUT!\n", DRIVER_NAME); 1730 break; 1731 } 1732 1733 qla4_8xxx_idc_unlock(ha); 1734 msleep(1000); 1735 qla4_8xxx_idc_lock(ha); 1736 1737 drv_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_STATE); 1738 drv_active = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); 1739 } 1740 1741 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1742 ql4_printk(KERN_INFO, ha, "3:Device state is 0x%x = %s\n", dev_state, 1743 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1744 1745 /* Force to DEV_COLD unless someone else is starting a reset */ 1746 if (dev_state != QLA82XX_DEV_INITIALIZING) { 1747 ql4_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); 1748 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); 1749 } 1750 } 1751 1752 /** 1753 * qla4_8xxx_need_qsnt_handler - Code to start qsnt 1754 * @ha: pointer to adapter structure 1755 **/ 1756 void 1757 qla4_8xxx_need_qsnt_handler(struct scsi_qla_host *ha) 1758 { 1759 qla4_8xxx_idc_lock(ha); 1760 qla4_8xxx_set_qsnt_ready(ha); 1761 qla4_8xxx_idc_unlock(ha); 1762 } 1763 1764 /** 1765 * qla4_8xxx_device_state_handler - Adapter state machine 1766 * @ha: pointer to host adapter structure. 1767 * 1768 * Note: IDC lock must be UNLOCKED upon entry 1769 **/ 1770 int qla4_8xxx_device_state_handler(struct scsi_qla_host *ha) 1771 { 1772 uint32_t dev_state; 1773 int rval = QLA_SUCCESS; 1774 unsigned long dev_init_timeout; 1775 1776 if (!test_bit(AF_INIT_DONE, &ha->flags)) { 1777 qla4_8xxx_idc_lock(ha); 1778 qla4_8xxx_set_drv_active(ha); 1779 qla4_8xxx_idc_unlock(ha); 1780 } 1781 1782 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1783 ql4_printk(KERN_INFO, ha, "1:Device state is 0x%x = %s\n", dev_state, 1784 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1785 1786 /* wait for 30 seconds for device to go ready */ 1787 dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); 1788 1789 qla4_8xxx_idc_lock(ha); 1790 while (1) { 1791 1792 if (time_after_eq(jiffies, dev_init_timeout)) { 1793 ql4_printk(KERN_WARNING, ha, "Device init failed!\n"); 1794 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 1795 QLA82XX_DEV_FAILED); 1796 } 1797 1798 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 1799 ql4_printk(KERN_INFO, ha, 1800 "2:Device state is 0x%x = %s\n", dev_state, 1801 dev_state < MAX_STATES ? qdev_state[dev_state] : "Unknown"); 1802 1803 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 1804 switch (dev_state) { 1805 case QLA82XX_DEV_READY: 1806 goto exit; 1807 case QLA82XX_DEV_COLD: 1808 rval = qla4_8xxx_device_bootstrap(ha); 1809 goto exit; 1810 case QLA82XX_DEV_INITIALIZING: 1811 qla4_8xxx_idc_unlock(ha); 1812 msleep(1000); 1813 qla4_8xxx_idc_lock(ha); 1814 break; 1815 case QLA82XX_DEV_NEED_RESET: 1816 if (!ql4xdontresethba) { 1817 qla4_8xxx_need_reset_handler(ha); 1818 /* Update timeout value after need 1819 * reset handler */ 1820 dev_init_timeout = jiffies + 1821 (ha->nx_dev_init_timeout * HZ); 1822 } else { 1823 qla4_8xxx_idc_unlock(ha); 1824 msleep(1000); 1825 qla4_8xxx_idc_lock(ha); 1826 } 1827 break; 1828 case QLA82XX_DEV_NEED_QUIESCENT: 1829 /* idc locked/unlocked in handler */ 1830 qla4_8xxx_need_qsnt_handler(ha); 1831 break; 1832 case QLA82XX_DEV_QUIESCENT: 1833 qla4_8xxx_idc_unlock(ha); 1834 msleep(1000); 1835 qla4_8xxx_idc_lock(ha); 1836 break; 1837 case QLA82XX_DEV_FAILED: 1838 qla4_8xxx_idc_unlock(ha); 1839 qla4xxx_dead_adapter_cleanup(ha); 1840 rval = QLA_ERROR; 1841 qla4_8xxx_idc_lock(ha); 1842 goto exit; 1843 default: 1844 qla4_8xxx_idc_unlock(ha); 1845 qla4xxx_dead_adapter_cleanup(ha); 1846 rval = QLA_ERROR; 1847 qla4_8xxx_idc_lock(ha); 1848 goto exit; 1849 } 1850 } 1851 exit: 1852 qla4_8xxx_idc_unlock(ha); 1853 return rval; 1854 } 1855 1856 int qla4_8xxx_load_risc(struct scsi_qla_host *ha) 1857 { 1858 int retval; 1859 1860 /* clear the interrupt */ 1861 writel(0, &ha->qla4_8xxx_reg->host_int); 1862 readl(&ha->qla4_8xxx_reg->host_int); 1863 1864 retval = qla4_8xxx_device_state_handler(ha); 1865 1866 if (retval == QLA_SUCCESS && !test_bit(AF_INIT_DONE, &ha->flags)) 1867 retval = qla4xxx_request_irqs(ha); 1868 1869 return retval; 1870 } 1871 1872 /*****************************************************************************/ 1873 /* Flash Manipulation Routines */ 1874 /*****************************************************************************/ 1875 1876 #define OPTROM_BURST_SIZE 0x1000 1877 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 1878 1879 #define FARX_DATA_FLAG BIT_31 1880 #define FARX_ACCESS_FLASH_CONF 0x7FFD0000 1881 #define FARX_ACCESS_FLASH_DATA 0x7FF00000 1882 1883 static inline uint32_t 1884 flash_conf_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1885 { 1886 return hw->flash_conf_off | faddr; 1887 } 1888 1889 static inline uint32_t 1890 flash_data_addr(struct ql82xx_hw_data *hw, uint32_t faddr) 1891 { 1892 return hw->flash_data_off | faddr; 1893 } 1894 1895 static uint32_t * 1896 qla4_8xxx_read_flash_data(struct scsi_qla_host *ha, uint32_t *dwptr, 1897 uint32_t faddr, uint32_t length) 1898 { 1899 uint32_t i; 1900 uint32_t val; 1901 int loops = 0; 1902 while ((qla4_8xxx_rom_lock(ha) != 0) && (loops < 50000)) { 1903 udelay(100); 1904 cond_resched(); 1905 loops++; 1906 } 1907 if (loops >= 50000) { 1908 ql4_printk(KERN_WARNING, ha, "ROM lock failed\n"); 1909 return dwptr; 1910 } 1911 1912 /* Dword reads to flash. */ 1913 for (i = 0; i < length/4; i++, faddr += 4) { 1914 if (qla4_8xxx_do_rom_fast_read(ha, faddr, &val)) { 1915 ql4_printk(KERN_WARNING, ha, 1916 "Do ROM fast read failed\n"); 1917 goto done_read; 1918 } 1919 dwptr[i] = __constant_cpu_to_le32(val); 1920 } 1921 1922 done_read: 1923 qla4_8xxx_rom_unlock(ha); 1924 return dwptr; 1925 } 1926 1927 /** 1928 * Address and length are byte address 1929 **/ 1930 static uint8_t * 1931 qla4_8xxx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf, 1932 uint32_t offset, uint32_t length) 1933 { 1934 qla4_8xxx_read_flash_data(ha, (uint32_t *)buf, offset, length); 1935 return buf; 1936 } 1937 1938 static int 1939 qla4_8xxx_find_flt_start(struct scsi_qla_host *ha, uint32_t *start) 1940 { 1941 const char *loc, *locations[] = { "DEF", "PCI" }; 1942 1943 /* 1944 * FLT-location structure resides after the last PCI region. 1945 */ 1946 1947 /* Begin with sane defaults. */ 1948 loc = locations[0]; 1949 *start = FA_FLASH_LAYOUT_ADDR_82; 1950 1951 DEBUG2(ql4_printk(KERN_INFO, ha, "FLTL[%s] = 0x%x.\n", loc, *start)); 1952 return QLA_SUCCESS; 1953 } 1954 1955 static void 1956 qla4_8xxx_get_flt_info(struct scsi_qla_host *ha, uint32_t flt_addr) 1957 { 1958 const char *loc, *locations[] = { "DEF", "FLT" }; 1959 uint16_t *wptr; 1960 uint16_t cnt, chksum; 1961 uint32_t start; 1962 struct qla_flt_header *flt; 1963 struct qla_flt_region *region; 1964 struct ql82xx_hw_data *hw = &ha->hw; 1965 1966 hw->flt_region_flt = flt_addr; 1967 wptr = (uint16_t *)ha->request_ring; 1968 flt = (struct qla_flt_header *)ha->request_ring; 1969 region = (struct qla_flt_region *)&flt[1]; 1970 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 1971 flt_addr << 2, OPTROM_BURST_SIZE); 1972 if (*wptr == __constant_cpu_to_le16(0xffff)) 1973 goto no_flash_data; 1974 if (flt->version != __constant_cpu_to_le16(1)) { 1975 DEBUG2(ql4_printk(KERN_INFO, ha, "Unsupported FLT detected: " 1976 "version=0x%x length=0x%x checksum=0x%x.\n", 1977 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1978 le16_to_cpu(flt->checksum))); 1979 goto no_flash_data; 1980 } 1981 1982 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1; 1983 for (chksum = 0; cnt; cnt--) 1984 chksum += le16_to_cpu(*wptr++); 1985 if (chksum) { 1986 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FLT detected: " 1987 "version=0x%x length=0x%x checksum=0x%x.\n", 1988 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 1989 chksum)); 1990 goto no_flash_data; 1991 } 1992 1993 loc = locations[1]; 1994 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 1995 for ( ; cnt; cnt--, region++) { 1996 /* Store addresses as DWORD offsets. */ 1997 start = le32_to_cpu(region->start) >> 2; 1998 1999 DEBUG3(ql4_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x " 2000 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start, 2001 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size))); 2002 2003 switch (le32_to_cpu(region->code) & 0xff) { 2004 case FLT_REG_FDT: 2005 hw->flt_region_fdt = start; 2006 break; 2007 case FLT_REG_BOOT_CODE_82: 2008 hw->flt_region_boot = start; 2009 break; 2010 case FLT_REG_FW_82: 2011 case FLT_REG_FW_82_1: 2012 hw->flt_region_fw = start; 2013 break; 2014 case FLT_REG_BOOTLOAD_82: 2015 hw->flt_region_bootload = start; 2016 break; 2017 case FLT_REG_ISCSI_PARAM: 2018 hw->flt_iscsi_param = start; 2019 break; 2020 case FLT_REG_ISCSI_CHAP: 2021 hw->flt_region_chap = start; 2022 hw->flt_chap_size = le32_to_cpu(region->size); 2023 break; 2024 } 2025 } 2026 goto done; 2027 2028 no_flash_data: 2029 /* Use hardcoded defaults. */ 2030 loc = locations[0]; 2031 2032 hw->flt_region_fdt = FA_FLASH_DESCR_ADDR_82; 2033 hw->flt_region_boot = FA_BOOT_CODE_ADDR_82; 2034 hw->flt_region_bootload = FA_BOOT_LOAD_ADDR_82; 2035 hw->flt_region_fw = FA_RISC_CODE_ADDR_82; 2036 hw->flt_region_chap = FA_FLASH_ISCSI_CHAP; 2037 hw->flt_chap_size = FA_FLASH_CHAP_SIZE; 2038 2039 done: 2040 DEBUG2(ql4_printk(KERN_INFO, ha, "FLT[%s]: flt=0x%x fdt=0x%x " 2041 "boot=0x%x bootload=0x%x fw=0x%x\n", loc, hw->flt_region_flt, 2042 hw->flt_region_fdt, hw->flt_region_boot, hw->flt_region_bootload, 2043 hw->flt_region_fw)); 2044 } 2045 2046 static void 2047 qla4_8xxx_get_fdt_info(struct scsi_qla_host *ha) 2048 { 2049 #define FLASH_BLK_SIZE_4K 0x1000 2050 #define FLASH_BLK_SIZE_32K 0x8000 2051 #define FLASH_BLK_SIZE_64K 0x10000 2052 const char *loc, *locations[] = { "MID", "FDT" }; 2053 uint16_t cnt, chksum; 2054 uint16_t *wptr; 2055 struct qla_fdt_layout *fdt; 2056 uint16_t mid = 0; 2057 uint16_t fid = 0; 2058 struct ql82xx_hw_data *hw = &ha->hw; 2059 2060 hw->flash_conf_off = FARX_ACCESS_FLASH_CONF; 2061 hw->flash_data_off = FARX_ACCESS_FLASH_DATA; 2062 2063 wptr = (uint16_t *)ha->request_ring; 2064 fdt = (struct qla_fdt_layout *)ha->request_ring; 2065 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2066 hw->flt_region_fdt << 2, OPTROM_BURST_SIZE); 2067 2068 if (*wptr == __constant_cpu_to_le16(0xffff)) 2069 goto no_flash_data; 2070 2071 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' || 2072 fdt->sig[3] != 'D') 2073 goto no_flash_data; 2074 2075 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1; 2076 cnt++) 2077 chksum += le16_to_cpu(*wptr++); 2078 2079 if (chksum) { 2080 DEBUG2(ql4_printk(KERN_INFO, ha, "Inconsistent FDT detected: " 2081 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0], 2082 le16_to_cpu(fdt->version))); 2083 goto no_flash_data; 2084 } 2085 2086 loc = locations[1]; 2087 mid = le16_to_cpu(fdt->man_id); 2088 fid = le16_to_cpu(fdt->id); 2089 hw->fdt_wrt_disable = fdt->wrt_disable_bits; 2090 hw->fdt_erase_cmd = flash_conf_addr(hw, 0x0300 | fdt->erase_cmd); 2091 hw->fdt_block_size = le32_to_cpu(fdt->block_size); 2092 2093 if (fdt->unprotect_sec_cmd) { 2094 hw->fdt_unprotect_sec_cmd = flash_conf_addr(hw, 0x0300 | 2095 fdt->unprotect_sec_cmd); 2096 hw->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 2097 flash_conf_addr(hw, 0x0300 | fdt->protect_sec_cmd) : 2098 flash_conf_addr(hw, 0x0336); 2099 } 2100 goto done; 2101 2102 no_flash_data: 2103 loc = locations[0]; 2104 hw->fdt_block_size = FLASH_BLK_SIZE_64K; 2105 done: 2106 DEBUG2(ql4_printk(KERN_INFO, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x " 2107 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid, 2108 hw->fdt_erase_cmd, hw->fdt_protect_sec_cmd, 2109 hw->fdt_unprotect_sec_cmd, hw->fdt_wrt_disable, 2110 hw->fdt_block_size)); 2111 } 2112 2113 static void 2114 qla4_8xxx_get_idc_param(struct scsi_qla_host *ha) 2115 { 2116 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 2117 uint32_t *wptr; 2118 2119 if (!is_qla8022(ha)) 2120 return; 2121 wptr = (uint32_t *)ha->request_ring; 2122 qla4_8xxx_read_optrom_data(ha, (uint8_t *)ha->request_ring, 2123 QLA82XX_IDC_PARAM_ADDR , 8); 2124 2125 if (*wptr == __constant_cpu_to_le32(0xffffffff)) { 2126 ha->nx_dev_init_timeout = ROM_DEV_INIT_TIMEOUT; 2127 ha->nx_reset_timeout = ROM_DRV_RESET_ACK_TIMEOUT; 2128 } else { 2129 ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); 2130 ha->nx_reset_timeout = le32_to_cpu(*wptr); 2131 } 2132 2133 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2134 "ha->nx_dev_init_timeout = %d\n", ha->nx_dev_init_timeout)); 2135 DEBUG2(ql4_printk(KERN_DEBUG, ha, 2136 "ha->nx_reset_timeout = %d\n", ha->nx_reset_timeout)); 2137 return; 2138 } 2139 2140 int 2141 qla4_8xxx_get_flash_info(struct scsi_qla_host *ha) 2142 { 2143 int ret; 2144 uint32_t flt_addr; 2145 2146 ret = qla4_8xxx_find_flt_start(ha, &flt_addr); 2147 if (ret != QLA_SUCCESS) 2148 return ret; 2149 2150 qla4_8xxx_get_flt_info(ha, flt_addr); 2151 qla4_8xxx_get_fdt_info(ha); 2152 qla4_8xxx_get_idc_param(ha); 2153 2154 return QLA_SUCCESS; 2155 } 2156 2157 /** 2158 * qla4_8xxx_stop_firmware - stops firmware on specified adapter instance 2159 * @ha: pointer to host adapter structure. 2160 * 2161 * Remarks: 2162 * For iSCSI, throws away all I/O and AENs into bit bucket, so they will 2163 * not be available after successful return. Driver must cleanup potential 2164 * outstanding I/O's after calling this funcion. 2165 **/ 2166 int 2167 qla4_8xxx_stop_firmware(struct scsi_qla_host *ha) 2168 { 2169 int status; 2170 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2171 uint32_t mbox_sts[MBOX_REG_COUNT]; 2172 2173 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2174 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2175 2176 mbox_cmd[0] = MBOX_CMD_STOP_FW; 2177 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, 2178 &mbox_cmd[0], &mbox_sts[0]); 2179 2180 DEBUG2(printk("scsi%ld: %s: status = %d\n", ha->host_no, 2181 __func__, status)); 2182 return status; 2183 } 2184 2185 /** 2186 * qla4_8xxx_isp_reset - Resets ISP and aborts all outstanding commands. 2187 * @ha: pointer to host adapter structure. 2188 **/ 2189 int 2190 qla4_8xxx_isp_reset(struct scsi_qla_host *ha) 2191 { 2192 int rval; 2193 uint32_t dev_state; 2194 2195 qla4_8xxx_idc_lock(ha); 2196 dev_state = qla4_8xxx_rd_32(ha, QLA82XX_CRB_DEV_STATE); 2197 2198 if (dev_state == QLA82XX_DEV_READY) { 2199 ql4_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); 2200 qla4_8xxx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 2201 QLA82XX_DEV_NEED_RESET); 2202 } else 2203 ql4_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); 2204 2205 qla4_8xxx_idc_unlock(ha); 2206 2207 rval = qla4_8xxx_device_state_handler(ha); 2208 2209 qla4_8xxx_idc_lock(ha); 2210 qla4_8xxx_clear_rst_ready(ha); 2211 qla4_8xxx_idc_unlock(ha); 2212 2213 if (rval == QLA_SUCCESS) 2214 clear_bit(AF_FW_RECOVERY, &ha->flags); 2215 2216 return rval; 2217 } 2218 2219 /** 2220 * qla4_8xxx_get_sys_info - get adapter MAC address(es) and serial number 2221 * @ha: pointer to host adapter structure. 2222 * 2223 **/ 2224 int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha) 2225 { 2226 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2227 uint32_t mbox_sts[MBOX_REG_COUNT]; 2228 struct mbx_sys_info *sys_info; 2229 dma_addr_t sys_info_dma; 2230 int status = QLA_ERROR; 2231 2232 sys_info = dma_alloc_coherent(&ha->pdev->dev, sizeof(*sys_info), 2233 &sys_info_dma, GFP_KERNEL); 2234 if (sys_info == NULL) { 2235 DEBUG2(printk("scsi%ld: %s: Unable to allocate dma buffer.\n", 2236 ha->host_no, __func__)); 2237 return status; 2238 } 2239 2240 memset(sys_info, 0, sizeof(*sys_info)); 2241 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2242 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2243 2244 mbox_cmd[0] = MBOX_CMD_GET_SYS_INFO; 2245 mbox_cmd[1] = LSDW(sys_info_dma); 2246 mbox_cmd[2] = MSDW(sys_info_dma); 2247 mbox_cmd[4] = sizeof(*sys_info); 2248 2249 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 6, &mbox_cmd[0], 2250 &mbox_sts[0]) != QLA_SUCCESS) { 2251 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO failed\n", 2252 ha->host_no, __func__)); 2253 goto exit_validate_mac82; 2254 } 2255 2256 /* Make sure we receive the minimum required data to cache internally */ 2257 if (mbox_sts[4] < offsetof(struct mbx_sys_info, reserved)) { 2258 DEBUG2(printk("scsi%ld: %s: GET_SYS_INFO data receive" 2259 " error (%x)\n", ha->host_no, __func__, mbox_sts[4])); 2260 goto exit_validate_mac82; 2261 2262 } 2263 2264 /* Save M.A.C. address & serial_number */ 2265 ha->port_num = sys_info->port_num; 2266 memcpy(ha->my_mac, &sys_info->mac_addr[0], 2267 min(sizeof(ha->my_mac), sizeof(sys_info->mac_addr))); 2268 memcpy(ha->serial_number, &sys_info->serial_number, 2269 min(sizeof(ha->serial_number), sizeof(sys_info->serial_number))); 2270 memcpy(ha->model_name, &sys_info->board_id_str, 2271 min(sizeof(ha->model_name), sizeof(sys_info->board_id_str))); 2272 ha->phy_port_cnt = sys_info->phys_port_cnt; 2273 ha->phy_port_num = sys_info->port_num; 2274 ha->iscsi_pci_func_cnt = sys_info->iscsi_pci_func_cnt; 2275 2276 DEBUG2(printk("scsi%ld: %s: " 2277 "mac %02x:%02x:%02x:%02x:%02x:%02x " 2278 "serial %s\n", ha->host_no, __func__, 2279 ha->my_mac[0], ha->my_mac[1], ha->my_mac[2], 2280 ha->my_mac[3], ha->my_mac[4], ha->my_mac[5], 2281 ha->serial_number)); 2282 2283 status = QLA_SUCCESS; 2284 2285 exit_validate_mac82: 2286 dma_free_coherent(&ha->pdev->dev, sizeof(*sys_info), sys_info, 2287 sys_info_dma); 2288 return status; 2289 } 2290 2291 /* Interrupt handling helpers. */ 2292 2293 static int 2294 qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha) 2295 { 2296 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2297 uint32_t mbox_sts[MBOX_REG_COUNT]; 2298 2299 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2300 2301 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2302 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2303 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2304 mbox_cmd[1] = INTR_ENABLE; 2305 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2306 &mbox_sts[0]) != QLA_SUCCESS) { 2307 DEBUG2(ql4_printk(KERN_INFO, ha, 2308 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2309 __func__, mbox_sts[0])); 2310 return QLA_ERROR; 2311 } 2312 return QLA_SUCCESS; 2313 } 2314 2315 static int 2316 qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha) 2317 { 2318 uint32_t mbox_cmd[MBOX_REG_COUNT]; 2319 uint32_t mbox_sts[MBOX_REG_COUNT]; 2320 2321 DEBUG2(ql4_printk(KERN_INFO, ha, "%s\n", __func__)); 2322 2323 memset(&mbox_cmd, 0, sizeof(mbox_cmd)); 2324 memset(&mbox_sts, 0, sizeof(mbox_sts)); 2325 mbox_cmd[0] = MBOX_CMD_ENABLE_INTRS; 2326 mbox_cmd[1] = INTR_DISABLE; 2327 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], 2328 &mbox_sts[0]) != QLA_SUCCESS) { 2329 DEBUG2(ql4_printk(KERN_INFO, ha, 2330 "%s: MBOX_CMD_ENABLE_INTRS failed (0x%04x)\n", 2331 __func__, mbox_sts[0])); 2332 return QLA_ERROR; 2333 } 2334 2335 return QLA_SUCCESS; 2336 } 2337 2338 void 2339 qla4_8xxx_enable_intrs(struct scsi_qla_host *ha) 2340 { 2341 qla4_8xxx_mbx_intr_enable(ha); 2342 2343 spin_lock_irq(&ha->hardware_lock); 2344 /* BIT 10 - reset */ 2345 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); 2346 spin_unlock_irq(&ha->hardware_lock); 2347 set_bit(AF_INTERRUPTS_ON, &ha->flags); 2348 } 2349 2350 void 2351 qla4_8xxx_disable_intrs(struct scsi_qla_host *ha) 2352 { 2353 if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags)) 2354 qla4_8xxx_mbx_intr_disable(ha); 2355 2356 spin_lock_irq(&ha->hardware_lock); 2357 /* BIT 10 - set */ 2358 qla4_8xxx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); 2359 spin_unlock_irq(&ha->hardware_lock); 2360 } 2361 2362 struct ql4_init_msix_entry { 2363 uint16_t entry; 2364 uint16_t index; 2365 const char *name; 2366 irq_handler_t handler; 2367 }; 2368 2369 static struct ql4_init_msix_entry qla4_8xxx_msix_entries[QLA_MSIX_ENTRIES] = { 2370 { QLA_MSIX_DEFAULT, QLA_MIDX_DEFAULT, 2371 "qla4xxx (default)", 2372 (irq_handler_t)qla4_8xxx_default_intr_handler }, 2373 { QLA_MSIX_RSP_Q, QLA_MIDX_RSP_Q, 2374 "qla4xxx (rsp_q)", (irq_handler_t)qla4_8xxx_msix_rsp_q }, 2375 }; 2376 2377 void 2378 qla4_8xxx_disable_msix(struct scsi_qla_host *ha) 2379 { 2380 int i; 2381 struct ql4_msix_entry *qentry; 2382 2383 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2384 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2385 if (qentry->have_irq) { 2386 free_irq(qentry->msix_vector, ha); 2387 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2388 __func__, qla4_8xxx_msix_entries[i].name)); 2389 } 2390 } 2391 pci_disable_msix(ha->pdev); 2392 clear_bit(AF_MSIX_ENABLED, &ha->flags); 2393 } 2394 2395 int 2396 qla4_8xxx_enable_msix(struct scsi_qla_host *ha) 2397 { 2398 int i, ret; 2399 struct msix_entry entries[QLA_MSIX_ENTRIES]; 2400 struct ql4_msix_entry *qentry; 2401 2402 for (i = 0; i < QLA_MSIX_ENTRIES; i++) 2403 entries[i].entry = qla4_8xxx_msix_entries[i].entry; 2404 2405 ret = pci_enable_msix(ha->pdev, entries, ARRAY_SIZE(entries)); 2406 if (ret) { 2407 ql4_printk(KERN_WARNING, ha, 2408 "MSI-X: Failed to enable support -- %d/%d\n", 2409 QLA_MSIX_ENTRIES, ret); 2410 goto msix_out; 2411 } 2412 set_bit(AF_MSIX_ENABLED, &ha->flags); 2413 2414 for (i = 0; i < QLA_MSIX_ENTRIES; i++) { 2415 qentry = &ha->msix_entries[qla4_8xxx_msix_entries[i].index]; 2416 qentry->msix_vector = entries[i].vector; 2417 qentry->msix_entry = entries[i].entry; 2418 qentry->have_irq = 0; 2419 ret = request_irq(qentry->msix_vector, 2420 qla4_8xxx_msix_entries[i].handler, 0, 2421 qla4_8xxx_msix_entries[i].name, ha); 2422 if (ret) { 2423 ql4_printk(KERN_WARNING, ha, 2424 "MSI-X: Unable to register handler -- %x/%d.\n", 2425 qla4_8xxx_msix_entries[i].index, ret); 2426 qla4_8xxx_disable_msix(ha); 2427 goto msix_out; 2428 } 2429 qentry->have_irq = 1; 2430 DEBUG2(ql4_printk(KERN_INFO, ha, "%s: %s\n", 2431 __func__, qla4_8xxx_msix_entries[i].name)); 2432 } 2433 msix_out: 2434 return ret; 2435 } 2436