1 /******************************************************************************** 2 * QLOGIC LINUX SOFTWARE 3 * 4 * QLogic ISP2x00 device driver for Linux 2.6.x 5 * Copyright (C) 2003-2005 QLogic Corporation 6 * (www.qlogic.com) 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2, or (at your option) any 11 * later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 ** 18 ******************************************************************************/ 19 20 #ifndef __QLA_DEF_H 21 #define __QLA_DEF_H 22 23 #include <linux/kernel.h> 24 #include <linux/init.h> 25 #include <linux/types.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/pci.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sched.h> 31 #include <linux/slab.h> 32 #include <linux/dmapool.h> 33 #include <linux/mempool.h> 34 #include <linux/spinlock.h> 35 #include <linux/completion.h> 36 #include <linux/interrupt.h> 37 #include <asm/semaphore.h> 38 39 #include <scsi/scsi.h> 40 #include <scsi/scsi_host.h> 41 #include <scsi/scsi_device.h> 42 #include <scsi/scsi_cmnd.h> 43 44 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE) 45 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100) 46 #else 47 #define IS_QLA2100(ha) 0 48 #endif 49 50 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE) 51 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200) 52 #else 53 #define IS_QLA2200(ha) 0 54 #endif 55 56 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE) 57 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300) 58 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312) 59 #else 60 #define IS_QLA2300(ha) 0 61 #define IS_QLA2312(ha) 0 62 #endif 63 64 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE) 65 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322) 66 #else 67 #define IS_QLA2322(ha) 0 68 #endif 69 70 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE) 71 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312) 72 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322) 73 #else 74 #define IS_QLA6312(ha) 0 75 #define IS_QLA6322(ha) 0 76 #endif 77 78 #if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE) 79 #define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422) 80 #define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432) 81 #else 82 #define IS_QLA2422(ha) 0 83 #define IS_QLA2432(ha) 0 84 #endif 85 86 #if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE) 87 #define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512) 88 #define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522) 89 #else 90 #define IS_QLA2512(ha) 0 91 #define IS_QLA2522(ha) 0 92 #endif 93 94 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 95 IS_QLA6312(ha) || IS_QLA6322(ha)) 96 97 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 98 #define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha)) 99 100 /* 101 * Only non-ISP2[12]00 have extended addressing support in the firmware. 102 */ 103 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 104 105 /* 106 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 107 * but that's fine as we don't look at the last 24 ones for 108 * ISP2100 HBAs. 109 */ 110 #define MAILBOX_REGISTER_COUNT_2100 8 111 #define MAILBOX_REGISTER_COUNT 32 112 113 #define QLA2200A_RISC_ROM_VER 4 114 #define FPM_2300 6 115 #define FPM_2310 7 116 117 #include "qla_settings.h" 118 119 /* 120 * Data bit definitions 121 */ 122 #define BIT_0 0x1 123 #define BIT_1 0x2 124 #define BIT_2 0x4 125 #define BIT_3 0x8 126 #define BIT_4 0x10 127 #define BIT_5 0x20 128 #define BIT_6 0x40 129 #define BIT_7 0x80 130 #define BIT_8 0x100 131 #define BIT_9 0x200 132 #define BIT_10 0x400 133 #define BIT_11 0x800 134 #define BIT_12 0x1000 135 #define BIT_13 0x2000 136 #define BIT_14 0x4000 137 #define BIT_15 0x8000 138 #define BIT_16 0x10000 139 #define BIT_17 0x20000 140 #define BIT_18 0x40000 141 #define BIT_19 0x80000 142 #define BIT_20 0x100000 143 #define BIT_21 0x200000 144 #define BIT_22 0x400000 145 #define BIT_23 0x800000 146 #define BIT_24 0x1000000 147 #define BIT_25 0x2000000 148 #define BIT_26 0x4000000 149 #define BIT_27 0x8000000 150 #define BIT_28 0x10000000 151 #define BIT_29 0x20000000 152 #define BIT_30 0x40000000 153 #define BIT_31 0x80000000 154 155 #define LSB(x) ((uint8_t)(x)) 156 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 157 158 #define LSW(x) ((uint16_t)(x)) 159 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 160 161 #define LSD(x) ((uint32_t)((uint64_t)(x))) 162 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 163 164 165 /* 166 * I/O register 167 */ 168 169 #define RD_REG_BYTE(addr) readb(addr) 170 #define RD_REG_WORD(addr) readw(addr) 171 #define RD_REG_DWORD(addr) readl(addr) 172 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 173 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 174 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 175 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 176 #define WRT_REG_WORD(addr, data) writew(data,addr) 177 #define WRT_REG_DWORD(addr, data) writel(data,addr) 178 179 /* 180 * Fibre Channel device definitions. 181 */ 182 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 183 #define MAX_FIBRE_DEVICES 512 184 #define MAX_FIBRE_LUNS 0xFFFF 185 #define MAX_RSCN_COUNT 32 186 #define MAX_HOST_COUNT 16 187 188 /* 189 * Host adapter default definitions. 190 */ 191 #define MAX_BUSES 1 /* We only have one bus today */ 192 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES 193 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES 194 #define MIN_LUNS 8 195 #define MAX_LUNS MAX_FIBRE_LUNS 196 #define MAX_CMDS_PER_LUN 255 197 198 /* 199 * Fibre Channel device definitions. 200 */ 201 #define SNS_LAST_LOOP_ID_2100 0xfe 202 #define SNS_LAST_LOOP_ID_2300 0x7ff 203 204 #define LAST_LOCAL_LOOP_ID 0x7d 205 #define SNS_FL_PORT 0x7e 206 #define FABRIC_CONTROLLER 0x7f 207 #define SIMPLE_NAME_SERVER 0x80 208 #define SNS_FIRST_LOOP_ID 0x81 209 #define MANAGEMENT_SERVER 0xfe 210 #define BROADCAST 0xff 211 212 /* 213 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 214 * valid range of an N-PORT id is 0 through 0x7ef. 215 */ 216 #define NPH_LAST_HANDLE 0x7ef 217 #define NPH_SNS 0x7fc /* FFFFFC */ 218 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 219 #define NPH_F_PORT 0x7fe /* FFFFFE */ 220 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 221 222 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 223 #include "qla_fw.h" 224 225 /* 226 * Timeout timer counts in seconds 227 */ 228 #define PORT_RETRY_TIME 1 229 #define LOOP_DOWN_TIMEOUT 60 230 #define LOOP_DOWN_TIME 255 /* 240 */ 231 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 232 233 /* Maximum outstanding commands in ISP queues (1-65535) */ 234 #define MAX_OUTSTANDING_COMMANDS 1024 235 236 /* ISP request and response entry counts (37-65535) */ 237 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 238 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 239 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */ 240 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */ 241 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 242 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 243 244 /* 245 * SCSI Request Block 246 */ 247 typedef struct srb { 248 struct list_head list; 249 250 struct scsi_qla_host *ha; /* HA the SP is queued on */ 251 struct fc_port *fcport; 252 253 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 254 255 struct timer_list timer; /* Command timer */ 256 atomic_t ref_count; /* Reference count for this structure */ 257 uint16_t flags; 258 259 /* Request state */ 260 uint16_t state; 261 262 /* Single transfer DMA context */ 263 dma_addr_t dma_handle; 264 265 uint32_t request_sense_length; 266 uint8_t *request_sense_ptr; 267 268 /* SRB magic number */ 269 uint16_t magic; 270 #define SRB_MAGIC 0x10CB 271 } srb_t; 272 273 /* 274 * SRB flag definitions 275 */ 276 #define SRB_TIMEOUT BIT_0 /* Command timed out */ 277 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */ 278 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */ 279 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */ 280 281 #define SRB_ABORTED BIT_4 /* Command aborted command already */ 282 #define SRB_RETRY BIT_5 /* Command needs retrying */ 283 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */ 284 #define SRB_FAILOVER BIT_7 /* Command in failover state */ 285 286 #define SRB_BUSY BIT_8 /* Command is in busy retry state */ 287 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */ 288 #define SRB_IOCTL BIT_10 /* IOCTL command. */ 289 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */ 290 291 /* 292 * SRB state definitions 293 */ 294 #define SRB_FREE_STATE 0 /* returned back */ 295 #define SRB_PENDING_STATE 1 /* queued in LUN Q */ 296 #define SRB_ACTIVE_STATE 2 /* in Active Array */ 297 #define SRB_DONE_STATE 3 /* queued in Done Queue */ 298 #define SRB_RETRY_STATE 4 /* in Retry Queue */ 299 #define SRB_SUSPENDED_STATE 5 /* in suspended state */ 300 #define SRB_NO_QUEUE_STATE 6 /* is in between states */ 301 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */ 302 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */ 303 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */ 304 305 306 /* 307 * ISP I/O Register Set structure definitions. 308 */ 309 struct device_reg_2xxx { 310 uint16_t flash_address; /* Flash BIOS address */ 311 uint16_t flash_data; /* Flash BIOS data */ 312 uint16_t unused_1[1]; /* Gap */ 313 uint16_t ctrl_status; /* Control/Status */ 314 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 315 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 316 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 317 318 uint16_t ictrl; /* Interrupt control */ 319 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 320 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 321 322 uint16_t istatus; /* Interrupt status */ 323 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 324 325 uint16_t semaphore; /* Semaphore */ 326 uint16_t nvram; /* NVRAM register. */ 327 #define NVR_DESELECT 0 328 #define NVR_BUSY BIT_15 329 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 330 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 331 #define NVR_DATA_IN BIT_3 332 #define NVR_DATA_OUT BIT_2 333 #define NVR_SELECT BIT_1 334 #define NVR_CLOCK BIT_0 335 336 union { 337 struct { 338 uint16_t mailbox0; 339 uint16_t mailbox1; 340 uint16_t mailbox2; 341 uint16_t mailbox3; 342 uint16_t mailbox4; 343 uint16_t mailbox5; 344 uint16_t mailbox6; 345 uint16_t mailbox7; 346 uint16_t unused_2[59]; /* Gap */ 347 } __attribute__((packed)) isp2100; 348 struct { 349 /* Request Queue */ 350 uint16_t req_q_in; /* In-Pointer */ 351 uint16_t req_q_out; /* Out-Pointer */ 352 /* Response Queue */ 353 uint16_t rsp_q_in; /* In-Pointer */ 354 uint16_t rsp_q_out; /* Out-Pointer */ 355 356 /* RISC to Host Status */ 357 uint32_t host_status; 358 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 359 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 360 361 /* Host to Host Semaphore */ 362 uint16_t host_semaphore; 363 uint16_t unused_3[17]; /* Gap */ 364 uint16_t mailbox0; 365 uint16_t mailbox1; 366 uint16_t mailbox2; 367 uint16_t mailbox3; 368 uint16_t mailbox4; 369 uint16_t mailbox5; 370 uint16_t mailbox6; 371 uint16_t mailbox7; 372 uint16_t mailbox8; 373 uint16_t mailbox9; 374 uint16_t mailbox10; 375 uint16_t mailbox11; 376 uint16_t mailbox12; 377 uint16_t mailbox13; 378 uint16_t mailbox14; 379 uint16_t mailbox15; 380 uint16_t mailbox16; 381 uint16_t mailbox17; 382 uint16_t mailbox18; 383 uint16_t mailbox19; 384 uint16_t mailbox20; 385 uint16_t mailbox21; 386 uint16_t mailbox22; 387 uint16_t mailbox23; 388 uint16_t mailbox24; 389 uint16_t mailbox25; 390 uint16_t mailbox26; 391 uint16_t mailbox27; 392 uint16_t mailbox28; 393 uint16_t mailbox29; 394 uint16_t mailbox30; 395 uint16_t mailbox31; 396 uint16_t fb_cmd; 397 uint16_t unused_4[10]; /* Gap */ 398 } __attribute__((packed)) isp2300; 399 } u; 400 401 uint16_t fpm_diag_config; 402 uint16_t unused_5[0x6]; /* Gap */ 403 uint16_t pcr; /* Processor Control Register. */ 404 uint16_t unused_6[0x5]; /* Gap */ 405 uint16_t mctr; /* Memory Configuration and Timing. */ 406 uint16_t unused_7[0x3]; /* Gap */ 407 uint16_t fb_cmd_2100; /* Unused on 23XX */ 408 uint16_t unused_8[0x3]; /* Gap */ 409 uint16_t hccr; /* Host command & control register. */ 410 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 411 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 412 /* HCCR commands */ 413 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 414 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 415 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 416 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 417 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 418 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 419 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 420 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 421 422 uint16_t unused_9[5]; /* Gap */ 423 uint16_t gpiod; /* GPIO Data register. */ 424 uint16_t gpioe; /* GPIO Enable register. */ 425 #define GPIO_LED_MASK 0x00C0 426 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 427 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 428 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 429 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 430 431 union { 432 struct { 433 uint16_t unused_10[8]; /* Gap */ 434 uint16_t mailbox8; 435 uint16_t mailbox9; 436 uint16_t mailbox10; 437 uint16_t mailbox11; 438 uint16_t mailbox12; 439 uint16_t mailbox13; 440 uint16_t mailbox14; 441 uint16_t mailbox15; 442 uint16_t mailbox16; 443 uint16_t mailbox17; 444 uint16_t mailbox18; 445 uint16_t mailbox19; 446 uint16_t mailbox20; 447 uint16_t mailbox21; 448 uint16_t mailbox22; 449 uint16_t mailbox23; /* Also probe reg. */ 450 } __attribute__((packed)) isp2200; 451 } u_end; 452 }; 453 454 typedef union { 455 struct device_reg_2xxx isp; 456 struct device_reg_24xx isp24; 457 } device_reg_t; 458 459 #define ISP_REQ_Q_IN(ha, reg) \ 460 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 461 &(reg)->u.isp2100.mailbox4 : \ 462 &(reg)->u.isp2300.req_q_in) 463 #define ISP_REQ_Q_OUT(ha, reg) \ 464 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 465 &(reg)->u.isp2100.mailbox4 : \ 466 &(reg)->u.isp2300.req_q_out) 467 #define ISP_RSP_Q_IN(ha, reg) \ 468 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 469 &(reg)->u.isp2100.mailbox5 : \ 470 &(reg)->u.isp2300.rsp_q_in) 471 #define ISP_RSP_Q_OUT(ha, reg) \ 472 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 473 &(reg)->u.isp2100.mailbox5 : \ 474 &(reg)->u.isp2300.rsp_q_out) 475 476 #define MAILBOX_REG(ha, reg, num) \ 477 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 478 (num < 8 ? \ 479 &(reg)->u.isp2100.mailbox0 + (num) : \ 480 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 481 &(reg)->u.isp2300.mailbox0 + (num)) 482 #define RD_MAILBOX_REG(ha, reg, num) \ 483 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 484 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 485 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 486 487 #define FB_CMD_REG(ha, reg) \ 488 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 489 &(reg)->fb_cmd_2100 : \ 490 &(reg)->u.isp2300.fb_cmd) 491 #define RD_FB_CMD_REG(ha, reg) \ 492 RD_REG_WORD(FB_CMD_REG(ha, reg)) 493 #define WRT_FB_CMD_REG(ha, reg, data) \ 494 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 495 496 typedef struct { 497 uint32_t out_mb; /* outbound from driver */ 498 uint32_t in_mb; /* Incoming from RISC */ 499 uint16_t mb[MAILBOX_REGISTER_COUNT]; 500 long buf_size; 501 void *bufp; 502 uint32_t tov; 503 uint8_t flags; 504 #define MBX_DMA_IN BIT_0 505 #define MBX_DMA_OUT BIT_1 506 #define IOCTL_CMD BIT_2 507 } mbx_cmd_t; 508 509 #define MBX_TOV_SECONDS 30 510 511 /* 512 * ISP product identification definitions in mailboxes after reset. 513 */ 514 #define PROD_ID_1 0x4953 515 #define PROD_ID_2 0x0000 516 #define PROD_ID_2a 0x5020 517 #define PROD_ID_3 0x2020 518 519 /* 520 * ISP mailbox Self-Test status codes 521 */ 522 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 523 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 524 #define MBS_BUSY 4 /* Busy. */ 525 526 /* 527 * ISP mailbox command complete status codes 528 */ 529 #define MBS_COMMAND_COMPLETE 0x4000 530 #define MBS_INVALID_COMMAND 0x4001 531 #define MBS_HOST_INTERFACE_ERROR 0x4002 532 #define MBS_TEST_FAILED 0x4003 533 #define MBS_COMMAND_ERROR 0x4005 534 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 535 #define MBS_PORT_ID_USED 0x4007 536 #define MBS_LOOP_ID_USED 0x4008 537 #define MBS_ALL_IDS_IN_USE 0x4009 538 #define MBS_NOT_LOGGED_IN 0x400A 539 #define MBS_LINK_DOWN_ERROR 0x400B 540 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 541 542 /* 543 * ISP mailbox asynchronous event status codes 544 */ 545 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 546 #define MBA_RESET 0x8001 /* Reset Detected. */ 547 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 548 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 549 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 550 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 551 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 552 /* occurred. */ 553 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 554 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 555 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 556 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 557 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 558 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 559 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 560 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 561 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 562 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 563 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 564 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 565 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 566 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 567 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 568 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 569 /* used. */ 570 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 571 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 572 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 573 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 574 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 575 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 576 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 577 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 578 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 579 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 580 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 581 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 582 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 583 584 /* 585 * Firmware options 1, 2, 3. 586 */ 587 #define FO1_AE_ON_LIPF8 BIT_0 588 #define FO1_AE_ALL_LIP_RESET BIT_1 589 #define FO1_CTIO_RETRY BIT_3 590 #define FO1_DISABLE_LIP_F7_SW BIT_4 591 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 592 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 593 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 594 #define FO1_SET_EMPHASIS_SWING BIT_8 595 #define FO1_AE_AUTO_BYPASS BIT_9 596 #define FO1_ENABLE_PURE_IOCB BIT_10 597 #define FO1_AE_PLOGI_RJT BIT_11 598 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 599 #define FO1_AE_QUEUE_FULL BIT_13 600 601 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 602 #define FO2_REV_LOOPBACK BIT_1 603 604 #define FO3_ENABLE_EMERG_IOCB BIT_0 605 #define FO3_AE_RND_ERROR BIT_1 606 607 /* 24XX additional firmware options */ 608 #define ADD_FO_COUNT 3 609 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 610 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 611 612 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 613 614 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 615 616 /* 617 * ISP mailbox commands 618 */ 619 #define MBC_LOAD_RAM 1 /* Load RAM. */ 620 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 621 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 622 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 623 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 624 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 625 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 626 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 627 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 628 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 629 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 630 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 631 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 632 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 633 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 634 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 635 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 636 #define MBC_RESET 0x18 /* Reset. */ 637 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 638 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 639 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 640 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 641 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 642 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 643 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 644 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 645 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 646 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 647 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 648 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 649 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 650 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 651 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 652 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 653 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 654 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 655 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */ 656 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */ 657 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 658 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 659 /* Initialization Procedure */ 660 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 661 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 662 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 663 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 664 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 665 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 666 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 667 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 668 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 669 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 670 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 671 /* commandd. */ 672 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 673 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 674 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 675 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 676 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 677 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 678 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 679 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 680 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 681 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 682 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 683 684 /* 685 * ISP24xx mailbox commands 686 */ 687 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 688 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 689 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 690 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 691 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 692 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 693 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 694 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 695 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 696 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 697 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 698 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 699 700 /* Firmware return data sizes */ 701 #define FCAL_MAP_SIZE 128 702 703 /* Mailbox bit definitions for out_mb and in_mb */ 704 #define MBX_31 BIT_31 705 #define MBX_30 BIT_30 706 #define MBX_29 BIT_29 707 #define MBX_28 BIT_28 708 #define MBX_27 BIT_27 709 #define MBX_26 BIT_26 710 #define MBX_25 BIT_25 711 #define MBX_24 BIT_24 712 #define MBX_23 BIT_23 713 #define MBX_22 BIT_22 714 #define MBX_21 BIT_21 715 #define MBX_20 BIT_20 716 #define MBX_19 BIT_19 717 #define MBX_18 BIT_18 718 #define MBX_17 BIT_17 719 #define MBX_16 BIT_16 720 #define MBX_15 BIT_15 721 #define MBX_14 BIT_14 722 #define MBX_13 BIT_13 723 #define MBX_12 BIT_12 724 #define MBX_11 BIT_11 725 #define MBX_10 BIT_10 726 #define MBX_9 BIT_9 727 #define MBX_8 BIT_8 728 #define MBX_7 BIT_7 729 #define MBX_6 BIT_6 730 #define MBX_5 BIT_5 731 #define MBX_4 BIT_4 732 #define MBX_3 BIT_3 733 #define MBX_2 BIT_2 734 #define MBX_1 BIT_1 735 #define MBX_0 BIT_0 736 737 /* 738 * Firmware state codes from get firmware state mailbox command 739 */ 740 #define FSTATE_CONFIG_WAIT 0 741 #define FSTATE_WAIT_AL_PA 1 742 #define FSTATE_WAIT_LOGIN 2 743 #define FSTATE_READY 3 744 #define FSTATE_LOSS_OF_SYNC 4 745 #define FSTATE_ERROR 5 746 #define FSTATE_REINIT 6 747 #define FSTATE_NON_PART 7 748 749 #define FSTATE_CONFIG_CORRECT 0 750 #define FSTATE_P2P_RCV_LIP 1 751 #define FSTATE_P2P_CHOOSE_LOOP 2 752 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 753 #define FSTATE_FATAL_ERROR 4 754 #define FSTATE_LOOP_BACK_CONN 5 755 756 /* 757 * Port Database structure definition 758 * Little endian except where noted. 759 */ 760 #define PORT_DATABASE_SIZE 128 /* bytes */ 761 typedef struct { 762 uint8_t options; 763 uint8_t control; 764 uint8_t master_state; 765 uint8_t slave_state; 766 uint8_t reserved[2]; 767 uint8_t hard_address; 768 uint8_t reserved_1; 769 uint8_t port_id[4]; 770 uint8_t node_name[WWN_SIZE]; 771 uint8_t port_name[WWN_SIZE]; 772 uint16_t execution_throttle; 773 uint16_t execution_count; 774 uint8_t reset_count; 775 uint8_t reserved_2; 776 uint16_t resource_allocation; 777 uint16_t current_allocation; 778 uint16_t queue_head; 779 uint16_t queue_tail; 780 uint16_t transmit_execution_list_next; 781 uint16_t transmit_execution_list_previous; 782 uint16_t common_features; 783 uint16_t total_concurrent_sequences; 784 uint16_t RO_by_information_category; 785 uint8_t recipient; 786 uint8_t initiator; 787 uint16_t receive_data_size; 788 uint16_t concurrent_sequences; 789 uint16_t open_sequences_per_exchange; 790 uint16_t lun_abort_flags; 791 uint16_t lun_stop_flags; 792 uint16_t stop_queue_head; 793 uint16_t stop_queue_tail; 794 uint16_t port_retry_timer; 795 uint16_t next_sequence_id; 796 uint16_t frame_count; 797 uint16_t PRLI_payload_length; 798 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 799 /* Bits 15-0 of word 0 */ 800 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 801 /* Bits 15-0 of word 3 */ 802 uint16_t loop_id; 803 uint16_t extended_lun_info_list_pointer; 804 uint16_t extended_lun_stop_list_pointer; 805 } port_database_t; 806 807 /* 808 * Port database slave/master states 809 */ 810 #define PD_STATE_DISCOVERY 0 811 #define PD_STATE_WAIT_DISCOVERY_ACK 1 812 #define PD_STATE_PORT_LOGIN 2 813 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 814 #define PD_STATE_PROCESS_LOGIN 4 815 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 816 #define PD_STATE_PORT_LOGGED_IN 6 817 #define PD_STATE_PORT_UNAVAILABLE 7 818 #define PD_STATE_PROCESS_LOGOUT 8 819 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 820 #define PD_STATE_PORT_LOGOUT 10 821 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 822 823 824 /* 825 * ISP Initialization Control Block. 826 * Little endian except where noted. 827 */ 828 #define ICB_VERSION 1 829 typedef struct { 830 uint8_t version; 831 uint8_t reserved_1; 832 833 /* 834 * LSB BIT 0 = Enable Hard Loop Id 835 * LSB BIT 1 = Enable Fairness 836 * LSB BIT 2 = Enable Full-Duplex 837 * LSB BIT 3 = Enable Fast Posting 838 * LSB BIT 4 = Enable Target Mode 839 * LSB BIT 5 = Disable Initiator Mode 840 * LSB BIT 6 = Enable ADISC 841 * LSB BIT 7 = Enable Target Inquiry Data 842 * 843 * MSB BIT 0 = Enable PDBC Notify 844 * MSB BIT 1 = Non Participating LIP 845 * MSB BIT 2 = Descending Loop ID Search 846 * MSB BIT 3 = Acquire Loop ID in LIPA 847 * MSB BIT 4 = Stop PortQ on Full Status 848 * MSB BIT 5 = Full Login after LIP 849 * MSB BIT 6 = Node Name Option 850 * MSB BIT 7 = Ext IFWCB enable bit 851 */ 852 uint8_t firmware_options[2]; 853 854 uint16_t frame_payload_size; 855 uint16_t max_iocb_allocation; 856 uint16_t execution_throttle; 857 uint8_t retry_count; 858 uint8_t retry_delay; /* unused */ 859 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 860 uint16_t hard_address; 861 uint8_t inquiry_data; 862 uint8_t login_timeout; 863 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 864 865 uint16_t request_q_outpointer; 866 uint16_t response_q_inpointer; 867 uint16_t request_q_length; 868 uint16_t response_q_length; 869 uint32_t request_q_address[2]; 870 uint32_t response_q_address[2]; 871 872 uint16_t lun_enables; 873 uint8_t command_resource_count; 874 uint8_t immediate_notify_resource_count; 875 uint16_t timeout; 876 uint8_t reserved_2[2]; 877 878 /* 879 * LSB BIT 0 = Timer Operation mode bit 0 880 * LSB BIT 1 = Timer Operation mode bit 1 881 * LSB BIT 2 = Timer Operation mode bit 2 882 * LSB BIT 3 = Timer Operation mode bit 3 883 * LSB BIT 4 = Init Config Mode bit 0 884 * LSB BIT 5 = Init Config Mode bit 1 885 * LSB BIT 6 = Init Config Mode bit 2 886 * LSB BIT 7 = Enable Non part on LIHA failure 887 * 888 * MSB BIT 0 = Enable class 2 889 * MSB BIT 1 = Enable ACK0 890 * MSB BIT 2 = 891 * MSB BIT 3 = 892 * MSB BIT 4 = FC Tape Enable 893 * MSB BIT 5 = Enable FC Confirm 894 * MSB BIT 6 = Enable command queuing in target mode 895 * MSB BIT 7 = No Logo On Link Down 896 */ 897 uint8_t add_firmware_options[2]; 898 899 uint8_t response_accumulation_timer; 900 uint8_t interrupt_delay_timer; 901 902 /* 903 * LSB BIT 0 = Enable Read xfr_rdy 904 * LSB BIT 1 = Soft ID only 905 * LSB BIT 2 = 906 * LSB BIT 3 = 907 * LSB BIT 4 = FCP RSP Payload [0] 908 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 909 * LSB BIT 6 = Enable Out-of-Order frame handling 910 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 911 * 912 * MSB BIT 0 = Sbus enable - 2300 913 * MSB BIT 1 = 914 * MSB BIT 2 = 915 * MSB BIT 3 = 916 * MSB BIT 4 = 917 * MSB BIT 5 = enable 50 ohm termination 918 * MSB BIT 6 = Data Rate (2300 only) 919 * MSB BIT 7 = Data Rate (2300 only) 920 */ 921 uint8_t special_options[2]; 922 923 uint8_t reserved_3[26]; 924 } init_cb_t; 925 926 /* 927 * Get Link Status mailbox command return buffer. 928 */ 929 #define GLSO_SEND_RPS BIT_0 930 #define GLSO_USE_DID BIT_3 931 932 typedef struct { 933 uint32_t link_fail_cnt; 934 uint32_t loss_sync_cnt; 935 uint32_t loss_sig_cnt; 936 uint32_t prim_seq_err_cnt; 937 uint32_t inval_xmit_word_cnt; 938 uint32_t inval_crc_cnt; 939 } link_stat_t; 940 941 /* 942 * NVRAM Command values. 943 */ 944 #define NV_START_BIT BIT_2 945 #define NV_WRITE_OP (BIT_26+BIT_24) 946 #define NV_READ_OP (BIT_26+BIT_25) 947 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 948 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 949 #define NV_DELAY_COUNT 10 950 951 /* 952 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 953 */ 954 typedef struct { 955 /* 956 * NVRAM header 957 */ 958 uint8_t id[4]; 959 uint8_t nvram_version; 960 uint8_t reserved_0; 961 962 /* 963 * NVRAM RISC parameter block 964 */ 965 uint8_t parameter_block_version; 966 uint8_t reserved_1; 967 968 /* 969 * LSB BIT 0 = Enable Hard Loop Id 970 * LSB BIT 1 = Enable Fairness 971 * LSB BIT 2 = Enable Full-Duplex 972 * LSB BIT 3 = Enable Fast Posting 973 * LSB BIT 4 = Enable Target Mode 974 * LSB BIT 5 = Disable Initiator Mode 975 * LSB BIT 6 = Enable ADISC 976 * LSB BIT 7 = Enable Target Inquiry Data 977 * 978 * MSB BIT 0 = Enable PDBC Notify 979 * MSB BIT 1 = Non Participating LIP 980 * MSB BIT 2 = Descending Loop ID Search 981 * MSB BIT 3 = Acquire Loop ID in LIPA 982 * MSB BIT 4 = Stop PortQ on Full Status 983 * MSB BIT 5 = Full Login after LIP 984 * MSB BIT 6 = Node Name Option 985 * MSB BIT 7 = Ext IFWCB enable bit 986 */ 987 uint8_t firmware_options[2]; 988 989 uint16_t frame_payload_size; 990 uint16_t max_iocb_allocation; 991 uint16_t execution_throttle; 992 uint8_t retry_count; 993 uint8_t retry_delay; /* unused */ 994 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 995 uint16_t hard_address; 996 uint8_t inquiry_data; 997 uint8_t login_timeout; 998 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 999 1000 /* 1001 * LSB BIT 0 = Timer Operation mode bit 0 1002 * LSB BIT 1 = Timer Operation mode bit 1 1003 * LSB BIT 2 = Timer Operation mode bit 2 1004 * LSB BIT 3 = Timer Operation mode bit 3 1005 * LSB BIT 4 = Init Config Mode bit 0 1006 * LSB BIT 5 = Init Config Mode bit 1 1007 * LSB BIT 6 = Init Config Mode bit 2 1008 * LSB BIT 7 = Enable Non part on LIHA failure 1009 * 1010 * MSB BIT 0 = Enable class 2 1011 * MSB BIT 1 = Enable ACK0 1012 * MSB BIT 2 = 1013 * MSB BIT 3 = 1014 * MSB BIT 4 = FC Tape Enable 1015 * MSB BIT 5 = Enable FC Confirm 1016 * MSB BIT 6 = Enable command queuing in target mode 1017 * MSB BIT 7 = No Logo On Link Down 1018 */ 1019 uint8_t add_firmware_options[2]; 1020 1021 uint8_t response_accumulation_timer; 1022 uint8_t interrupt_delay_timer; 1023 1024 /* 1025 * LSB BIT 0 = Enable Read xfr_rdy 1026 * LSB BIT 1 = Soft ID only 1027 * LSB BIT 2 = 1028 * LSB BIT 3 = 1029 * LSB BIT 4 = FCP RSP Payload [0] 1030 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1031 * LSB BIT 6 = Enable Out-of-Order frame handling 1032 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1033 * 1034 * MSB BIT 0 = Sbus enable - 2300 1035 * MSB BIT 1 = 1036 * MSB BIT 2 = 1037 * MSB BIT 3 = 1038 * MSB BIT 4 = 1039 * MSB BIT 5 = enable 50 ohm termination 1040 * MSB BIT 6 = Data Rate (2300 only) 1041 * MSB BIT 7 = Data Rate (2300 only) 1042 */ 1043 uint8_t special_options[2]; 1044 1045 /* Reserved for expanded RISC parameter block */ 1046 uint8_t reserved_2[22]; 1047 1048 /* 1049 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1050 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1051 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1052 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1053 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1054 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1055 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1056 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1057 * 1058 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1059 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1060 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1061 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1062 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1063 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1064 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1065 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1066 * 1067 * LSB BIT 0 = Output Swing 1G bit 0 1068 * LSB BIT 1 = Output Swing 1G bit 1 1069 * LSB BIT 2 = Output Swing 1G bit 2 1070 * LSB BIT 3 = Output Emphasis 1G bit 0 1071 * LSB BIT 4 = Output Emphasis 1G bit 1 1072 * LSB BIT 5 = Output Swing 2G bit 0 1073 * LSB BIT 6 = Output Swing 2G bit 1 1074 * LSB BIT 7 = Output Swing 2G bit 2 1075 * 1076 * MSB BIT 0 = Output Emphasis 2G bit 0 1077 * MSB BIT 1 = Output Emphasis 2G bit 1 1078 * MSB BIT 2 = Output Enable 1079 * MSB BIT 3 = 1080 * MSB BIT 4 = 1081 * MSB BIT 5 = 1082 * MSB BIT 6 = 1083 * MSB BIT 7 = 1084 */ 1085 uint8_t seriallink_options[4]; 1086 1087 /* 1088 * NVRAM host parameter block 1089 * 1090 * LSB BIT 0 = Enable spinup delay 1091 * LSB BIT 1 = Disable BIOS 1092 * LSB BIT 2 = Enable Memory Map BIOS 1093 * LSB BIT 3 = Enable Selectable Boot 1094 * LSB BIT 4 = Disable RISC code load 1095 * LSB BIT 5 = Set cache line size 1 1096 * LSB BIT 6 = PCI Parity Disable 1097 * LSB BIT 7 = Enable extended logging 1098 * 1099 * MSB BIT 0 = Enable 64bit addressing 1100 * MSB BIT 1 = Enable lip reset 1101 * MSB BIT 2 = Enable lip full login 1102 * MSB BIT 3 = Enable target reset 1103 * MSB BIT 4 = Enable database storage 1104 * MSB BIT 5 = Enable cache flush read 1105 * MSB BIT 6 = Enable database load 1106 * MSB BIT 7 = Enable alternate WWN 1107 */ 1108 uint8_t host_p[2]; 1109 1110 uint8_t boot_node_name[WWN_SIZE]; 1111 uint8_t boot_lun_number; 1112 uint8_t reset_delay; 1113 uint8_t port_down_retry_count; 1114 uint8_t boot_id_number; 1115 uint16_t max_luns_per_target; 1116 uint8_t fcode_boot_port_name[WWN_SIZE]; 1117 uint8_t alternate_port_name[WWN_SIZE]; 1118 uint8_t alternate_node_name[WWN_SIZE]; 1119 1120 /* 1121 * BIT 0 = Selective Login 1122 * BIT 1 = Alt-Boot Enable 1123 * BIT 2 = 1124 * BIT 3 = Boot Order List 1125 * BIT 4 = 1126 * BIT 5 = Selective LUN 1127 * BIT 6 = 1128 * BIT 7 = unused 1129 */ 1130 uint8_t efi_parameters; 1131 1132 uint8_t link_down_timeout; 1133 1134 uint8_t adapter_id_0[4]; 1135 uint8_t adapter_id_1[4]; 1136 uint8_t adapter_id_2[4]; 1137 uint8_t adapter_id_3[4]; 1138 1139 uint8_t alt1_boot_node_name[WWN_SIZE]; 1140 uint16_t alt1_boot_lun_number; 1141 uint8_t alt2_boot_node_name[WWN_SIZE]; 1142 uint16_t alt2_boot_lun_number; 1143 uint8_t alt3_boot_node_name[WWN_SIZE]; 1144 uint16_t alt3_boot_lun_number; 1145 uint8_t alt4_boot_node_name[WWN_SIZE]; 1146 uint16_t alt4_boot_lun_number; 1147 uint8_t alt5_boot_node_name[WWN_SIZE]; 1148 uint16_t alt5_boot_lun_number; 1149 uint8_t alt6_boot_node_name[WWN_SIZE]; 1150 uint16_t alt6_boot_lun_number; 1151 uint8_t alt7_boot_node_name[WWN_SIZE]; 1152 uint16_t alt7_boot_lun_number; 1153 1154 uint8_t reserved_3[2]; 1155 1156 /* Offset 200-215 : Model Number */ 1157 uint8_t model_number[16]; 1158 1159 /* OEM related items */ 1160 uint8_t oem_specific[16]; 1161 1162 /* 1163 * NVRAM Adapter Features offset 232-239 1164 * 1165 * LSB BIT 0 = External GBIC 1166 * LSB BIT 1 = Risc RAM parity 1167 * LSB BIT 2 = Buffer Plus Module 1168 * LSB BIT 3 = Multi Chip Adapter 1169 * LSB BIT 4 = Internal connector 1170 * LSB BIT 5 = 1171 * LSB BIT 6 = 1172 * LSB BIT 7 = 1173 * 1174 * MSB BIT 0 = 1175 * MSB BIT 1 = 1176 * MSB BIT 2 = 1177 * MSB BIT 3 = 1178 * MSB BIT 4 = 1179 * MSB BIT 5 = 1180 * MSB BIT 6 = 1181 * MSB BIT 7 = 1182 */ 1183 uint8_t adapter_features[2]; 1184 1185 uint8_t reserved_4[16]; 1186 1187 /* Subsystem vendor ID for ISP2200 */ 1188 uint16_t subsystem_vendor_id_2200; 1189 1190 /* Subsystem device ID for ISP2200 */ 1191 uint16_t subsystem_device_id_2200; 1192 1193 uint8_t reserved_5; 1194 uint8_t checksum; 1195 } nvram_t; 1196 1197 /* 1198 * ISP queue - response queue entry definition. 1199 */ 1200 typedef struct { 1201 uint8_t data[60]; 1202 uint32_t signature; 1203 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1204 } response_t; 1205 1206 typedef union { 1207 uint16_t extended; 1208 struct { 1209 uint8_t reserved; 1210 uint8_t standard; 1211 } id; 1212 } target_id_t; 1213 1214 #define SET_TARGET_ID(ha, to, from) \ 1215 do { \ 1216 if (HAS_EXTENDED_IDS(ha)) \ 1217 to.extended = cpu_to_le16(from); \ 1218 else \ 1219 to.id.standard = (uint8_t)from; \ 1220 } while (0) 1221 1222 /* 1223 * ISP queue - command entry structure definition. 1224 */ 1225 #define COMMAND_TYPE 0x11 /* Command entry */ 1226 typedef struct { 1227 uint8_t entry_type; /* Entry type. */ 1228 uint8_t entry_count; /* Entry count. */ 1229 uint8_t sys_define; /* System defined. */ 1230 uint8_t entry_status; /* Entry Status. */ 1231 uint32_t handle; /* System handle. */ 1232 target_id_t target; /* SCSI ID */ 1233 uint16_t lun; /* SCSI LUN */ 1234 uint16_t control_flags; /* Control flags. */ 1235 #define CF_WRITE BIT_6 1236 #define CF_READ BIT_5 1237 #define CF_SIMPLE_TAG BIT_3 1238 #define CF_ORDERED_TAG BIT_2 1239 #define CF_HEAD_TAG BIT_1 1240 uint16_t reserved_1; 1241 uint16_t timeout; /* Command timeout. */ 1242 uint16_t dseg_count; /* Data segment count. */ 1243 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1244 uint32_t byte_count; /* Total byte count. */ 1245 uint32_t dseg_0_address; /* Data segment 0 address. */ 1246 uint32_t dseg_0_length; /* Data segment 0 length. */ 1247 uint32_t dseg_1_address; /* Data segment 1 address. */ 1248 uint32_t dseg_1_length; /* Data segment 1 length. */ 1249 uint32_t dseg_2_address; /* Data segment 2 address. */ 1250 uint32_t dseg_2_length; /* Data segment 2 length. */ 1251 } cmd_entry_t; 1252 1253 /* 1254 * ISP queue - 64-Bit addressing, command entry structure definition. 1255 */ 1256 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1257 typedef struct { 1258 uint8_t entry_type; /* Entry type. */ 1259 uint8_t entry_count; /* Entry count. */ 1260 uint8_t sys_define; /* System defined. */ 1261 uint8_t entry_status; /* Entry Status. */ 1262 uint32_t handle; /* System handle. */ 1263 target_id_t target; /* SCSI ID */ 1264 uint16_t lun; /* SCSI LUN */ 1265 uint16_t control_flags; /* Control flags. */ 1266 uint16_t reserved_1; 1267 uint16_t timeout; /* Command timeout. */ 1268 uint16_t dseg_count; /* Data segment count. */ 1269 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1270 uint32_t byte_count; /* Total byte count. */ 1271 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1272 uint32_t dseg_0_length; /* Data segment 0 length. */ 1273 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1274 uint32_t dseg_1_length; /* Data segment 1 length. */ 1275 } cmd_a64_entry_t, request_t; 1276 1277 /* 1278 * ISP queue - continuation entry structure definition. 1279 */ 1280 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1281 typedef struct { 1282 uint8_t entry_type; /* Entry type. */ 1283 uint8_t entry_count; /* Entry count. */ 1284 uint8_t sys_define; /* System defined. */ 1285 uint8_t entry_status; /* Entry Status. */ 1286 uint32_t reserved; 1287 uint32_t dseg_0_address; /* Data segment 0 address. */ 1288 uint32_t dseg_0_length; /* Data segment 0 length. */ 1289 uint32_t dseg_1_address; /* Data segment 1 address. */ 1290 uint32_t dseg_1_length; /* Data segment 1 length. */ 1291 uint32_t dseg_2_address; /* Data segment 2 address. */ 1292 uint32_t dseg_2_length; /* Data segment 2 length. */ 1293 uint32_t dseg_3_address; /* Data segment 3 address. */ 1294 uint32_t dseg_3_length; /* Data segment 3 length. */ 1295 uint32_t dseg_4_address; /* Data segment 4 address. */ 1296 uint32_t dseg_4_length; /* Data segment 4 length. */ 1297 uint32_t dseg_5_address; /* Data segment 5 address. */ 1298 uint32_t dseg_5_length; /* Data segment 5 length. */ 1299 uint32_t dseg_6_address; /* Data segment 6 address. */ 1300 uint32_t dseg_6_length; /* Data segment 6 length. */ 1301 } cont_entry_t; 1302 1303 /* 1304 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1305 */ 1306 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1307 typedef struct { 1308 uint8_t entry_type; /* Entry type. */ 1309 uint8_t entry_count; /* Entry count. */ 1310 uint8_t sys_define; /* System defined. */ 1311 uint8_t entry_status; /* Entry Status. */ 1312 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1313 uint32_t dseg_0_length; /* Data segment 0 length. */ 1314 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1315 uint32_t dseg_1_length; /* Data segment 1 length. */ 1316 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1317 uint32_t dseg_2_length; /* Data segment 2 length. */ 1318 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1319 uint32_t dseg_3_length; /* Data segment 3 length. */ 1320 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1321 uint32_t dseg_4_length; /* Data segment 4 length. */ 1322 } cont_a64_entry_t; 1323 1324 /* 1325 * ISP queue - status entry structure definition. 1326 */ 1327 #define STATUS_TYPE 0x03 /* Status entry. */ 1328 typedef struct { 1329 uint8_t entry_type; /* Entry type. */ 1330 uint8_t entry_count; /* Entry count. */ 1331 uint8_t sys_define; /* System defined. */ 1332 uint8_t entry_status; /* Entry Status. */ 1333 uint32_t handle; /* System handle. */ 1334 uint16_t scsi_status; /* SCSI status. */ 1335 uint16_t comp_status; /* Completion status. */ 1336 uint16_t state_flags; /* State flags. */ 1337 uint16_t status_flags; /* Status flags. */ 1338 uint16_t rsp_info_len; /* Response Info Length. */ 1339 uint16_t req_sense_length; /* Request sense data length. */ 1340 uint32_t residual_length; /* Residual transfer length. */ 1341 uint8_t rsp_info[8]; /* FCP response information. */ 1342 uint8_t req_sense_data[32]; /* Request sense data. */ 1343 } sts_entry_t; 1344 1345 /* 1346 * Status entry entry status 1347 */ 1348 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1349 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1350 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1351 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1352 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1353 #define RF_BUSY BIT_1 /* Busy */ 1354 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1355 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1356 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1357 RF_INV_E_TYPE) 1358 1359 /* 1360 * Status entry SCSI status bit definitions. 1361 */ 1362 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1363 #define SS_RESIDUAL_UNDER BIT_11 1364 #define SS_RESIDUAL_OVER BIT_10 1365 #define SS_SENSE_LEN_VALID BIT_9 1366 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1367 1368 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1369 #define SS_BUSY_CONDITION BIT_3 1370 #define SS_CONDITION_MET BIT_2 1371 #define SS_CHECK_CONDITION BIT_1 1372 1373 /* 1374 * Status entry completion status 1375 */ 1376 #define CS_COMPLETE 0x0 /* No errors */ 1377 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1378 #define CS_DMA 0x2 /* A DMA direction error. */ 1379 #define CS_TRANSPORT 0x3 /* Transport error. */ 1380 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1381 #define CS_ABORTED 0x5 /* System aborted command. */ 1382 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1383 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1384 1385 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1386 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1387 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1388 /* (selection timeout) */ 1389 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1390 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1391 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1392 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1393 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1394 #define CS_UNKNOWN 0x81 /* Driver defined */ 1395 #define CS_RETRY 0x82 /* Driver defined */ 1396 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1397 1398 /* 1399 * Status entry status flags 1400 */ 1401 #define SF_ABTS_TERMINATED BIT_10 1402 #define SF_LOGOUT_SENT BIT_13 1403 1404 /* 1405 * ISP queue - status continuation entry structure definition. 1406 */ 1407 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1408 typedef struct { 1409 uint8_t entry_type; /* Entry type. */ 1410 uint8_t entry_count; /* Entry count. */ 1411 uint8_t sys_define; /* System defined. */ 1412 uint8_t entry_status; /* Entry Status. */ 1413 uint8_t data[60]; /* data */ 1414 } sts_cont_entry_t; 1415 1416 /* 1417 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1418 * structure definition. 1419 */ 1420 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1421 typedef struct { 1422 uint8_t entry_type; /* Entry type. */ 1423 uint8_t entry_count; /* Entry count. */ 1424 uint8_t handle_count; /* Handle count. */ 1425 uint8_t entry_status; /* Entry Status. */ 1426 uint32_t handle[15]; /* System handles. */ 1427 } sts21_entry_t; 1428 1429 /* 1430 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1431 * structure definition. 1432 */ 1433 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1434 typedef struct { 1435 uint8_t entry_type; /* Entry type. */ 1436 uint8_t entry_count; /* Entry count. */ 1437 uint8_t handle_count; /* Handle count. */ 1438 uint8_t entry_status; /* Entry Status. */ 1439 uint16_t handle[30]; /* System handles. */ 1440 } sts22_entry_t; 1441 1442 /* 1443 * ISP queue - marker entry structure definition. 1444 */ 1445 #define MARKER_TYPE 0x04 /* Marker entry. */ 1446 typedef struct { 1447 uint8_t entry_type; /* Entry type. */ 1448 uint8_t entry_count; /* Entry count. */ 1449 uint8_t handle_count; /* Handle count. */ 1450 uint8_t entry_status; /* Entry Status. */ 1451 uint32_t sys_define_2; /* System defined. */ 1452 target_id_t target; /* SCSI ID */ 1453 uint8_t modifier; /* Modifier (7-0). */ 1454 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1455 #define MK_SYNC_ID 1 /* Synchronize ID */ 1456 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1457 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1458 /* clear port changed, */ 1459 /* use sequence number. */ 1460 uint8_t reserved_1; 1461 uint16_t sequence_number; /* Sequence number of event */ 1462 uint16_t lun; /* SCSI LUN */ 1463 uint8_t reserved_2[48]; 1464 } mrk_entry_t; 1465 1466 /* 1467 * ISP queue - Management Server entry structure definition. 1468 */ 1469 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1470 typedef struct { 1471 uint8_t entry_type; /* Entry type. */ 1472 uint8_t entry_count; /* Entry count. */ 1473 uint8_t handle_count; /* Handle count. */ 1474 uint8_t entry_status; /* Entry Status. */ 1475 uint32_t handle1; /* System handle. */ 1476 target_id_t loop_id; 1477 uint16_t status; 1478 uint16_t control_flags; /* Control flags. */ 1479 uint16_t reserved2; 1480 uint16_t timeout; 1481 uint16_t cmd_dsd_count; 1482 uint16_t total_dsd_count; 1483 uint8_t type; 1484 uint8_t r_ctl; 1485 uint16_t rx_id; 1486 uint16_t reserved3; 1487 uint32_t handle2; 1488 uint32_t rsp_bytecount; 1489 uint32_t req_bytecount; 1490 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1491 uint32_t dseg_req_length; /* Data segment 0 length. */ 1492 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1493 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1494 } ms_iocb_entry_t; 1495 1496 1497 /* 1498 * ISP queue - Mailbox Command entry structure definition. 1499 */ 1500 #define MBX_IOCB_TYPE 0x39 1501 struct mbx_entry { 1502 uint8_t entry_type; 1503 uint8_t entry_count; 1504 uint8_t sys_define1; 1505 /* Use sys_define1 for source type */ 1506 #define SOURCE_SCSI 0x00 1507 #define SOURCE_IP 0x01 1508 #define SOURCE_VI 0x02 1509 #define SOURCE_SCTP 0x03 1510 #define SOURCE_MP 0x04 1511 #define SOURCE_MPIOCTL 0x05 1512 #define SOURCE_ASYNC_IOCB 0x07 1513 1514 uint8_t entry_status; 1515 1516 uint32_t handle; 1517 target_id_t loop_id; 1518 1519 uint16_t status; 1520 uint16_t state_flags; 1521 uint16_t status_flags; 1522 1523 uint32_t sys_define2[2]; 1524 1525 uint16_t mb0; 1526 uint16_t mb1; 1527 uint16_t mb2; 1528 uint16_t mb3; 1529 uint16_t mb6; 1530 uint16_t mb7; 1531 uint16_t mb9; 1532 uint16_t mb10; 1533 uint32_t reserved_2[2]; 1534 uint8_t node_name[WWN_SIZE]; 1535 uint8_t port_name[WWN_SIZE]; 1536 }; 1537 1538 /* 1539 * ISP request and response queue entry sizes 1540 */ 1541 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1542 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1543 1544 1545 /* 1546 * 24 bit port ID type definition. 1547 */ 1548 typedef union { 1549 uint32_t b24 : 24; 1550 1551 struct { 1552 uint8_t d_id[3]; 1553 uint8_t rsvd_1; 1554 } r; 1555 1556 struct { 1557 uint8_t al_pa; 1558 uint8_t area; 1559 uint8_t domain; 1560 uint8_t rsvd_1; 1561 } b; 1562 } port_id_t; 1563 #define INVALID_PORT_ID 0xFFFFFF 1564 1565 /* 1566 * Switch info gathering structure. 1567 */ 1568 typedef struct { 1569 port_id_t d_id; 1570 uint8_t node_name[WWN_SIZE]; 1571 uint8_t port_name[WWN_SIZE]; 1572 } sw_info_t; 1573 1574 /* 1575 * Inquiry command structure. 1576 */ 1577 #define INQ_DATA_SIZE 36 1578 1579 /* 1580 * Inquiry mailbox IOCB packet definition. 1581 */ 1582 typedef struct { 1583 union { 1584 cmd_a64_entry_t cmd; 1585 sts_entry_t rsp; 1586 struct cmd_type_7 cmd24; 1587 struct sts_entry_24xx rsp24; 1588 } p; 1589 uint8_t inq[INQ_DATA_SIZE]; 1590 } inq_cmd_rsp_t; 1591 1592 /* 1593 * Report LUN command structure. 1594 */ 1595 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a) 1596 1597 typedef struct { 1598 uint32_t len; 1599 uint32_t rsrv; 1600 } rpt_hdr_t; 1601 1602 typedef struct { 1603 struct { 1604 uint8_t b : 6; 1605 uint8_t address_method : 2; 1606 } msb; 1607 uint8_t lsb; 1608 uint8_t unused[6]; 1609 } rpt_lun_t; 1610 1611 typedef struct { 1612 rpt_hdr_t hdr; 1613 rpt_lun_t lst[MAX_LUNS]; 1614 } rpt_lun_lst_t; 1615 1616 /* 1617 * Report Lun mailbox IOCB packet definition. 1618 */ 1619 typedef struct { 1620 union { 1621 cmd_a64_entry_t cmd; 1622 sts_entry_t rsp; 1623 struct cmd_type_7 cmd24; 1624 struct sts_entry_24xx rsp24; 1625 } p; 1626 rpt_lun_lst_t list; 1627 } rpt_lun_cmd_rsp_t; 1628 1629 1630 /* 1631 * Fibre channel port type. 1632 */ 1633 typedef enum { 1634 FCT_UNKNOWN, 1635 FCT_RSCN, 1636 FCT_SWITCH, 1637 FCT_BROADCAST, 1638 FCT_INITIATOR, 1639 FCT_TARGET 1640 } fc_port_type_t; 1641 1642 /* 1643 * Fibre channel port structure. 1644 */ 1645 typedef struct fc_port { 1646 struct list_head list; 1647 struct scsi_qla_host *ha; 1648 struct scsi_qla_host *vis_ha; /* only used when suspending lun */ 1649 1650 uint8_t node_name[WWN_SIZE]; 1651 uint8_t port_name[WWN_SIZE]; 1652 port_id_t d_id; 1653 uint16_t loop_id; 1654 uint16_t old_loop_id; 1655 1656 fc_port_type_t port_type; 1657 1658 atomic_t state; 1659 uint32_t flags; 1660 1661 unsigned int os_target_id; 1662 1663 uint16_t iodesc_idx_sent; 1664 1665 int port_login_retry_count; 1666 int login_retry; 1667 atomic_t port_down_timer; 1668 1669 uint8_t device_type; 1670 uint8_t unused; 1671 1672 uint8_t mp_byte; /* multi-path byte (not used) */ 1673 uint8_t cur_path; /* current path id */ 1674 1675 struct fc_rport *rport; 1676 } fc_port_t; 1677 1678 /* 1679 * Fibre channel port/lun states. 1680 */ 1681 #define FCS_UNCONFIGURED 1 1682 #define FCS_DEVICE_DEAD 2 1683 #define FCS_DEVICE_LOST 3 1684 #define FCS_ONLINE 4 1685 #define FCS_NOT_SUPPORTED 5 1686 #define FCS_FAILOVER 6 1687 #define FCS_FAILOVER_FAILED 7 1688 1689 /* 1690 * FC port flags. 1691 */ 1692 #define FCF_FABRIC_DEVICE BIT_0 1693 #define FCF_LOGIN_NEEDED BIT_1 1694 #define FCF_FO_MASKED BIT_2 1695 #define FCF_FAILOVER_NEEDED BIT_3 1696 #define FCF_RESET_NEEDED BIT_4 1697 #define FCF_PERSISTENT_BOUND BIT_5 1698 #define FCF_TAPE_PRESENT BIT_6 1699 #define FCF_FARP_DONE BIT_7 1700 #define FCF_FARP_FAILED BIT_8 1701 #define FCF_FARP_REPLY_NEEDED BIT_9 1702 #define FCF_AUTH_REQ BIT_10 1703 #define FCF_SEND_AUTH_REQ BIT_11 1704 #define FCF_RECEIVE_AUTH_REQ BIT_12 1705 #define FCF_AUTH_SUCCESS BIT_13 1706 #define FCF_RLC_SUPPORT BIT_14 1707 #define FCF_CONFIG BIT_15 /* Needed? */ 1708 #define FCF_RESCAN_NEEDED BIT_16 1709 #define FCF_XP_DEVICE BIT_17 1710 #define FCF_MSA_DEVICE BIT_18 1711 #define FCF_EVA_DEVICE BIT_19 1712 #define FCF_MSA_PORT_ACTIVE BIT_20 1713 #define FCF_FAILBACK_DISABLE BIT_21 1714 #define FCF_FAILOVER_DISABLE BIT_22 1715 #define FCF_DSXXX_DEVICE BIT_23 1716 #define FCF_AA_EVA_DEVICE BIT_24 1717 #define FCF_AA_MSA_DEVICE BIT_25 1718 1719 /* No loop ID flag. */ 1720 #define FC_NO_LOOP_ID 0x1000 1721 1722 /* 1723 * FC-CT interface 1724 * 1725 * NOTE: All structures are big-endian in form. 1726 */ 1727 1728 #define CT_REJECT_RESPONSE 0x8001 1729 #define CT_ACCEPT_RESPONSE 0x8002 1730 1731 #define NS_N_PORT_TYPE 0x01 1732 #define NS_NL_PORT_TYPE 0x02 1733 #define NS_NX_PORT_TYPE 0x7F 1734 1735 #define GA_NXT_CMD 0x100 1736 #define GA_NXT_REQ_SIZE (16 + 4) 1737 #define GA_NXT_RSP_SIZE (16 + 620) 1738 1739 #define GID_PT_CMD 0x1A1 1740 #define GID_PT_REQ_SIZE (16 + 4) 1741 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4)) 1742 1743 #define GPN_ID_CMD 0x112 1744 #define GPN_ID_REQ_SIZE (16 + 4) 1745 #define GPN_ID_RSP_SIZE (16 + 8) 1746 1747 #define GNN_ID_CMD 0x113 1748 #define GNN_ID_REQ_SIZE (16 + 4) 1749 #define GNN_ID_RSP_SIZE (16 + 8) 1750 1751 #define GFT_ID_CMD 0x117 1752 #define GFT_ID_REQ_SIZE (16 + 4) 1753 #define GFT_ID_RSP_SIZE (16 + 32) 1754 1755 #define RFT_ID_CMD 0x217 1756 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 1757 #define RFT_ID_RSP_SIZE 16 1758 1759 #define RFF_ID_CMD 0x21F 1760 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 1761 #define RFF_ID_RSP_SIZE 16 1762 1763 #define RNN_ID_CMD 0x213 1764 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 1765 #define RNN_ID_RSP_SIZE 16 1766 1767 #define RSNN_NN_CMD 0x239 1768 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 1769 #define RSNN_NN_RSP_SIZE 16 1770 1771 /* CT command header -- request/response common fields */ 1772 struct ct_cmd_hdr { 1773 uint8_t revision; 1774 uint8_t in_id[3]; 1775 uint8_t gs_type; 1776 uint8_t gs_subtype; 1777 uint8_t options; 1778 uint8_t reserved; 1779 }; 1780 1781 /* CT command request */ 1782 struct ct_sns_req { 1783 struct ct_cmd_hdr header; 1784 uint16_t command; 1785 uint16_t max_rsp_size; 1786 uint8_t fragment_id; 1787 uint8_t reserved[3]; 1788 1789 union { 1790 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */ 1791 struct { 1792 uint8_t reserved; 1793 uint8_t port_id[3]; 1794 } port_id; 1795 1796 struct { 1797 uint8_t port_type; 1798 uint8_t domain; 1799 uint8_t area; 1800 uint8_t reserved; 1801 } gid_pt; 1802 1803 struct { 1804 uint8_t reserved; 1805 uint8_t port_id[3]; 1806 uint8_t fc4_types[32]; 1807 } rft_id; 1808 1809 struct { 1810 uint8_t reserved; 1811 uint8_t port_id[3]; 1812 uint16_t reserved2; 1813 uint8_t fc4_feature; 1814 uint8_t fc4_type; 1815 } rff_id; 1816 1817 struct { 1818 uint8_t reserved; 1819 uint8_t port_id[3]; 1820 uint8_t node_name[8]; 1821 } rnn_id; 1822 1823 struct { 1824 uint8_t node_name[8]; 1825 uint8_t name_len; 1826 uint8_t sym_node_name[255]; 1827 } rsnn_nn; 1828 } req; 1829 }; 1830 1831 /* CT command response header */ 1832 struct ct_rsp_hdr { 1833 struct ct_cmd_hdr header; 1834 uint16_t response; 1835 uint16_t residual; 1836 uint8_t fragment_id; 1837 uint8_t reason_code; 1838 uint8_t explanation_code; 1839 uint8_t vendor_unique; 1840 }; 1841 1842 struct ct_sns_gid_pt_data { 1843 uint8_t control_byte; 1844 uint8_t port_id[3]; 1845 }; 1846 1847 struct ct_sns_rsp { 1848 struct ct_rsp_hdr header; 1849 1850 union { 1851 struct { 1852 uint8_t port_type; 1853 uint8_t port_id[3]; 1854 uint8_t port_name[8]; 1855 uint8_t sym_port_name_len; 1856 uint8_t sym_port_name[255]; 1857 uint8_t node_name[8]; 1858 uint8_t sym_node_name_len; 1859 uint8_t sym_node_name[255]; 1860 uint8_t init_proc_assoc[8]; 1861 uint8_t node_ip_addr[16]; 1862 uint8_t class_of_service[4]; 1863 uint8_t fc4_types[32]; 1864 uint8_t ip_address[16]; 1865 uint8_t fabric_port_name[8]; 1866 uint8_t reserved; 1867 uint8_t hard_address[3]; 1868 } ga_nxt; 1869 1870 struct { 1871 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES]; 1872 } gid_pt; 1873 1874 struct { 1875 uint8_t port_name[8]; 1876 } gpn_id; 1877 1878 struct { 1879 uint8_t node_name[8]; 1880 } gnn_id; 1881 1882 struct { 1883 uint8_t fc4_types[32]; 1884 } gft_id; 1885 } rsp; 1886 }; 1887 1888 struct ct_sns_pkt { 1889 union { 1890 struct ct_sns_req req; 1891 struct ct_sns_rsp rsp; 1892 } p; 1893 }; 1894 1895 /* 1896 * SNS command structures -- for 2200 compatability. 1897 */ 1898 #define RFT_ID_SNS_SCMD_LEN 22 1899 #define RFT_ID_SNS_CMD_SIZE 60 1900 #define RFT_ID_SNS_DATA_SIZE 16 1901 1902 #define RNN_ID_SNS_SCMD_LEN 10 1903 #define RNN_ID_SNS_CMD_SIZE 36 1904 #define RNN_ID_SNS_DATA_SIZE 16 1905 1906 #define GA_NXT_SNS_SCMD_LEN 6 1907 #define GA_NXT_SNS_CMD_SIZE 28 1908 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 1909 1910 #define GID_PT_SNS_SCMD_LEN 6 1911 #define GID_PT_SNS_CMD_SIZE 28 1912 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16) 1913 1914 #define GPN_ID_SNS_SCMD_LEN 6 1915 #define GPN_ID_SNS_CMD_SIZE 28 1916 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 1917 1918 #define GNN_ID_SNS_SCMD_LEN 6 1919 #define GNN_ID_SNS_CMD_SIZE 28 1920 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 1921 1922 struct sns_cmd_pkt { 1923 union { 1924 struct { 1925 uint16_t buffer_length; 1926 uint16_t reserved_1; 1927 uint32_t buffer_address[2]; 1928 uint16_t subcommand_length; 1929 uint16_t reserved_2; 1930 uint16_t subcommand; 1931 uint16_t size; 1932 uint32_t reserved_3; 1933 uint8_t param[36]; 1934 } cmd; 1935 1936 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 1937 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 1938 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 1939 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 1940 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 1941 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 1942 } p; 1943 }; 1944 1945 /* IO descriptors */ 1946 #define MAX_IO_DESCRIPTORS 32 1947 1948 #define ABORT_IOCB_CB 0 1949 #define ADISC_PORT_IOCB_CB 1 1950 #define LOGOUT_PORT_IOCB_CB 2 1951 #define LOGIN_PORT_IOCB_CB 3 1952 #define LAST_IOCB_CB 4 1953 1954 #define IODESC_INVALID_INDEX 0xFFFF 1955 #define IODESC_ADISC_NEEDED 0xFFFE 1956 #define IODESC_LOGIN_NEEDED 0xFFFD 1957 1958 struct io_descriptor { 1959 uint16_t used:1; 1960 uint16_t idx:11; 1961 uint16_t cb_idx:4; 1962 1963 struct timer_list timer; 1964 1965 struct scsi_qla_host *ha; 1966 1967 port_id_t d_id; 1968 fc_port_t *remote_fcport; 1969 1970 uint32_t signature; 1971 }; 1972 1973 struct qla_fw_info { 1974 unsigned short addressing; /* addressing method used to load fw */ 1975 #define FW_INFO_ADDR_NORMAL 0 1976 #define FW_INFO_ADDR_EXTENDED 1 1977 #define FW_INFO_ADDR_NOMORE 0xffff 1978 unsigned short *fwcode; /* pointer to FW array */ 1979 unsigned short *fwlen; /* number of words in array */ 1980 unsigned short *fwstart; /* start address for F/W */ 1981 unsigned long *lfwstart; /* start address (long) for F/W */ 1982 }; 1983 1984 struct qla_board_info { 1985 char *drv_name; 1986 1987 char isp_name[8]; 1988 struct qla_fw_info *fw_info; 1989 char *fw_fname; 1990 struct scsi_host_template *sht; 1991 }; 1992 1993 /* Return data from MBC_GET_ID_LIST call. */ 1994 struct gid_list_info { 1995 uint8_t al_pa; 1996 uint8_t area; 1997 uint8_t domain; 1998 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 1999 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2000 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2001 }; 2002 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES) 2003 2004 /* 2005 * ISP operations 2006 */ 2007 struct isp_operations { 2008 2009 int (*pci_config) (struct scsi_qla_host *); 2010 void (*reset_chip) (struct scsi_qla_host *); 2011 int (*chip_diag) (struct scsi_qla_host *); 2012 void (*config_rings) (struct scsi_qla_host *); 2013 void (*reset_adapter) (struct scsi_qla_host *); 2014 int (*nvram_config) (struct scsi_qla_host *); 2015 void (*update_fw_options) (struct scsi_qla_host *); 2016 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2017 2018 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2019 char * (*fw_version_str) (struct scsi_qla_host *, char *); 2020 2021 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *); 2022 void (*enable_intrs) (struct scsi_qla_host *); 2023 void (*disable_intrs) (struct scsi_qla_host *); 2024 2025 int (*abort_command) (struct scsi_qla_host *, srb_t *); 2026 int (*abort_target) (struct fc_port *); 2027 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2028 uint8_t, uint8_t, uint16_t *, uint8_t); 2029 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2030 uint8_t, uint8_t); 2031 2032 uint16_t (*calc_req_entries) (uint16_t); 2033 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2034 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2035 2036 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2037 uint32_t, uint32_t); 2038 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2039 uint32_t); 2040 2041 void (*fw_dump) (struct scsi_qla_host *, int); 2042 void (*ascii_fw_dump) (struct scsi_qla_host *); 2043 }; 2044 2045 /* 2046 * Linux Host Adapter structure 2047 */ 2048 typedef struct scsi_qla_host { 2049 struct list_head list; 2050 2051 /* Commonly used flags and state information. */ 2052 struct Scsi_Host *host; 2053 struct pci_dev *pdev; 2054 2055 unsigned long host_no; 2056 unsigned long instance; 2057 2058 volatile struct { 2059 uint32_t init_done :1; 2060 uint32_t online :1; 2061 uint32_t mbox_int :1; 2062 uint32_t mbox_busy :1; 2063 uint32_t rscn_queue_overflow :1; 2064 uint32_t reset_active :1; 2065 2066 uint32_t management_server_logged_in :1; 2067 uint32_t process_response_queue :1; 2068 2069 uint32_t disable_risc_code_load :1; 2070 uint32_t enable_64bit_addressing :1; 2071 uint32_t enable_lip_reset :1; 2072 uint32_t enable_lip_full_login :1; 2073 uint32_t enable_target_reset :1; 2074 uint32_t enable_led_scheme :1; 2075 uint32_t msi_enabled :1; 2076 uint32_t msix_enabled :1; 2077 } flags; 2078 2079 atomic_t loop_state; 2080 #define LOOP_TIMEOUT 1 2081 #define LOOP_DOWN 2 2082 #define LOOP_UP 3 2083 #define LOOP_UPDATE 4 2084 #define LOOP_READY 5 2085 #define LOOP_DEAD 6 2086 2087 unsigned long dpc_flags; 2088 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 2089 #define RESET_ACTIVE 1 2090 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 2091 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 2092 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 2093 #define LOOP_RESYNC_ACTIVE 5 2094 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 2095 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 2096 #define MAILBOX_RETRY 8 2097 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */ 2098 #define FAILOVER_EVENT_NEEDED 10 2099 #define FAILOVER_EVENT 11 2100 #define FAILOVER_NEEDED 12 2101 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */ 2102 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */ 2103 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */ 2104 #define ABORT_QUEUES_NEEDED 16 2105 #define RELOGIN_NEEDED 17 2106 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */ 2107 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */ 2108 #define ISP_ABORT_RETRY 20 /* ISP aborted. */ 2109 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */ 2110 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */ 2111 #define IOCTL_ERROR_RECOVERY 23 2112 #define LOOP_RESET_NEEDED 24 2113 #define BEACON_BLINK_NEEDED 25 2114 2115 uint32_t device_flags; 2116 #define DFLG_LOCAL_DEVICES BIT_0 2117 #define DFLG_RETRY_LOCAL_DEVICES BIT_1 2118 #define DFLG_FABRIC_DEVICES BIT_2 2119 #define SWITCH_FOUND BIT_3 2120 #define DFLG_NO_CABLE BIT_4 2121 2122 /* SRB cache. */ 2123 #define SRB_MIN_REQ 128 2124 mempool_t *srb_mempool; 2125 2126 /* This spinlock is used to protect "io transactions", you must 2127 * aquire it before doing any IO to the card, eg with RD_REG*() and 2128 * WRT_REG*() for the duration of your entire commandtransaction. 2129 * 2130 * This spinlock is of lower priority than the io request lock. 2131 */ 2132 2133 spinlock_t hardware_lock ____cacheline_aligned; 2134 2135 device_reg_t __iomem *iobase; /* Base I/O address */ 2136 unsigned long pio_address; 2137 unsigned long pio_length; 2138 #define MIN_IOBASE_LEN 0x100 2139 2140 /* ISP ring lock, rings, and indexes */ 2141 dma_addr_t request_dma; /* Physical address. */ 2142 request_t *request_ring; /* Base virtual address */ 2143 request_t *request_ring_ptr; /* Current address. */ 2144 uint16_t req_ring_index; /* Current index. */ 2145 uint16_t req_q_cnt; /* Number of available entries. */ 2146 uint16_t request_q_length; 2147 2148 dma_addr_t response_dma; /* Physical address. */ 2149 response_t *response_ring; /* Base virtual address */ 2150 response_t *response_ring_ptr; /* Current address. */ 2151 uint16_t rsp_ring_index; /* Current index. */ 2152 uint16_t response_q_length; 2153 2154 struct isp_operations isp_ops; 2155 2156 /* Outstandings ISP commands. */ 2157 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; 2158 uint32_t current_outstanding_cmd; 2159 srb_t *status_srb; /* Status continuation entry. */ 2160 2161 uint16_t revision; 2162 uint8_t ports; 2163 2164 /* ISP configuration data. */ 2165 uint16_t loop_id; /* Host adapter loop id */ 2166 uint16_t fb_rev; 2167 2168 port_id_t d_id; /* Host adapter port id */ 2169 uint16_t max_public_loop_ids; 2170 uint16_t min_external_loopid; /* First external loop Id */ 2171 2172 uint16_t link_data_rate; /* F/W operating speed */ 2173 2174 uint8_t current_topology; 2175 uint8_t prev_topology; 2176 #define ISP_CFG_NL 1 2177 #define ISP_CFG_N 2 2178 #define ISP_CFG_FL 4 2179 #define ISP_CFG_F 8 2180 2181 uint8_t operating_mode; /* F/W operating mode */ 2182 #define LOOP 0 2183 #define P2P 1 2184 #define LOOP_P2P 2 2185 #define P2P_LOOP 3 2186 2187 uint8_t marker_needed; 2188 2189 uint8_t interrupts_on; 2190 2191 /* HBA serial number */ 2192 uint8_t serial0; 2193 uint8_t serial1; 2194 uint8_t serial2; 2195 2196 /* NVRAM configuration data */ 2197 uint16_t nvram_size; 2198 uint16_t nvram_base; 2199 2200 uint16_t loop_reset_delay; 2201 uint8_t retry_count; 2202 uint8_t login_timeout; 2203 uint16_t r_a_tov; 2204 int port_down_retry_count; 2205 uint8_t mbx_count; 2206 uint16_t last_loop_id; 2207 2208 uint32_t login_retry_count; 2209 2210 /* Fibre Channel Device List. */ 2211 struct list_head fcports; 2212 struct list_head rscn_fcports; 2213 2214 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS]; 2215 uint16_t iodesc_signature; 2216 2217 /* RSCN queue. */ 2218 uint32_t rscn_queue[MAX_RSCN_COUNT]; 2219 uint8_t rscn_in_ptr; 2220 uint8_t rscn_out_ptr; 2221 2222 /* SNS command interfaces. */ 2223 ms_iocb_entry_t *ms_iocb; 2224 dma_addr_t ms_iocb_dma; 2225 struct ct_sns_pkt *ct_sns; 2226 dma_addr_t ct_sns_dma; 2227 /* SNS command interfaces for 2200. */ 2228 struct sns_cmd_pkt *sns_cmd; 2229 dma_addr_t sns_cmd_dma; 2230 2231 pid_t dpc_pid; 2232 int dpc_should_die; 2233 struct completion dpc_inited; 2234 struct completion dpc_exited; 2235 struct semaphore *dpc_wait; 2236 uint8_t dpc_active; /* DPC routine is active */ 2237 2238 /* Timeout timers. */ 2239 uint8_t loop_down_abort_time; /* port down timer */ 2240 atomic_t loop_down_timer; /* loop down timer */ 2241 uint8_t link_down_timeout; /* link down timeout */ 2242 2243 uint32_t timer_active; 2244 struct timer_list timer; 2245 2246 dma_addr_t gid_list_dma; 2247 struct gid_list_info *gid_list; 2248 int gid_list_info_size; 2249 2250 dma_addr_t rlc_rsp_dma; 2251 rpt_lun_cmd_rsp_t *rlc_rsp; 2252 2253 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 2254 #define DMA_POOL_SIZE 256 2255 struct dma_pool *s_dma_pool; 2256 2257 dma_addr_t init_cb_dma; 2258 init_cb_t *init_cb; 2259 int init_cb_size; 2260 2261 dma_addr_t iodesc_pd_dma; 2262 port_database_t *iodesc_pd; 2263 2264 /* These are used by mailbox operations. */ 2265 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 2266 2267 mbx_cmd_t *mcp; 2268 unsigned long mbx_cmd_flags; 2269 #define MBX_INTERRUPT 1 2270 #define MBX_INTR_WAIT 2 2271 #define MBX_UPDATE_FLASH_ACTIVE 3 2272 2273 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */ 2274 2275 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */ 2276 struct semaphore mbx_intr_sem; /* Used for completion notification */ 2277 2278 uint32_t mbx_flags; 2279 #define MBX_IN_PROGRESS BIT_0 2280 #define MBX_BUSY BIT_1 /* Got the Access */ 2281 #define MBX_SLEEPING_ON_SEM BIT_2 2282 #define MBX_POLLING_FOR_COMP BIT_3 2283 #define MBX_COMPLETED BIT_4 2284 #define MBX_TIMEDOUT BIT_5 2285 #define MBX_ACCESS_TIMEDOUT BIT_6 2286 2287 mbx_cmd_t mc; 2288 2289 /* Basic firmware related information. */ 2290 struct qla_board_info *brd_info; 2291 uint16_t fw_major_version; 2292 uint16_t fw_minor_version; 2293 uint16_t fw_subminor_version; 2294 uint16_t fw_attributes; 2295 uint32_t fw_memory_size; 2296 uint32_t fw_transfer_size; 2297 2298 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 2299 uint8_t fw_seriallink_options[4]; 2300 uint16_t fw_seriallink_options24[4]; 2301 2302 /* Firmware dump information. */ 2303 void *fw_dump; 2304 int fw_dump_order; 2305 int fw_dump_reading; 2306 char *fw_dump_buffer; 2307 int fw_dump_buffer_len; 2308 2309 int fw_dumped; 2310 void *fw_dump24; 2311 int fw_dump24_len; 2312 2313 uint8_t host_str[16]; 2314 uint32_t pci_attr; 2315 2316 uint16_t product_id[4]; 2317 2318 uint8_t model_number[16+1]; 2319 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 2320 char *model_desc; 2321 2322 uint8_t *node_name; 2323 uint8_t *port_name; 2324 uint32_t isp_abort_cnt; 2325 2326 /* Needed for BEACON */ 2327 uint16_t beacon_blink_led; 2328 uint16_t beacon_green_on; 2329 } scsi_qla_host_t; 2330 2331 2332 /* 2333 * Macros to help code, maintain, etc. 2334 */ 2335 #define LOOP_TRANSITION(ha) \ 2336 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 2337 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 2338 2339 #define LOOP_NOT_READY(ha) \ 2340 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 2341 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \ 2342 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 2343 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \ 2344 atomic_read(&ha->loop_state) == LOOP_DOWN) 2345 2346 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha)) 2347 2348 #define TGT_Q(ha, t) (ha->otgt[t]) 2349 2350 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata) 2351 2352 #define qla_printk(level, ha, format, arg...) \ 2353 dev_printk(level , &((ha)->pdev->dev) , format , ## arg) 2354 2355 /* 2356 * qla2x00 local function return status codes 2357 */ 2358 #define MBS_MASK 0x3fff 2359 2360 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 2361 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 2362 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 2363 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 2364 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 2365 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 2366 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 2367 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 2368 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 2369 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 2370 2371 #define QLA_FUNCTION_TIMEOUT 0x100 2372 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 2373 #define QLA_FUNCTION_FAILED 0x102 2374 #define QLA_MEMORY_ALLOC_FAILED 0x103 2375 #define QLA_LOCK_TIMEOUT 0x104 2376 #define QLA_ABORTED 0x105 2377 #define QLA_SUSPENDED 0x106 2378 #define QLA_BUSY 0x107 2379 #define QLA_RSCNS_HANDLED 0x108 2380 2381 /* 2382 * Stat info for all adpaters 2383 */ 2384 struct _qla2x00stats { 2385 unsigned long mboxtout; /* mailbox timeouts */ 2386 unsigned long mboxerr; /* mailbox errors */ 2387 unsigned long ispAbort; /* ISP aborts */ 2388 unsigned long debugNo; 2389 unsigned long loop_resync; 2390 unsigned long outarray_full; 2391 unsigned long retry_q_cnt; 2392 }; 2393 2394 #define NVRAM_DELAY() udelay(10) 2395 2396 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1) 2397 2398 /* 2399 * Flash support definitions 2400 */ 2401 #define FLASH_IMAGE_SIZE 131072 2402 2403 #include "qla_gbl.h" 2404 #include "qla_dbg.h" 2405 #include "qla_inline.h" 2406 2407 /* 2408 * String arrays 2409 */ 2410 #define LINESIZE 256 2411 #define MAXARGS 26 2412 2413 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 2414 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual) 2415 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual) 2416 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status) 2417 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message) 2418 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in) 2419 2420 #endif 2421